src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
author lucy
Mon, 18 Nov 2019 17:11:06 +0100
changeset 59122 5d73255c2d52
parent 57804 9b7b9f16dfd9
permissions -rw-r--r--
8233787: Break cycle in vm_version* includes Reviewed-by: kbarrett, mdoerr
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/*
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 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2015, 2019, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/os.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/vm_version.hpp"
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#include "utilities/macros.hpp"
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#include OS_HEADER_INLINE(os)
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#include <sys/auxv.h>
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#include <asm/hwcap.h>
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#ifndef HWCAP_AES
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#define HWCAP_AES   (1<<3)
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#endif
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#ifndef HWCAP_PMULL
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#define HWCAP_PMULL (1<<4)
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#endif
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#ifndef HWCAP_SHA1
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#define HWCAP_SHA1  (1<<5)
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#endif
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#ifndef HWCAP_SHA2
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#define HWCAP_SHA2  (1<<6)
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#endif
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#ifndef HWCAP_CRC32
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#define HWCAP_CRC32 (1<<7)
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#endif
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#ifndef HWCAP_ATOMICS
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#define HWCAP_ATOMICS (1<<8)
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#endif
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_model2;
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int VM_Version::_variant;
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int VM_Version::_revision;
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int VM_Version::_stepping;
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bool VM_Version::_dcpop;
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VM_Version::PsrInfo VM_Version::_psr_info   = { 0, };
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static BufferBlob* stub_blob;
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static const int stub_size = 550;
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extern "C" {
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  typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_getPsrInfo() {
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    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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#   define __ _masm->
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    address start = __ pc();
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    // void getPsrInfo(VM_Version::PsrInfo* psr_info);
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    address entry = __ pc();
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    __ enter();
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    __ get_dczid_el0(rscratch1);
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    __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
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    __ get_ctr_el0(rscratch1);
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    __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
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    __ leave();
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    __ ret(lr);
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#   undef __
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    return start;
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  }
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};
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void VM_Version::get_processor_features() {
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  _supports_cx8 = true;
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  _supports_atomic_getset4 = true;
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  _supports_atomic_getadd4 = true;
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  _supports_atomic_getset8 = true;
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  _supports_atomic_getadd8 = true;
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  getPsrInfo_stub(&_psr_info);
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  int dcache_line = VM_Version::dcache_line_size();
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  // Limit AllocatePrefetchDistance so that it does not exceed the
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  // constraint in AllocatePrefetchDistanceConstraintFunc.
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  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
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    FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
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  if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
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    FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
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  if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
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    FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
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  if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
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    FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
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  if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
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    FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
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  if (PrefetchCopyIntervalInBytes != -1 &&
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       ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
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    warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
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    PrefetchCopyIntervalInBytes &= ~7;
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    if (PrefetchCopyIntervalInBytes >= 32768)
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      PrefetchCopyIntervalInBytes = 32760;
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  }
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  if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
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    warning("AllocatePrefetchDistance must be multiple of 8");
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    AllocatePrefetchDistance &= ~7;
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  }
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   153
  if (AllocatePrefetchStepSize & 7) {
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   154
    warning("AllocatePrefetchStepSize must be multiple of 8");
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   155
    AllocatePrefetchStepSize &= ~7;
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   156
  }
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parents: 47571
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   157
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   158
  if (SoftwarePrefetchHintDistance != -1 &&
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   159
       (SoftwarePrefetchHintDistance & 7)) {
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   160
    warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
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   161
    SoftwarePrefetchHintDistance &= ~7;
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   162
  }
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   163
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   164
  unsigned long auxv = getauxval(AT_HWCAP);
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  char buf[512];
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parents:
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  _features = auxv;
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   169
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   170
  int cpu_lines = 0;
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   171
  if (FILE *f = fopen("/proc/cpuinfo", "r")) {
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    // need a large buffer as the flags line may include lots of text
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   173
    char buf[1024], *p;
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   174
    while (fgets(buf, sizeof (buf), f) != NULL) {
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   175
      if ((p = strchr(buf, ':')) != NULL) {
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   176
        long v = strtol(p+1, NULL, 0);
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   177
        if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
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   178
          _cpu = v;
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          cpu_lines++;
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   180
        } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
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   181
          _variant = v;
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   182
        } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
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   183
          if (_model != v)  _model2 = _model;
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   184
          _model = v;
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   185
        } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
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   186
          _revision = v;
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   187
        } else if (strncmp(buf, "flags", sizeof("flags") - 1) == 0) {
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   188
          if (strstr(p+1, "dcpop")) {
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   189
            _dcpop = true;
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   190
          }
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   191
        }
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   192
      }
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   193
    }
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   194
    fclose(f);
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   195
  }
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parents: 30225
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   196
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   197
  if (os::supports_map_sync()) {
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   198
    // if dcpop is available publish data cache line flush size via
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   199
    // generic field, otherwise let if default to zero thereby
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   200
    // disabling writeback
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   201
    if (_dcpop) {
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   202
      _data_cache_line_flush_size = dcache_line;
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diff changeset
   203
    }
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   204
  }
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parents: 57565
diff changeset
   205
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   206
  // Enable vendor specific features
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   207
54117
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   208
  // Ampere eMAG
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   209
  if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
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   210
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
a6221f993616 8220566: AArch64: Set default vm features for Ampere eMAG CPUs
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parents: 53989
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   211
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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parents: 53989
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   212
    }
a6221f993616 8220566: AArch64: Set default vm features for Ampere eMAG CPUs
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   213
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
a6221f993616 8220566: AArch64: Set default vm features for Ampere eMAG CPUs
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   214
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
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diff changeset
   215
    }
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   216
    if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
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parents: 53989
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   217
      FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
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parents: 53989
diff changeset
   218
    }
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parents: 53989
diff changeset
   219
  }
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parents: 53989
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   220
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   221
  // ThunderX
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   222
  if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
40023
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   223
    if (_variant == 0) _features |= CPU_DMB_ATOMICS;
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parents: 38714
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   224
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
49d647eeb7f0 8159063: aarch64: optimise unaligned array copy long
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   225
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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   226
    }
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   227
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
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   228
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
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diff changeset
   229
    }
49724
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   230
    if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
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   231
      FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
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diff changeset
   232
    }
40023
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diff changeset
   233
  }
49724
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   234
49173
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   235
  // ThunderX2
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diff changeset
   236
  if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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diff changeset
   237
      (_cpu == CPU_BROADCOM && (_model == 0x516))) {
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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parents: 48196
diff changeset
   238
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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parents: 48196
diff changeset
   239
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
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diff changeset
   240
    }
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dchuyko
parents: 48196
diff changeset
   241
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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parents: 48196
diff changeset
   242
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
dchuyko
parents: 48196
diff changeset
   243
    }
cf4562e8a3f9 8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2
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parents: 48196
diff changeset
   244
  }
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parents: 48196
diff changeset
   245
53989
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   246
  // HiSilicon TSV110
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
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parents: 53943
diff changeset
   247
  if (_cpu == CPU_HISILICON && _model == 0xd01) {
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   248
    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   249
      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   250
    }
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   251
    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
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parents: 53943
diff changeset
   252
      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   253
    }
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   254
  }
247f1a85d736 8219888: aarch64: add CPU detection code for HiSilicon TSV110
fyang
parents: 53943
diff changeset
   255
49724
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
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diff changeset
   256
  // Cortex A53
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   257
  if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
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diff changeset
   258
    _features |= CPU_A53MAC;
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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parents: 49173
diff changeset
   259
    if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   260
      FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   261
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   262
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   263
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   264
  // Cortex A73
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
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diff changeset
   265
  if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   266
    if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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parents: 49173
diff changeset
   267
      FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
parents: 49173
diff changeset
   268
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
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diff changeset
   269
    // A73 is faster with short-and-easy-for-speculative-execution-loop
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
dpochepk
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diff changeset
   270
    if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   271
      FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
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diff changeset
   272
    }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   273
  }
bf7f42f2f025 8187472: AARCH64: array_equals intrinsic doesn't use prefetch for large arrays
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diff changeset
   274
38714
170464570e45 8157841: aarch64: prefetch ignores cache line size
enevill
parents: 38143
diff changeset
   275
  if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
30429
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diff changeset
   276
  // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
parents: 30225
diff changeset
   277
  // we assume the worst and assume we could be on a big little system and have
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
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diff changeset
   278
  // undisclosed A53 cores which we could be swapped to at any stage
35148
5cfafc99d791 8143072: [JVMCI] Port JVMCI to AArch64
twisti
parents: 35110
diff changeset
   279
  if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
30429
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
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diff changeset
   280
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
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diff changeset
   281
  sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
parents: 30225
diff changeset
   282
  if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
parents: 30225
diff changeset
   283
  if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   284
  if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   285
  if (auxv & HWCAP_AES)   strcat(buf, ", aes");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   286
  if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   287
  if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   288
  if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   289
35148
5cfafc99d791 8143072: [JVMCI] Port JVMCI to AArch64
twisti
parents: 35110
diff changeset
   290
  _features_string = os::strdup(buf);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   291
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   292
  if (FLAG_IS_DEFAULT(UseCRC32)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   293
    UseCRC32 = (auxv & HWCAP_CRC32) != 0;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   294
  }
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   295
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   296
  if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   297
    warning("UseCRC32 specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   298
    FLAG_SET_DEFAULT(UseCRC32, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   299
  }
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   300
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32581
diff changeset
   301
  if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
enevill
parents: 32581
diff changeset
   302
    FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   303
  }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31961
diff changeset
   304
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   305
  if (UseVectorizedMismatchIntrinsic) {
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   306
    warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   307
    FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   308
  }
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 33176
diff changeset
   309
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   310
  if (auxv & HWCAP_ATOMICS) {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   311
    if (FLAG_IS_DEFAULT(UseLSE))
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   312
      FLAG_SET_DEFAULT(UseLSE, true);
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   313
  } else {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   314
    if (UseLSE) {
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   315
      warning("UseLSE specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   316
      FLAG_SET_DEFAULT(UseLSE, false);
36562
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   317
    }
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   318
  }
4d1e93624d6a 8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents: 35841
diff changeset
   319
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   320
  if (auxv & HWCAP_AES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   321
    UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   322
    UseAESIntrinsics =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   323
        UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   324
    if (UseAESIntrinsics && !UseAES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   325
      warning("UseAESIntrinsics enabled, but UseAES not, enabling");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   326
      UseAES = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   327
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   328
  } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   329
    if (UseAES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   330
      warning("UseAES specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   331
      FLAG_SET_DEFAULT(UseAES, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   332
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   333
    if (UseAESIntrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   334
      warning("UseAESIntrinsics specified, but not supported on this CPU");
53943
72ce7dd54939 8219698: aarch64: SIGILL triggered when specifying unsupported hardware features
fyang
parents: 52425
diff changeset
   335
      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   336
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   337
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   338
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   339
  if (UseAESCTRIntrinsics) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   340
    warning("AES/CTR intrinsics are not available on this CPU");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   341
    FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   342
  }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35148
diff changeset
   343
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   344
  if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   345
    UseCRC32Intrinsics = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   346
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   347
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   348
  if (auxv & HWCAP_CRC32) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   349
    if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   350
      FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   351
    }
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   352
  } else if (UseCRC32CIntrinsics) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31588
diff changeset
   353
    warning("CRC32C is not available on the CPU");
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   354
    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   355
  }
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   356
42653
62a5d76872d4 8162338: AArch64: Intrinsify fused mac operations
roland
parents: 41323
diff changeset
   357
  if (FLAG_IS_DEFAULT(UseFMA)) {
62a5d76872d4 8162338: AArch64: Intrinsify fused mac operations
roland
parents: 41323
diff changeset
   358
    FLAG_SET_DEFAULT(UseFMA, true);
41323
ddd5600d4762 8154122: Intrinsify fused mac operations
vdeshpande
parents: 40093
diff changeset
   359
  }
ddd5600d4762 8154122: Intrinsify fused mac operations
vdeshpande
parents: 40093
diff changeset
   360
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   361
  if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   362
    if (FLAG_IS_DEFAULT(UseSHA)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   363
      FLAG_SET_DEFAULT(UseSHA, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   364
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   365
  } else if (UseSHA) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   366
    warning("SHA instructions are not available on this CPU");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   367
    FLAG_SET_DEFAULT(UseSHA, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   368
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   369
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   370
  if (UseSHA && (auxv & HWCAP_SHA1)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   371
    if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   372
      FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   373
    }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   374
  } else if (UseSHA1Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   375
    warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   376
    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   377
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   378
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   379
  if (UseSHA && (auxv & HWCAP_SHA2)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   380
    if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   381
      FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   382
    }
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   383
  } else if (UseSHA256Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   384
    warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
31960
4e66771a3e0a 8132010: aarch64: regression test fails compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnSupportedCPU.java
enevill
parents: 31955
diff changeset
   385
    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   386
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   387
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   388
  if (UseSHA512Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   389
    warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   390
    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   391
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   392
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   393
  if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   394
    FLAG_SET_DEFAULT(UseSHA, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   395
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   396
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   397
  if (auxv & HWCAP_PMULL) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   398
    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   399
      FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   400
    }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   401
  } else if (UseGHASHIntrinsics) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   402
    warning("GHASH intrinsics are not available on this CPU");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   403
    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   404
  }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   405
38143
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   406
  if (is_zva_enabled()) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   407
    if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   408
      FLAG_SET_DEFAULT(UseBlockZeroing, true);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   409
    }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   410
    if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   411
      FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   412
    }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   413
  } else if (UseBlockZeroing) {
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   414
    warning("DC ZVA is not available on this CPU");
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   415
    FLAG_SET_DEFAULT(UseBlockZeroing, false);
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   416
  }
3b732f17ea7d 8155617: aarch64: ClearArray does not use DC ZVA
enevill
parents: 36562
diff changeset
   417
30209
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   418
  // This machine allows unaligned memory accesses
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   419
  if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   420
    FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   421
  }
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   422
51619
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   423
  if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   424
    UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   425
  }
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   426
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   427
  if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   428
    UsePopCountInstruction = true;
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   429
  }
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   430
dca697c71e5d 8207247: AARCH64: Enable Minimal and Client VM builds
avoitylov
parents: 49724
diff changeset
   431
#ifdef COMPILER2
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   432
  if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   433
    UseMultiplyToLenIntrinsic = true;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   434
  }
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   435
47571
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   436
  if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   437
    UseSquareToLenIntrinsic = true;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   438
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   439
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   440
  if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   441
    UseMulAddIntrinsic = true;
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   442
  }
c19054f06c14 8186915: AARCH64: Intrinsify squareToLen and mulAdd
dpochepk
parents: 47216
diff changeset
   443
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   444
  if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   445
    UseMontgomeryMultiplyIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   446
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   447
  if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   448
    UseMontgomerySquareIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   449
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   450
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   451
  if (FLAG_IS_DEFAULT(OptoScheduling)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   452
    OptoScheduling = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   453
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   454
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   455
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   456
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   457
void VM_Version::initialize() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   458
  ResourceMark rm;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   459
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   460
  stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   461
  if (stub_blob == NULL) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   462
    vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   463
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   464
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   465
  CodeBuffer c(stub_blob);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   466
  VM_Version_StubGenerator g(&c);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   467
  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   468
                                   g.generate_getPsrInfo());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   469
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   470
  get_processor_features();
48182
5fb0f3f24f6b 8191129: AARCH64: Invalid value passed to critical JNI function
dchuyko
parents: 47571
diff changeset
   471
5fb0f3f24f6b 8191129: AARCH64: Invalid value passed to critical JNI function
dchuyko
parents: 47571
diff changeset
   472
  UNSUPPORTED_OPTION(CriticalJNINatives);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   473
}