hotspot/src/cpu/aarch64/vm/vm_version_aarch64.cpp
author kvn
Mon, 28 Dec 2015 23:11:01 -0800
changeset 35154 a9b3c1984a01
parent 35148 5cfafc99d791
child 35581 dd47cf4734f2
permissions -rw-r--r--
8143925: Enhancing CounterMode.crypt() for AES Summary: Add intrinsic for CounterMode.crypt() to leverage the parallel nature of AES in Counter(CTR) Mode. Reviewed-by: kvn, ascarpino Contributed-by: kishor.kharbas@intel.com
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/*
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 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_aarch64.hpp"
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#ifdef TARGET_OS_FAMILY_linux
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# include "os_linux.inline.hpp"
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#endif
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#ifndef BUILTIN_SIM
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#include <sys/auxv.h>
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#include <asm/hwcap.h>
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#else
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#define getauxval(hwcap) 0
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#endif
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#ifndef HWCAP_AES
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#define HWCAP_AES   (1<<3)
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#endif
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#ifndef HWCAP_PMULL
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#define HWCAP_PMULL (1<<4)
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#endif
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#ifndef HWCAP_SHA1
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#define HWCAP_SHA1  (1<<5)
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#endif
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#ifndef HWCAP_SHA2
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#define HWCAP_SHA2  (1<<6)
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#endif
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#ifndef HWCAP_CRC32
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#define HWCAP_CRC32 (1<<7)
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#endif
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_model2;
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int VM_Version::_variant;
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int VM_Version::_revision;
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int VM_Version::_stepping;
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static BufferBlob* stub_blob;
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static const int stub_size = 550;
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extern "C" {
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  typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_getPsrInfo() {
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    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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#   define __ _masm->
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    address start = __ pc();
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#ifdef BUILTIN_SIM
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    __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
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#endif
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    // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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    address entry = __ pc();
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    // TODO : redefine fields in CpuidInfo and generate
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    // code to fill them in
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    __ ret(lr);
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#   undef __
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    return start;
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  }
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};
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void VM_Version::get_processor_features() {
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  _supports_cx8 = true;
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  _supports_atomic_getset4 = true;
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  _supports_atomic_getadd4 = true;
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  _supports_atomic_getset8 = true;
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  _supports_atomic_getadd8 = true;
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  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
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    FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
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  if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
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    FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
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  FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
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  FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
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  FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
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  FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
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  unsigned long auxv = getauxval(AT_HWCAP);
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  char buf[512];
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  _features = auxv;
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  int cpu_lines = 0;
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  if (FILE *f = fopen("/proc/cpuinfo", "r")) {
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    char buf[128], *p;
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    while (fgets(buf, sizeof (buf), f) != NULL) {
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      if (p = strchr(buf, ':')) {
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        long v = strtol(p+1, NULL, 0);
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        if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
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          _cpu = v;
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          cpu_lines++;
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        } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
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          _variant = v;
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        } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
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          if (_model != v)  _model2 = _model;
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          _model = v;
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        } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
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          _revision = v;
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        }
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      }
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    }
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    fclose(f);
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  }
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   154
  // Enable vendor specific features
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  if (_cpu == CPU_CAVIUM && _variant == 0) _features |= CPU_DMB_ATOMICS;
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   156
  if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
30429
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   157
  // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
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   158
  // we assume the worst and assume we could be on a big little system and have
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   159
  // undisclosed A53 cores which we could be swapped to at any stage
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   160
  if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
30429
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   161
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   162
  sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
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   163
  if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
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   164
  if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
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   165
  if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
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   166
  if (auxv & HWCAP_AES)   strcat(buf, ", aes");
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   167
  if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
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   168
  if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
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diff changeset
   169
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   170
  _features_string = os::strdup(buf);
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   171
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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   172
  if (FLAG_IS_DEFAULT(UseCRC32)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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   173
    UseCRC32 = (auxv & HWCAP_CRC32) != 0;
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diff changeset
   174
  }
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   175
  if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
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   176
    warning("UseCRC32 specified, but not supported on this CPU");
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   177
  }
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
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   178
33176
54393049bf1e 8139043: aarch64: add support for adler32 intrinsic
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   179
  if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
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   180
    FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
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632402f18fe6 8132081: C2 support for Adler32 on SPARC
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diff changeset
   181
  }
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diff changeset
   182
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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diff changeset
   183
  if (UseVectorizedMismatchIntrinsic) {
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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   184
    warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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   185
    FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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diff changeset
   186
  }
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
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parents: 33176
diff changeset
   187
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   188
  if (auxv & HWCAP_AES) {
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   189
    UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
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   190
    UseAESIntrinsics =
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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   191
        UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
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diff changeset
   192
    if (UseAESIntrinsics && !UseAES) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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   193
      warning("UseAESIntrinsics enabled, but UseAES not, enabling");
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   194
      UseAES = true;
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diff changeset
   195
    }
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diff changeset
   196
  } else {
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diff changeset
   197
    if (UseAES) {
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parents:
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   198
      warning("UseAES specified, but not supported on this CPU");
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diff changeset
   199
    }
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   200
    if (UseAESIntrinsics) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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parents:
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   201
      warning("UseAESIntrinsics specified, but not supported on this CPU");
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diff changeset
   202
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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diff changeset
   203
  }
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parents:
diff changeset
   204
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a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
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   205
  if (UseAESCTRIntrinsics) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
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diff changeset
   206
    warning("AES/CTR intrinsics are not available on this CPU");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
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diff changeset
   207
    FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
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diff changeset
   208
  }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
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diff changeset
   209
29183
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   210
  if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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diff changeset
   211
    UseCRC32Intrinsics = true;
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aph
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diff changeset
   212
  }
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diff changeset
   213
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82134a118aea 8130687: aarch64: add support for hardware crc32c
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   214
  if (auxv & HWCAP_CRC32) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
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diff changeset
   215
    if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
82134a118aea 8130687: aarch64: add support for hardware crc32c
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diff changeset
   216
      FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
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diff changeset
   217
    }
82134a118aea 8130687: aarch64: add support for hardware crc32c
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   218
  } else if (UseCRC32CIntrinsics) {
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   219
    warning("CRC32C is not available on the CPU");
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
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   220
    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
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parents: 31404
diff changeset
   221
  }
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
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parents: 31404
diff changeset
   222
29183
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   223
  if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
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   224
    if (FLAG_IS_DEFAULT(UseSHA)) {
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   225
      FLAG_SET_DEFAULT(UseSHA, true);
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diff changeset
   226
    }
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diff changeset
   227
  } else if (UseSHA) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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diff changeset
   228
    warning("SHA instructions are not available on this CPU");
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   229
    FLAG_SET_DEFAULT(UseSHA, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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parents:
diff changeset
   230
  }
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parents:
diff changeset
   231
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   232
  if (UseSHA && (auxv & HWCAP_SHA1)) {
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diff changeset
   233
    if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   234
      FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   235
    }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   236
  } else if (UseSHA1Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   237
    warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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diff changeset
   238
    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   239
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   240
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   241
  if (UseSHA && (auxv & HWCAP_SHA2)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   242
    if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   243
      FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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parents:
diff changeset
   244
    }
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   245
  } else if (UseSHA256Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   246
    warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
31960
4e66771a3e0a 8132010: aarch64: regression test fails compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnSupportedCPU.java
enevill
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diff changeset
   247
    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   248
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   249
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   250
  if (UseSHA512Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   251
    warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   252
    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31517
diff changeset
   253
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   254
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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diff changeset
   255
  if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
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parents: 31517
diff changeset
   256
    FLAG_SET_DEFAULT(UseSHA, false);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   257
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   258
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   259
  if (auxv & HWCAP_PMULL) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   260
    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   261
      FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   262
    }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   263
  } else if (UseGHASHIntrinsics) {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   264
    warning("GHASH intrinsics are not available on this CPU");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   265
    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   266
  }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31960
diff changeset
   267
30209
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
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diff changeset
   268
  // This machine allows unaligned memory accesses
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
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diff changeset
   269
  if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
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diff changeset
   270
    FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
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diff changeset
   271
  }
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 29183
diff changeset
   272
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   273
  if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   274
    UseMultiplyToLenIntrinsic = true;
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   275
  }
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 30209
diff changeset
   276
30429
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
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diff changeset
   277
  if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
35148
5cfafc99d791 8143072: [JVMCI] Port JVMCI to AArch64
twisti
parents: 35110
diff changeset
   278
    UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
30429
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
parents: 30225
diff changeset
   279
  }
c980154ed1a3 8079203: AARCH64: Need to cater for different partner implementations
enevill
parents: 30225
diff changeset
   280
31517
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31515
diff changeset
   281
  if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31515
diff changeset
   282
    UsePopCountInstruction = true;
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31515
diff changeset
   283
  }
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31515
diff changeset
   284
31955
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   285
  if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   286
    UseMontgomeryMultiplyIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   287
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   288
  if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   289
    UseMontgomerySquareIntrinsic = true;
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   290
  }
c6ac18ab3d6b 8131779: AARCH64: add Montgomery multiply intrinsic
aph
parents: 31591
diff changeset
   291
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
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parents:
diff changeset
   292
#ifdef COMPILER2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   293
  if (FLAG_IS_DEFAULT(OptoScheduling)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   294
    OptoScheduling = true;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   295
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   296
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
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}
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void VM_Version::initialize() {
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  ResourceMark rm;
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  stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
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  if (stub_blob == NULL) {
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    vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
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  }
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  CodeBuffer c(stub_blob);
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  VM_Version_StubGenerator g(&c);
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  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
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                                   g.generate_getPsrInfo());
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  get_processor_features();
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}