/*

 * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_FrameMap.hpp"

#include "c1/c1_Instruction.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_LIRGenerator.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArray.hpp"

#include "ci/ciObjArrayKlass.hpp"

#include "ci/ciTypeArrayKlass.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "vmreg_ppc.inline.hpp"

#ifdef ASSERT

#define __ gen()->lir(__FILE__, __LINE__)->

#else

#define __ gen()->lir()->

#endif

void LIRItem::load_byte_item() {

  // Byte loads use same registers as other loads.

  load_item();

}

void LIRItem::load_nonconstant() {

  LIR_Opr r = value()->operand();

  if (_gen->can_inline_as_constant(value())) {

    if (!r->is_constant()) {

      r = LIR_OprFact::value_type(value()->type());

    }

    _result = r;

  } else {

    load_item();

  }

}

//--------------------------------------------------------------

//               LIRGenerator

//--------------------------------------------------------------

LIR_Opr LIRGenerator::exceptionOopOpr()              { return FrameMap::R3_oop_opr; }

LIR_Opr LIRGenerator::exceptionPcOpr()               { return FrameMap::R4_opr; }

LIR_Opr LIRGenerator::syncLockOpr()                  { return FrameMap::R5_opr; }     // Need temp effect for MonitorEnterStub.

LIR_Opr LIRGenerator::syncTempOpr()                  { return FrameMap::R4_oop_opr; } // Need temp effect for MonitorEnterStub.

LIR_Opr LIRGenerator::getThreadTemp()                { return LIR_OprFact::illegalOpr; } // not needed

LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {

  LIR_Opr opr;

  switch (type->tag()) {

  case intTag:     opr = FrameMap::R3_opr;         break;

  case objectTag:  opr = FrameMap::R3_oop_opr;     break;

  case longTag:    opr = FrameMap::R3_long_opr;    break;

  case floatTag:   opr = FrameMap::F1_opr;         break;

  case doubleTag:  opr = FrameMap::F1_double_opr;  break;

  case addressTag:

  default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;

  }

  assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");

  return opr;

}

LIR_Opr LIRGenerator::rlock_callee_saved(BasicType type) {

  ShouldNotReachHere();

  return LIR_OprFact::illegalOpr;

}

LIR_Opr LIRGenerator::rlock_byte(BasicType type) {

  return new_register(T_INT);

}

//--------- loading items into registers --------------------------------

// PPC cannot inline all constants.

bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {

  if (v->type()->as_IntConstant() != NULL) {

    return Assembler::is_simm16(v->type()->as_IntConstant()->value());

  } else if (v->type()->as_LongConstant() != NULL) {

    return Assembler::is_simm16(v->type()->as_LongConstant()->value());

  } else if (v->type()->as_ObjectConstant() != NULL) {

    return v->type()->as_ObjectConstant()->value()->is_null_object();

  } else {

    return false;

  }

}

// Only simm16 constants can be inlined.

bool LIRGenerator::can_inline_as_constant(Value i) const {

  return can_store_as_constant(i, as_BasicType(i->type()));

}

bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {

  if (c->type() == T_INT) {

    return Assembler::is_simm16(c->as_jint());

  }

  if (c->type() == T_LONG) {

    return Assembler::is_simm16(c->as_jlong());

  }

  if (c->type() == T_OBJECT) {

    return c->as_jobject() == NULL;

  }

  return false;

}

LIR_Opr LIRGenerator::safepoint_poll_register() {

  return new_register(T_INT);

}

LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,

                                            int shift, int disp, BasicType type) {

  assert(base->is_register(), "must be");

  intx large_disp = disp;

  // Accumulate fixed displacements.

  if (index->is_constant()) {

    index = LIR_OprFact::illegalOpr;

  }

  if (index->is_register()) {

    // Apply the shift and accumulate the displacement.

    if (shift > 0) {

      LIR_Opr tmp = new_pointer_register();

      __ shift_left(index, shift, tmp);

      index = tmp;

    }

    if (large_disp != 0) {

      LIR_Opr tmp = new_pointer_register();

      if (Assembler::is_simm16(large_disp)) {

        __ add(index, LIR_OprFact::intptrConst(large_disp), tmp);

        index = tmp;

      } else {

        __ move(LIR_OprFact::intptrConst(large_disp), tmp);

        __ add(tmp, index, tmp);

        index = tmp;

      }

      large_disp = 0;

    }

  } else if (!Assembler::is_simm16(large_disp)) {

    // Index is illegal so replace it with the displacement loaded into a register.

    index = new_pointer_register();

    __ move(LIR_OprFact::intptrConst(large_disp), index);

    large_disp = 0;

  }

  // At this point we either have base + index or base + displacement.

  if (large_disp == 0) {

    return new LIR_Address(base, index, type);

  } else {

    assert(Assembler::is_simm16(large_disp), "must be");

    return new LIR_Address(base, large_disp, type);

  }

}

LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,

  int elem_size = type2aelembytes(type);

  int shift = exact_log2(elem_size);

  LIR_Opr base_opr;

  intx offset = arrayOopDesc::base_offset_in_bytes(type);

  if (index_opr->is_constant()) {

    intx i = index_opr->as_constant_ptr()->as_jint();

    intx array_offset = i * elem_size;

    if (Assembler::is_simm16(array_offset + offset)) {

      base_opr = array_opr;

      offset = array_offset + offset;

    } else {

      base_opr = new_pointer_register();

      if (Assembler::is_simm16(array_offset)) {

        __ add(array_opr, LIR_OprFact::intptrConst(array_offset), base_opr);

      } else {

        __ move(LIR_OprFact::intptrConst(array_offset), base_opr);

        __ add(base_opr, array_opr, base_opr);

      }

    }

  } else {

#ifdef _LP64

    if (index_opr->type() == T_INT) {

      LIR_Opr tmp = new_register(T_LONG);

      __ convert(Bytecodes::_i2l, index_opr, tmp);

      index_opr = tmp;

    }

#endif

    base_opr = new_pointer_register();

    assert (index_opr->is_register(), "Must be register");

    if (shift > 0) {

      __ shift_left(index_opr, shift, base_opr);

      __ add(base_opr, array_opr, base_opr);

    } else {

      __ add(index_opr, array_opr, base_opr);

    }

  }

}

LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {

  LIR_Opr r = NULL;

  if (type == T_LONG) {

    r = LIR_OprFact::longConst(x);

  } else if (type == T_INT) {

    r = LIR_OprFact::intConst(x);

  } else {

    ShouldNotReachHere();

  }

  if (!Assembler::is_simm16(x)) {

    LIR_Opr tmp = new_register(type);

    __ move(r, tmp);

    return tmp;

  }

  return r;

}

void LIRGenerator::increment_counter(address counter, BasicType type, int step) {

  LIR_Opr pointer = new_pointer_register();

  __ move(LIR_OprFact::intptrConst(counter), pointer);

  LIR_Address* addr = new LIR_Address(pointer, type);

  increment_counter(addr, step);

}

void LIRGenerator::increment_counter(LIR_Address* addr, int step) {

  LIR_Opr temp = new_register(addr->type());

  __ move(addr, temp);

  __ add(temp, load_immediate(step, addr->type()), temp);

  __ move(temp, addr);

}

void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {

  LIR_Opr tmp = FrameMap::R0_opr;

  __ load(new LIR_Address(base, disp, T_INT), tmp, info);

  __ cmp(condition, tmp, c);

}

void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base,

                               int disp, BasicType type, CodeEmitInfo* info) {

  LIR_Opr tmp = FrameMap::R0_opr;

  __ load(new LIR_Address(base, disp, type), tmp, info);

  __ cmp(condition, reg, tmp);

}

bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {

  assert(left != result, "should be different registers");

  if (is_power_of_2(c + 1)) {

    __ shift_left(left, log2_intptr(c + 1), result);

    __ sub(result, left, result);

    return true;

  } else if (is_power_of_2(c - 1)) {

    __ shift_left(left, log2_intptr(c - 1), result);

    __ add(result, left, result);

    return true;

  }

  return false;

}

void LIRGenerator::store_stack_parameter(LIR_Opr item, ByteSize offset_from_sp) {

  BasicType t = item->type();

  LIR_Opr sp_opr = FrameMap::SP_opr;

  if ((t == T_LONG || t == T_DOUBLE) &&

      ((in_bytes(offset_from_sp) - STACK_BIAS) % 8 != 0)) {

    __ unaligned_move(item, new LIR_Address(sp_opr, in_bytes(offset_from_sp), t));

  } else {

    __ move(item, new LIR_Address(sp_opr, in_bytes(offset_from_sp), t));

  }

}

//----------------------------------------------------------------------

//             visitor functions

//----------------------------------------------------------------------

}

void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.load_item();

  set_no_result(x);

  // We use R4+R5 in order to get a temp effect. These regs are used in slow path (MonitorEnterStub).

  LIR_Opr lock    = FrameMap::R5_opr;

  LIR_Opr scratch = FrameMap::R4_opr;

  LIR_Opr hdr     = FrameMap::R6_opr;

  CodeEmitInfo* info_for_exception = NULL;

  if (x->needs_null_check()) {

    info_for_exception = state_for(x);

  }

  // This CodeEmitInfo must not have the xhandlers because here the

  // object is already locked (xhandlers expects object to be unlocked).

  CodeEmitInfo* info = state_for(x, x->state(), true);

  monitor_enter(obj.result(), lock, hdr, scratch, x->monitor_no(), info_for_exception, info);

}

void LIRGenerator::do_MonitorExit(MonitorExit* x) {

  assert(x->is_pinned(),"");

  LIRItem obj(x->obj(), this);

  obj.dont_load_item();

  set_no_result(x);

  LIR_Opr lock     = FrameMap::R5_opr;

  LIR_Opr hdr      = FrameMap::R4_opr; // Used for slow path (MonitorExitStub).

  LIR_Opr obj_temp = FrameMap::R6_opr;

  monitor_exit(obj_temp, lock, hdr, LIR_OprFact::illegalOpr, x->monitor_no());

}

// _ineg, _lneg, _fneg, _dneg

void LIRGenerator::do_NegateOp(NegateOp* x) {

  LIRItem value(x->x(), this);

  value.load_item();

  LIR_Opr reg = rlock_result(x);

  __ negate(value.result(), reg);

}

// for  _fadd, _fmul, _fsub, _fdiv, _frem

//      _dadd, _dmul, _dsub, _ddiv, _drem

void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {

  switch (x->op()) {

  case Bytecodes::_fadd:

  case Bytecodes::_fmul:

  case Bytecodes::_fsub:

  case Bytecodes::_fdiv:

  case Bytecodes::_dadd:

  case Bytecodes::_dmul:

  case Bytecodes::_dsub:

  case Bytecodes::_ddiv: {

    LIRItem left(x->x(), this);

    LIRItem right(x->y(), this);

    left.load_item();

    right.load_item();

    rlock_result(x);

    arithmetic_op_fpu(x->op(), x->operand(), left.result(), right.result(), x->is_strictfp());

  }

  break;

  case Bytecodes::_frem:

  case Bytecodes::_drem: {

    address entry = NULL;

    switch (x->op()) {

    case Bytecodes::_frem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::frem);

      break;

    case Bytecodes::_drem:

      entry = CAST_FROM_FN_PTR(address, SharedRuntime::drem);

      break;

    default:

      ShouldNotReachHere();

    }

    LIR_Opr result = call_runtime(x->x(), x->y(), entry, x->type(), NULL);

    set_result(x, result);

  }

  break;

  default: ShouldNotReachHere();

  }

}

// for  _ladd, _lmul, _lsub, _ldiv, _lrem

void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {

  bool is_div_rem = x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem;

  LIRItem right(x->y(), this);

  // Missing test if instr is commutative and if we should swap.

  if (right.value()->type()->as_LongConstant() &&

      (x->op() == Bytecodes::_lsub && right.value()->type()->as_LongConstant()->value() == ((-1)<<15)) ) {

    // Sub is implemented by addi and can't support min_simm16 as constant..

    right.load_item();

  } else {

    right.load_nonconstant();

  }

  assert(right.is_constant() || right.is_register(), "wrong state of right");

  if (is_div_rem) {

    LIR_Opr divisor = right.result();

    if (divisor->is_register()) {

      CodeEmitInfo* null_check_info = state_for(x);

      __ cmp(lir_cond_equal, divisor, LIR_OprFact::longConst(0));

      __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(null_check_info));

    } else {

      jlong const_divisor = divisor->as_constant_ptr()->as_jlong();

      if (const_divisor == 0) {

        CodeEmitInfo* null_check_info = state_for(x);

        __ jump(new DivByZeroStub(null_check_info));

        rlock_result(x);

        __ move(LIR_OprFact::longConst(0), x->operand()); // dummy

        return;

      }

      if (x->op() == Bytecodes::_lrem && !is_power_of_2(const_divisor) && const_divisor != -1) {

        // Remainder computation would need additional tmp != R0.

        right.load_item();

      }

    }

  }

  LIRItem left(x->x(), this);

  left.load_item();

  rlock_result(x);

  if (is_div_rem) {

    CodeEmitInfo* info = NULL; // Null check already done above.

    LIR_Opr tmp = FrameMap::R0_opr;

    if (x->op() == Bytecodes::_lrem) {

      __ irem(left.result(), right.result(), x->operand(), tmp, info);

    } else if (x->op() == Bytecodes::_ldiv) {

      __ idiv(left.result(), right.result(), x->operand(), tmp, info);

    }

  } else {

    arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);

  }

}

// for: _iadd, _imul, _isub, _idiv, _irem

void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {

  bool is_div_rem = x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem;

  LIRItem right(x->y(), this);

  // Missing test if instr is commutative and if we should swap.

  if (right.value()->type()->as_IntConstant() &&

      (x->op() == Bytecodes::_isub && right.value()->type()->as_IntConstant()->value() == ((-1)<<15)) ) {

    // Sub is implemented by addi and can't support min_simm16 as constant.

    right.load_item();

  } else {

    right.load_nonconstant();

  }

  assert(right.is_constant() || right.is_register(), "wrong state of right");

  if (is_div_rem) {

    LIR_Opr divisor = right.result();

    if (divisor->is_register()) {

      CodeEmitInfo* null_check_info = state_for(x);

      __ cmp(lir_cond_equal, divisor, LIR_OprFact::intConst(0));

      __ branch(lir_cond_equal, T_INT, new DivByZeroStub(null_check_info));

    } else {

      jint const_divisor = divisor->as_constant_ptr()->as_jint();

      if (const_divisor == 0) {

        CodeEmitInfo* null_check_info = state_for(x);

        __ jump(new DivByZeroStub(null_check_info));

        rlock_result(x);

        __ move(LIR_OprFact::intConst(0), x->operand()); // dummy

        return;

      }

      if (x->op() == Bytecodes::_irem && !is_power_of_2(const_divisor) && const_divisor != -1) {

        // Remainder computation would need additional tmp != R0.

        right.load_item();

      }

    }

  }

  LIRItem left(x->x(), this);

  left.load_item();

  rlock_result(x);

  if (is_div_rem) {

    CodeEmitInfo* info = NULL; // Null check already done above.

    LIR_Opr tmp = FrameMap::R0_opr;

    if (x->op() == Bytecodes::_irem) {

      __ irem(left.result(), right.result(), x->operand(), tmp, info);

    } else if (x->op() == Bytecodes::_idiv) {

      __ idiv(left.result(), right.result(), x->operand(), tmp, info);

    }

  } else {

    arithmetic_op_int(x->op(), x->operand(), left.result(), right.result(), FrameMap::R0_opr);