147 assert(base->is_register(), "must be"); |
147 assert(base->is_register(), "must be"); |
148 intx large_disp = disp; |
148 intx large_disp = disp; |
149 |
149 |
150 // Accumulate fixed displacements. |
150 // Accumulate fixed displacements. |
151 if (index->is_constant()) { |
151 if (index->is_constant()) { |
152 large_disp += (intx)(index->as_constant_ptr()->as_jint()) << shift; |
152 LIR_Const *constant = index->as_constant_ptr(); |
|
153 if (constant->type() == T_LONG) { |
|
154 large_disp += constant->as_jlong() << shift; |
|
155 } else { |
|
156 large_disp += (intx)(constant->as_jint()) << shift; |
|
157 } |
153 index = LIR_OprFact::illegalOpr; |
158 index = LIR_OprFact::illegalOpr; |
154 } |
159 } |
155 |
160 |
156 if (index->is_register()) { |
161 if (index->is_register()) { |
157 // Apply the shift and accumulate the displacement. |
162 // Apply the shift and accumulate the displacement. |
318 |
317 |
319 //---------------------------------------------------------------------- |
318 //---------------------------------------------------------------------- |
320 // visitor functions |
319 // visitor functions |
321 //---------------------------------------------------------------------- |
320 //---------------------------------------------------------------------- |
322 |
321 |
323 void LIRGenerator::do_StoreIndexed(StoreIndexed* x) { |
322 void LIRGenerator::array_store_check(LIR_Opr value, LIR_Opr array, CodeEmitInfo* store_check_info, ciMethod* profiled_method, int profiled_bci) { |
324 assert(x->is_pinned(),""); |
323 // Following registers are used by slow_subtype_check: |
325 bool needs_range_check = x->compute_needs_range_check(); |
324 LIR_Opr tmp1 = FrameMap::R4_opr; // super_klass |
326 bool use_length = x->length() != NULL; |
325 LIR_Opr tmp2 = FrameMap::R5_opr; // sub_klass |
327 bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT; |
326 LIR_Opr tmp3 = FrameMap::R6_opr; // temp |
328 bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL || |
327 __ store_check(value, array, tmp1, tmp2, tmp3, store_check_info, profiled_method, profiled_bci); |
329 !get_jobject_constant(x->value())->is_null_object() || |
|
330 x->should_profile()); |
|
331 |
|
332 LIRItem array(x->array(), this); |
|
333 LIRItem index(x->index(), this); |
|
334 LIRItem value(x->value(), this); |
|
335 LIRItem length(this); |
|
336 |
|
337 array.load_item(); |
|
338 index.load_nonconstant(); |
|
339 |
|
340 if (use_length && needs_range_check) { |
|
341 length.set_instruction(x->length()); |
|
342 length.load_item(); |
|
343 } |
|
344 if (needs_store_check || x->check_boolean()) { |
|
345 value.load_item(); |
|
346 } else { |
|
347 value.load_for_store(x->elt_type()); |
|
348 } |
|
349 |
|
350 set_no_result(x); |
|
351 |
|
352 // The CodeEmitInfo must be duplicated for each different |
|
353 // LIR-instruction because spilling can occur anywhere between two |
|
354 // instructions and so the debug information must be different. |
|
355 CodeEmitInfo* range_check_info = state_for(x); |
|
356 CodeEmitInfo* null_check_info = NULL; |
|
357 if (x->needs_null_check()) { |
|
358 null_check_info = new CodeEmitInfo(range_check_info); |
|
359 } |
|
360 |
|
361 // Emit array address setup early so it schedules better. |
|
362 LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store); |
|
363 |
|
364 if (GenerateRangeChecks && needs_range_check) { |
|
365 if (use_length) { |
|
366 __ cmp(lir_cond_belowEqual, length.result(), index.result()); |
|
367 __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result())); |
|
368 } else { |
|
369 array_range_check(array.result(), index.result(), null_check_info, range_check_info); |
|
370 // Range_check also does the null check. |
|
371 null_check_info = NULL; |
|
372 } |
|
373 } |
|
374 |
|
375 if (GenerateArrayStoreCheck && needs_store_check) { |
|
376 // Following registers are used by slow_subtype_check: |
|
377 LIR_Opr tmp1 = FrameMap::R4_opr; // super_klass |
|
378 LIR_Opr tmp2 = FrameMap::R5_opr; // sub_klass |
|
379 LIR_Opr tmp3 = FrameMap::R6_opr; // temp |
|
380 |
|
381 CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info); |
|
382 __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, |
|
383 store_check_info, x->profiled_method(), x->profiled_bci()); |
|
384 } |
|
385 |
|
386 if (obj_store) { |
|
387 // Needs GC write barriers. |
|
388 pre_barrier(LIR_OprFact::address(array_addr), LIR_OprFact::illegalOpr /* pre_val */, |
|
389 true /* do_load */, false /* patch */, NULL); |
|
390 } |
|
391 LIR_Opr result = maybe_mask_boolean(x, array.result(), value.result(), null_check_info); |
|
392 __ move(result, array_addr, null_check_info); |
|
393 if (obj_store) { |
|
394 // Precise card mark. |
|
395 post_barrier(LIR_OprFact::address(array_addr), value.result()); |
|
396 } |
|
397 } |
328 } |
398 |
329 |
399 |
330 |
400 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) { |
331 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) { |
401 assert(x->is_pinned(),""); |
332 assert(x->is_pinned(),""); |
700 Unimplemented(); |
631 Unimplemented(); |
701 } |
632 } |
702 } |
633 } |
703 |
634 |
704 |
635 |
705 void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) { |
636 LIR_Opr LIRGenerator::atomic_cmpxchg(BasicType type, LIR_Opr addr, LIRItem& cmp_value, LIRItem& new_value) { |
706 assert(x->number_of_arguments() == 4, "wrong type"); |
637 LIR_Opr result = new_register(T_INT); |
707 LIRItem obj (x->argument_at(0), this); // object |
|
708 LIRItem offset(x->argument_at(1), this); // offset of field |
|
709 LIRItem cmp (x->argument_at(2), this); // Value to compare with field. |
|
710 LIRItem val (x->argument_at(3), this); // Replace field with val if matches cmp. |
|
711 |
|
712 LIR_Opr t1 = LIR_OprFact::illegalOpr; |
638 LIR_Opr t1 = LIR_OprFact::illegalOpr; |
713 LIR_Opr t2 = LIR_OprFact::illegalOpr; |
639 LIR_Opr t2 = LIR_OprFact::illegalOpr; |
714 LIR_Opr addr = new_pointer_register(); |
640 cmp_value.load_item(); |
715 |
641 new_value.load_item(); |
716 // Get address of field. |
642 |
717 obj.load_item(); |
643 // Volatile load may be followed by Unsafe CAS. |
718 offset.load_item(); |
644 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
719 cmp.load_item(); |
645 __ membar(); |
720 val.load_item(); |
646 } else { |
721 |
647 __ membar_release(); |
722 __ add(obj.result(), offset.result(), addr); |
648 } |
|
649 |
|
650 if (type == T_OBJECT || type == T_ARRAY) { |
|
651 if (UseCompressedOops) { |
|
652 t1 = new_register(T_OBJECT); |
|
653 t2 = new_register(T_OBJECT); |
|
654 } |
|
655 __ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), t1, t2); |
|
656 } else if (type == T_INT) { |
|
657 __ cas_int(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), t1, t2); |
|
658 } else if (type == T_LONG) { |
|
659 __ cas_long(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), t1, t2); |
|
660 } else { |
|
661 Unimplemented(); |
|
662 } |
|
663 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), |
|
664 result, type); |
|
665 return result; |
|
666 } |
|
667 |
|
668 |
|
669 LIR_Opr LIRGenerator::atomic_xchg(BasicType type, LIR_Opr addr, LIRItem& value) { |
|
670 LIR_Opr result = new_register(type); |
|
671 LIR_Opr tmp = FrameMap::R0_opr; |
|
672 |
|
673 value.load_item(); |
|
674 |
|
675 // Volatile load may be followed by Unsafe CAS. |
|
676 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
|
677 __ membar(); |
|
678 } else { |
|
679 __ membar_release(); |
|
680 } |
|
681 |
|
682 __ xchg(addr, value.result(), result, tmp); |
|
683 |
|
684 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
|
685 __ membar_acquire(); |
|
686 } else { |
|
687 __ membar(); |
|
688 } |
|
689 return result; |
|
690 } |
|
691 |
|
692 |
|
693 LIR_Opr LIRGenerator::atomic_add(BasicType type, LIR_Opr addr, LIRItem& value) { |
|
694 LIR_Opr result = new_register(type); |
|
695 LIR_Opr tmp = FrameMap::R0_opr; |
|
696 |
|
697 value.load_item(); |
723 |
698 |
724 // Volatile load may be followed by Unsafe CAS. |
699 // Volatile load may be followed by Unsafe CAS. |
725 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
700 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
726 __ membar(); // To be safe. Unsafe semantics are unclear. |
701 __ membar(); // To be safe. Unsafe semantics are unclear. |
727 } else { |
702 } else { |
728 __ membar_release(); |
703 __ membar_release(); |
729 } |
704 } |
730 |
705 |
731 if (type == objectType) { // Write-barrier needed for Object fields. |
706 __ xadd(addr, value.result(), result, tmp); |
732 // Only cmp value can get overwritten, no do_load required. |
707 |
733 pre_barrier(LIR_OprFact::illegalOpr /* addr */, cmp.result() /* pre_val */, |
708 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
734 false /* do_load */, false /* patch */, NULL); |
709 __ membar_acquire(); |
735 } |
710 } else { |
736 |
711 __ membar(); |
737 if (type == objectType) { |
712 } |
738 if (UseCompressedOops) { |
713 return result; |
739 t1 = new_register(T_OBJECT); |
|
740 t2 = new_register(T_OBJECT); |
|
741 } |
|
742 __ cas_obj(addr, cmp.result(), val.result(), t1, t2); |
|
743 } else if (type == intType) { |
|
744 __ cas_int(addr, cmp.result(), val.result(), t1, t2); |
|
745 } else if (type == longType) { |
|
746 __ cas_long(addr, cmp.result(), val.result(), t1, t2); |
|
747 } else { |
|
748 ShouldNotReachHere(); |
|
749 } |
|
750 // Benerate conditional move of boolean result. |
|
751 LIR_Opr result = rlock_result(x); |
|
752 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), |
|
753 result, as_BasicType(type)); |
|
754 if (type == objectType) { // Write-barrier needed for Object fields. |
|
755 // Precise card mark since could either be object or array. |
|
756 post_barrier(addr, val.result()); |
|
757 } |
|
758 } |
714 } |
759 |
715 |
760 |
716 |
761 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) { |
717 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) { |
762 switch (x->id()) { |
718 switch (x->id()) { |
1253 // __ volatile_load_mem_reg(address, result, info); |
1209 // __ volatile_load_mem_reg(address, result, info); |
1254 #endif |
1210 #endif |
1255 } |
1211 } |
1256 |
1212 |
1257 |
1213 |
1258 void LIRGenerator::put_Object_unsafe(LIR_Opr src, LIR_Opr offset, LIR_Opr data, |
|
1259 BasicType type, bool is_volatile) { |
|
1260 LIR_Opr base_op = src; |
|
1261 LIR_Opr index_op = offset; |
|
1262 |
|
1263 bool is_obj = (type == T_ARRAY || type == T_OBJECT); |
|
1264 #ifndef _LP64 |
|
1265 if (is_volatile && type == T_LONG) { |
|
1266 __ volatile_store_unsafe_reg(data, src, offset, type, NULL, lir_patch_none); |
|
1267 } else |
|
1268 #endif |
|
1269 { |
|
1270 if (type == T_BOOLEAN) { |
|
1271 type = T_BYTE; |
|
1272 } |
|
1273 LIR_Address* addr; |
|
1274 if (type == T_ARRAY || type == T_OBJECT) { |
|
1275 LIR_Opr tmp = new_pointer_register(); |
|
1276 __ add(base_op, index_op, tmp); |
|
1277 addr = new LIR_Address(tmp, type); |
|
1278 } else { |
|
1279 addr = new LIR_Address(base_op, index_op, type); |
|
1280 } |
|
1281 |
|
1282 if (is_obj) { |
|
1283 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */, |
|
1284 true /* do_load */, false /* patch */, NULL); |
|
1285 // _bs->c1_write_barrier_pre(this, LIR_OprFact::address(addr)); |
|
1286 } |
|
1287 __ move(data, addr); |
|
1288 if (is_obj) { |
|
1289 // This address is precise. |
|
1290 post_barrier(LIR_OprFact::address(addr), data); |
|
1291 } |
|
1292 } |
|
1293 } |
|
1294 |
|
1295 |
|
1296 void LIRGenerator::get_Object_unsafe(LIR_Opr dst, LIR_Opr src, LIR_Opr offset, |
|
1297 BasicType type, bool is_volatile) { |
|
1298 #ifndef _LP64 |
|
1299 if (is_volatile && type == T_LONG) { |
|
1300 __ volatile_load_unsafe_reg(src, offset, dst, type, NULL, lir_patch_none); |
|
1301 } else |
|
1302 #endif |
|
1303 { |
|
1304 LIR_Address* addr = new LIR_Address(src, offset, type); |
|
1305 __ load(addr, dst); |
|
1306 } |
|
1307 } |
|
1308 |
|
1309 |
|
1310 void LIRGenerator::do_UnsafeGetAndSetObject(UnsafeGetAndSetObject* x) { |
|
1311 BasicType type = x->basic_type(); |
|
1312 LIRItem src(x->object(), this); |
|
1313 LIRItem off(x->offset(), this); |
|
1314 LIRItem value(x->value(), this); |
|
1315 |
|
1316 src.load_item(); |
|
1317 value.load_item(); |
|
1318 off.load_nonconstant(); |
|
1319 |
|
1320 LIR_Opr dst = rlock_result(x, type); |
|
1321 LIR_Opr data = value.result(); |
|
1322 bool is_obj = (type == T_ARRAY || type == T_OBJECT); |
|
1323 |
|
1324 LIR_Opr tmp = FrameMap::R0_opr; |
|
1325 LIR_Opr ptr = new_pointer_register(); |
|
1326 __ add(src.result(), off.result(), ptr); |
|
1327 |
|
1328 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
|
1329 __ membar(); |
|
1330 } else { |
|
1331 __ membar_release(); |
|
1332 } |
|
1333 |
|
1334 if (x->is_add()) { |
|
1335 __ xadd(ptr, data, dst, tmp); |
|
1336 } else { |
|
1337 const bool can_move_barrier = true; // TODO: port GraphKit::can_move_pre_barrier() from C2 |
|
1338 if (!can_move_barrier && is_obj) { |
|
1339 // Do the pre-write barrier, if any. |
|
1340 pre_barrier(ptr, LIR_OprFact::illegalOpr /* pre_val */, |
|
1341 true /* do_load */, false /* patch */, NULL); |
|
1342 } |
|
1343 __ xchg(ptr, data, dst, tmp); |
|
1344 if (is_obj) { |
|
1345 // Seems to be a precise address. |
|
1346 post_barrier(ptr, data); |
|
1347 if (can_move_barrier) { |
|
1348 pre_barrier(LIR_OprFact::illegalOpr, dst /* pre_val */, |
|
1349 false /* do_load */, false /* patch */, NULL); |
|
1350 } |
|
1351 } |
|
1352 } |
|
1353 |
|
1354 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
|
1355 __ membar_acquire(); |
|
1356 } else { |
|
1357 __ membar(); |
|
1358 } |
|
1359 } |
|
1360 |
|
1361 |
|
1362 void LIRGenerator::do_update_CRC32(Intrinsic* x) { |
1214 void LIRGenerator::do_update_CRC32(Intrinsic* x) { |
1363 assert(UseCRC32Intrinsics, "or should not be here"); |
1215 assert(UseCRC32Intrinsics, "or should not be here"); |
1364 LIR_Opr result = rlock_result(x); |
1216 LIR_Opr result = rlock_result(x); |
1365 |
1217 |
1366 switch (x->id()) { |
1218 switch (x->id()) { |