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/*
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* Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.lir.aarch64;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.aarch64.AArch64ArithmeticOp.ARMv8ConstantCategory.ARITHMETIC;
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import static org.graalvm.compiler.lir.aarch64.AArch64ArithmeticOp.ARMv8ConstantCategory.LOGICAL;
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import static org.graalvm.compiler.lir.aarch64.AArch64ArithmeticOp.ARMv8ConstantCategory.NONE;
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import static org.graalvm.compiler.lir.aarch64.AArch64ArithmeticOp.ARMv8ConstantCategory.SHIFT;
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import static jdk.vm.ci.aarch64.AArch64.zr;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import org.graalvm.compiler.asm.aarch64.AArch64Assembler;
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import org.graalvm.compiler.asm.aarch64.AArch64Assembler.ConditionFlag;
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import org.graalvm.compiler.debug.GraalError;
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import org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.Opcode;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.meta.AllocatableValue;
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import jdk.vm.ci.meta.JavaConstant;
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public enum AArch64ArithmeticOp {
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// TODO At least add and sub *can* be used with SP, so this should be supported
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NEG,
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NOT,
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ADD(ARITHMETIC),
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ADDS(ARITHMETIC),
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SUB(ARITHMETIC),
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SUBS(ARITHMETIC),
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MUL,
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MULVS,
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MNEG,
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DIV,
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SMULH,
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UMULH,
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REM,
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UDIV,
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UREM,
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AND(LOGICAL),
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ANDS(LOGICAL),
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OR(LOGICAL),
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XOR(LOGICAL),
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SHL(SHIFT),
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LSHR(SHIFT),
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ASHR(SHIFT),
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ABS,
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FADD,
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FSUB,
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FMUL,
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FDIV,
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FREM,
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FNEG,
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FABS,
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FRINTM,
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FRINTN,
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FRINTP,
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SQRT;
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/**
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* Specifies what constants can be used directly without having to be loaded into a register
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* with the given instruction.
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*/
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public enum ARMv8ConstantCategory {
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NONE,
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LOGICAL,
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ARITHMETIC,
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SHIFT
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}
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public final ARMv8ConstantCategory category;
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AArch64ArithmeticOp(ARMv8ConstantCategory category) {
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this.category = category;
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}
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AArch64ArithmeticOp() {
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this(NONE);
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}
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public static class UnaryOp extends AArch64LIRInstruction {
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private static final LIRInstructionClass<UnaryOp> TYPE = LIRInstructionClass.create(UnaryOp.class);
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@Opcode private final AArch64ArithmeticOp opcode;
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue x;
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public UnaryOp(AArch64ArithmeticOp opcode, AllocatableValue result, AllocatableValue x) {
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super(TYPE);
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this.opcode = opcode;
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this.result = result;
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this.x = x;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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Register dst = asRegister(result);
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Register src = asRegister(x);
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int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
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switch (opcode) {
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case NEG:
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masm.sub(size, dst, zr, src);
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break;
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case FNEG:
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masm.fneg(size, dst, src);
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break;
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case NOT:
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masm.not(size, dst, src);
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break;
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case ABS:
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masm.cmp(size, src, 0);
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masm.csneg(size, dst, src, ConditionFlag.LT);
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break;
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case FABS:
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masm.fabs(size, dst, src);
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break;
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case FRINTM:
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masm.frintm(size, dst, src);
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break;
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case FRINTN:
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masm.frintn(size, dst, src);
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break;
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case FRINTP:
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masm.frintp(size, dst, src);
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break;
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case SQRT:
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masm.fsqrt(size, dst, src);
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break;
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default:
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throw GraalError.shouldNotReachHere("op=" + opcode.name());
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}
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}
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}
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public static class BinaryConstOp extends AArch64LIRInstruction {
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private static final LIRInstructionClass<BinaryConstOp> TYPE = LIRInstructionClass.create(BinaryConstOp.class);
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@Opcode private final AArch64ArithmeticOp op;
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue a;
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private final JavaConstant b;
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public BinaryConstOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue a, JavaConstant b) {
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super(TYPE);
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this.op = op;
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this.result = result;
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this.a = a;
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this.b = b;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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assert op.category != NONE;
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Register dst = asRegister(result);
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Register src = asRegister(a);
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int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
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switch (op) {
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case ADD:
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// Don't use asInt() here, since we can't use asInt on a long variable, even
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// if the constant easily fits as an int.
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assert AArch64MacroAssembler.isArithmeticImmediate(b.asLong());
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masm.add(size, dst, src, (int) b.asLong());
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break;
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case SUB:
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// Don't use asInt() here, since we can't use asInt on a long variable, even
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// if the constant easily fits as an int.
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assert AArch64MacroAssembler.isArithmeticImmediate(b.asLong());
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masm.sub(size, dst, src, (int) b.asLong());
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break;
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case ADDS:
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assert AArch64MacroAssembler.isArithmeticImmediate(b.asLong());
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masm.adds(size, dst, src, (int) b.asLong());
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break;
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case SUBS:
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assert AArch64MacroAssembler.isArithmeticImmediate(b.asLong());
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masm.subs(size, dst, src, (int) b.asLong());
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break;
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case AND:
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// XXX Should this be handled somewhere else?
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if (size == 32 && b.asLong() == 0xFFFF_FFFFL) {
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masm.mov(size, dst, src);
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} else {
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masm.and(size, dst, src, b.asLong());
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}
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break;
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case ANDS:
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masm.ands(size, dst, src, b.asLong());
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break;
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case OR:
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masm.or(size, dst, src, b.asLong());
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break;
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case XOR:
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masm.eor(size, dst, src, b.asLong());
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break;
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case SHL:
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masm.shl(size, dst, src, b.asLong());
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break;
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case LSHR:
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masm.lshr(size, dst, src, b.asLong());
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break;
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case ASHR:
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masm.ashr(size, dst, src, b.asLong());
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break;
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default:
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throw GraalError.shouldNotReachHere("op=" + op.name());
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}
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}
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}
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public static class BinaryOp extends AArch64LIRInstruction {
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private static final LIRInstructionClass<BinaryOp> TYPE = LIRInstructionClass.create(BinaryOp.class);
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@Opcode private final AArch64ArithmeticOp op;
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@Def({REG}) protected AllocatableValue result;
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@Use({REG}) protected AllocatableValue a;
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@Use({REG}) protected AllocatableValue b;
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public BinaryOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue a, AllocatableValue b) {
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super(TYPE);
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this.op = op;
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this.result = result;
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this.a = a;
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this.b = b;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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Register dst = asRegister(result);
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Register src1 = asRegister(a);
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Register src2 = asRegister(b);
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int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
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switch (op) {
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case ADD:
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masm.add(size, dst, src1, src2);
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break;
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case ADDS:
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masm.adds(size, dst, src1, src2);
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break;
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case SUB:
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masm.sub(size, dst, src1, src2);
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break;
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case SUBS:
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masm.subs(size, dst, src1, src2);
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break;
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case MUL:
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masm.mul(size, dst, src1, src2);
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break;
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case UMULH:
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masm.umulh(size, dst, src1, src2);
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break;
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case SMULH:
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masm.smulh(size, dst, src1, src2);
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break;
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case MNEG:
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masm.mneg(size, dst, src1, src2);
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break;
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case DIV:
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masm.sdiv(size, dst, src1, src2);
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break;
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case UDIV:
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masm.udiv(size, dst, src1, src2);
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break;
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case AND:
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masm.and(size, dst, src1, src2);
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break;
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case ANDS:
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masm.ands(size, dst, src1, src2);
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break;
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case OR:
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masm.or(size, dst, src1, src2);
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break;
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case XOR:
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masm.eor(size, dst, src1, src2);
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break;
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case SHL:
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masm.shl(size, dst, src1, src2);
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break;
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case LSHR:
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masm.lshr(size, dst, src1, src2);
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break;
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case ASHR:
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masm.ashr(size, dst, src1, src2);
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break;
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case FADD:
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masm.fadd(size, dst, src1, src2);
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break;
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case FSUB:
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masm.fsub(size, dst, src1, src2);
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break;
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case FMUL:
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masm.fmul(size, dst, src1, src2);
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break;
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case FDIV:
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masm.fdiv(size, dst, src1, src2);
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break;
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case MULVS:
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masm.mulvs(size, dst, src1, src2);
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break;
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default:
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throw GraalError.shouldNotReachHere("op=" + op.name());
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}
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}
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}
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/**
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* Class used for instructions that have to reuse one of their arguments. This only applies to
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* the remainder instructions at the moment, since we have to compute n % d using rem = n -
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* TruncatingDivision(n, d) * d
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*
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* TODO (das) Replace the remainder nodes in the LIR.
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*/
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public static class BinaryCompositeOp extends AArch64LIRInstruction {
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private static final LIRInstructionClass<BinaryCompositeOp> TYPE = LIRInstructionClass.create(BinaryCompositeOp.class);
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@Opcode private final AArch64ArithmeticOp op;
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@Def({REG}) protected AllocatableValue result;
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@Alive({REG}) protected AllocatableValue a;
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@Alive({REG}) protected AllocatableValue b;
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public BinaryCompositeOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue a, AllocatableValue b) {
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super(TYPE);
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this.op = op;
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this.result = result;
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this.a = a;
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this.b = b;
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}
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@Override
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public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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Register dst = asRegister(result);
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Register src1 = asRegister(a);
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Register src2 = asRegister(b);
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int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
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switch (op) {
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case REM:
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masm.rem(size, dst, src1, src2);
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break;
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case UREM:
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masm.urem(size, dst, src1, src2);
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break;
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case FREM:
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masm.frem(size, dst, src1, src2);
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break;
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default:
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throw GraalError.shouldNotReachHere();
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}
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}
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}
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public static class BinaryShiftOp extends AArch64LIRInstruction {
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private static final LIRInstructionClass<BinaryShiftOp> TYPE = LIRInstructionClass.create(BinaryShiftOp.class);
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@Opcode private final AArch64ArithmeticOp op;
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@Def(REG) protected AllocatableValue result;
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@Use(REG) protected AllocatableValue src1;
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@Use(REG) protected AllocatableValue src2;
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private final AArch64MacroAssembler.ShiftType shiftType;
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private final int shiftAmt;
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52910
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private final boolean isShiftNot;
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43972
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/**
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52910
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* If shiftNot: Computes <code>result = src1 <op> ~(src2 <shiftType> <shiftAmt>)</code>
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* (Only for logic ops). else: Computes
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* <code>result = src1 <op> src2 <shiftType> <shiftAmt></code>.
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43972
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*/
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52910
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public BinaryShiftOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2,
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AArch64MacroAssembler.ShiftType shiftType, int shiftAmt, boolean isShiftNot) {
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43972
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super(TYPE);
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52910
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assert op == ADD || op == SUB || op == AND || op == OR || op == XOR;
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43972
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this.op = op;
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|
395 |
this.result = result;
|
|
396 |
this.src1 = src1;
|
|
397 |
this.src2 = src2;
|
|
398 |
this.shiftType = shiftType;
|
|
399 |
this.shiftAmt = shiftAmt;
|
52910
|
400 |
this.isShiftNot = isShiftNot;
|
43972
|
401 |
}
|
|
402 |
|
|
403 |
@Override
|
|
404 |
public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
|
|
405 |
int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
|
|
406 |
switch (op) {
|
|
407 |
case ADD:
|
|
408 |
masm.add(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
409 |
break;
|
|
410 |
case SUB:
|
|
411 |
masm.sub(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
412 |
break;
|
52910
|
413 |
case AND:
|
|
414 |
if (!isShiftNot) {
|
|
415 |
masm.and(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
416 |
} else {
|
|
417 |
masm.bic(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
418 |
}
|
|
419 |
break;
|
|
420 |
case OR:
|
|
421 |
if (!isShiftNot) {
|
|
422 |
masm.or(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
423 |
} else {
|
|
424 |
masm.orn(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
425 |
}
|
|
426 |
break;
|
|
427 |
case XOR:
|
|
428 |
if (!isShiftNot) {
|
|
429 |
masm.eor(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
430 |
} else {
|
|
431 |
masm.eon(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
|
|
432 |
}
|
|
433 |
break;
|
43972
|
434 |
default:
|
|
435 |
throw GraalError.shouldNotReachHere();
|
|
436 |
}
|
|
437 |
}
|
|
438 |
}
|
|
439 |
|
|
440 |
public static class ExtendedAddShiftOp extends AArch64LIRInstruction {
|
|
441 |
private static final LIRInstructionClass<ExtendedAddShiftOp> TYPE = LIRInstructionClass.create(ExtendedAddShiftOp.class);
|
|
442 |
@Def(REG) protected AllocatableValue result;
|
|
443 |
@Use(REG) protected AllocatableValue src1;
|
|
444 |
@Use(REG) protected AllocatableValue src2;
|
|
445 |
private final AArch64Assembler.ExtendType extendType;
|
|
446 |
private final int shiftAmt;
|
|
447 |
|
|
448 |
/**
|
|
449 |
* Computes <code>result = src1 + extendType(src2) << shiftAmt</code>.
|
|
450 |
*
|
|
451 |
* @param extendType defines how src2 is extended to the same size as src1.
|
|
452 |
* @param shiftAmt must be in range 0 to 4.
|
|
453 |
*/
|
|
454 |
public ExtendedAddShiftOp(AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AArch64Assembler.ExtendType extendType, int shiftAmt) {
|
|
455 |
super(TYPE);
|
|
456 |
this.result = result;
|
|
457 |
this.src1 = src1;
|
|
458 |
this.src2 = src2;
|
|
459 |
this.extendType = extendType;
|
|
460 |
this.shiftAmt = shiftAmt;
|
|
461 |
}
|
|
462 |
|
|
463 |
@Override
|
|
464 |
public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
|
|
465 |
int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
|
|
466 |
masm.add(size, asRegister(result), asRegister(src1), asRegister(src2), extendType, shiftAmt);
|
|
467 |
}
|
|
468 |
}
|
|
469 |
|
52910
|
470 |
public static class MultiplyAddSubOp extends AArch64LIRInstruction {
|
|
471 |
private static final LIRInstructionClass<MultiplyAddSubOp> TYPE = LIRInstructionClass.create(MultiplyAddSubOp.class);
|
|
472 |
|
|
473 |
@Opcode private final AArch64ArithmeticOp op;
|
|
474 |
@Def(REG) protected AllocatableValue result;
|
|
475 |
@Use(REG) protected AllocatableValue src1;
|
|
476 |
@Use(REG) protected AllocatableValue src2;
|
|
477 |
@Use(REG) protected AllocatableValue src3;
|
|
478 |
|
|
479 |
/**
|
|
480 |
* Computes <code>result = src3 <op> src1 * src2</code>.
|
|
481 |
*/
|
|
482 |
public MultiplyAddSubOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AllocatableValue src3) {
|
|
483 |
super(TYPE);
|
58533
|
484 |
assert op == ADD || op == SUB || op == FADD;
|
52910
|
485 |
this.op = op;
|
|
486 |
this.result = result;
|
|
487 |
this.src1 = src1;
|
|
488 |
this.src2 = src2;
|
|
489 |
this.src3 = src3;
|
|
490 |
}
|
|
491 |
|
|
492 |
@Override
|
|
493 |
public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
|
|
494 |
int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
|
|
495 |
switch (op) {
|
|
496 |
case ADD:
|
|
497 |
masm.madd(size, asRegister(result), asRegister(src1), asRegister(src2), asRegister(src3));
|
|
498 |
break;
|
|
499 |
case SUB:
|
|
500 |
masm.msub(size, asRegister(result), asRegister(src1), asRegister(src2), asRegister(src3));
|
|
501 |
break;
|
58533
|
502 |
case FADD:
|
|
503 |
masm.fmadd(size, asRegister(result), asRegister(src1), asRegister(src2), asRegister(src3));
|
|
504 |
break;
|
52910
|
505 |
default:
|
|
506 |
throw GraalError.shouldNotReachHere();
|
|
507 |
}
|
|
508 |
}
|
|
509 |
}
|
|
510 |
|
43972
|
511 |
}
|