--- a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.aarch64/src/org/graalvm/compiler/lir/aarch64/AArch64ArithmeticOp.java	Sat Dec 08 05:04:19 2018 +0100
+++ b/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.aarch64/src/org/graalvm/compiler/lir/aarch64/AArch64ArithmeticOp.java	Sat Dec 08 00:56:10 2018 -0800
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -54,6 +54,7 @@
     SUBS(ARITHMETIC),
     MUL,
     MULVS,
+    MNEG,
     DIV,
     SMULH,
     UMULH,
@@ -275,6 +276,9 @@
                 case SMULH:
                     masm.smulh(size, dst, src1, src2);
                     break;
+                case MNEG:
+                    masm.mneg(size, dst, src1, src2);
+                    break;
                 case DIV:
                     masm.sdiv(size, dst, src1, src2);
                     break;
@@ -367,8 +371,8 @@
         }
     }
 
-    public static class AddSubShiftOp extends AArch64LIRInstruction {
-        private static final LIRInstructionClass<AddSubShiftOp> TYPE = LIRInstructionClass.create(AddSubShiftOp.class);
+    public static class BinaryShiftOp extends AArch64LIRInstruction {
+        private static final LIRInstructionClass<BinaryShiftOp> TYPE = LIRInstructionClass.create(BinaryShiftOp.class);
 
         @Opcode private final AArch64ArithmeticOp op;
         @Def(REG) protected AllocatableValue result;
@@ -376,19 +380,24 @@
         @Use(REG) protected AllocatableValue src2;
         private final AArch64MacroAssembler.ShiftType shiftType;
         private final int shiftAmt;
+        private final boolean isShiftNot;
 
         /**
-         * Computes <code>result = src1 <op> src2 <shiftType> <shiftAmt></code>.
+         * If shiftNot: Computes <code>result = src1 <op> ~(src2 <shiftType> <shiftAmt>)</code>
+         * (Only for logic ops). else: Computes
+         * <code>result = src1 <op> src2 <shiftType> <shiftAmt></code>.
          */
-        public AddSubShiftOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AArch64MacroAssembler.ShiftType shiftType, int shiftAmt) {
+        public BinaryShiftOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2,
+                        AArch64MacroAssembler.ShiftType shiftType, int shiftAmt, boolean isShiftNot) {
             super(TYPE);
-            assert op == ADD || op == SUB;
+            assert op == ADD || op == SUB || op == AND || op == OR || op == XOR;
             this.op = op;
             this.result = result;
             this.src1 = src1;
             this.src2 = src2;
             this.shiftType = shiftType;
             this.shiftAmt = shiftAmt;
+            this.isShiftNot = isShiftNot;
         }
 
         @Override
@@ -401,6 +410,27 @@
                 case SUB:
                     masm.sub(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
                     break;
+                case AND:
+                    if (!isShiftNot) {
+                        masm.and(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    } else {
+                        masm.bic(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    }
+                    break;
+                case OR:
+                    if (!isShiftNot) {
+                        masm.or(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    } else {
+                        masm.orn(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    }
+                    break;
+                case XOR:
+                    if (!isShiftNot) {
+                        masm.eor(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    } else {
+                        masm.eon(size, asRegister(result), asRegister(src1), asRegister(src2), shiftType, shiftAmt);
+                    }
+                    break;
                 default:
                     throw GraalError.shouldNotReachHere();
             }
@@ -437,4 +467,42 @@
         }
     }
 
+    public static class MultiplyAddSubOp extends AArch64LIRInstruction {
+        private static final LIRInstructionClass<MultiplyAddSubOp> TYPE = LIRInstructionClass.create(MultiplyAddSubOp.class);
+
+        @Opcode private final AArch64ArithmeticOp op;
+        @Def(REG) protected AllocatableValue result;
+        @Use(REG) protected AllocatableValue src1;
+        @Use(REG) protected AllocatableValue src2;
+        @Use(REG) protected AllocatableValue src3;
+
+        /**
+         * Computes <code>result = src3 <op> src1 * src2</code>.
+         */
+        public MultiplyAddSubOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AllocatableValue src3) {
+            super(TYPE);
+            assert op == ADD || op == SUB;
+            this.op = op;
+            this.result = result;
+            this.src1 = src1;
+            this.src2 = src2;
+            this.src3 = src3;
+        }
+
+        @Override
+        public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
+            int size = result.getPlatformKind().getSizeInBytes() * Byte.SIZE;
+            switch (op) {
+                case ADD:
+                    masm.madd(size, asRegister(result), asRegister(src1), asRegister(src2), asRegister(src3));
+                    break;
+                case SUB:
+                    masm.msub(size, asRegister(result), asRegister(src1), asRegister(src2), asRegister(src3));
+                    break;
+                default:
+                    throw GraalError.shouldNotReachHere();
+            }
+        }
+    }
+
 }