/*

 * Copyright 2003-2007 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

class BiasedLockingCounters;

// Contains all the definitions needed for amd64 assembly code generation.

#ifdef _LP64

// Calling convention

class Argument VALUE_OBJ_CLASS_SPEC {

 public:

  enum {

#ifdef _WIN64

    n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)

    n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )

#else

    n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)

    n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )

#endif

    n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...

    n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...

  };

};

// Symbolically name the register arguments used by the c calling convention.

// Windows is different from linux/solaris. So much for standards...

#ifdef _WIN64

REGISTER_DECLARATION(Register, c_rarg0, rcx);

REGISTER_DECLARATION(Register, c_rarg1, rdx);

REGISTER_DECLARATION(Register, c_rarg2, r8);

REGISTER_DECLARATION(Register, c_rarg3, r9);

REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);

#else

REGISTER_DECLARATION(Register, c_rarg0, rdi);

REGISTER_DECLARATION(Register, c_rarg1, rsi);

REGISTER_DECLARATION(Register, c_rarg2, rdx);

REGISTER_DECLARATION(Register, c_rarg3, rcx);

REGISTER_DECLARATION(Register, c_rarg4, r8);

REGISTER_DECLARATION(Register, c_rarg5, r9);

REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);

REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);

REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);

REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);

REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);

#endif

// Symbolically name the register arguments used by the Java calling convention.

// We have control over the convention for java so we can do what we please.

// What pleases us is to offset the java calling convention so that when

// we call a suitable jni method the arguments are lined up and we don't

// have to do little shuffling. A suitable jni method is non-static and a

// small number of arguments (two fewer args on windows)

//

//        |-------------------------------------------------------|

//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |

//        |-------------------------------------------------------|

//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)

//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux

//        |-------------------------------------------------------|

//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |

//        |-------------------------------------------------------|

REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);

REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);

REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);

// Windows runs out of register args here

#ifdef _WIN64

REGISTER_DECLARATION(Register, j_rarg3, rdi);

REGISTER_DECLARATION(Register, j_rarg4, rsi);

#else

REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);

REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);

#endif /* _WIN64 */

REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);

REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);

REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);

REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);

REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);

REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);

REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);

REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);

REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);

REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile

REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile

REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved

#endif // _LP64

// Address is an abstraction used to represent a memory location

// using any of the amd64 addressing modes with one object.

//

// Note: A register location is represented via a Register, not

//       via an address for efficiency & simplicity reasons.

class ArrayAddress;

class Address VALUE_OBJ_CLASS_SPEC {

 public:

  enum ScaleFactor {

    no_scale = -1,

    times_1  =  0,

    times_2  =  1,

    times_4  =  2,

    times_8  =  3

  };

 private:

  Register         _base;

  Register         _index;

  ScaleFactor      _scale;

  int              _disp;

  RelocationHolder _rspec;

  // Easily misused constructors make them private

  Address(int disp, address loc, relocInfo::relocType rtype);

  Address(int disp, address loc, RelocationHolder spec);

 public:

  // creation

  Address()

    : _base(noreg),

      _index(noreg),

      _scale(no_scale),

      _disp(0) {

  }

  // No default displacement otherwise Register can be implicitly

  // converted to 0(Register) which is quite a different animal.

  Address(Register base, int disp)

    : _base(base),

      _index(noreg),

      _scale(no_scale),

      _disp(disp) {

  }

  Address(Register base, Register index, ScaleFactor scale, int disp = 0)

    : _base (base),

      _index(index),

      _scale(scale),

      _disp (disp) {

    assert(!index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

  // The following two overloads are used in connection with the

  // ByteSize type (see sizes.hpp).  They simplify the use of

  // ByteSize'd arguments in assembly code. Note that their equivalent

  // for the optimized build are the member functions with int disp

  // argument since ByteSize is mapped to an int type in that case.

  //

  // Note: DO NOT introduce similar overloaded functions for WordSize

  // arguments as in the optimized mode, both ByteSize and WordSize

  // are mapped to the same type and thus the compiler cannot make a

  // distinction anymore (=> compiler errors).

#ifdef ASSERT

  Address(Register base, ByteSize disp)

    : _base(base),

      _index(noreg),

      _scale(no_scale),

      _disp(in_bytes(disp)) {

  }

  Address(Register base, Register index, ScaleFactor scale, ByteSize disp)

    : _base(base),

      _index(index),

      _scale(scale),

      _disp(in_bytes(disp)) {

    assert(!index->is_valid() == (scale == Address::no_scale),

           "inconsistent address");

  }

#endif // ASSERT

  // accessors

  bool uses(Register reg) const {

    return _base == reg || _index == reg;

  }

  // Convert the raw encoding form into the form expected by the constructor for

  // Address.  An index of 4 (rsp) corresponds to having no index, so convert

  // that to noreg for the Address constructor.

  static Address make_raw(int base, int index, int scale, int disp);

  static Address make_array(ArrayAddress);

 private:

  bool base_needs_rex() const {

    return _base != noreg && _base->encoding() >= 8;

  }

  bool index_needs_rex() const {

    return _index != noreg &&_index->encoding() >= 8;

  }

  relocInfo::relocType reloc() const { return _rspec.type(); }

  friend class Assembler;

  friend class MacroAssembler;

  friend class LIR_Assembler; // base/index/scale/disp

};

//

// AddressLiteral has been split out from Address because operands of this type

// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out

// the few instructions that need to deal with address literals are unique and the

// MacroAssembler does not have to implement every instruction in the Assembler

// in order to search for address literals that may need special handling depending

// on the instruction and the platform. As small step on the way to merging i486/amd64

// directories.

//

class AddressLiteral VALUE_OBJ_CLASS_SPEC {

  friend class ArrayAddress;

  RelocationHolder _rspec;

  // Typically we use AddressLiterals we want to use their rval

  // However in some situations we want the lval (effect address) of the item.

  // We provide a special factory for making those lvals.

  bool _is_lval;

  // If the target is far we'll need to load the ea of this to

  // a register to reach it. Otherwise if near we can do rip

  // relative addressing.

  address          _target;

 protected:

  // creation

  AddressLiteral()

    : _is_lval(false),

      _target(NULL)

  {}

  public:

  AddressLiteral(address target, relocInfo::relocType rtype);

  AddressLiteral(address target, RelocationHolder const& rspec)

    : _rspec(rspec),

      _is_lval(false),

      _target(target)

  {}

  AddressLiteral addr() {

    AddressLiteral ret = *this;

    ret._is_lval = true;

    return ret;

  }

 private:

  address target() { return _target; }

  bool is_lval() { return _is_lval; }

  relocInfo::relocType reloc() const { return _rspec.type(); }

  const RelocationHolder& rspec() const { return _rspec; }

  friend class Assembler;

  friend class MacroAssembler;

  friend class Address;

  friend class LIR_Assembler;

};

// Convience classes

class RuntimeAddress: public AddressLiteral {

  public:

  RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}

};

class OopAddress: public AddressLiteral {

  public:

  OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}

};

class ExternalAddress: public AddressLiteral {

  public:

  ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}

};

class InternalAddress: public AddressLiteral {

  public:

  InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}

};

// x86 can do array addressing as a single operation since disp can be an absolute

// address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class

// that expresses the concept but does extra magic on amd64 to get the final result

class ArrayAddress VALUE_OBJ_CLASS_SPEC {

  private:

  AddressLiteral _base;

  Address        _index;

  public:

  ArrayAddress() {};

  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};

  AddressLiteral base() { return _base; }

  Address index() { return _index; }

};

// The amd64 Assembler: Pure assembler doing NO optimizations on

// the instruction level (e.g. mov rax, 0 is not translated into xor

// rax, rax!); i.e., what you write is what you get. The Assembler is

// generating code into a CodeBuffer.

const int FPUStateSizeInWords = 512 / wordSize;

class Assembler : public AbstractAssembler  {

  friend class AbstractAssembler; // for the non-virtual hack

  friend class StubGenerator;

 protected:

#ifdef ASSERT

  void check_relocation(RelocationHolder const& rspec, int format);

#endif

  inline void emit_long64(jlong x);

  void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);

  void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);

  void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);

  void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);

  // Helper functions for groups of instructions

  void emit_arith_b(int op1, int op2, Register dst, int imm8);

  void emit_arith(int op1, int op2, Register dst, int imm32);

  // only x86??

  void emit_arith(int op1, int op2, Register dst, jobject obj);

  void emit_arith(int op1, int op2, Register dst, Register src);

  void emit_operand(Register reg,

                    Register base, Register index, Address::ScaleFactor scale,

                    int disp,

                    RelocationHolder const& rspec,

                    int rip_relative_correction = 0);

  void emit_operand(Register reg, Address adr,

                    int rip_relative_correction = 0);

  void emit_operand(XMMRegister reg,

                    Register base, Register index, Address::ScaleFactor scale,

                    int disp,

                    RelocationHolder const& rspec,

                    int rip_relative_correction = 0);

  void emit_operand(XMMRegister reg, Address adr,

                    int rip_relative_correction = 0);

  // Immediate-to-memory forms

  void emit_arith_operand(int op1, Register rm, Address adr, int imm32);

  void emit_farith(int b1, int b2, int i);

  bool reachable(AddressLiteral adr);

  // These are all easily abused and hence protected

  // Make these disappear in 64bit mode since they would never be correct

#ifndef _LP64

  void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);

  void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);

  void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);

  void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);

  void push_literal32(int32_t imm32, RelocationHolder const& rspec);

#endif // _LP64

  void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);

  // These are unique in that we are ensured by the caller that the 32bit

  // relative in these instructions will always be able to reach the potentially

  // 64bit address described by entry. Since they can take a 64bit address they

  // don't have the 32 suffix like the other instructions in this class.

  void jmp_literal(address entry, RelocationHolder const& rspec);

  void call_literal(address entry, RelocationHolder const& rspec);

 public:

  enum Condition { // The amd64 condition codes used for conditional jumps/moves.

    zero          = 0x4,

    notZero       = 0x5,

    equal         = 0x4,

    notEqual      = 0x5,

    less          = 0xc,

    lessEqual     = 0xe,

    greater       = 0xf,

    greaterEqual  = 0xd,

    below         = 0x2,

    belowEqual    = 0x6,

    above         = 0x7,

    aboveEqual    = 0x3,

    overflow      = 0x0,

    noOverflow    = 0x1,

    carrySet      = 0x2,

    carryClear    = 0x3,

    negative      = 0x8,

    positive      = 0x9,

    parity        = 0xa,

    noParity      = 0xb

  };

  enum Prefix {

    // segment overrides

    // XXX remove segment prefixes

    CS_segment = 0x2e,

    SS_segment = 0x36,

    DS_segment = 0x3e,

    ES_segment = 0x26,

    FS_segment = 0x64,

    GS_segment = 0x65,

    REX        = 0x40,

    REX_B      = 0x41,

    REX_X      = 0x42,

    REX_XB     = 0x43,

    REX_R      = 0x44,

    REX_RB     = 0x45,

    REX_RX     = 0x46,

    REX_RXB    = 0x47,

    REX_W      = 0x48,

    REX_WB     = 0x49,

    REX_WX     = 0x4A,

    REX_WXB    = 0x4B,

    REX_WR     = 0x4C,

    REX_WRB    = 0x4D,

    REX_WRX    = 0x4E,

    REX_WRXB   = 0x4F

  };

  enum WhichOperand {

    // input to locate_operand, and format code for relocations

    imm64_operand  = 0,          // embedded 64-bit immediate operand

    disp32_operand = 1,          // embedded 32-bit displacement

    call32_operand = 2,          // embedded 32-bit self-relative displacement

    _WhichOperand_limit = 3

  };

  public:

  // Creation

  Assembler(CodeBuffer* code)

    : AbstractAssembler(code) {

  }

  // Decoding

  static address locate_operand(address inst, WhichOperand which);

  static address locate_next_instruction(address inst);

  // Utilities

 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) )  <= x   &&   x  <  ( CONST64(1) << (nbits-1) ); }

 static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }

  // Stack

  void pushaq();

  void popaq();

  void pushfq();

  void popfq();

  void pushq(int imm32);

  void pushq(Register src);

  void pushq(Address src);

  void popq(Register dst);

  void popq(Address dst);

  // Instruction prefixes

  void prefix(Prefix p);