author | coleenp |
Sun, 13 Apr 2008 17:43:42 -0400 | |
changeset 360 | 21d113ecbf6a |
parent 244 | c8ad6f221400 |
child 371 | 1aacedc9db7c |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
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* CA 95054 USA or visit www.sun.com if you need additional information or |
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* have any questions. |
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* |
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*/ |
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class BiasedLockingCounters; |
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// Contains all the definitions needed for amd64 assembly code generation. |
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#ifdef _LP64 |
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// Calling convention |
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class Argument VALUE_OBJ_CLASS_SPEC { |
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public: |
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enum { |
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#ifdef _WIN64 |
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n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
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#else |
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n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
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parents:
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#endif // _WIN64 |
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n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
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n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
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}; |
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}; |
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// Symbolically name the register arguments used by the c calling convention. |
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// Windows is different from linux/solaris. So much for standards... |
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#ifdef _WIN64 |
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REGISTER_DECLARATION(Register, c_rarg0, rcx); |
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REGISTER_DECLARATION(Register, c_rarg1, rdx); |
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REGISTER_DECLARATION(Register, c_rarg2, r8); |
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REGISTER_DECLARATION(Register, c_rarg3, r9); |
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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#else |
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REGISTER_DECLARATION(Register, c_rarg0, rdi); |
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REGISTER_DECLARATION(Register, c_rarg1, rsi); |
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REGISTER_DECLARATION(Register, c_rarg2, rdx); |
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REGISTER_DECLARATION(Register, c_rarg3, rcx); |
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REGISTER_DECLARATION(Register, c_rarg4, r8); |
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REGISTER_DECLARATION(Register, c_rarg5, r9); |
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
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REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
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parents:
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diff
changeset
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#endif // _WIN64 |
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// Symbolically name the register arguments used by the Java calling convention. |
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// We have control over the convention for java so we can do what we please. |
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// What pleases us is to offset the java calling convention so that when |
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// we call a suitable jni method the arguments are lined up and we don't |
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// have to do little shuffling. A suitable jni method is non-static and a |
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// small number of arguments (two fewer args on windows) |
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// |
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// |-------------------------------------------------------| |
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// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
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// |-------------------------------------------------------| |
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// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
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// | rdi rsi rdx rcx r8 r9 | solaris/linux |
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// |-------------------------------------------------------| |
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// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
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// |-------------------------------------------------------| |
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REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
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REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
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REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
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// Windows runs out of register args here |
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#ifdef _WIN64 |
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REGISTER_DECLARATION(Register, j_rarg3, rdi); |
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REGISTER_DECLARATION(Register, j_rarg4, rsi); |
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#else |
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REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
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REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
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#endif // _WIN64 |
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REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
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REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
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REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
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REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
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REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
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coleenp
parents:
244
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changeset
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REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
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REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
1 | 125 |
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#endif // _LP64 |
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// Address is an abstraction used to represent a memory location |
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// using any of the amd64 addressing modes with one object. |
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// |
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// Note: A register location is represented via a Register, not |
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// via an address for efficiency & simplicity reasons. |
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class ArrayAddress; |
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class Address VALUE_OBJ_CLASS_SPEC { |
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public: |
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enum ScaleFactor { |
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no_scale = -1, |
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times_1 = 0, |
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times_2 = 1, |
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times_4 = 2, |
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times_8 = 3 |
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}; |
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private: |
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Register _base; |
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Register _index; |
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ScaleFactor _scale; |
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int _disp; |
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RelocationHolder _rspec; |
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// Easily misused constructors make them private |
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Address(int disp, address loc, relocInfo::relocType rtype); |
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Address(int disp, address loc, RelocationHolder spec); |
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public: |
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// creation |
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Address() |
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: _base(noreg), |
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_index(noreg), |
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_scale(no_scale), |
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_disp(0) { |
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} |
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// No default displacement otherwise Register can be implicitly |
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// converted to 0(Register) which is quite a different animal. |
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Address(Register base, int disp) |
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: _base(base), |
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_index(noreg), |
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_scale(no_scale), |
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_disp(disp) { |
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} |
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Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
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: _base (base), |
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_index(index), |
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_scale(scale), |
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_disp (disp) { |
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assert(!index->is_valid() == (scale == Address::no_scale), |
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"inconsistent address"); |
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} |
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// The following two overloads are used in connection with the |
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// ByteSize type (see sizes.hpp). They simplify the use of |
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// ByteSize'd arguments in assembly code. Note that their equivalent |
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// for the optimized build are the member functions with int disp |
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// argument since ByteSize is mapped to an int type in that case. |
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// |
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// Note: DO NOT introduce similar overloaded functions for WordSize |
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// arguments as in the optimized mode, both ByteSize and WordSize |
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// are mapped to the same type and thus the compiler cannot make a |
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// distinction anymore (=> compiler errors). |
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#ifdef ASSERT |
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Address(Register base, ByteSize disp) |
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: _base(base), |
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_index(noreg), |
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_scale(no_scale), |
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_disp(in_bytes(disp)) { |
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} |
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Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
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: _base(base), |
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_index(index), |
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_scale(scale), |
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_disp(in_bytes(disp)) { |
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assert(!index->is_valid() == (scale == Address::no_scale), |
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"inconsistent address"); |
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} |
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#endif // ASSERT |
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// accessors |
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bool uses(Register reg) const { |
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return _base == reg || _index == reg; |
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} |
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// Convert the raw encoding form into the form expected by the constructor for |
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// Address. An index of 4 (rsp) corresponds to having no index, so convert |
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// that to noreg for the Address constructor. |
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static Address make_raw(int base, int index, int scale, int disp); |
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static Address make_array(ArrayAddress); |
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private: |
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bool base_needs_rex() const { |
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return _base != noreg && _base->encoding() >= 8; |
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} |
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bool index_needs_rex() const { |
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return _index != noreg &&_index->encoding() >= 8; |
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} |
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relocInfo::relocType reloc() const { return _rspec.type(); } |
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friend class Assembler; |
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friend class MacroAssembler; |
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friend class LIR_Assembler; // base/index/scale/disp |
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}; |
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// |
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// AddressLiteral has been split out from Address because operands of this type |
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// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
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// the few instructions that need to deal with address literals are unique and the |
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// MacroAssembler does not have to implement every instruction in the Assembler |
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// in order to search for address literals that may need special handling depending |
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// on the instruction and the platform. As small step on the way to merging i486/amd64 |
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// directories. |
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// |
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class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
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friend class ArrayAddress; |
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RelocationHolder _rspec; |
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// Typically we use AddressLiterals we want to use their rval |
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// However in some situations we want the lval (effect address) of the item. |
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// We provide a special factory for making those lvals. |
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bool _is_lval; |
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// If the target is far we'll need to load the ea of this to |
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// a register to reach it. Otherwise if near we can do rip |
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// relative addressing. |
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address _target; |
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protected: |
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// creation |
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AddressLiteral() |
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: _is_lval(false), |
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_target(NULL) |
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{} |
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public: |
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273 |
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AddressLiteral(address target, relocInfo::relocType rtype); |
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AddressLiteral(address target, RelocationHolder const& rspec) |
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: _rspec(rspec), |
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_is_lval(false), |
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_target(target) |
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{} |
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282 |
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AddressLiteral addr() { |
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AddressLiteral ret = *this; |
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ret._is_lval = true; |
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return ret; |
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} |
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288 |
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289 |
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private: |
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291 |
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address target() { return _target; } |
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bool is_lval() { return _is_lval; } |
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294 |
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295 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
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296 |
const RelocationHolder& rspec() const { return _rspec; } |
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297 |
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298 |
friend class Assembler; |
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friend class MacroAssembler; |
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300 |
friend class Address; |
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301 |
friend class LIR_Assembler; |
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}; |
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303 |
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304 |
// Convience classes |
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class RuntimeAddress: public AddressLiteral { |
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306 |
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public: |
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308 |
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RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
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310 |
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}; |
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312 |
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class OopAddress: public AddressLiteral { |
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314 |
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public: |
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316 |
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OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} |
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318 |
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}; |
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320 |
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class ExternalAddress: public AddressLiteral { |
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322 |
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public: |
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324 |
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ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} |
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}; |
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328 |
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class InternalAddress: public AddressLiteral { |
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330 |
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public: |
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332 |
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InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
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334 |
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}; |
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336 |
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337 |
// x86 can do array addressing as a single operation since disp can be an absolute |
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// address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class |
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// that expresses the concept but does extra magic on amd64 to get the final result |
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340 |
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341 |
class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
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private: |
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343 |
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AddressLiteral _base; |
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Address _index; |
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346 |
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347 |
public: |
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348 |
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349 |
ArrayAddress() {}; |
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ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
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AddressLiteral base() { return _base; } |
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Address index() { return _index; } |
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353 |
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354 |
}; |
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355 |
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356 |
// The amd64 Assembler: Pure assembler doing NO optimizations on |
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357 |
// the instruction level (e.g. mov rax, 0 is not translated into xor |
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358 |
// rax, rax!); i.e., what you write is what you get. The Assembler is |
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359 |
// generating code into a CodeBuffer. |
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360 |
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361 |
const int FPUStateSizeInWords = 512 / wordSize; |
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362 |
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363 |
class Assembler : public AbstractAssembler { |
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364 |
friend class AbstractAssembler; // for the non-virtual hack |
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365 |
friend class StubGenerator; |
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366 |
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367 |
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368 |
protected: |
|
369 |
#ifdef ASSERT |
|
370 |
void check_relocation(RelocationHolder const& rspec, int format); |
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371 |
#endif |
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372 |
||
373 |
inline void emit_long64(jlong x); |
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374 |
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375 |
void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */); |
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376 |
void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */); |
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377 |
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
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378 |
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
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379 |
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380 |
// Helper functions for groups of instructions |
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381 |
void emit_arith_b(int op1, int op2, Register dst, int imm8); |
|
382 |
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383 |
void emit_arith(int op1, int op2, Register dst, int imm32); |
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384 |
// only x86?? |
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385 |
void emit_arith(int op1, int op2, Register dst, jobject obj); |
|
386 |
void emit_arith(int op1, int op2, Register dst, Register src); |
|
387 |
||
388 |
void emit_operand(Register reg, |
|
389 |
Register base, Register index, Address::ScaleFactor scale, |
|
390 |
int disp, |
|
391 |
RelocationHolder const& rspec, |
|
392 |
int rip_relative_correction = 0); |
|
393 |
void emit_operand(Register reg, Address adr, |
|
394 |
int rip_relative_correction = 0); |
|
395 |
void emit_operand(XMMRegister reg, |
|
396 |
Register base, Register index, Address::ScaleFactor scale, |
|
397 |
int disp, |
|
398 |
RelocationHolder const& rspec, |
|
399 |
int rip_relative_correction = 0); |
|
400 |
void emit_operand(XMMRegister reg, Address adr, |
|
401 |
int rip_relative_correction = 0); |
|
402 |
||
403 |
// Immediate-to-memory forms |
|
404 |
void emit_arith_operand(int op1, Register rm, Address adr, int imm32); |
|
405 |
||
406 |
void emit_farith(int b1, int b2, int i); |
|
407 |
||
408 |
bool reachable(AddressLiteral adr); |
|
409 |
||
410 |
// These are all easily abused and hence protected |
|
411 |
||
412 |
// Make these disappear in 64bit mode since they would never be correct |
|
413 |
#ifndef _LP64 |
|
414 |
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); |
|
415 |
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); |
|
416 |
||
417 |
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); |
|
418 |
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); |
|
419 |
||
420 |
void push_literal32(int32_t imm32, RelocationHolder const& rspec); |
|
421 |
#endif // _LP64 |
|
422 |
||
423 |
||
424 |
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); |
|
425 |
||
426 |
// These are unique in that we are ensured by the caller that the 32bit |
|
427 |
// relative in these instructions will always be able to reach the potentially |
|
428 |
// 64bit address described by entry. Since they can take a 64bit address they |
|
429 |
// don't have the 32 suffix like the other instructions in this class. |
|
430 |
void jmp_literal(address entry, RelocationHolder const& rspec); |
|
431 |
void call_literal(address entry, RelocationHolder const& rspec); |
|
432 |
||
433 |
public: |
|
434 |
enum Condition { // The amd64 condition codes used for conditional jumps/moves. |
|
435 |
zero = 0x4, |
|
436 |
notZero = 0x5, |
|
437 |
equal = 0x4, |
|
438 |
notEqual = 0x5, |
|
439 |
less = 0xc, |
|
440 |
lessEqual = 0xe, |
|
441 |
greater = 0xf, |
|
442 |
greaterEqual = 0xd, |
|
443 |
below = 0x2, |
|
444 |
belowEqual = 0x6, |
|
445 |
above = 0x7, |
|
446 |
aboveEqual = 0x3, |
|
447 |
overflow = 0x0, |
|
448 |
noOverflow = 0x1, |
|
449 |
carrySet = 0x2, |
|
450 |
carryClear = 0x3, |
|
451 |
negative = 0x8, |
|
452 |
positive = 0x9, |
|
453 |
parity = 0xa, |
|
454 |
noParity = 0xb |
|
455 |
}; |
|
456 |
||
457 |
enum Prefix { |
|
458 |
// segment overrides |
|
459 |
// XXX remove segment prefixes |
|
460 |
CS_segment = 0x2e, |
|
461 |
SS_segment = 0x36, |
|
462 |
DS_segment = 0x3e, |
|
463 |
ES_segment = 0x26, |
|
464 |
FS_segment = 0x64, |
|
465 |
GS_segment = 0x65, |
|
466 |
||
467 |
REX = 0x40, |
|
468 |
||
469 |
REX_B = 0x41, |
|
470 |
REX_X = 0x42, |
|
471 |
REX_XB = 0x43, |
|
472 |
REX_R = 0x44, |
|
473 |
REX_RB = 0x45, |
|
474 |
REX_RX = 0x46, |
|
475 |
REX_RXB = 0x47, |
|
476 |
||
477 |
REX_W = 0x48, |
|
478 |
||
479 |
REX_WB = 0x49, |
|
480 |
REX_WX = 0x4A, |
|
481 |
REX_WXB = 0x4B, |
|
482 |
REX_WR = 0x4C, |
|
483 |
REX_WRB = 0x4D, |
|
484 |
REX_WRX = 0x4E, |
|
485 |
REX_WRXB = 0x4F |
|
486 |
}; |
|
487 |
||
488 |
enum WhichOperand { |
|
489 |
// input to locate_operand, and format code for relocations |
|
490 |
imm64_operand = 0, // embedded 64-bit immediate operand |
|
491 |
disp32_operand = 1, // embedded 32-bit displacement |
|
492 |
call32_operand = 2, // embedded 32-bit self-relative displacement |
|
493 |
_WhichOperand_limit = 3 |
|
494 |
}; |
|
495 |
||
496 |
public: |
|
497 |
||
498 |
// Creation |
|
499 |
Assembler(CodeBuffer* code) |
|
500 |
: AbstractAssembler(code) { |
|
501 |
} |
|
502 |
||
503 |
// Decoding |
|
504 |
static address locate_operand(address inst, WhichOperand which); |
|
505 |
static address locate_next_instruction(address inst); |
|
506 |
||
507 |
// Utilities |
|
508 |
||
509 |
static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } |
|
510 |
static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; } |
|
511 |
||
512 |
||
513 |
// Stack |
|
514 |
void pushaq(); |
|
515 |
void popaq(); |
|
516 |
||
517 |
void pushfq(); |
|
518 |
void popfq(); |
|
519 |
||
520 |
void pushq(int imm32); |
|
521 |
||
522 |
void pushq(Register src); |
|
523 |
void pushq(Address src); |
|
524 |
||
525 |
void popq(Register dst); |
|
526 |
void popq(Address dst); |
|
527 |
||
528 |
// Instruction prefixes |
|
529 |
void prefix(Prefix p); |
|
530 |
||
531 |
int prefix_and_encode(int reg_enc, bool byteinst = false); |
|
532 |
int prefixq_and_encode(int reg_enc); |
|
533 |
||
534 |
int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); |
|
535 |
int prefixq_and_encode(int dst_enc, int src_enc); |
|
536 |
||
537 |
void prefix(Register reg); |
|
538 |
void prefix(Address adr); |
|
539 |
void prefixq(Address adr); |
|
540 |
||
541 |
void prefix(Address adr, Register reg, bool byteinst = false); |
|
542 |
void prefixq(Address adr, Register reg); |
|
543 |
||
544 |
void prefix(Address adr, XMMRegister reg); |
|
545 |
||
546 |
// Moves |
|
547 |
void movb(Register dst, Address src); |
|
548 |
void movb(Address dst, int imm8); |
|
549 |
void movb(Address dst, Register src); |
|
550 |
||
551 |
void movw(Address dst, int imm16); |
|
552 |
void movw(Register dst, Address src); |
|
553 |
void movw(Address dst, Register src); |
|
554 |
||
555 |
void movl(Register dst, int imm32); |
|
556 |
void movl(Register dst, Register src); |
|
557 |
void movl(Register dst, Address src); |
|
558 |
void movl(Address dst, int imm32); |
|
559 |
void movl(Address dst, Register src); |
|
560 |
||
561 |
void movq(Register dst, Register src); |
|
562 |
void movq(Register dst, Address src); |
|
563 |
void movq(Address dst, Register src); |
|
564 |
// These prevent using movq from converting a zero (like NULL) into Register |
|
565 |
// by giving the compiler two choices it can't resolve |
|
566 |
void movq(Address dst, void* dummy); |
|
567 |
void movq(Register dst, void* dummy); |
|
568 |
||
569 |
void mov64(Register dst, intptr_t imm64); |
|
570 |
void mov64(Address dst, intptr_t imm64); |
|
571 |
||
572 |
void movsbl(Register dst, Address src); |
|
573 |
void movsbl(Register dst, Register src); |
|
574 |
void movswl(Register dst, Address src); |
|
575 |
void movswl(Register dst, Register src); |
|
576 |
void movslq(Register dst, Address src); |
|
577 |
void movslq(Register dst, Register src); |
|
578 |
||
579 |
void movzbl(Register dst, Address src); |
|
580 |
void movzbl(Register dst, Register src); |
|
581 |
void movzwl(Register dst, Address src); |
|
582 |
void movzwl(Register dst, Register src); |
|
583 |
||
584 |
protected: // Avoid using the next instructions directly. |
|
585 |
// New cpus require use of movsd and movss to avoid partial register stall |
|
586 |
// when loading from memory. But for old Opteron use movlpd instead of movsd. |
|
587 |
// The selection is done in MacroAssembler::movdbl() and movflt(). |
|
588 |
void movss(XMMRegister dst, XMMRegister src); |
|
589 |
void movss(XMMRegister dst, Address src); |
|
590 |
void movss(Address dst, XMMRegister src); |
|
591 |
void movsd(XMMRegister dst, XMMRegister src); |
|
592 |
void movsd(Address dst, XMMRegister src); |
|
593 |
void movsd(XMMRegister dst, Address src); |
|
594 |
void movlpd(XMMRegister dst, Address src); |
|
595 |
// New cpus require use of movaps and movapd to avoid partial register stall |
|
596 |
// when moving between registers. |
|
597 |
void movapd(XMMRegister dst, XMMRegister src); |
|
598 |
void movaps(XMMRegister dst, XMMRegister src); |
|
599 |
public: |
|
600 |
||
601 |
void movdl(XMMRegister dst, Register src); |
|
602 |
void movdl(Register dst, XMMRegister src); |
|
603 |
void movdq(XMMRegister dst, Register src); |
|
604 |
void movdq(Register dst, XMMRegister src); |
|
605 |
||
606 |
void cmovl(Condition cc, Register dst, Register src); |
|
607 |
void cmovl(Condition cc, Register dst, Address src); |
|
608 |
void cmovq(Condition cc, Register dst, Register src); |
|
609 |
void cmovq(Condition cc, Register dst, Address src); |
|
610 |
||
611 |
// Prefetches |
|
612 |
private: |
|
613 |
void prefetch_prefix(Address src); |
|
614 |
public: |
|
615 |
void prefetcht0(Address src); |
|
616 |
void prefetcht1(Address src); |
|
617 |
void prefetcht2(Address src); |
|
618 |
void prefetchnta(Address src); |
|
619 |
void prefetchw(Address src); |
|
620 |
||
621 |
// Arithmetics |
|
622 |
void adcl(Register dst, int imm32); |
|
623 |
void adcl(Register dst, Address src); |
|
624 |
void adcl(Register dst, Register src); |
|
625 |
void adcq(Register dst, int imm32); |
|
626 |
void adcq(Register dst, Address src); |
|
627 |
void adcq(Register dst, Register src); |
|
628 |
||
629 |
void addl(Address dst, int imm32); |
|
630 |
void addl(Address dst, Register src); |
|
631 |
void addl(Register dst, int imm32); |
|
632 |
void addl(Register dst, Address src); |
|
633 |
void addl(Register dst, Register src); |
|
634 |
void addq(Address dst, int imm32); |
|
635 |
void addq(Address dst, Register src); |
|
636 |
void addq(Register dst, int imm32); |
|
637 |
void addq(Register dst, Address src); |
|
638 |
void addq(Register dst, Register src); |
|
639 |
||
640 |
void andl(Register dst, int imm32); |
|
641 |
void andl(Register dst, Address src); |
|
642 |
void andl(Register dst, Register src); |
|
643 |
void andq(Register dst, int imm32); |
|
644 |
void andq(Register dst, Address src); |
|
645 |
void andq(Register dst, Register src); |
|
646 |
||
647 |
void cmpb(Address dst, int imm8); |
|
648 |
void cmpl(Address dst, int imm32); |
|
649 |
void cmpl(Register dst, int imm32); |
|
650 |
void cmpl(Register dst, Register src); |
|
651 |
void cmpl(Register dst, Address src); |
|
652 |
void cmpq(Address dst, int imm32); |
|
653 |
void cmpq(Address dst, Register src); |
|
654 |
void cmpq(Register dst, int imm32); |
|
655 |
void cmpq(Register dst, Register src); |
|
656 |
void cmpq(Register dst, Address src); |
|
657 |
||
658 |
void ucomiss(XMMRegister dst, XMMRegister src); |
|
659 |
void ucomisd(XMMRegister dst, XMMRegister src); |
|
660 |
||
661 |
protected: |
|
662 |
// Don't use next inc() and dec() methods directly. INC & DEC instructions |
|
663 |
// could cause a partial flag stall since they don't set CF flag. |
|
664 |
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
|
665 |
// which call inc() & dec() or add() & sub() in accordance with |
|
666 |
// the product flag UseIncDec value. |
|
667 |
||
668 |
void decl(Register dst); |
|
669 |
void decl(Address dst); |
|
670 |
void decq(Register dst); |
|
671 |
void decq(Address dst); |
|
672 |
||
673 |
void incl(Register dst); |
|
674 |
void incl(Address dst); |
|
675 |
void incq(Register dst); |
|
676 |
void incq(Address dst); |
|
677 |
||
678 |
public: |
|
679 |
void idivl(Register src); |
|
680 |
void idivq(Register src); |
|
681 |
void cdql(); |
|
682 |
void cdqq(); |
|
683 |
||
684 |
void imull(Register dst, Register src); |
|
685 |
void imull(Register dst, Register src, int value); |
|
686 |
void imulq(Register dst, Register src); |
|
687 |
void imulq(Register dst, Register src, int value); |
|
688 |
||
689 |
void leal(Register dst, Address src); |
|
690 |
void leaq(Register dst, Address src); |
|
691 |
||
692 |
void mull(Address src); |
|
693 |
void mull(Register src); |
|
694 |
||
695 |
void negl(Register dst); |
|
696 |
void negq(Register dst); |
|
697 |
||
698 |
void notl(Register dst); |
|
699 |
void notq(Register dst); |
|
700 |
||
701 |
void orl(Address dst, int imm32); |
|
702 |
void orl(Register dst, int imm32); |
|
703 |
void orl(Register dst, Address src); |
|
704 |
void orl(Register dst, Register src); |
|
705 |
void orq(Address dst, int imm32); |
|
706 |
void orq(Register dst, int imm32); |
|
707 |
void orq(Register dst, Address src); |
|
708 |
void orq(Register dst, Register src); |
|
709 |
||
710 |
void rcll(Register dst, int imm8); |
|
711 |
void rclq(Register dst, int imm8); |
|
712 |
||
713 |
void sarl(Register dst, int imm8); |
|
714 |
void sarl(Register dst); |
|
715 |
void sarq(Register dst, int imm8); |
|
716 |
void sarq(Register dst); |
|
717 |
||
718 |
void sbbl(Address dst, int imm32); |
|
719 |
void sbbl(Register dst, int imm32); |
|
720 |
void sbbl(Register dst, Address src); |
|
721 |
void sbbl(Register dst, Register src); |
|
722 |
void sbbq(Address dst, int imm32); |
|
723 |
void sbbq(Register dst, int imm32); |
|
724 |
void sbbq(Register dst, Address src); |
|
725 |
void sbbq(Register dst, Register src); |
|
726 |
||
727 |
void shll(Register dst, int imm8); |
|
728 |
void shll(Register dst); |
|
729 |
void shlq(Register dst, int imm8); |
|
730 |
void shlq(Register dst); |
|
731 |
||
732 |
void shrl(Register dst, int imm8); |
|
733 |
void shrl(Register dst); |
|
734 |
void shrq(Register dst, int imm8); |
|
735 |
void shrq(Register dst); |
|
736 |
||
737 |
void subl(Address dst, int imm32); |
|
738 |
void subl(Address dst, Register src); |
|
739 |
void subl(Register dst, int imm32); |
|
740 |
void subl(Register dst, Address src); |
|
741 |
void subl(Register dst, Register src); |
|
742 |
void subq(Address dst, int imm32); |
|
743 |
void subq(Address dst, Register src); |
|
744 |
void subq(Register dst, int imm32); |
|
745 |
void subq(Register dst, Address src); |
|
746 |
void subq(Register dst, Register src); |
|
747 |
||
748 |
void testb(Register dst, int imm8); |
|
749 |
void testl(Register dst, int imm32); |
|
750 |
void testl(Register dst, Register src); |
|
751 |
void testq(Register dst, int imm32); |
|
752 |
void testq(Register dst, Register src); |
|
753 |
||
754 |
void xaddl(Address dst, Register src); |
|
755 |
void xaddq(Address dst, Register src); |
|
756 |
||
757 |
void xorl(Register dst, int imm32); |
|
758 |
void xorl(Register dst, Address src); |
|
759 |
void xorl(Register dst, Register src); |
|
760 |
void xorq(Register dst, int imm32); |
|
761 |
void xorq(Register dst, Address src); |
|
762 |
void xorq(Register dst, Register src); |
|
763 |
||
764 |
// Miscellaneous |
|
765 |
void bswapl(Register reg); |
|
766 |
void bswapq(Register reg); |
|
767 |
void lock(); |
|
768 |
||
769 |
void xchgl(Register reg, Address adr); |
|
770 |
void xchgl(Register dst, Register src); |
|
771 |
void xchgq(Register reg, Address adr); |
|
772 |
void xchgq(Register dst, Register src); |
|
773 |
||
774 |
void cmpxchgl(Register reg, Address adr); |
|
775 |
void cmpxchgq(Register reg, Address adr); |
|
776 |
||
777 |
void nop(int i = 1); |
|
778 |
void addr_nop_4(); |
|
779 |
void addr_nop_5(); |
|
780 |
void addr_nop_7(); |
|
781 |
void addr_nop_8(); |
|
782 |
||
783 |
void hlt(); |
|
784 |
void ret(int imm16); |
|
785 |
void smovl(); |
|
786 |
void rep_movl(); |
|
787 |
void rep_movq(); |
|
788 |
void rep_set(); |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
789 |
void repne_scanl(); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
790 |
void repne_scanq(); |
1 | 791 |
void setb(Condition cc, Register dst); |
792 |
||
793 |
void clflush(Address adr); |
|
794 |
||
795 |
enum Membar_mask_bits { |
|
796 |
StoreStore = 1 << 3, |
|
797 |
LoadStore = 1 << 2, |
|
798 |
StoreLoad = 1 << 1, |
|
799 |
LoadLoad = 1 << 0 |
|
800 |
}; |
|
801 |
||
802 |
// Serializes memory. |
|
803 |
void membar(Membar_mask_bits order_constraint) { |
|
804 |
// We only have to handle StoreLoad and LoadLoad |
|
805 |
if (order_constraint & StoreLoad) { |
|
806 |
// MFENCE subsumes LFENCE |
|
807 |
mfence(); |
|
808 |
} /* [jk] not needed currently: else if (order_constraint & LoadLoad) { |
|
809 |
lfence(); |
|
810 |
} */ |
|
811 |
} |
|
812 |
||
813 |
void lfence() { |
|
814 |
emit_byte(0x0F); |
|
815 |
emit_byte(0xAE); |
|
816 |
emit_byte(0xE8); |
|
817 |
} |
|
818 |
||
819 |
void mfence() { |
|
820 |
emit_byte(0x0F); |
|
821 |
emit_byte(0xAE); |
|
822 |
emit_byte(0xF0); |
|
823 |
} |
|
824 |
||
825 |
// Identify processor type and features |
|
826 |
void cpuid() { |
|
827 |
emit_byte(0x0F); |
|
828 |
emit_byte(0xA2); |
|
829 |
} |
|
830 |
||
831 |
void cld() { emit_byte(0xfc); |
|
832 |
} |
|
833 |
||
834 |
void std() { emit_byte(0xfd); |
|
835 |
} |
|
836 |
||
837 |
||
838 |
// Calls |
|
839 |
||
840 |
void call(Label& L, relocInfo::relocType rtype); |
|
841 |
void call(Register reg); |
|
842 |
void call(Address adr); |
|
843 |
||
844 |
// Jumps |
|
845 |
||
846 |
void jmp(Register reg); |
|
847 |
void jmp(Address adr); |
|
848 |
||
849 |
// Label operations & relative jumps (PPUM Appendix D) |
|
850 |
// unconditional jump to L |
|
851 |
void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); |
|
852 |
||
853 |
||
854 |
// Unconditional 8-bit offset jump to L. |
|
855 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
856 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
857 |
// will occur. |
|
858 |
void jmpb(Label& L); |
|
859 |
||
860 |
// jcc is the generic conditional branch generator to run- time |
|
861 |
// routines, jcc is used for branches to labels. jcc takes a branch |
|
862 |
// opcode (cc) and a label (L) and generates either a backward |
|
863 |
// branch or a forward branch and links it to the label fixup |
|
864 |
// chain. Usage: |
|
865 |
// |
|
866 |
// Label L; // unbound label |
|
867 |
// jcc(cc, L); // forward branch to unbound label |
|
868 |
// bind(L); // bind label to the current pc |
|
869 |
// jcc(cc, L); // backward branch to bound label |
|
870 |
// bind(L); // illegal: a label may be bound only once |
|
871 |
// |
|
872 |
// Note: The same Label can be used for forward and backward branches |
|
873 |
// but it may be bound only once. |
|
874 |
||
875 |
void jcc(Condition cc, Label& L, |
|
876 |
relocInfo::relocType rtype = relocInfo::none); |
|
877 |
||
878 |
// Conditional jump to a 8-bit offset to L. |
|
879 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
880 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
881 |
// will occur. |
|
882 |
void jccb(Condition cc, Label& L); |
|
883 |
||
884 |
// Floating-point operations |
|
885 |
||
886 |
void fxsave(Address dst); |
|
887 |
void fxrstor(Address src); |
|
888 |
void ldmxcsr(Address src); |
|
889 |
void stmxcsr(Address dst); |
|
890 |
||
891 |
void addss(XMMRegister dst, XMMRegister src); |
|
892 |
void addss(XMMRegister dst, Address src); |
|
893 |
void subss(XMMRegister dst, XMMRegister src); |
|
894 |
void subss(XMMRegister dst, Address src); |
|
895 |
void mulss(XMMRegister dst, XMMRegister src); |
|
896 |
void mulss(XMMRegister dst, Address src); |
|
897 |
void divss(XMMRegister dst, XMMRegister src); |
|
898 |
void divss(XMMRegister dst, Address src); |
|
899 |
void addsd(XMMRegister dst, XMMRegister src); |
|
900 |
void addsd(XMMRegister dst, Address src); |
|
901 |
void subsd(XMMRegister dst, XMMRegister src); |
|
902 |
void subsd(XMMRegister dst, Address src); |
|
903 |
void mulsd(XMMRegister dst, XMMRegister src); |
|
904 |
void mulsd(XMMRegister dst, Address src); |
|
905 |
void divsd(XMMRegister dst, XMMRegister src); |
|
906 |
void divsd(XMMRegister dst, Address src); |
|
907 |
||
908 |
// We only need the double form |
|
909 |
void sqrtsd(XMMRegister dst, XMMRegister src); |
|
910 |
void sqrtsd(XMMRegister dst, Address src); |
|
911 |
||
912 |
void xorps(XMMRegister dst, XMMRegister src); |
|
913 |
void xorps(XMMRegister dst, Address src); |
|
914 |
void xorpd(XMMRegister dst, XMMRegister src); |
|
915 |
void xorpd(XMMRegister dst, Address src); |
|
916 |
||
917 |
void cvtsi2ssl(XMMRegister dst, Register src); |
|
918 |
void cvtsi2ssq(XMMRegister dst, Register src); |
|
919 |
void cvtsi2sdl(XMMRegister dst, Register src); |
|
920 |
void cvtsi2sdq(XMMRegister dst, Register src); |
|
921 |
void cvttss2sil(Register dst, XMMRegister src); // truncates |
|
922 |
void cvttss2siq(Register dst, XMMRegister src); // truncates |
|
923 |
void cvttsd2sil(Register dst, XMMRegister src); // truncates |
|
924 |
void cvttsd2siq(Register dst, XMMRegister src); // truncates |
|
925 |
void cvtss2sd(XMMRegister dst, XMMRegister src); |
|
926 |
void cvtsd2ss(XMMRegister dst, XMMRegister src); |
|
244 | 927 |
void cvtdq2pd(XMMRegister dst, XMMRegister src); |
928 |
void cvtdq2ps(XMMRegister dst, XMMRegister src); |
|
1 | 929 |
|
930 |
void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values |
|
931 |
void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values |
|
932 |
||
933 |
void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword |
|
934 |
void movdqa(XMMRegister dst, XMMRegister src); |
|
935 |
void movdqa(Address dst, XMMRegister src); |
|
936 |
||
937 |
void movq(XMMRegister dst, Address src); |
|
938 |
void movq(Address dst, XMMRegister src); |
|
939 |
||
940 |
void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords |
|
941 |
void pshufd(XMMRegister dst, Address src, int mode); |
|
942 |
void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words |
|
943 |
void pshuflw(XMMRegister dst, Address src, int mode); |
|
944 |
||
945 |
void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate |
|
946 |
||
947 |
void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes |
|
948 |
void punpcklbw(XMMRegister dst, Address src); |
|
949 |
}; |
|
950 |
||
951 |
||
952 |
// MacroAssembler extends Assembler by frequently used macros. |
|
953 |
// |
|
954 |
// Instructions for which a 'better' code sequence exists depending |
|
955 |
// on arguments should also go in here. |
|
956 |
||
957 |
class MacroAssembler : public Assembler { |
|
958 |
friend class LIR_Assembler; |
|
959 |
protected: |
|
960 |
||
961 |
Address as_Address(AddressLiteral adr); |
|
962 |
Address as_Address(ArrayAddress adr); |
|
963 |
||
964 |
// Support for VM calls |
|
965 |
// |
|
966 |
// This is the base routine called by the different versions of |
|
967 |
// call_VM_leaf. The interpreter may customize this version by |
|
968 |
// overriding it for its purposes (e.g., to save/restore additional |
|
969 |
// registers when doing a VM call). |
|
970 |
||
971 |
virtual void call_VM_leaf_base( |
|
972 |
address entry_point, // the entry point |
|
973 |
int number_of_arguments // the number of arguments to |
|
974 |
// pop after the call |
|
975 |
); |
|
976 |
||
977 |
// This is the base routine called by the different versions of |
|
978 |
// call_VM. The interpreter may customize this version by overriding |
|
979 |
// it for its purposes (e.g., to save/restore additional registers |
|
980 |
// when doing a VM call). |
|
981 |
// |
|
982 |
// If no java_thread register is specified (noreg) than rdi will be |
|
983 |
// used instead. call_VM_base returns the register which contains |
|
984 |
// the thread upon return. If a thread register has been specified, |
|
985 |
// the return value will correspond to that register. If no |
|
986 |
// last_java_sp is specified (noreg) than rsp will be used instead. |
|
987 |
virtual void call_VM_base( // returns the register |
|
988 |
// containing the thread upon |
|
989 |
// return |
|
990 |
Register oop_result, // where an oop-result ends up |
|
991 |
// if any; use noreg otherwise |
|
992 |
Register java_thread, // the thread if computed |
|
993 |
// before ; use noreg otherwise |
|
994 |
Register last_java_sp, // to set up last_Java_frame in |
|
995 |
// stubs; use noreg otherwise |
|
996 |
address entry_point, // the entry point |
|
997 |
int number_of_arguments, // the number of arguments (w/o |
|
998 |
// thread) to pop after the |
|
999 |
// call |
|
1000 |
bool check_exceptions // whether to check for pending |
|
1001 |
// exceptions after return |
|
1002 |
); |
|
1003 |
||
1004 |
// This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code. |
|
1005 |
// The implementation is only non-empty for the InterpreterMacroAssembler, |
|
1006 |
// as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
|
1007 |
virtual void check_and_handle_popframe(Register java_thread); |
|
1008 |
virtual void check_and_handle_earlyret(Register java_thread); |
|
1009 |
||
1010 |
void call_VM_helper(Register oop_result, |
|
1011 |
address entry_point, |
|
1012 |
int number_of_arguments, |
|
1013 |
bool check_exceptions = true); |
|
1014 |
||
1015 |
public: |
|
1016 |
MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
|
1017 |
||
1018 |
// Support for NULL-checks |
|
1019 |
// |
|
1020 |
// Generates code that causes a NULL OS exception if the content of |
|
1021 |
// reg is NULL. If the accessed location is M[reg + offset] and the |
|
1022 |
// offset is known, provide the offset. No explicit code generation |
|
1023 |
// is needed if the offset is within a certain range (0 <= offset <= |
|
1024 |
// page_size). |
|
1025 |
void null_check(Register reg, int offset = -1); |
|
1026 |
static bool needs_explicit_null_check(int offset); |
|
1027 |
||
1028 |
// Required platform-specific helpers for Label::patch_instructions. |
|
1029 |
// They _shadow_ the declarations in AbstractAssembler, which are undefined. |
|
1030 |
void pd_patch_instruction(address branch, address target); |
|
1031 |
#ifndef PRODUCT |
|
1032 |
static void pd_print_patched_instruction(address branch); |
|
1033 |
#endif |
|
1034 |
||
1035 |
||
1036 |
// The following 4 methods return the offset of the appropriate move |
|
1037 |
// instruction. Note: these are 32 bit instructions |
|
1038 |
||
1039 |
// Support for fast byte/word loading with zero extension (depending |
|
1040 |
// on particular CPU) |
|
1041 |
int load_unsigned_byte(Register dst, Address src); |
|
1042 |
int load_unsigned_word(Register dst, Address src); |
|
1043 |
||
1044 |
// Support for fast byte/word loading with sign extension (depending |
|
1045 |
// on particular CPU) |
|
1046 |
int load_signed_byte(Register dst, Address src); |
|
1047 |
int load_signed_word(Register dst, Address src); |
|
1048 |
||
1049 |
// Support for inc/dec with optimal instruction selection depending |
|
1050 |
// on value |
|
1051 |
void incrementl(Register reg, int value = 1); |
|
1052 |
void decrementl(Register reg, int value = 1); |
|
1053 |
void incrementq(Register reg, int value = 1); |
|
1054 |
void decrementq(Register reg, int value = 1); |
|
1055 |
||
1056 |
void incrementl(Address dst, int value = 1); |
|
1057 |
void decrementl(Address dst, int value = 1); |
|
1058 |
void incrementq(Address dst, int value = 1); |
|
1059 |
void decrementq(Address dst, int value = 1); |
|
1060 |
||
1061 |
// Support optimal SSE move instructions. |
|
1062 |
void movflt(XMMRegister dst, XMMRegister src) { |
|
1063 |
if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
|
1064 |
else { movss (dst, src); return; } |
|
1065 |
} |
|
1066 |
||
1067 |
void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
|
1068 |
||
1069 |
void movflt(XMMRegister dst, AddressLiteral src); |
|
1070 |
||
1071 |
void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
|
1072 |
||
1073 |
void movdbl(XMMRegister dst, XMMRegister src) { |
|
1074 |
if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
|
1075 |
else { movsd (dst, src); return; } |
|
1076 |
} |
|
1077 |
||
1078 |
void movdbl(XMMRegister dst, AddressLiteral src); |
|
1079 |
||
1080 |
void movdbl(XMMRegister dst, Address src) { |
|
1081 |
if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
|
1082 |
else { movlpd(dst, src); return; } |
|
1083 |
} |
|
1084 |
||
1085 |
void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
|
1086 |
||
1087 |
void incrementl(AddressLiteral dst); |
|
1088 |
void incrementl(ArrayAddress dst); |
|
1089 |
||
1090 |
// Alignment |
|
1091 |
void align(int modulus); |
|
1092 |
||
1093 |
// Misc |
|
1094 |
void fat_nop(); // 5 byte nop |
|
1095 |
||
1096 |
||
1097 |
// C++ bool manipulation |
|
1098 |
||
1099 |
void movbool(Register dst, Address src); |
|
1100 |
void movbool(Address dst, bool boolconst); |
|
1101 |
void movbool(Address dst, Register src); |
|
1102 |
void testbool(Register dst); |
|
1103 |
||
360
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|
1104 |
// oop manipulations |
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|
1105 |
void load_klass(Register dst, Register src); |
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|
1106 |
void store_klass(Register dst, Register src); |
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diff
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|
1107 |
|
21d113ecbf6a
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diff
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|
1108 |
void load_heap_oop(Register dst, Address src); |
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|
1109 |
void store_heap_oop(Address dst, Register src); |
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|
1110 |
void encode_heap_oop(Register r); |
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|
1111 |
void decode_heap_oop(Register r); |
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|
1112 |
void encode_heap_oop_not_null(Register r); |
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|
1113 |
void decode_heap_oop_not_null(Register r); |
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|
1114 |
|
1 | 1115 |
// Stack frame creation/removal |
1116 |
void enter(); |
|
1117 |
void leave(); |
|
1118 |
||
1119 |
// Support for getting the JavaThread pointer (i.e.; a reference to |
|
1120 |
// thread-local information) The pointer will be loaded into the |
|
1121 |
// thread register. |
|
1122 |
void get_thread(Register thread); |
|
1123 |
||
1124 |
void int3(); |
|
1125 |
||
1126 |
// Support for VM calls |
|
1127 |
// |
|
1128 |
// It is imperative that all calls into the VM are handled via the |
|
1129 |
// call_VM macros. They make sure that the stack linkage is setup |
|
1130 |
// correctly. call_VM's correspond to ENTRY/ENTRY_X entry points |
|
1131 |
// while call_VM_leaf's correspond to LEAF entry points. |
|
1132 |
void call_VM(Register oop_result, |
|
1133 |
address entry_point, |
|
1134 |
bool check_exceptions = true); |
|
1135 |
void call_VM(Register oop_result, |
|
1136 |
address entry_point, |
|
1137 |
Register arg_1, |
|
1138 |
bool check_exceptions = true); |
|
1139 |
void call_VM(Register oop_result, |
|
1140 |
address entry_point, |
|
1141 |
Register arg_1, Register arg_2, |
|
1142 |
bool check_exceptions = true); |
|
1143 |
void call_VM(Register oop_result, |
|
1144 |
address entry_point, |
|
1145 |
Register arg_1, Register arg_2, Register arg_3, |
|
1146 |
bool check_exceptions = true); |
|
1147 |
||
1148 |
// Overloadings with last_Java_sp |
|
1149 |
void call_VM(Register oop_result, |
|
1150 |
Register last_java_sp, |
|
1151 |
address entry_point, |
|
1152 |
int number_of_arguments = 0, |
|
1153 |
bool check_exceptions = true); |
|
1154 |
void call_VM(Register oop_result, |
|
1155 |
Register last_java_sp, |
|
1156 |
address entry_point, |
|
1157 |
Register arg_1, bool |
|
1158 |
check_exceptions = true); |
|
1159 |
void call_VM(Register oop_result, |
|
1160 |
Register last_java_sp, |
|
1161 |
address entry_point, |
|
1162 |
Register arg_1, Register arg_2, |
|
1163 |
bool check_exceptions = true); |
|
1164 |
void call_VM(Register oop_result, |
|
1165 |
Register last_java_sp, |
|
1166 |
address entry_point, |
|
1167 |
Register arg_1, Register arg_2, Register arg_3, |
|
1168 |
bool check_exceptions = true); |
|
1169 |
||
1170 |
void call_VM_leaf(address entry_point, |
|
1171 |
int number_of_arguments = 0); |
|
1172 |
void call_VM_leaf(address entry_point, |
|
1173 |
Register arg_1); |
|
1174 |
void call_VM_leaf(address entry_point, |
|
1175 |
Register arg_1, Register arg_2); |
|
1176 |
void call_VM_leaf(address entry_point, |
|
1177 |
Register arg_1, Register arg_2, Register arg_3); |
|
1178 |
||
1179 |
// last Java Frame (fills frame anchor) |
|
1180 |
void set_last_Java_frame(Register last_java_sp, |
|
1181 |
Register last_java_fp, |
|
1182 |
address last_java_pc); |
|
1183 |
void reset_last_Java_frame(bool clear_fp, bool clear_pc); |
|
1184 |
||
1185 |
// Stores |
|
1186 |
void store_check(Register obj); // store check for |
|
1187 |
// obj - register is |
|
1188 |
// destroyed |
|
1189 |
// afterwards |
|
1190 |
void store_check(Register obj, Address dst); // same as above, dst |
|
1191 |
// is exact store |
|
1192 |
// location (reg. is |
|
1193 |
// destroyed) |
|
1194 |
||
1195 |
// split store_check(Register obj) to enhance instruction interleaving |
|
1196 |
void store_check_part_1(Register obj); |
|
1197 |
void store_check_part_2(Register obj); |
|
1198 |
||
1199 |
// C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
|
1200 |
void c2bool(Register x); |
|
1201 |
||
1202 |
// Int division/reminder for Java |
|
1203 |
// (as idivl, but checks for special case as described in JVM spec.) |
|
1204 |
// returns idivl instruction offset for implicit exception handling |
|
1205 |
int corrected_idivl(Register reg); |
|
1206 |
// Long division/reminder for Java |
|
1207 |
// (as idivq, but checks for special case as described in JVM spec.) |
|
1208 |
// returns idivq instruction offset for implicit exception handling |
|
1209 |
int corrected_idivq(Register reg); |
|
1210 |
||
1211 |
// Push and pop integer/fpu/cpu state |
|
1212 |
void push_IU_state(); |
|
1213 |
void pop_IU_state(); |
|
1214 |
||
1215 |
void push_FPU_state(); |
|
1216 |
void pop_FPU_state(); |
|
1217 |
||
1218 |
void push_CPU_state(); |
|
1219 |
void pop_CPU_state(); |
|
1220 |
||
1221 |
// Sign extension |
|
1222 |
void sign_extend_short(Register reg); |
|
1223 |
void sign_extend_byte(Register reg); |
|
1224 |
||
1225 |
// Division by power of 2, rounding towards 0 |
|
1226 |
void division_with_shift(Register reg, int shift_value); |
|
1227 |
||
1228 |
// Round up to a power of two |
|
1229 |
void round_to_l(Register reg, int modulus); |
|
1230 |
void round_to_q(Register reg, int modulus); |
|
1231 |
||
1232 |
// allocation |
|
1233 |
void eden_allocate( |
|
1234 |
Register obj, // result: pointer to object after |
|
1235 |
// successful allocation |
|
1236 |
Register var_size_in_bytes, // object size in bytes if unknown at |
|
1237 |
// compile time; invalid otherwise |
|
1238 |
int con_size_in_bytes, // object size in bytes if known at |
|
1239 |
// compile time |
|
1240 |
Register t1, // temp register |
|
1241 |
Label& slow_case // continuation point if fast |
|
1242 |
// allocation fails |
|
1243 |
); |
|
1244 |
void tlab_allocate( |
|
1245 |
Register obj, // result: pointer to object after |
|
1246 |
// successful allocation |
|
1247 |
Register var_size_in_bytes, // object size in bytes if unknown at |
|
1248 |
// compile time; invalid otherwise |
|
1249 |
int con_size_in_bytes, // object size in bytes if known at |
|
1250 |
// compile time |
|
1251 |
Register t1, // temp register |
|
1252 |
Register t2, // temp register |
|
1253 |
Label& slow_case // continuation point if fast |
|
1254 |
// allocation fails |
|
1255 |
); |
|
1256 |
void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); |
|
1257 |
||
1258 |
//---- |
|
1259 |
||
1260 |
// Debugging |
|
1261 |
||
1262 |
// only if +VerifyOops |
|
1263 |
void verify_oop(Register reg, const char* s = "broken oop"); |
|
1264 |
void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
|
1265 |
||
360
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|
1266 |
// if heap base register is used - reinit it with the correct value |
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|
1267 |
void reinit_heapbase(); |
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|
1268 |
|
1 | 1269 |
// only if +VerifyFPU |
1270 |
void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {} |
|
1271 |
||
1272 |
// prints msg, dumps registers and stops execution |
|
1273 |
void stop(const char* msg); |
|
1274 |
||
1275 |
// prints message and continues |
|
1276 |
void warn(const char* msg); |
|
1277 |
||
1278 |
static void debug(char* msg, int64_t pc, int64_t regs[]); |
|
1279 |
||
1280 |
void os_breakpoint(); |
|
1281 |
||
1282 |
void untested() |
|
1283 |
{ |
|
1284 |
stop("untested"); |
|
1285 |
} |
|
1286 |
||
1287 |
void unimplemented(const char* what = "") |
|
1288 |
{ |
|
1289 |
char* b = new char[1024]; |
|
1290 |
sprintf(b, "unimplemented: %s", what); |
|
1291 |
stop(b); |
|
1292 |
} |
|
1293 |
||
1294 |
void should_not_reach_here() |
|
1295 |
{ |
|
1296 |
stop("should not reach here"); |
|
1297 |
} |
|
1298 |
||
1299 |
// Stack overflow checking |
|
1300 |
void bang_stack_with_offset(int offset) |
|
1301 |
{ |
|
1302 |
// stack grows down, caller passes positive offset |
|
1303 |
assert(offset > 0, "must bang with negative offset"); |
|
1304 |
movl(Address(rsp, (-offset)), rax); |
|
1305 |
} |
|
1306 |
||
1307 |
// Writes to stack successive pages until offset reached to check for |
|
1308 |
// stack overflow + shadow pages. Also, clobbers tmp |
|
1309 |
void bang_stack_size(Register offset, Register tmp); |
|
1310 |
||
1311 |
// Support for serializing memory accesses between threads. |
|
1312 |
void serialize_memory(Register thread, Register tmp); |
|
1313 |
||
1314 |
void verify_tlab(); |
|
1315 |
||
1316 |
// Biased locking support |
|
1317 |
// lock_reg and obj_reg must be loaded up with the appropriate values. |
|
1318 |
// swap_reg must be rax and is killed. |
|
1319 |
// tmp_reg must be supplied and is killed. |
|
1320 |
// If swap_reg_contains_mark is true then the code assumes that the |
|
1321 |
// mark word of the object has already been loaded into swap_reg. |
|
1322 |
// Optional slow case is for implementations (interpreter and C1) which branch to |
|
1323 |
// slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
|
1324 |
// Returns offset of first potentially-faulting instruction for null |
|
1325 |
// check info (currently consumed only by C1). If |
|
1326 |
// swap_reg_contains_mark is true then returns -1 as it is assumed |
|
1327 |
// the calling code has already passed any potential faults. |
|
1328 |
int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, |
|
1329 |
bool swap_reg_contains_mark, |
|
1330 |
Label& done, Label* slow_case = NULL, |
|
1331 |
BiasedLockingCounters* counters = NULL); |
|
1332 |
void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
|
1333 |
||
1334 |
Condition negate_condition(Condition cond); |
|
1335 |
||
1336 |
// Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
|
1337 |
// operands. In general the names are modified to avoid hiding the instruction in Assembler |
|
1338 |
// so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
|
1339 |
// here in MacroAssembler. The major exception to this rule is call |
|
1340 |
||
1341 |
// Arithmetics |
|
1342 |
||
1343 |
void cmp8(AddressLiteral src1, int8_t imm32); |
|
1344 |
||
1345 |
void cmp32(AddressLiteral src1, int32_t src2); |
|
1346 |
// compare reg - mem, or reg - &mem |
|
1347 |
void cmp32(Register src1, AddressLiteral src2); |
|
1348 |
||
1349 |
void cmp32(Register src1, Address src2); |
|
1350 |
||
1351 |
#ifndef _LP64 |
|
1352 |
void cmpoop(Address dst, jobject obj); |
|
1353 |
void cmpoop(Register dst, jobject obj); |
|
1354 |
#endif // _LP64 |
|
1355 |
||
1356 |
// NOTE src2 must be the lval. This is NOT an mem-mem compare |
|
1357 |
void cmpptr(Address src1, AddressLiteral src2); |
|
1358 |
||
1359 |
void cmpptr(Register src1, AddressLiteral src); |
|
1360 |
||
1361 |
// will be cmpreg(?) |
|
1362 |
void cmp64(Register src1, AddressLiteral src); |
|
1363 |
||
1364 |
void cmpxchgptr(Register reg, Address adr); |
|
1365 |
void cmpxchgptr(Register reg, AddressLiteral adr); |
|
1366 |
||
1367 |
// Helper functions for statistics gathering. |
|
1368 |
// Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
|
1369 |
void cond_inc32(Condition cond, AddressLiteral counter_addr); |
|
1370 |
// Unconditional atomic increment. |
|
1371 |
void atomic_incl(AddressLiteral counter_addr); |
|
1372 |
||
1373 |
||
1374 |
void lea(Register dst, AddressLiteral src); |
|
1375 |
void lea(Register dst, Address src); |
|
1376 |
||
1377 |
||
1378 |
// Calls |
|
1379 |
void call(Label& L, relocInfo::relocType rtype); |
|
1380 |
void call(Register entry); |
|
1381 |
void call(AddressLiteral entry); |
|
1382 |
||
1383 |
// Jumps |
|
1384 |
||
1385 |
// 32bit can do a case table jump in one instruction but we no longer allow the base |
|
1386 |
// to be installed in the Address class |
|
1387 |
void jump(ArrayAddress entry); |
|
1388 |
||
1389 |
void jump(AddressLiteral entry); |
|
1390 |
void jump_cc(Condition cc, AddressLiteral dst); |
|
1391 |
||
1392 |
// Floating |
|
1393 |
||
1394 |
void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
|
1395 |
void ldmxcsr(AddressLiteral src); |
|
1396 |
||
1397 |
private: |
|
1398 |
// these are private because users should be doing movflt/movdbl |
|
1399 |
||
1400 |
void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
|
1401 |
void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
|
1402 |
void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
|
1403 |
void movss(XMMRegister dst, AddressLiteral src); |
|
1404 |
||
1405 |
void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
|
1406 |
void movlpd(XMMRegister dst, AddressLiteral src); |
|
1407 |
||
1408 |
public: |
|
1409 |
||
1410 |
||
1411 |
void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); } |
|
1412 |
void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); } |
|
1413 |
void xorpd(XMMRegister dst, AddressLiteral src); |
|
1414 |
||
1415 |
void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); } |
|
1416 |
void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); } |
|
1417 |
void xorps(XMMRegister dst, AddressLiteral src); |
|
1418 |
||
1419 |
||
1420 |
// Data |
|
1421 |
||
1422 |
void movoop(Register dst, jobject obj); |
|
1423 |
void movoop(Address dst, jobject obj); |
|
1424 |
||
1425 |
void movptr(ArrayAddress dst, Register src); |
|
1426 |
void movptr(Register dst, AddressLiteral src); |
|
1427 |
||
1428 |
void movptr(Register dst, intptr_t src); |
|
1429 |
void movptr(Address dst, intptr_t src); |
|
1430 |
||
1431 |
void movptr(Register dst, ArrayAddress src); |
|
1432 |
||
1433 |
// to avoid hiding movl |
|
1434 |
void mov32(AddressLiteral dst, Register src); |
|
1435 |
void mov32(Register dst, AddressLiteral src); |
|
1436 |
||
1437 |
void pushoop(jobject obj); |
|
1438 |
||
1439 |
// Can push value or effective address |
|
1440 |
void pushptr(AddressLiteral src); |
|
1441 |
||
1442 |
}; |
|
1443 |
||
1444 |
/** |
|
1445 |
* class SkipIfEqual: |
|
1446 |
* |
|
1447 |
* Instantiating this class will result in assembly code being output that will |
|
1448 |
* jump around any code emitted between the creation of the instance and it's |
|
1449 |
* automatic destruction at the end of a scope block, depending on the value of |
|
1450 |
* the flag passed to the constructor, which will be checked at run-time. |
|
1451 |
*/ |
|
1452 |
class SkipIfEqual { |
|
1453 |
private: |
|
1454 |
MacroAssembler* _masm; |
|
1455 |
Label _label; |
|
1456 |
||
1457 |
public: |
|
1458 |
SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
|
1459 |
~SkipIfEqual(); |
|
1460 |
}; |
|
1461 |
||
1462 |
||
1463 |
#ifdef ASSERT |
|
1464 |
inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
|
1465 |
#endif |