/*

 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "interp_masm_x86_32.hpp"

#include "interpreter/interpreter.hpp"

#include "interpreter/interpreterRuntime.hpp"

#include "oops/arrayOop.hpp"

#include "oops/markOop.hpp"

#include "oops/methodDataOop.hpp"

#include "oops/methodOop.hpp"

#include "prims/jvmtiExport.hpp"

#include "prims/jvmtiRedefineClassesTrace.hpp"

#include "prims/jvmtiThreadState.hpp"

#include "runtime/basicLock.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/sharedRuntime.hpp"

#ifdef TARGET_OS_FAMILY_linux

# include "thread_linux.inline.hpp"

#endif

#ifdef TARGET_OS_FAMILY_solaris

# include "thread_solaris.inline.hpp"

#endif

#ifdef TARGET_OS_FAMILY_windows

# include "thread_windows.inline.hpp"

#endif

#ifdef TARGET_OS_FAMILY_bsd

# include "thread_bsd.inline.hpp"

#endif

// Implementation of InterpreterMacroAssembler

#ifdef CC_INTERP

void InterpreterMacroAssembler::get_method(Register reg) {

  movptr(reg, Address(rbp, -(sizeof(BytecodeInterpreter) + 2 * wordSize)));

  movptr(reg, Address(reg, byte_offset_of(BytecodeInterpreter, _method)));

}

#endif // CC_INTERP

#ifndef CC_INTERP

void InterpreterMacroAssembler::call_VM_leaf_base(

  address entry_point,

  int     number_of_arguments

) {

  // interpreter specific

  //

  // Note: No need to save/restore bcp & locals (rsi & rdi) pointer

  //       since these are callee saved registers and no blocking/

  //       GC can happen in leaf calls.

  // Further Note: DO NOT save/restore bcp/locals. If a caller has

  // already saved them so that it can use rsi/rdi as temporaries

  // then a save/restore here will DESTROY the copy the caller

  // saved! There used to be a save_bcp() that only happened in

  // the ASSERT path (no restore_bcp). Which caused bizarre failures

  // when jvm built with ASSERTs.

#ifdef ASSERT

  { Label L;

    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);

    jcc(Assembler::equal, L);

    stop("InterpreterMacroAssembler::call_VM_leaf_base: last_sp != NULL");

    bind(L);

  }

#endif

  // super call

  MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);

  // interpreter specific

  // Used to ASSERT that rsi/rdi were equal to frame's bcp/locals

  // but since they may not have been saved (and we don't want to

  // save them here (see note above) the assert is invalid.

}

void InterpreterMacroAssembler::call_VM_base(

  Register oop_result,

  Register java_thread,

  Register last_java_sp,

  address  entry_point,

  int      number_of_arguments,

  bool     check_exceptions

) {

#ifdef ASSERT

  { Label L;

    cmpptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD);

    jcc(Assembler::equal, L);

    stop("InterpreterMacroAssembler::call_VM_base: last_sp != NULL");

    bind(L);

  }

#endif /* ASSERT */

  // interpreter specific

  //

  // Note: Could avoid restoring locals ptr (callee saved) - however doesn't

  //       really make a difference for these runtime calls, since they are

  //       slow anyway. Btw., bcp must be saved/restored since it may change

  //       due to GC.

  assert(java_thread == noreg , "not expecting a precomputed java thread");

  save_bcp();

  // super call

  MacroAssembler::call_VM_base(oop_result, java_thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);

  // interpreter specific

  restore_bcp();

  restore_locals();

}

void InterpreterMacroAssembler::check_and_handle_popframe(Register java_thread) {

  if (JvmtiExport::can_pop_frame()) {

    Label L;

    // Initiate popframe handling only if it is not already being processed.  If the flag

    // has the popframe_processing bit set, it means that this code is called *during* popframe

    // handling - we don't want to reenter.

    Register pop_cond = java_thread;  // Not clear if any other register is available...

    movl(pop_cond, Address(java_thread, JavaThread::popframe_condition_offset()));

    testl(pop_cond, JavaThread::popframe_pending_bit);

    jcc(Assembler::zero, L);

    testl(pop_cond, JavaThread::popframe_processing_bit);

    jcc(Assembler::notZero, L);

    // Call Interpreter::remove_activation_preserving_args_entry() to get the

    // address of the same-named entrypoint in the generated interpreter code.

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry));

    jmp(rax);

    bind(L);

    get_thread(java_thread);

  }

}

void InterpreterMacroAssembler::load_earlyret_value(TosState state) {

  get_thread(rcx);

  movl(rcx, Address(rcx, JavaThread::jvmti_thread_state_offset()));

  const Address tos_addr (rcx, JvmtiThreadState::earlyret_tos_offset());

  const Address oop_addr (rcx, JvmtiThreadState::earlyret_oop_offset());

  const Address val_addr (rcx, JvmtiThreadState::earlyret_value_offset());

  const Address val_addr1(rcx, JvmtiThreadState::earlyret_value_offset()

                             + in_ByteSize(wordSize));

  switch (state) {

    case atos: movptr(rax, oop_addr);

               movptr(oop_addr, NULL_WORD);

               verify_oop(rax, state);                break;

    case ltos:

               movl(rdx, val_addr1);               // fall through

    case btos:                                     // fall through

    case ctos:                                     // fall through

    case stos:                                     // fall through

    case itos: movl(rax, val_addr);                   break;

    case ftos: fld_s(val_addr);                       break;

    case dtos: fld_d(val_addr);                       break;

    case vtos: /* nothing to do */                    break;

    default  : ShouldNotReachHere();

  }

  // Clean up tos value in the thread object

  movl(tos_addr,  (int32_t) ilgl);

  movptr(val_addr,  NULL_WORD);

  NOT_LP64(movptr(val_addr1, NULL_WORD));

}

void InterpreterMacroAssembler::check_and_handle_earlyret(Register java_thread) {

  if (JvmtiExport::can_force_early_return()) {

    Label L;

    Register tmp = java_thread;

    movptr(tmp, Address(tmp, JavaThread::jvmti_thread_state_offset()));

    testptr(tmp, tmp);

    jcc(Assembler::zero, L); // if (thread->jvmti_thread_state() == NULL) exit;

    // Initiate earlyret handling only if it is not already being processed.

    // If the flag has the earlyret_processing bit set, it means that this code

    // is called *during* earlyret handling - we don't want to reenter.

    movl(tmp, Address(tmp, JvmtiThreadState::earlyret_state_offset()));

    cmpl(tmp, JvmtiThreadState::earlyret_pending);

    jcc(Assembler::notEqual, L);

    // Call Interpreter::remove_activation_early_entry() to get the address of the

    // same-named entrypoint in the generated interpreter code.

    get_thread(java_thread);

    movptr(tmp, Address(java_thread, JavaThread::jvmti_thread_state_offset()));

    pushl(Address(tmp, JvmtiThreadState::earlyret_tos_offset()));

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), 1);

    jmp(rax);

    bind(L);

    get_thread(java_thread);

  }

}

void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset) {

  assert(bcp_offset >= 0, "bcp is still pointing to start of bytecode");

  movl(reg, Address(rsi, bcp_offset));

  bswapl(reg);

  shrl(reg, 16);

}

void InterpreterMacroAssembler::get_cache_index_at_bcp(Register reg, int bcp_offset, size_t index_size) {

  assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");

  if (index_size == sizeof(u2)) {

    load_unsigned_short(reg, Address(rsi, bcp_offset));

  } else if (index_size == sizeof(u4)) {

    assert(EnableInvokeDynamic, "giant index used only for JSR 292");

    movl(reg, Address(rsi, bcp_offset));

    // Check if the secondary index definition is still ~x, otherwise

    // we have to change the following assembler code to calculate the

    // plain index.

    assert(constantPoolCacheOopDesc::decode_secondary_index(~123) == 123, "else change next line");

    notl(reg);  // convert to plain index

  } else if (index_size == sizeof(u1)) {

    assert(EnableInvokeDynamic, "tiny index used only for JSR 292");

    load_unsigned_byte(reg, Address(rsi, bcp_offset));

  } else {

    ShouldNotReachHere();

  }

}

void InterpreterMacroAssembler::get_cache_and_index_at_bcp(Register cache, Register index,

                                                           int bcp_offset, size_t index_size) {

  assert_different_registers(cache, index);

  get_cache_index_at_bcp(index, bcp_offset, index_size);

  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));

  assert(sizeof(ConstantPoolCacheEntry) == 4*wordSize, "adjust code below");

  shlptr(index, 2); // convert from field index to ConstantPoolCacheEntry index

}

void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache,

                                                                        Register index,

                                                                        Register bytecode,

                                                                        int byte_no,

                                                                        int bcp_offset,

                                                                        size_t index_size) {

  get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size);

  movptr(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));

  const int shift_count = (1 + byte_no) * BitsPerByte;

  shrptr(bytecode, shift_count);

}

void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache, Register tmp,

                                                               int bcp_offset, size_t index_size) {

  assert(cache != tmp, "must use different register");

  get_cache_index_at_bcp(tmp, bcp_offset, index_size);

  assert(sizeof(ConstantPoolCacheEntry) == 4*wordSize, "adjust code below");

                               // convert from field index to ConstantPoolCacheEntry index

                               // and from word offset to byte offset

  shll(tmp, 2 + LogBytesPerWord);

  movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));

                               // skip past the header

  addptr(cache, in_bytes(constantPoolCacheOopDesc::base_offset()));

  addptr(cache, tmp);            // construct pointer to cache entry

}

  // Generate a subtype check: branch to ok_is_subtype if sub_klass is

  // a subtype of super_klass.  EAX holds the super_klass.  Blows ECX.

  // Resets EDI to locals.  Register sub_klass cannot be any of the above.

void InterpreterMacroAssembler::gen_subtype_check( Register Rsub_klass, Label &ok_is_subtype ) {

  assert( Rsub_klass != rax, "rax, holds superklass" );

  assert( Rsub_klass != rcx, "used as a temp" );

  assert( Rsub_klass != rdi, "used as a temp, restored from locals" );

  // Profile the not-null value's klass.

  profile_typecheck(rcx, Rsub_klass, rdi); // blows rcx, reloads rdi

  // Do the check.

  check_klass_subtype(Rsub_klass, rax, rcx, ok_is_subtype); // blows rcx

  // Profile the failure of the check.

  profile_typecheck_failed(rcx); // blows rcx

}

void InterpreterMacroAssembler::f2ieee() {

  if (IEEEPrecision) {

    fstp_s(Address(rsp, 0));

    fld_s(Address(rsp, 0));

  }

}

void InterpreterMacroAssembler::d2ieee() {

  if (IEEEPrecision) {

    fstp_d(Address(rsp, 0));

    fld_d(Address(rsp, 0));

  }

}

// Java Expression Stack

void InterpreterMacroAssembler::pop_ptr(Register r) {

  pop(r);

}

void InterpreterMacroAssembler::pop_i(Register r) {

  pop(r);

}

void InterpreterMacroAssembler::pop_l(Register lo, Register hi) {

  pop(lo);

  pop(hi);

}

void InterpreterMacroAssembler::pop_f() {

  fld_s(Address(rsp, 0));

  addptr(rsp, 1 * wordSize);

}

void InterpreterMacroAssembler::pop_d() {

  fld_d(Address(rsp, 0));

  addptr(rsp, 2 * wordSize);

}

void InterpreterMacroAssembler::pop(TosState state) {

  switch (state) {

    case atos: pop_ptr(rax);                                 break;

    case btos:                                               // fall through

    case ctos:                                               // fall through

    case stos:                                               // fall through

    case itos: pop_i(rax);                                   break;

    case ltos: pop_l(rax, rdx);                              break;

    case ftos: pop_f();                                      break;

    case dtos: pop_d();                                      break;

    case vtos: /* nothing to do */                           break;

    default  : ShouldNotReachHere();

  }

  verify_oop(rax, state);

}

void InterpreterMacroAssembler::push_ptr(Register r) {

  push(r);

}

void InterpreterMacroAssembler::push_i(Register r) {

  push(r);

}

void InterpreterMacroAssembler::push_l(Register lo, Register hi) {

  push(hi);

  push(lo);

}

void InterpreterMacroAssembler::push_f() {

  // Do not schedule for no AGI! Never write beyond rsp!

  subptr(rsp, 1 * wordSize);

  fstp_s(Address(rsp, 0));

}

void InterpreterMacroAssembler::push_d(Register r) {

  // Do not schedule for no AGI! Never write beyond rsp!

  subptr(rsp, 2 * wordSize);

  fstp_d(Address(rsp, 0));

}

void InterpreterMacroAssembler::push(TosState state) {

  verify_oop(rax, state);

  switch (state) {

    case atos: push_ptr(rax); break;

    case btos:                                               // fall through

    case ctos:                                               // fall through

    case stos:                                               // fall through

    case itos: push_i(rax);                                    break;

    case ltos: push_l(rax, rdx);                               break;

    case ftos: push_f();                                       break;

    case dtos: push_d(rax);                                    break;

    case vtos: /* nothing to do */                             break;

    default  : ShouldNotReachHere();

  }

}

// Helpers for swap and dup

void InterpreterMacroAssembler::load_ptr(int n, Register val) {

  movptr(val, Address(rsp, Interpreter::expr_offset_in_bytes(n)));

}

void InterpreterMacroAssembler::store_ptr(int n, Register val) {

  movptr(Address(rsp, Interpreter::expr_offset_in_bytes(n)), val);

}

void InterpreterMacroAssembler::prepare_to_jump_from_interpreted() {

  // set sender sp

  lea(rsi, Address(rsp, wordSize));

  // record last_sp

  movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), rsi);

}

// Jump to from_interpreted entry of a call unless single stepping is possible

// in this thread in which case we must call the i2i entry

void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {

  prepare_to_jump_from_interpreted();

  if (JvmtiExport::can_post_interpreter_events()) {

    Label run_compiled_code;

    // JVMTI events, such as single-stepping, are implemented partly by avoiding running

    // compiled code in threads for which the event is enabled.  Check here for

    // interp_only_mode if these events CAN be enabled.

    get_thread(temp);

    // interp_only is an int, on little endian it is sufficient to test the byte only

    // Is a cmpl faster?

    cmpb(Address(temp, JavaThread::interp_only_mode_offset()), 0);

    jccb(Assembler::zero, run_compiled_code);

    jmp(Address(method, methodOopDesc::interpreter_entry_offset()));

    bind(run_compiled_code);

  }

  jmp(Address(method, methodOopDesc::from_interpreted_offset()));

}

// The following two routines provide a hook so that an implementation

// can schedule the dispatch in two parts.  Intel does not do this.

void InterpreterMacroAssembler::dispatch_prolog(TosState state, int step) {

  // Nothing Intel-specific to be done here.

}

void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) {

  dispatch_next(state, step);

}

void InterpreterMacroAssembler::dispatch_base(TosState state, address* table,

                                              bool verifyoop) {

  verify_FPU(1, state);

  if (VerifyActivationFrameSize) {

    Label L;

    mov(rcx, rbp);

    subptr(rcx, rsp);

    int min_frame_size = (frame::link_offset - frame::interpreter_frame_initial_sp_offset) * wordSize;

    cmpptr(rcx, min_frame_size);

    jcc(Assembler::greaterEqual, L);

    stop("broken stack frame");

    bind(L);

  }

  if (verifyoop) verify_oop(rax, state);

  Address index(noreg, rbx, Address::times_ptr);

  ExternalAddress tbl((address)table);

  ArrayAddress dispatch(tbl, index);

  jump(dispatch);

}

void InterpreterMacroAssembler::dispatch_only(TosState state) {

  dispatch_base(state, Interpreter::dispatch_table(state));

}

void InterpreterMacroAssembler::dispatch_only_normal(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state));

}

void InterpreterMacroAssembler::dispatch_only_noverify(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state), false);

}

void InterpreterMacroAssembler::dispatch_next(TosState state, int step) {

  // load next bytecode (load before advancing rsi to prevent AGI)

  load_unsigned_byte(rbx, Address(rsi, step));

  // advance rsi

  increment(rsi, step);

  dispatch_base(state, Interpreter::dispatch_table(state));

}

void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {

  // load current bytecode

  load_unsigned_byte(rbx, Address(rsi, 0));

  dispatch_base(state, table);

}

// remove activation

//

// Unlock the receiver if this is a synchronized method.

// Unlock any Java monitors from syncronized blocks.

// Remove the activation from the stack.

//

// If there are locked Java monitors

//    If throw_monitor_exception

//       throws IllegalMonitorStateException

//    Else if install_monitor_exception

//       installs IllegalMonitorStateException

//    Else

//       no error processing

void InterpreterMacroAssembler::remove_activation(TosState state, Register ret_addr,