//

// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

//

// AMD64 Architecture Description File

//----------REGISTER DEFINITION BLOCK------------------------------------------

// This information is used by the matcher and the register allocator to

// describe individual registers and classes of registers within the target

// archtecture.

register %{

//----------Architecture Description Register Definitions----------------------

// General Registers

// "reg_def"  name ( register save type, C convention save type,

//                   ideal register type, encoding );

// Register Save Types:

//

// NS  = No-Save:       The register allocator assumes that these registers

//                      can be used without saving upon entry to the method, &

//                      that they do not need to be saved at call sites.

//

// SOC = Save-On-Call:  The register allocator assumes that these registers

//                      can be used without saving upon entry to the method,

//                      but that they must be saved at call sites.

//

// SOE = Save-On-Entry: The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, but they do not need to be saved at call

//                      sites.

//

// AS  = Always-Save:   The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, & that they must be saved at call sites.

//

// Ideal Register Type is used to determine how to save & restore a

// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

//

// The encoding number is the actual bit-pattern placed into the opcodes.

// General Registers

// R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when

// used as byte registers)

// Previously set RBX, RSI, and RDI as save-on-entry for java code

// Turn off SOE in java-code due to frequent use of uncommon-traps.

// Now that allocator is better, turn on RSI and RDI as SOE registers.

reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());

reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());

reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());

reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());

reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());

reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());

reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());

reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());

reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());

reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());

// now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code

reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());

reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());

#ifdef _WIN64

reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());

reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());

reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());

reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());

#else

reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());

reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());

reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());

reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());

#endif

reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());

reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());

reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());

reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());

reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());

reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());

reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());

reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());

reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());

reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());

reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());

reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());

reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());

reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());

reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());

reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());

// Floating Point Registers

// Specify priority of register selection within phases of register

// allocation.  Highest priority is first.  A useful heuristic is to

// give registers a low priority when they are required by machine

// instructions, like EAX and EDX on I486, and choose no-save registers

// before save-on-call, & save-on-call before save-on-entry.  Registers

// which participate in fixed calling sequences should come last.

// Registers which are used as pairs must fall on an even boundary.

alloc_class chunk0(R10,         R10_H,

                   R11,         R11_H,

                   R8,          R8_H,

                   R9,          R9_H,

                   R12,         R12_H,

                   RCX,         RCX_H,

                   RBX,         RBX_H,

                   RDI,         RDI_H,

                   RDX,         RDX_H,

                   RSI,         RSI_H,

                   RAX,         RAX_H,

                   RBP,         RBP_H,

                   R13,         R13_H,

                   R14,         R14_H,

                   R15,         R15_H,

                   RSP,         RSP_H);

//----------Architecture Description Register Classes--------------------------

// Several register classes are automatically defined based upon information in

// this architecture description.

// 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )

// 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )

// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )

// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

//

// Class for all pointer registers (including RSP)

reg_class any_reg(RAX, RAX_H,

                  RDX, RDX_H,

                  RBP, RBP_H,

                  RDI, RDI_H,

                  RSI, RSI_H,

                  RCX, RCX_H,

                  RBX, RBX_H,

                  RSP, RSP_H,

                  R8,  R8_H,

                  R9,  R9_H,

                  R10, R10_H,

                  R11, R11_H,

                  R12, R12_H,

                  R13, R13_H,

                  R14, R14_H,

                  R15, R15_H);

// Class for all pointer registers except RSP

reg_class ptr_reg(RAX, RAX_H,

                  RDX, RDX_H,

                  RBP, RBP_H,

                  RDI, RDI_H,

                  RSI, RSI_H,

                  RCX, RCX_H,

                  RBX, RBX_H,

                  R8,  R8_H,

                  R9,  R9_H,

                  R10, R10_H,

                  R11, R11_H,

                  R13, R13_H,

                  R14, R14_H);

// Class for all pointer registers except RAX and RSP

reg_class ptr_no_rax_reg(RDX, RDX_H,

                         RBP, RBP_H,

                         RDI, RDI_H,

                         RSI, RSI_H,

                         RCX, RCX_H,

                         RBX, RBX_H,

                         R8,  R8_H,

                         R9,  R9_H,

                         R10, R10_H,

                         R11, R11_H,

                         R13, R13_H,

                         R14, R14_H);

reg_class ptr_no_rbp_reg(RDX, RDX_H,

                         RAX, RAX_H,

                         RDI, RDI_H,

                         RSI, RSI_H,

                         RCX, RCX_H,

                         RBX, RBX_H,

                         R8,  R8_H,

                         R9,  R9_H,

                         R10, R10_H,

                         R11, R11_H,

                         R13, R13_H,

                         R14, R14_H);

// Class for all pointer registers except RAX, RBX and RSP

reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,

                             RBP, RBP_H,

                             RDI, RDI_H,

                             RSI, RSI_H,

                             RCX, RCX_H,

                             R8,  R8_H,

                             R9,  R9_H,

                             R10, R10_H,

                             R11, R11_H,

                             R13, R13_H,

                             R14, R14_H);

// Singleton class for RAX pointer register

reg_class ptr_rax_reg(RAX, RAX_H);

// Singleton class for RBX pointer register

reg_class ptr_rbx_reg(RBX, RBX_H);

// Singleton class for RSI pointer register

reg_class ptr_rsi_reg(RSI, RSI_H);

// Singleton class for RDI pointer register

reg_class ptr_rdi_reg(RDI, RDI_H);

// Singleton class for RBP pointer register

reg_class ptr_rbp_reg(RBP, RBP_H);

// Singleton class for stack pointer

reg_class ptr_rsp_reg(RSP, RSP_H);

// Singleton class for TLS pointer

reg_class ptr_r15_reg(R15, R15_H);

// Class for all long registers (except RSP)

reg_class long_reg(RAX, RAX_H,

                   RDX, RDX_H,

                   RBP, RBP_H,

                   RDI, RDI_H,

                   RSI, RSI_H,

                   RCX, RCX_H,

                   RBX, RBX_H,

                   R8,  R8_H,

                   R9,  R9_H,

                   R10, R10_H,

                   R11, R11_H,

                   R13, R13_H,

                   R14, R14_H);

// Class for all long registers except RAX, RDX (and RSP)

reg_class long_no_rax_rdx_reg(RBP, RBP_H,

                              RDI, RDI_H,

                              RSI, RSI_H,

                              RCX, RCX_H,

                              RBX, RBX_H,

                              R8,  R8_H,

                              R9,  R9_H,

                              R10, R10_H,

                              R11, R11_H,

                              R13, R13_H,

                              R14, R14_H);

// Class for all long registers except RCX (and RSP)

reg_class long_no_rcx_reg(RBP, RBP_H,

                          RDI, RDI_H,

                          RSI, RSI_H,

                          RAX, RAX_H,

                          RDX, RDX_H,

                          RBX, RBX_H,

                          R8,  R8_H,

                          R9,  R9_H,

                          R10, R10_H,

                          R11, R11_H,

                          R13, R13_H,

                          R14, R14_H);

// Class for all long registers except RAX (and RSP)

reg_class long_no_rax_reg(RBP, RBP_H,

                          RDX, RDX_H,

                          RDI, RDI_H,

                          RSI, RSI_H,

                          RCX, RCX_H,

                          RBX, RBX_H,

                          R8,  R8_H,

                          R9,  R9_H,

                          R10, R10_H,

                          R11, R11_H,

                          R13, R13_H,

                          R14, R14_H);

// Singleton class for RAX long register

reg_class long_rax_reg(RAX, RAX_H);

// Singleton class for RCX long register

reg_class long_rcx_reg(RCX, RCX_H);

// Singleton class for RDX long register

reg_class long_rdx_reg(RDX, RDX_H);

// Class for all int registers (except RSP)

reg_class int_reg(RAX,

                  RDX,

                  RBP,

                  RDI,

                  RSI,

                  RCX,

                  RBX,

                  R8,

                  R9,

                  R10,

                  R11,

                  R13,

                  R14);

// Class for all int registers except RCX (and RSP)

reg_class int_no_rcx_reg(RAX,

                         RDX,

                         RBP,

                         RDI,

                         RSI,

                         RBX,

                         R8,

                         R9,

                         R10,

                         R11,

                         R13,

                         R14);

// Class for all int registers except RAX, RDX (and RSP)

reg_class int_no_rax_rdx_reg(RBP,

                             RDI,

                             RSI,

                             RCX,

                             RBX,

                             R8,

                             R9,

                             R10,

                             R11,

                             R13,

                             R14);

// Singleton class for RAX int register

reg_class int_rax_reg(RAX);

// Singleton class for RBX int register

reg_class int_rbx_reg(RBX);

// Singleton class for RCX int register

reg_class int_rcx_reg(RCX);

// Singleton class for RCX int register

reg_class int_rdx_reg(RDX);

// Singleton class for RCX int register

reg_class int_rdi_reg(RDI);

// Singleton class for instruction pointer

// reg_class ip_reg(RIP);

%}

//----------SOURCE BLOCK-------------------------------------------------------

// This is a block of C++ code which provides values, functions, and

// definitions necessary in the rest of the architecture description

source %{

#define   RELOC_IMM64    Assembler::imm_operand

#define   RELOC_DISP32   Assembler::disp32_operand

#define __ _masm.

static int preserve_SP_size() {

  return 3;  // rex.w, op, rm(reg/reg)

}

static int clear_avx_size() {

  return (Compile::current()->max_vector_size() > 16) ? 3 : 0;  // vzeroupper

}

// !!!!! Special hack to get all types of calls to specify the byte offset

//       from the start of the call to the point where the return address

//       will point.

int MachCallStaticJavaNode::ret_addr_offset()

{

  int offset = 5; // 5 bytes from start of call to where return address points

  offset += clear_avx_size();

  if (_method_handle_invoke)

    offset += preserve_SP_size();

  return offset;

}

int MachCallDynamicJavaNode::ret_addr_offset()

{

  int offset = 15; // 15 bytes from start of call to where return address points

  offset += clear_avx_size();

  return offset;

}

int MachCallRuntimeNode::ret_addr_offset() {

  int offset = 13; // movq r10,#addr; callq (r10)

  offset += clear_avx_size();

  return offset;

}

// Indicate if the safepoint node needs the polling page as an input,

// it does if the polling page is more than disp32 away.

bool SafePointNode::needs_polling_address_input()

{

  return Assembler::is_polling_page_far();

}

//

// Compute padding required for nodes which need alignment

//

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallStaticJavaDirectNode::compute_padding(int current_offset) const

{

  current_offset += clear_avx_size(); // skip vzeroupper

  current_offset += 1; // skip call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallStaticJavaHandleNode::compute_padding(int current_offset) const

{

  current_offset += preserve_SP_size();   // skip mov rbp, rsp

  current_offset += clear_avx_size(); // skip vzeroupper

  current_offset += 1; // skip call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// The address of the call instruction needs to be 4-byte aligned to

// ensure that it does not span a cache line so that it can be patched.

int CallDynamicJavaDirectNode::compute_padding(int current_offset) const

{

  current_offset += clear_avx_size(); // skip vzeroupper

  current_offset += 11; // skip movq instruction + call opcode byte

  return round_to(current_offset, alignment_required()) - current_offset;

}

// EMIT_RM()

void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {

  unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);

  cbuf.insts()->emit_int8(c);

}

// EMIT_CC()

void emit_cc(CodeBuffer &cbuf, int f1, int f2) {

  unsigned char c = (unsigned char) (f1 | f2);

  cbuf.insts()->emit_int8(c);

}

// EMIT_OPCODE()

void emit_opcode(CodeBuffer &cbuf, int code) {

  cbuf.insts()->emit_int8((unsigned char) code);

}

// EMIT_OPCODE() w/ relocation information

void emit_opcode(CodeBuffer &cbuf,

                 int code, relocInfo::relocType reloc, int offset, int format)

{

  cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);

  emit_opcode(cbuf, code);

}

// EMIT_D8()

void emit_d8(CodeBuffer &cbuf, int d8) {

  cbuf.insts()->emit_int8((unsigned char) d8);

}

// EMIT_D16()

void emit_d16(CodeBuffer &cbuf, int d16) {

  cbuf.insts()->emit_int16(d16);

}

// EMIT_D32()

void emit_d32(CodeBuffer &cbuf, int d32) {

  cbuf.insts()->emit_int32(d32);

}

// EMIT_D64()

void emit_d64(CodeBuffer &cbuf, int64_t d64) {

  cbuf.insts()->emit_int64(d64);

}

// emit 32 bit value and construct relocation entry from relocInfo::relocType

void emit_d32_reloc(CodeBuffer& cbuf,

                    int d32,

                    relocInfo::relocType reloc,

                    int format)

{

  assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");