author | roland |
Thu, 20 Sep 2012 16:49:17 +0200 | |
changeset 13886 | 8d82c4dfa722 |
parent 13728 | 882756847a04 |
child 13969 | d2a189b83b87 |
permissions | -rw-r--r-- |
1 | 1 |
// |
11794 | 2 |
// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
1 | 3 |
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 |
// |
|
5 |
// This code is free software; you can redistribute it and/or modify it |
|
6 |
// under the terms of the GNU General Public License version 2 only, as |
|
7 |
// published by the Free Software Foundation. |
|
8 |
// |
|
9 |
// This code is distributed in the hope that it will be useful, but WITHOUT |
|
10 |
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
11 |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
12 |
// version 2 for more details (a copy is included in the LICENSE file that |
|
13 |
// accompanied this code). |
|
14 |
// |
|
15 |
// You should have received a copy of the GNU General Public License version |
|
16 |
// 2 along with this work; if not, write to the Free Software Foundation, |
|
17 |
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
18 |
// |
|
5547
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5352
diff
changeset
|
19 |
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5352
diff
changeset
|
20 |
// or visit www.oracle.com if you need additional information or have any |
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5352
diff
changeset
|
21 |
// questions. |
1 | 22 |
// |
23 |
// |
|
24 |
||
25 |
// AMD64 Architecture Description File |
|
26 |
||
27 |
//----------REGISTER DEFINITION BLOCK------------------------------------------ |
|
28 |
// This information is used by the matcher and the register allocator to |
|
29 |
// describe individual registers and classes of registers within the target |
|
30 |
// archtecture. |
|
31 |
||
32 |
register %{ |
|
33 |
//----------Architecture Description Register Definitions---------------------- |
|
34 |
// General Registers |
|
35 |
// "reg_def" name ( register save type, C convention save type, |
|
36 |
// ideal register type, encoding ); |
|
37 |
// Register Save Types: |
|
38 |
// |
|
39 |
// NS = No-Save: The register allocator assumes that these registers |
|
40 |
// can be used without saving upon entry to the method, & |
|
41 |
// that they do not need to be saved at call sites. |
|
42 |
// |
|
43 |
// SOC = Save-On-Call: The register allocator assumes that these registers |
|
44 |
// can be used without saving upon entry to the method, |
|
45 |
// but that they must be saved at call sites. |
|
46 |
// |
|
47 |
// SOE = Save-On-Entry: The register allocator assumes that these registers |
|
48 |
// must be saved before using them upon entry to the |
|
49 |
// method, but they do not need to be saved at call |
|
50 |
// sites. |
|
51 |
// |
|
52 |
// AS = Always-Save: The register allocator assumes that these registers |
|
53 |
// must be saved before using them upon entry to the |
|
54 |
// method, & that they must be saved at call sites. |
|
55 |
// |
|
56 |
// Ideal Register Type is used to determine how to save & restore a |
|
57 |
// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
|
58 |
// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
|
59 |
// |
|
60 |
// The encoding number is the actual bit-pattern placed into the opcodes. |
|
61 |
||
62 |
// General Registers |
|
63 |
// R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when |
|
64 |
// used as byte registers) |
|
65 |
||
66 |
// Previously set RBX, RSI, and RDI as save-on-entry for java code |
|
67 |
// Turn off SOE in java-code due to frequent use of uncommon-traps. |
|
68 |
// Now that allocator is better, turn on RSI and RDI as SOE registers. |
|
69 |
||
70 |
reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); |
|
71 |
reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); |
|
72 |
||
73 |
reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); |
|
74 |
reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); |
|
75 |
||
76 |
reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); |
|
77 |
reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); |
|
78 |
||
79 |
reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); |
|
80 |
reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); |
|
81 |
||
82 |
reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); |
|
83 |
reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); |
|
84 |
||
85 |
// now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code |
|
86 |
reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); |
|
87 |
reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); |
|
88 |
||
89 |
#ifdef _WIN64 |
|
90 |
||
91 |
reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); |
|
92 |
reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); |
|
93 |
||
94 |
reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); |
|
95 |
reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); |
|
96 |
||
97 |
#else |
|
98 |
||
99 |
reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); |
|
100 |
reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); |
|
101 |
||
102 |
reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); |
|
103 |
reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); |
|
104 |
||
105 |
#endif |
|
106 |
||
107 |
reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); |
|
108 |
reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); |
|
109 |
||
110 |
reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); |
|
111 |
reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); |
|
112 |
||
113 |
reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); |
|
114 |
reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); |
|
115 |
||
116 |
reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); |
|
117 |
reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); |
|
118 |
||
119 |
reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); |
|
120 |
reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); |
|
121 |
||
122 |
reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); |
|
123 |
reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); |
|
124 |
||
125 |
reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); |
|
126 |
reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); |
|
127 |
||
128 |
reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); |
|
129 |
reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); |
|
130 |
||
131 |
||
132 |
// Floating Point Registers |
|
133 |
||
134 |
// Specify priority of register selection within phases of register |
|
135 |
// allocation. Highest priority is first. A useful heuristic is to |
|
136 |
// give registers a low priority when they are required by machine |
|
137 |
// instructions, like EAX and EDX on I486, and choose no-save registers |
|
138 |
// before save-on-call, & save-on-call before save-on-entry. Registers |
|
139 |
// which participate in fixed calling sequences should come last. |
|
140 |
// Registers which are used as pairs must fall on an even boundary. |
|
141 |
||
142 |
alloc_class chunk0(R10, R10_H, |
|
143 |
R11, R11_H, |
|
144 |
R8, R8_H, |
|
145 |
R9, R9_H, |
|
146 |
R12, R12_H, |
|
147 |
RCX, RCX_H, |
|
148 |
RBX, RBX_H, |
|
149 |
RDI, RDI_H, |
|
150 |
RDX, RDX_H, |
|
151 |
RSI, RSI_H, |
|
152 |
RAX, RAX_H, |
|
153 |
RBP, RBP_H, |
|
154 |
R13, R13_H, |
|
155 |
R14, R14_H, |
|
156 |
R15, R15_H, |
|
157 |
RSP, RSP_H); |
|
158 |
||
159 |
||
160 |
//----------Architecture Description Register Classes-------------------------- |
|
161 |
// Several register classes are automatically defined based upon information in |
|
162 |
// this architecture description. |
|
163 |
// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) |
|
164 |
// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) |
|
165 |
// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) |
|
166 |
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) |
|
167 |
// |
|
168 |
||
169 |
// Class for all pointer registers (including RSP) |
|
170 |
reg_class any_reg(RAX, RAX_H, |
|
171 |
RDX, RDX_H, |
|
172 |
RBP, RBP_H, |
|
173 |
RDI, RDI_H, |
|
174 |
RSI, RSI_H, |
|
175 |
RCX, RCX_H, |
|
176 |
RBX, RBX_H, |
|
177 |
RSP, RSP_H, |
|
178 |
R8, R8_H, |
|
179 |
R9, R9_H, |
|
180 |
R10, R10_H, |
|
181 |
R11, R11_H, |
|
182 |
R12, R12_H, |
|
183 |
R13, R13_H, |
|
184 |
R14, R14_H, |
|
185 |
R15, R15_H); |
|
186 |
||
187 |
// Class for all pointer registers except RSP |
|
188 |
reg_class ptr_reg(RAX, RAX_H, |
|
189 |
RDX, RDX_H, |
|
190 |
RBP, RBP_H, |
|
191 |
RDI, RDI_H, |
|
192 |
RSI, RSI_H, |
|
193 |
RCX, RCX_H, |
|
194 |
RBX, RBX_H, |
|
195 |
R8, R8_H, |
|
196 |
R9, R9_H, |
|
197 |
R10, R10_H, |
|
198 |
R11, R11_H, |
|
199 |
R13, R13_H, |
|
200 |
R14, R14_H); |
|
201 |
||
202 |
// Class for all pointer registers except RAX and RSP |
|
203 |
reg_class ptr_no_rax_reg(RDX, RDX_H, |
|
204 |
RBP, RBP_H, |
|
205 |
RDI, RDI_H, |
|
206 |
RSI, RSI_H, |
|
207 |
RCX, RCX_H, |
|
208 |
RBX, RBX_H, |
|
209 |
R8, R8_H, |
|
210 |
R9, R9_H, |
|
211 |
R10, R10_H, |
|
212 |
R11, R11_H, |
|
213 |
R13, R13_H, |
|
214 |
R14, R14_H); |
|
215 |
||
216 |
reg_class ptr_no_rbp_reg(RDX, RDX_H, |
|
217 |
RAX, RAX_H, |
|
218 |
RDI, RDI_H, |
|
219 |
RSI, RSI_H, |
|
220 |
RCX, RCX_H, |
|
221 |
RBX, RBX_H, |
|
222 |
R8, R8_H, |
|
223 |
R9, R9_H, |
|
224 |
R10, R10_H, |
|
225 |
R11, R11_H, |
|
226 |
R13, R13_H, |
|
227 |
R14, R14_H); |
|
228 |
||
229 |
// Class for all pointer registers except RAX, RBX and RSP |
|
230 |
reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, |
|
231 |
RBP, RBP_H, |
|
232 |
RDI, RDI_H, |
|
233 |
RSI, RSI_H, |
|
234 |
RCX, RCX_H, |
|
235 |
R8, R8_H, |
|
236 |
R9, R9_H, |
|
237 |
R10, R10_H, |
|
238 |
R11, R11_H, |
|
239 |
R13, R13_H, |
|
240 |
R14, R14_H); |
|
241 |
||
242 |
// Singleton class for RAX pointer register |
|
243 |
reg_class ptr_rax_reg(RAX, RAX_H); |
|
244 |
||
245 |
// Singleton class for RBX pointer register |
|
246 |
reg_class ptr_rbx_reg(RBX, RBX_H); |
|
247 |
||
248 |
// Singleton class for RSI pointer register |
|
249 |
reg_class ptr_rsi_reg(RSI, RSI_H); |
|
250 |
||
251 |
// Singleton class for RDI pointer register |
|
252 |
reg_class ptr_rdi_reg(RDI, RDI_H); |
|
253 |
||
254 |
// Singleton class for RBP pointer register |
|
255 |
reg_class ptr_rbp_reg(RBP, RBP_H); |
|
256 |
||
257 |
// Singleton class for stack pointer |
|
258 |
reg_class ptr_rsp_reg(RSP, RSP_H); |
|
259 |
||
260 |
// Singleton class for TLS pointer |
|
261 |
reg_class ptr_r15_reg(R15, R15_H); |
|
262 |
||
263 |
// Class for all long registers (except RSP) |
|
264 |
reg_class long_reg(RAX, RAX_H, |
|
265 |
RDX, RDX_H, |
|
266 |
RBP, RBP_H, |
|
267 |
RDI, RDI_H, |
|
268 |
RSI, RSI_H, |
|
269 |
RCX, RCX_H, |
|
270 |
RBX, RBX_H, |
|
271 |
R8, R8_H, |
|
272 |
R9, R9_H, |
|
273 |
R10, R10_H, |
|
274 |
R11, R11_H, |
|
275 |
R13, R13_H, |
|
276 |
R14, R14_H); |
|
277 |
||
278 |
// Class for all long registers except RAX, RDX (and RSP) |
|
279 |
reg_class long_no_rax_rdx_reg(RBP, RBP_H, |
|
280 |
RDI, RDI_H, |
|
281 |
RSI, RSI_H, |
|
282 |
RCX, RCX_H, |
|
283 |
RBX, RBX_H, |
|
284 |
R8, R8_H, |
|
285 |
R9, R9_H, |
|
286 |
R10, R10_H, |
|
287 |
R11, R11_H, |
|
288 |
R13, R13_H, |
|
289 |
R14, R14_H); |
|
290 |
||
291 |
// Class for all long registers except RCX (and RSP) |
|
292 |
reg_class long_no_rcx_reg(RBP, RBP_H, |
|
293 |
RDI, RDI_H, |
|
294 |
RSI, RSI_H, |
|
295 |
RAX, RAX_H, |
|
296 |
RDX, RDX_H, |
|
297 |
RBX, RBX_H, |
|
298 |
R8, R8_H, |
|
299 |
R9, R9_H, |
|
300 |
R10, R10_H, |
|
301 |
R11, R11_H, |
|
302 |
R13, R13_H, |
|
303 |
R14, R14_H); |
|
304 |
||
305 |
// Class for all long registers except RAX (and RSP) |
|
306 |
reg_class long_no_rax_reg(RBP, RBP_H, |
|
307 |
RDX, RDX_H, |
|
308 |
RDI, RDI_H, |
|
309 |
RSI, RSI_H, |
|
310 |
RCX, RCX_H, |
|
311 |
RBX, RBX_H, |
|
312 |
R8, R8_H, |
|
313 |
R9, R9_H, |
|
314 |
R10, R10_H, |
|
315 |
R11, R11_H, |
|
316 |
R13, R13_H, |
|
317 |
R14, R14_H); |
|
318 |
||
319 |
// Singleton class for RAX long register |
|
320 |
reg_class long_rax_reg(RAX, RAX_H); |
|
321 |
||
322 |
// Singleton class for RCX long register |
|
323 |
reg_class long_rcx_reg(RCX, RCX_H); |
|
324 |
||
325 |
// Singleton class for RDX long register |
|
326 |
reg_class long_rdx_reg(RDX, RDX_H); |
|
327 |
||
328 |
// Class for all int registers (except RSP) |
|
329 |
reg_class int_reg(RAX, |
|
330 |
RDX, |
|
331 |
RBP, |
|
332 |
RDI, |
|
333 |
RSI, |
|
334 |
RCX, |
|
335 |
RBX, |
|
336 |
R8, |
|
337 |
R9, |
|
338 |
R10, |
|
339 |
R11, |
|
340 |
R13, |
|
341 |
R14); |
|
342 |
||
343 |
// Class for all int registers except RCX (and RSP) |
|
344 |
reg_class int_no_rcx_reg(RAX, |
|
345 |
RDX, |
|
346 |
RBP, |
|
347 |
RDI, |
|
348 |
RSI, |
|
349 |
RBX, |
|
350 |
R8, |
|
351 |
R9, |
|
352 |
R10, |
|
353 |
R11, |
|
354 |
R13, |
|
355 |
R14); |
|
356 |
||
357 |
// Class for all int registers except RAX, RDX (and RSP) |
|
358 |
reg_class int_no_rax_rdx_reg(RBP, |
|
1066 | 359 |
RDI, |
1 | 360 |
RSI, |
361 |
RCX, |
|
362 |
RBX, |
|
363 |
R8, |
|
364 |
R9, |
|
365 |
R10, |
|
366 |
R11, |
|
367 |
R13, |
|
368 |
R14); |
|
369 |
||
370 |
// Singleton class for RAX int register |
|
371 |
reg_class int_rax_reg(RAX); |
|
372 |
||
373 |
// Singleton class for RBX int register |
|
374 |
reg_class int_rbx_reg(RBX); |
|
375 |
||
376 |
// Singleton class for RCX int register |
|
377 |
reg_class int_rcx_reg(RCX); |
|
378 |
||
379 |
// Singleton class for RCX int register |
|
380 |
reg_class int_rdx_reg(RDX); |
|
381 |
||
382 |
// Singleton class for RCX int register |
|
383 |
reg_class int_rdi_reg(RDI); |
|
384 |
||
385 |
// Singleton class for instruction pointer |
|
386 |
// reg_class ip_reg(RIP); |
|
387 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
388 |
%} |
1 | 389 |
|
390 |
//----------SOURCE BLOCK------------------------------------------------------- |
|
391 |
// This is a block of C++ code which provides values, functions, and |
|
392 |
// definitions necessary in the rest of the architecture description |
|
393 |
source %{ |
|
1066 | 394 |
#define RELOC_IMM64 Assembler::imm_operand |
1 | 395 |
#define RELOC_DISP32 Assembler::disp32_operand |
396 |
||
397 |
#define __ _masm. |
|
398 |
||
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
399 |
static int preserve_SP_size() { |
11427 | 400 |
return 3; // rex.w, op, rm(reg/reg) |
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
401 |
} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
402 |
|
1 | 403 |
// !!!!! Special hack to get all types of calls to specify the byte offset |
404 |
// from the start of the call to the point where the return address |
|
405 |
// will point. |
|
406 |
int MachCallStaticJavaNode::ret_addr_offset() |
|
407 |
{ |
|
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
408 |
int offset = 5; // 5 bytes from start of call to where return address points |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
409 |
if (_method_handle_invoke) |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
410 |
offset += preserve_SP_size(); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
411 |
return offset; |
1 | 412 |
} |
413 |
||
414 |
int MachCallDynamicJavaNode::ret_addr_offset() |
|
415 |
{ |
|
416 |
return 15; // 15 bytes from start of call to where return address points |
|
417 |
} |
|
418 |
||
419 |
// In os_cpu .ad file |
|
420 |
// int MachCallRuntimeNode::ret_addr_offset() |
|
421 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
422 |
// Indicate if the safepoint node needs the polling page as an input, |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
423 |
// it does if the polling page is more than disp32 away. |
1 | 424 |
bool SafePointNode::needs_polling_address_input() |
425 |
{ |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
426 |
return Assembler::is_polling_page_far(); |
1 | 427 |
} |
428 |
||
429 |
// |
|
430 |
// Compute padding required for nodes which need alignment |
|
431 |
// |
|
432 |
||
433 |
// The address of the call instruction needs to be 4-byte aligned to |
|
434 |
// ensure that it does not span a cache line so that it can be patched. |
|
435 |
int CallStaticJavaDirectNode::compute_padding(int current_offset) const |
|
436 |
{ |
|
437 |
current_offset += 1; // skip call opcode byte |
|
438 |
return round_to(current_offset, alignment_required()) - current_offset; |
|
439 |
} |
|
440 |
||
441 |
// The address of the call instruction needs to be 4-byte aligned to |
|
442 |
// ensure that it does not span a cache line so that it can be patched. |
|
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
443 |
int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
444 |
{ |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
445 |
current_offset += preserve_SP_size(); // skip mov rbp, rsp |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
446 |
current_offset += 1; // skip call opcode byte |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
447 |
return round_to(current_offset, alignment_required()) - current_offset; |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
448 |
} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
449 |
|
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
450 |
// The address of the call instruction needs to be 4-byte aligned to |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
451 |
// ensure that it does not span a cache line so that it can be patched. |
1 | 452 |
int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
453 |
{ |
|
454 |
current_offset += 11; // skip movq instruction + call opcode byte |
|
455 |
return round_to(current_offset, alignment_required()) - current_offset; |
|
456 |
} |
|
457 |
||
458 |
// EMIT_RM() |
|
6418 | 459 |
void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
1 | 460 |
unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
6418 | 461 |
cbuf.insts()->emit_int8(c); |
1 | 462 |
} |
463 |
||
464 |
// EMIT_CC() |
|
6418 | 465 |
void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
1 | 466 |
unsigned char c = (unsigned char) (f1 | f2); |
6418 | 467 |
cbuf.insts()->emit_int8(c); |
1 | 468 |
} |
469 |
||
470 |
// EMIT_OPCODE() |
|
6418 | 471 |
void emit_opcode(CodeBuffer &cbuf, int code) { |
472 |
cbuf.insts()->emit_int8((unsigned char) code); |
|
1 | 473 |
} |
474 |
||
475 |
// EMIT_OPCODE() w/ relocation information |
|
476 |
void emit_opcode(CodeBuffer &cbuf, |
|
477 |
int code, relocInfo::relocType reloc, int offset, int format) |
|
478 |
{ |
|
6418 | 479 |
cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
1 | 480 |
emit_opcode(cbuf, code); |
481 |
} |
|
482 |
||
483 |
// EMIT_D8() |
|
6418 | 484 |
void emit_d8(CodeBuffer &cbuf, int d8) { |
485 |
cbuf.insts()->emit_int8((unsigned char) d8); |
|
1 | 486 |
} |
487 |
||
488 |
// EMIT_D16() |
|
6418 | 489 |
void emit_d16(CodeBuffer &cbuf, int d16) { |
490 |
cbuf.insts()->emit_int16(d16); |
|
1 | 491 |
} |
492 |
||
493 |
// EMIT_D32() |
|
6418 | 494 |
void emit_d32(CodeBuffer &cbuf, int d32) { |
495 |
cbuf.insts()->emit_int32(d32); |
|
1 | 496 |
} |
497 |
||
498 |
// EMIT_D64() |
|
6418 | 499 |
void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
500 |
cbuf.insts()->emit_int64(d64); |
|
1 | 501 |
} |
502 |
||
503 |
// emit 32 bit value and construct relocation entry from relocInfo::relocType |
|
504 |
void emit_d32_reloc(CodeBuffer& cbuf, |
|
505 |
int d32, |
|
506 |
relocInfo::relocType reloc, |
|
507 |
int format) |
|
508 |
{ |
|
509 |
assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); |
|
6418 | 510 |
cbuf.relocate(cbuf.insts_mark(), reloc, format); |
511 |
cbuf.insts()->emit_int32(d32); |
|
1 | 512 |
} |
513 |
||
514 |
// emit 32 bit value and construct relocation entry from RelocationHolder |
|
6418 | 515 |
void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
1 | 516 |
#ifdef ASSERT |
517 |
if (rspec.reloc()->type() == relocInfo::oop_type && |
|
518 |
d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
519 |
assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
3905
diff
changeset
|
520 |
assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
1 | 521 |
} |
522 |
#endif |
|
6418 | 523 |
cbuf.relocate(cbuf.insts_mark(), rspec, format); |
524 |
cbuf.insts()->emit_int32(d32); |
|
1 | 525 |
} |
526 |
||
527 |
void emit_d32_reloc(CodeBuffer& cbuf, address addr) { |
|
6418 | 528 |
address next_ip = cbuf.insts_end() + 4; |
1 | 529 |
emit_d32_reloc(cbuf, (int) (addr - next_ip), |
530 |
external_word_Relocation::spec(addr), |
|
531 |
RELOC_DISP32); |
|
532 |
} |
|
533 |
||
534 |
||
535 |
// emit 64 bit value and construct relocation entry from relocInfo::relocType |
|
6418 | 536 |
void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
537 |
cbuf.relocate(cbuf.insts_mark(), reloc, format); |
|
538 |
cbuf.insts()->emit_int64(d64); |
|
1 | 539 |
} |
540 |
||
541 |
// emit 64 bit value and construct relocation entry from RelocationHolder |
|
6418 | 542 |
void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
1 | 543 |
#ifdef ASSERT |
544 |
if (rspec.reloc()->type() == relocInfo::oop_type && |
|
545 |
d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
546 |
assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
3908
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
3905
diff
changeset
|
547 |
assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
24b55ad4c228
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
3905
diff
changeset
|
548 |
"cannot embed scavengable oops in code"); |
1 | 549 |
} |
550 |
#endif |
|
6418 | 551 |
cbuf.relocate(cbuf.insts_mark(), rspec, format); |
552 |
cbuf.insts()->emit_int64(d64); |
|
1 | 553 |
} |
554 |
||
555 |
// Access stack slot for load or store |
|
556 |
void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) |
|
557 |
{ |
|
558 |
emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) |
|
559 |
if (-0x80 <= disp && disp < 0x80) { |
|
560 |
emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte |
|
561 |
emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte |
|
562 |
emit_d8(cbuf, disp); // Displacement // R/M byte |
|
563 |
} else { |
|
564 |
emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte |
|
565 |
emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte |
|
566 |
emit_d32(cbuf, disp); // Displacement // R/M byte |
|
567 |
} |
|
568 |
} |
|
569 |
||
570 |
// rRegI ereg, memory mem) %{ // emit_reg_mem |
|
571 |
void encode_RegMem(CodeBuffer &cbuf, |
|
572 |
int reg, |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
573 |
int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
1 | 574 |
{ |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
575 |
assert(disp_reloc == relocInfo::none, "cannot have disp"); |
1 | 576 |
int regenc = reg & 7; |
577 |
int baseenc = base & 7; |
|
578 |
int indexenc = index & 7; |
|
579 |
||
580 |
// There is no index & no scale, use form without SIB byte |
|
581 |
if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { |
|
582 |
// If no displacement, mode is 0x0; unless base is [RBP] or [R13] |
|
583 |
if (disp == 0 && base != RBP_enc && base != R13_enc) { |
|
584 |
emit_rm(cbuf, 0x0, regenc, baseenc); // * |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
585 |
} else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
1 | 586 |
// If 8-bit displacement, mode 0x1 |
587 |
emit_rm(cbuf, 0x1, regenc, baseenc); // * |
|
588 |
emit_d8(cbuf, disp); |
|
589 |
} else { |
|
590 |
// If 32-bit displacement |
|
591 |
if (base == -1) { // Special flag for absolute address |
|
592 |
emit_rm(cbuf, 0x0, regenc, 0x5); // * |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
593 |
if (disp_reloc != relocInfo::none) { |
1 | 594 |
emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
595 |
} else { |
|
596 |
emit_d32(cbuf, disp); |
|
597 |
} |
|
598 |
} else { |
|
599 |
// Normal base + offset |
|
600 |
emit_rm(cbuf, 0x2, regenc, baseenc); // * |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
601 |
if (disp_reloc != relocInfo::none) { |
1 | 602 |
emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
603 |
} else { |
|
604 |
emit_d32(cbuf, disp); |
|
605 |
} |
|
606 |
} |
|
607 |
} |
|
608 |
} else { |
|
609 |
// Else, encode with the SIB byte |
|
610 |
// If no displacement, mode is 0x0; unless base is [RBP] or [R13] |
|
611 |
if (disp == 0 && base != RBP_enc && base != R13_enc) { |
|
612 |
// If no displacement |
|
613 |
emit_rm(cbuf, 0x0, regenc, 0x4); // * |
|
614 |
emit_rm(cbuf, scale, indexenc, baseenc); |
|
615 |
} else { |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
616 |
if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
1 | 617 |
// If 8-bit displacement, mode 0x1 |
618 |
emit_rm(cbuf, 0x1, regenc, 0x4); // * |
|
619 |
emit_rm(cbuf, scale, indexenc, baseenc); |
|
620 |
emit_d8(cbuf, disp); |
|
621 |
} else { |
|
622 |
// If 32-bit displacement |
|
623 |
if (base == 0x04 ) { |
|
624 |
emit_rm(cbuf, 0x2, regenc, 0x4); |
|
625 |
emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? |
|
626 |
} else { |
|
627 |
emit_rm(cbuf, 0x2, regenc, 0x4); |
|
628 |
emit_rm(cbuf, scale, indexenc, baseenc); // * |
|
629 |
} |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
630 |
if (disp_reloc != relocInfo::none) { |
1 | 631 |
emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
632 |
} else { |
|
633 |
emit_d32(cbuf, disp); |
|
634 |
} |
|
635 |
} |
|
636 |
} |
|
637 |
} |
|
638 |
} |
|
639 |
||
10006 | 640 |
// This could be in MacroAssembler but it's fairly C2 specific |
641 |
void emit_cmpfp_fixup(MacroAssembler& _masm) { |
|
642 |
Label exit; |
|
643 |
__ jccb(Assembler::noParity, exit); |
|
644 |
__ pushf(); |
|
11427 | 645 |
// |
646 |
// comiss/ucomiss instructions set ZF,PF,CF flags and |
|
647 |
// zero OF,AF,SF for NaN values. |
|
648 |
// Fixup flags by zeroing ZF,PF so that compare of NaN |
|
649 |
// values returns 'less than' result (CF is set). |
|
650 |
// Leave the rest of flags unchanged. |
|
651 |
// |
|
652 |
// 7 6 5 4 3 2 1 0 |
|
653 |
// |S|Z|r|A|r|P|r|C| (r - reserved bit) |
|
654 |
// 0 0 1 0 1 0 1 1 (0x2B) |
|
655 |
// |
|
10006 | 656 |
__ andq(Address(rsp, 0), 0xffffff2b); |
657 |
__ popf(); |
|
658 |
__ bind(exit); |
|
11427 | 659 |
} |
660 |
||
661 |
void emit_cmpfp3(MacroAssembler& _masm, Register dst) { |
|
662 |
Label done; |
|
663 |
__ movl(dst, -1); |
|
664 |
__ jcc(Assembler::parity, done); |
|
665 |
__ jcc(Assembler::below, done); |
|
666 |
__ setb(Assembler::notEqual, dst); |
|
667 |
__ movzbl(dst, dst); |
|
668 |
__ bind(done); |
|
10006 | 669 |
} |
670 |
||
1 | 671 |
|
672 |
//============================================================================= |
|
7433 | 673 |
const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
674 |
||
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
675 |
int Compile::ConstantTable::calculate_table_base_offset() const { |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
676 |
return 0; // absolute addressing, no offset |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
677 |
} |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
678 |
|
7433 | 679 |
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
680 |
// Empty encoding |
|
681 |
} |
|
682 |
||
683 |
uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { |
|
684 |
return 0; |
|
685 |
} |
|
686 |
||
687 |
#ifndef PRODUCT |
|
688 |
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
|
689 |
st->print("# MachConstantBaseNode (empty encoding)"); |
|
690 |
} |
|
691 |
#endif |
|
692 |
||
693 |
||
694 |
//============================================================================= |
|
1 | 695 |
#ifndef PRODUCT |
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
696 |
void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
1 | 697 |
Compile* C = ra_->C; |
698 |
||
699 |
int framesize = C->frame_slots() << LogBytesPerInt; |
|
700 |
assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
701 |
// Remove wordSize for return addr which is already pushed. |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
702 |
framesize -= wordSize; |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
703 |
|
1 | 704 |
if (C->need_stack_bang(framesize)) { |
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
705 |
framesize -= wordSize; |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
706 |
st->print("# stack bang"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
707 |
st->print("\n\t"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
708 |
st->print("pushq rbp\t# Save rbp"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
709 |
if (framesize) { |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
710 |
st->print("\n\t"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
711 |
st->print("subq rsp, #%d\t# Create frame",framesize); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
712 |
} |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
713 |
} else { |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
714 |
st->print("subq rsp, #%d\t# Create frame",framesize); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
715 |
st->print("\n\t"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
716 |
framesize -= wordSize; |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
717 |
st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
1 | 718 |
} |
719 |
||
720 |
if (VerifyStackAtCalls) { |
|
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
721 |
st->print("\n\t"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
722 |
framesize -= wordSize; |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
723 |
st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
724 |
#ifdef ASSERT |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
725 |
st->print("\n\t"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
726 |
st->print("# stack alignment check"); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
727 |
#endif |
1 | 728 |
} |
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
729 |
st->cr(); |
1 | 730 |
} |
731 |
#endif |
|
732 |
||
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
733 |
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
1 | 734 |
Compile* C = ra_->C; |
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
735 |
MacroAssembler _masm(&cbuf); |
1 | 736 |
|
737 |
int framesize = C->frame_slots() << LogBytesPerInt; |
|
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
738 |
|
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11445
diff
changeset
|
739 |
__ verified_entry(framesize, C->need_stack_bang(framesize), false); |
1 | 740 |
|
6418 | 741 |
C->set_frame_complete(cbuf.insts_size()); |
1 | 742 |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
743 |
if (C->has_mach_constant_base_node()) { |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
744 |
// NOTE: We set the table base offset here because users might be |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
745 |
// emitted before MachConstantBaseNode. |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
746 |
Compile::ConstantTable& constant_table = C->constant_table(); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
747 |
constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
748 |
} |
1 | 749 |
} |
750 |
||
751 |
uint MachPrologNode::size(PhaseRegAlloc* ra_) const |
|
752 |
{ |
|
753 |
return MachNode::size(ra_); // too many variables; just compute it |
|
754 |
// the hard way |
|
755 |
} |
|
756 |
||
757 |
int MachPrologNode::reloc() const |
|
758 |
{ |
|
759 |
return 0; // a large enough number |
|
760 |
} |
|
761 |
||
762 |
//============================================================================= |
|
763 |
#ifndef PRODUCT |
|
764 |
void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
|
765 |
{ |
|
766 |
Compile* C = ra_->C; |
|
767 |
int framesize = C->frame_slots() << LogBytesPerInt; |
|
768 |
assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
769 |
// Remove word for return adr already pushed |
|
770 |
// and RBP |
|
771 |
framesize -= 2*wordSize; |
|
772 |
||
773 |
if (framesize) { |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
774 |
st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
1 | 775 |
st->print("\t"); |
776 |
} |
|
777 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
778 |
st->print_cr("popq rbp"); |
1 | 779 |
if (do_polling() && C->is_method_compilation()) { |
780 |
st->print("\t"); |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
781 |
if (Assembler::is_polling_page_far()) { |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
782 |
st->print_cr("movq rscratch1, #polling_page_address\n\t" |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
783 |
"testl rax, [rscratch1]\t" |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
784 |
"# Safepoint: poll for GC"); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
785 |
} else { |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
786 |
st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
787 |
"# Safepoint: poll for GC"); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
788 |
} |
1 | 789 |
} |
790 |
} |
|
791 |
#endif |
|
792 |
||
793 |
void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const |
|
794 |
{ |
|
795 |
Compile* C = ra_->C; |
|
796 |
int framesize = C->frame_slots() << LogBytesPerInt; |
|
797 |
assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
798 |
// Remove word for return adr already pushed |
|
799 |
// and RBP |
|
800 |
framesize -= 2*wordSize; |
|
801 |
||
802 |
// Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here |
|
803 |
||
804 |
if (framesize) { |
|
805 |
emit_opcode(cbuf, Assembler::REX_W); |
|
806 |
if (framesize < 0x80) { |
|
807 |
emit_opcode(cbuf, 0x83); // addq rsp, #framesize |
|
808 |
emit_rm(cbuf, 0x3, 0x00, RSP_enc); |
|
809 |
emit_d8(cbuf, framesize); |
|
810 |
} else { |
|
811 |
emit_opcode(cbuf, 0x81); // addq rsp, #framesize |
|
812 |
emit_rm(cbuf, 0x3, 0x00, RSP_enc); |
|
813 |
emit_d32(cbuf, framesize); |
|
814 |
} |
|
815 |
} |
|
816 |
||
817 |
// popq rbp |
|
818 |
emit_opcode(cbuf, 0x58 | RBP_enc); |
|
819 |
||
820 |
if (do_polling() && C->is_method_compilation()) { |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
821 |
MacroAssembler _masm(&cbuf); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
822 |
AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
823 |
if (Assembler::is_polling_page_far()) { |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
824 |
__ lea(rscratch1, polling_page); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
825 |
__ relocate(relocInfo::poll_return_type); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
826 |
__ testl(rax, Address(rscratch1, 0)); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
827 |
} else { |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
828 |
__ testl(rax, polling_page); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
829 |
} |
1 | 830 |
} |
831 |
} |
|
832 |
||
833 |
uint MachEpilogNode::size(PhaseRegAlloc* ra_) const |
|
834 |
{ |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
835 |
return MachNode::size(ra_); // too many variables; just compute it |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
836 |
// the hard way |
1 | 837 |
} |
838 |
||
839 |
int MachEpilogNode::reloc() const |
|
840 |
{ |
|
841 |
return 2; // a large enough number |
|
842 |
} |
|
843 |
||
844 |
const Pipeline* MachEpilogNode::pipeline() const |
|
845 |
{ |
|
846 |
return MachNode::pipeline_class(); |
|
847 |
} |
|
848 |
||
849 |
int MachEpilogNode::safepoint_offset() const |
|
850 |
{ |
|
851 |
return 0; |
|
852 |
} |
|
853 |
||
854 |
//============================================================================= |
|
855 |
||
856 |
enum RC { |
|
857 |
rc_bad, |
|
858 |
rc_int, |
|
859 |
rc_float, |
|
860 |
rc_stack |
|
861 |
}; |
|
862 |
||
863 |
static enum RC rc_class(OptoReg::Name reg) |
|
864 |
{ |
|
865 |
if( !OptoReg::is_valid(reg) ) return rc_bad; |
|
866 |
||
867 |
if (OptoReg::is_stack(reg)) return rc_stack; |
|
868 |
||
869 |
VMReg r = OptoReg::as_VMReg(reg); |
|
870 |
||
871 |
if (r->is_Register()) return rc_int; |
|
872 |
||
873 |
assert(r->is_XMMRegister(), "must be"); |
|
874 |
return rc_float; |
|
875 |
} |
|
876 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
877 |
// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
878 |
static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
879 |
int src_hi, int dst_hi, uint ireg, outputStream* st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
880 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
881 |
static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
882 |
int stack_offset, int reg, uint ireg, outputStream* st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
883 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
884 |
static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
885 |
int dst_offset, uint ireg, outputStream* st) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
886 |
if (cbuf) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
887 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
888 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
889 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
890 |
__ movq(Address(rsp, -8), rax); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
891 |
__ movl(rax, Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
892 |
__ movl(Address(rsp, dst_offset), rax); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
893 |
__ movq(rax, Address(rsp, -8)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
894 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
895 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
896 |
__ pushq(Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
897 |
__ popq (Address(rsp, dst_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
898 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
899 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
900 |
__ pushq(Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
901 |
__ popq (Address(rsp, dst_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
902 |
__ pushq(Address(rsp, src_offset+8)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
903 |
__ popq (Address(rsp, dst_offset+8)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
904 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
905 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
906 |
__ vmovdqu(Address(rsp, -32), xmm0); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
907 |
__ vmovdqu(xmm0, Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
908 |
__ vmovdqu(Address(rsp, dst_offset), xmm0); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
909 |
__ vmovdqu(xmm0, Address(rsp, -32)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
910 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
911 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
912 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
913 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
914 |
#ifndef PRODUCT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
915 |
} else { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
916 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
917 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
918 |
st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
919 |
"movl rax, [rsp + #%d]\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
920 |
"movl [rsp + #%d], rax\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
921 |
"movq rax, [rsp - #8]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
922 |
src_offset, dst_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
923 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
924 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
925 |
st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
926 |
"popq [rsp + #%d]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
927 |
src_offset, dst_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
928 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
929 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
930 |
st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
931 |
"popq [rsp + #%d]\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
932 |
"pushq [rsp + #%d]\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
933 |
"popq [rsp + #%d]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
934 |
src_offset, dst_offset, src_offset+8, dst_offset+8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
935 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
936 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
937 |
st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
938 |
"vmovdqu xmm0, [rsp + #%d]\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
939 |
"vmovdqu [rsp + #%d], xmm0\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
940 |
"vmovdqu xmm0, [rsp - #32]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
941 |
src_offset, dst_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
942 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
943 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
944 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
945 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
946 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
947 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
948 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
949 |
|
1 | 950 |
uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
951 |
PhaseRegAlloc* ra_, |
|
952 |
bool do_size, |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
953 |
outputStream* st) const { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
954 |
assert(cbuf != NULL || st != NULL, "sanity"); |
1 | 955 |
// Get registers to move |
956 |
OptoReg::Name src_second = ra_->get_reg_second(in(1)); |
|
957 |
OptoReg::Name src_first = ra_->get_reg_first(in(1)); |
|
958 |
OptoReg::Name dst_second = ra_->get_reg_second(this); |
|
959 |
OptoReg::Name dst_first = ra_->get_reg_first(this); |
|
960 |
||
961 |
enum RC src_second_rc = rc_class(src_second); |
|
962 |
enum RC src_first_rc = rc_class(src_first); |
|
963 |
enum RC dst_second_rc = rc_class(dst_second); |
|
964 |
enum RC dst_first_rc = rc_class(dst_first); |
|
965 |
||
966 |
assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), |
|
967 |
"must move at least 1 register" ); |
|
968 |
||
969 |
if (src_first == dst_first && src_second == dst_second) { |
|
970 |
// Self copy, no move |
|
971 |
return 0; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
972 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
973 |
if (bottom_type()->isa_vect() != NULL) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
974 |
uint ireg = ideal_reg(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
975 |
assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
976 |
assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
977 |
if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
978 |
// mem -> mem |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
979 |
int src_offset = ra_->reg2offset(src_first); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
980 |
int dst_offset = ra_->reg2offset(dst_first); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
981 |
vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
982 |
} else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
983 |
vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
984 |
} else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
985 |
int stack_offset = ra_->reg2offset(dst_first); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
986 |
vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
987 |
} else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
988 |
int stack_offset = ra_->reg2offset(src_first); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
989 |
vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
990 |
} else { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
991 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
992 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
993 |
return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
994 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
995 |
if (src_first_rc == rc_stack) { |
1 | 996 |
// mem -> |
997 |
if (dst_first_rc == rc_stack) { |
|
998 |
// mem -> mem |
|
999 |
assert(src_second != dst_first, "overlap"); |
|
1000 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1001 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1002 |
// 64-bit |
|
1003 |
int src_offset = ra_->reg2offset(src_first); |
|
1004 |
int dst_offset = ra_->reg2offset(dst_first); |
|
1005 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1006 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1007 |
__ pushq(Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1008 |
__ popq (Address(rsp, dst_offset)); |
1 | 1009 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1010 |
} else { |
1 | 1011 |
st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1012 |
"popq [rsp + #%d]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1013 |
src_offset, dst_offset); |
1 | 1014 |
#endif |
1015 |
} |
|
1016 |
} else { |
|
1017 |
// 32-bit |
|
1018 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1019 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1020 |
// No pushl/popl, so: |
|
1021 |
int src_offset = ra_->reg2offset(src_first); |
|
1022 |
int dst_offset = ra_->reg2offset(dst_first); |
|
1023 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1024 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1025 |
__ movq(Address(rsp, -8), rax); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1026 |
__ movl(rax, Address(rsp, src_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1027 |
__ movl(Address(rsp, dst_offset), rax); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1028 |
__ movq(rax, Address(rsp, -8)); |
1 | 1029 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1030 |
} else { |
1 | 1031 |
st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1032 |
"movl rax, [rsp + #%d]\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1033 |
"movl [rsp + #%d], rax\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1034 |
"movq rax, [rsp - #8]", |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1035 |
src_offset, dst_offset); |
1 | 1036 |
#endif |
1037 |
} |
|
1038 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1039 |
return 0; |
1 | 1040 |
} else if (dst_first_rc == rc_int) { |
1041 |
// mem -> gpr |
|
1042 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1043 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1044 |
// 64-bit |
|
1045 |
int offset = ra_->reg2offset(src_first); |
|
1046 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1047 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1048 |
__ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
1 | 1049 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1050 |
} else { |
1 | 1051 |
st->print("movq %s, [rsp + #%d]\t# spill", |
1052 |
Matcher::regName[dst_first], |
|
1053 |
offset); |
|
1054 |
#endif |
|
1055 |
} |
|
1056 |
} else { |
|
1057 |
// 32-bit |
|
1058 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1059 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1060 |
int offset = ra_->reg2offset(src_first); |
|
1061 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1062 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1063 |
__ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
1 | 1064 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1065 |
} else { |
1 | 1066 |
st->print("movl %s, [rsp + #%d]\t# spill", |
1067 |
Matcher::regName[dst_first], |
|
1068 |
offset); |
|
1069 |
#endif |
|
1070 |
} |
|
1071 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1072 |
return 0; |
1 | 1073 |
} else if (dst_first_rc == rc_float) { |
1074 |
// mem-> xmm |
|
1075 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1076 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1077 |
// 64-bit |
|
1078 |
int offset = ra_->reg2offset(src_first); |
|
1079 |
if (cbuf) { |
|
11427 | 1080 |
MacroAssembler _masm(cbuf); |
1081 |
__ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
|
1 | 1082 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1083 |
} else { |
1 | 1084 |
st->print("%s %s, [rsp + #%d]\t# spill", |
1085 |
UseXmmLoadAndClearUpper ? "movsd " : "movlpd", |
|
1086 |
Matcher::regName[dst_first], |
|
1087 |
offset); |
|
1088 |
#endif |
|
1089 |
} |
|
1090 |
} else { |
|
1091 |
// 32-bit |
|
1092 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1093 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1094 |
int offset = ra_->reg2offset(src_first); |
|
1095 |
if (cbuf) { |
|
11427 | 1096 |
MacroAssembler _masm(cbuf); |
1097 |
__ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
|
1 | 1098 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1099 |
} else { |
1 | 1100 |
st->print("movss %s, [rsp + #%d]\t# spill", |
1101 |
Matcher::regName[dst_first], |
|
1102 |
offset); |
|
1103 |
#endif |
|
1104 |
} |
|
1105 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1106 |
return 0; |
1 | 1107 |
} |
1108 |
} else if (src_first_rc == rc_int) { |
|
1109 |
// gpr -> |
|
1110 |
if (dst_first_rc == rc_stack) { |
|
1111 |
// gpr -> mem |
|
1112 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1113 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1114 |
// 64-bit |
|
1115 |
int offset = ra_->reg2offset(dst_first); |
|
1116 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1117 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1118 |
__ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
1 | 1119 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1120 |
} else { |
1 | 1121 |
st->print("movq [rsp + #%d], %s\t# spill", |
1122 |
offset, |
|
1123 |
Matcher::regName[src_first]); |
|
1124 |
#endif |
|
1125 |
} |
|
1126 |
} else { |
|
1127 |
// 32-bit |
|
1128 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1129 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1130 |
int offset = ra_->reg2offset(dst_first); |
|
1131 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1132 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1133 |
__ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
1 | 1134 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1135 |
} else { |
1 | 1136 |
st->print("movl [rsp + #%d], %s\t# spill", |
1137 |
offset, |
|
1138 |
Matcher::regName[src_first]); |
|
1139 |
#endif |
|
1140 |
} |
|
1141 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1142 |
return 0; |
1 | 1143 |
} else if (dst_first_rc == rc_int) { |
1144 |
// gpr -> gpr |
|
1145 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1146 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1147 |
// 64-bit |
|
1148 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1149 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1150 |
__ movq(as_Register(Matcher::_regEncode[dst_first]), |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1151 |
as_Register(Matcher::_regEncode[src_first])); |
1 | 1152 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1153 |
} else { |
1 | 1154 |
st->print("movq %s, %s\t# spill", |
1155 |
Matcher::regName[dst_first], |
|
1156 |
Matcher::regName[src_first]); |
|
1157 |
#endif |
|
1158 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1159 |
return 0; |
1 | 1160 |
} else { |
1161 |
// 32-bit |
|
1162 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1163 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1164 |
if (cbuf) { |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1165 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1166 |
__ movl(as_Register(Matcher::_regEncode[dst_first]), |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1167 |
as_Register(Matcher::_regEncode[src_first])); |
1 | 1168 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1169 |
} else { |
1 | 1170 |
st->print("movl %s, %s\t# spill", |
1171 |
Matcher::regName[dst_first], |
|
1172 |
Matcher::regName[src_first]); |
|
1173 |
#endif |
|
1174 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1175 |
return 0; |
1 | 1176 |
} |
1177 |
} else if (dst_first_rc == rc_float) { |
|
1178 |
// gpr -> xmm |
|
1179 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1180 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1181 |
// 64-bit |
|
1182 |
if (cbuf) { |
|
11427 | 1183 |
MacroAssembler _masm(cbuf); |
1184 |
__ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); |
|
1 | 1185 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1186 |
} else { |
1 | 1187 |
st->print("movdq %s, %s\t# spill", |
1188 |
Matcher::regName[dst_first], |
|
1189 |
Matcher::regName[src_first]); |
|
1190 |
#endif |
|
1191 |
} |
|
1192 |
} else { |
|
1193 |
// 32-bit |
|
1194 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1195 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1196 |
if (cbuf) { |
|
11427 | 1197 |
MacroAssembler _masm(cbuf); |
1198 |
__ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); |
|
1 | 1199 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1200 |
} else { |
1 | 1201 |
st->print("movdl %s, %s\t# spill", |
1202 |
Matcher::regName[dst_first], |
|
1203 |
Matcher::regName[src_first]); |
|
1204 |
#endif |
|
1205 |
} |
|
1206 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1207 |
return 0; |
1 | 1208 |
} |
1209 |
} else if (src_first_rc == rc_float) { |
|
1210 |
// xmm -> |
|
1211 |
if (dst_first_rc == rc_stack) { |
|
1212 |
// xmm -> mem |
|
1213 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1214 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1215 |
// 64-bit |
|
1216 |
int offset = ra_->reg2offset(dst_first); |
|
1217 |
if (cbuf) { |
|
11427 | 1218 |
MacroAssembler _masm(cbuf); |
1219 |
__ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1220 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1221 |
} else { |
1 | 1222 |
st->print("movsd [rsp + #%d], %s\t# spill", |
1223 |
offset, |
|
1224 |
Matcher::regName[src_first]); |
|
1225 |
#endif |
|
1226 |
} |
|
1227 |
} else { |
|
1228 |
// 32-bit |
|
1229 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1230 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1231 |
int offset = ra_->reg2offset(dst_first); |
|
1232 |
if (cbuf) { |
|
11427 | 1233 |
MacroAssembler _masm(cbuf); |
1234 |
__ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1235 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1236 |
} else { |
1 | 1237 |
st->print("movss [rsp + #%d], %s\t# spill", |
1238 |
offset, |
|
1239 |
Matcher::regName[src_first]); |
|
1240 |
#endif |
|
1241 |
} |
|
1242 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1243 |
return 0; |
1 | 1244 |
} else if (dst_first_rc == rc_int) { |
1245 |
// xmm -> gpr |
|
1246 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1247 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1248 |
// 64-bit |
|
1249 |
if (cbuf) { |
|
11427 | 1250 |
MacroAssembler _masm(cbuf); |
1251 |
__ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1252 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1253 |
} else { |
1 | 1254 |
st->print("movdq %s, %s\t# spill", |
1255 |
Matcher::regName[dst_first], |
|
1256 |
Matcher::regName[src_first]); |
|
1257 |
#endif |
|
1258 |
} |
|
1259 |
} else { |
|
1260 |
// 32-bit |
|
1261 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1262 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1263 |
if (cbuf) { |
|
11427 | 1264 |
MacroAssembler _masm(cbuf); |
1265 |
__ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1266 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1267 |
} else { |
1 | 1268 |
st->print("movdl %s, %s\t# spill", |
1269 |
Matcher::regName[dst_first], |
|
1270 |
Matcher::regName[src_first]); |
|
1271 |
#endif |
|
1272 |
} |
|
1273 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1274 |
return 0; |
1 | 1275 |
} else if (dst_first_rc == rc_float) { |
1276 |
// xmm -> xmm |
|
1277 |
if ((src_first & 1) == 0 && src_first + 1 == src_second && |
|
1278 |
(dst_first & 1) == 0 && dst_first + 1 == dst_second) { |
|
1279 |
// 64-bit |
|
1280 |
if (cbuf) { |
|
11427 | 1281 |
MacroAssembler _masm(cbuf); |
1282 |
__ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1283 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1284 |
} else { |
1 | 1285 |
st->print("%s %s, %s\t# spill", |
1286 |
UseXmmRegToRegMoveAll ? "movapd" : "movsd ", |
|
1287 |
Matcher::regName[dst_first], |
|
1288 |
Matcher::regName[src_first]); |
|
1289 |
#endif |
|
1290 |
} |
|
1291 |
} else { |
|
1292 |
// 32-bit |
|
1293 |
assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); |
|
1294 |
assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); |
|
1295 |
if (cbuf) { |
|
11427 | 1296 |
MacroAssembler _masm(cbuf); |
1297 |
__ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); |
|
1 | 1298 |
#ifndef PRODUCT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1299 |
} else { |
1 | 1300 |
st->print("%s %s, %s\t# spill", |
1301 |
UseXmmRegToRegMoveAll ? "movaps" : "movss ", |
|
1302 |
Matcher::regName[dst_first], |
|
1303 |
Matcher::regName[src_first]); |
|
1304 |
#endif |
|
1305 |
} |
|
1306 |
} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1307 |
return 0; |
1 | 1308 |
} |
1309 |
} |
|
1310 |
||
1311 |
assert(0," foo "); |
|
1312 |
Unimplemented(); |
|
1313 |
return 0; |
|
1314 |
} |
|
1315 |
||
1316 |
#ifndef PRODUCT |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1317 |
void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
1 | 1318 |
implementation(NULL, ra_, false, st); |
1319 |
} |
|
1320 |
#endif |
|
1321 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1322 |
void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
1 | 1323 |
implementation(&cbuf, ra_, false, NULL); |
1324 |
} |
|
1325 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1326 |
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1327 |
return MachNode::size(ra_); |
1 | 1328 |
} |
1329 |
||
1330 |
//============================================================================= |
|
1331 |
#ifndef PRODUCT |
|
1332 |
void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
|
1333 |
{ |
|
1334 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1335 |
int reg = ra_->get_reg_first(this); |
|
1336 |
st->print("leaq %s, [rsp + #%d]\t# box lock", |
|
1337 |
Matcher::regName[reg], offset); |
|
1338 |
} |
|
1339 |
#endif |
|
1340 |
||
1341 |
void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const |
|
1342 |
{ |
|
1343 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1344 |
int reg = ra_->get_encode(this); |
|
1345 |
if (offset >= 0x80) { |
|
1346 |
emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); |
|
1347 |
emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] |
|
1348 |
emit_rm(cbuf, 0x2, reg & 7, 0x04); |
|
1349 |
emit_rm(cbuf, 0x0, 0x04, RSP_enc); |
|
1350 |
emit_d32(cbuf, offset); |
|
1351 |
} else { |
|
1352 |
emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); |
|
1353 |
emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] |
|
1354 |
emit_rm(cbuf, 0x1, reg & 7, 0x04); |
|
1355 |
emit_rm(cbuf, 0x0, 0x04, RSP_enc); |
|
1356 |
emit_d8(cbuf, offset); |
|
1357 |
} |
|
1358 |
} |
|
1359 |
||
1360 |
uint BoxLockNode::size(PhaseRegAlloc *ra_) const |
|
1361 |
{ |
|
1362 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1363 |
return (offset < 0x80) ? 5 : 8; // REX |
|
1364 |
} |
|
1365 |
||
1366 |
//============================================================================= |
|
1367 |
||
1368 |
// emit call stub, compiled java to interpreter |
|
1369 |
void emit_java_to_interp(CodeBuffer& cbuf) |
|
1370 |
{ |
|
1371 |
// Stub is fixed up when the corresponding call is converted from |
|
1372 |
// calling compiled code to calling interpreted code. |
|
1373 |
// movq rbx, 0 |
|
1374 |
// jmp -5 # to self |
|
1375 |
||
6418 | 1376 |
address mark = cbuf.insts_mark(); // get mark within main instrs section |
1377 |
||
1378 |
// Note that the code buffer's insts_mark is always relative to insts. |
|
1 | 1379 |
// That's why we must use the macroassembler to generate a stub. |
1380 |
MacroAssembler _masm(&cbuf); |
|
1381 |
||
1382 |
address base = |
|
1383 |
__ start_a_stub(Compile::MAX_stubs_size); |
|
1384 |
if (base == NULL) return; // CodeBuffer::expand failed |
|
1385 |
// static stub relocation stores the instruction address of the call |
|
1386 |
__ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
1387 |
// static stub relocation also tags the Method* in the code-stream. |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
1388 |
__ mov_metadata(rbx, (Metadata*) NULL); // method is zapped till fixup time |
1066 | 1389 |
// This is recognized as unresolved by relocs/nativeinst/ic code |
1 | 1390 |
__ jump(RuntimeAddress(__ pc())); |
1391 |
||
6418 | 1392 |
// Update current stubs pointer and restore insts_end. |
1 | 1393 |
__ end_a_stub(); |
1394 |
} |
|
1395 |
||
1396 |
// size of call stub, compiled java to interpretor |
|
1397 |
uint size_java_to_interp() |
|
1398 |
{ |
|
1399 |
return 15; // movq (1+1+8); jmp (1+4) |
|
1400 |
} |
|
1401 |
||
1402 |
// relocation entries for call stub, compiled java to interpretor |
|
1403 |
uint reloc_java_to_interp() |
|
1404 |
{ |
|
1405 |
return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call |
|
1406 |
} |
|
1407 |
||
1408 |
//============================================================================= |
|
1409 |
#ifndef PRODUCT |
|
1410 |
void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
|
1411 |
{ |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1412 |
if (UseCompressedOops) { |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1413 |
st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
1414 |
if (Universe::narrow_oop_shift() != 0) { |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1415 |
st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1"); |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1416 |
} |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1417 |
st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1418 |
} else { |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1419 |
st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1420 |
"# Inline cache check"); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1421 |
} |
1 | 1422 |
st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1423 |
st->print_cr("\tnop\t# nops to align entry point"); |
1 | 1424 |
} |
1425 |
#endif |
|
1426 |
||
1427 |
void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const |
|
1428 |
{ |
|
1429 |
MacroAssembler masm(&cbuf); |
|
6418 | 1430 |
uint insts_size = cbuf.insts_size(); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1431 |
if (UseCompressedOops) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1432 |
masm.load_klass(rscratch1, j_rarg0); |
1066 | 1433 |
masm.cmpptr(rax, rscratch1); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1434 |
} else { |
1066 | 1435 |
masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1436 |
} |
1 | 1437 |
|
1438 |
masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); |
|
1439 |
||
1440 |
/* WARNING these NOPs are critical so that verified entry point is properly |
|
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1441 |
4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
6418 | 1442 |
int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1443 |
if (OptoBreakpoint) { |
1 | 1444 |
// Leave space for int3 |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1445 |
nops_cnt -= 1; |
1 | 1446 |
} |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1447 |
nops_cnt &= 0x3; // Do not add nops if code is aligned. |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1448 |
if (nops_cnt > 0) |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1449 |
masm.nop(nops_cnt); |
1 | 1450 |
} |
1451 |
||
1452 |
uint MachUEPNode::size(PhaseRegAlloc* ra_) const |
|
1453 |
{ |
|
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1454 |
return MachNode::size(ra_); // too many variables; just compute it |
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
1455 |
// the hard way |
1 | 1456 |
} |
1457 |
||
1458 |
||
1459 |
//============================================================================= |
|
1460 |
uint size_exception_handler() |
|
1461 |
{ |
|
1462 |
// NativeCall instruction size is the same as NativeJump. |
|
1463 |
// Note that this value is also credited (in output.cpp) to |
|
1464 |
// the size of the code section. |
|
1465 |
return NativeJump::instruction_size; |
|
1466 |
} |
|
1467 |
||
1468 |
// Emit exception handler code. |
|
1469 |
int emit_exception_handler(CodeBuffer& cbuf) |
|
1470 |
{ |
|
1471 |
||
6418 | 1472 |
// Note that the code buffer's insts_mark is always relative to insts. |
1 | 1473 |
// That's why we must use the macroassembler to generate a handler. |
1474 |
MacroAssembler _masm(&cbuf); |
|
1475 |
address base = |
|
1476 |
__ start_a_stub(size_exception_handler()); |
|
1477 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
1478 |
int offset = __ offset(); |
|
6418 | 1479 |
__ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
1 | 1480 |
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
1481 |
__ end_a_stub(); |
|
1482 |
return offset; |
|
1483 |
} |
|
1484 |
||
1485 |
uint size_deopt_handler() |
|
1486 |
{ |
|
1487 |
// three 5 byte instructions |
|
1488 |
return 15; |
|
1489 |
} |
|
1490 |
||
1491 |
// Emit deopt handler code. |
|
1492 |
int emit_deopt_handler(CodeBuffer& cbuf) |
|
1493 |
{ |
|
1494 |
||
6418 | 1495 |
// Note that the code buffer's insts_mark is always relative to insts. |
1 | 1496 |
// That's why we must use the macroassembler to generate a handler. |
1497 |
MacroAssembler _masm(&cbuf); |
|
1498 |
address base = |
|
1499 |
__ start_a_stub(size_deopt_handler()); |
|
1500 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
1501 |
int offset = __ offset(); |
|
1502 |
address the_pc = (address) __ pc(); |
|
1503 |
Label next; |
|
1504 |
// push a "the_pc" on the stack without destroying any registers |
|
1505 |
// as they all may be live. |
|
1506 |
||
1507 |
// push address of "next" |
|
1508 |
__ call(next, relocInfo::none); // reloc none is fine since it is a disp32 |
|
1509 |
__ bind(next); |
|
1510 |
// adjust it so it matches "the_pc" |
|
1066 | 1511 |
__ subptr(Address(rsp, 0), __ offset() - offset); |
1 | 1512 |
__ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
1513 |
assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); |
|
1514 |
__ end_a_stub(); |
|
1515 |
return offset; |
|
1516 |
} |
|
1517 |
||
1518 |
int Matcher::regnum_to_fpu_offset(int regnum) |
|
1519 |
{ |
|
1520 |
return regnum - 32; // The FP registers are in the second chunk |
|
1521 |
} |
|
1522 |
||
1523 |
// This is UltraSparc specific, true just means we have fast l2f conversion |
|
1524 |
const bool Matcher::convL2FSupported(void) { |
|
1525 |
return true; |
|
1526 |
} |
|
1527 |
||
1528 |
// Is this branch offset short enough that a short branch can be used? |
|
1529 |
// |
|
1530 |
// NOTE: If the platform does not provide any short branch variants, then |
|
1531 |
// this method should return false for offset 0. |
|
10264 | 1532 |
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1533 |
// The passed offset is relative to address of the branch. |
|
1534 |
// On 86 a branch displacement is calculated relative to address |
|
1535 |
// of a next instruction. |
|
1536 |
offset -= br_size; |
|
1537 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
1538 |
// the short version of jmpConUCF2 contains multiple branches, |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
1539 |
// making the reach slightly less |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
1540 |
if (rule == jmpConUCF2_rule) |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
1541 |
return (-126 <= offset && offset <= 125); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
1542 |
return (-128 <= offset && offset <= 127); |
1 | 1543 |
} |
1544 |
||
1545 |
const bool Matcher::isSimpleConstant64(jlong value) { |
|
1546 |
// Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. |
|
1547 |
//return value == (int) value; // Cf. storeImmL and immL32. |
|
1548 |
||
1549 |
// Probably always true, even if a temp register is required. |
|
1550 |
return true; |
|
1551 |
} |
|
1552 |
||
1553 |
// The ecx parameter to rep stosq for the ClearArray node is in words. |
|
1554 |
const bool Matcher::init_array_count_is_in_bytes = false; |
|
1555 |
||
1556 |
// Threshold size for cleararray. |
|
1557 |
const int Matcher::init_array_short_size = 8 * BytesPerLong; |
|
1558 |
||
10971 | 1559 |
// No additional cost for CMOVL. |
1560 |
const int Matcher::long_cmove_cost() { return 0; } |
|
1561 |
||
1562 |
// No CMOVF/CMOVD with SSE2 |
|
1563 |
const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } |
|
1564 |
||
1 | 1565 |
// Should the Matcher clone shifts on addressing modes, expecting them |
1566 |
// to be subsumed into complex addressing expressions or compute them |
|
1567 |
// into registers? True for Intel but false for most RISCs |
|
1568 |
const bool Matcher::clone_shift_expressions = true; |
|
1569 |
||
8868
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8494
diff
changeset
|
1570 |
// Do we need to mask the count passed to shift instructions or does |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8494
diff
changeset
|
1571 |
// the cpu only look at the lower 5/6 bits anyway? |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8494
diff
changeset
|
1572 |
const bool Matcher::need_masked_shift_count = false; |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8494
diff
changeset
|
1573 |
|
5698
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1574 |
bool Matcher::narrow_oop_use_complex_address() { |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1575 |
assert(UseCompressedOops, "only for compressed oops code"); |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1576 |
return (LogMinObjAlignmentInBytes <= 3); |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1577 |
} |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1578 |
|
1 | 1579 |
// Is it better to copy float constants, or load them directly from |
1580 |
// memory? Intel can load a float constant from a direct address, |
|
1581 |
// requiring no extra registers. Most RISCs will have to materialize |
|
1582 |
// an address into a register first, so they would do better to copy |
|
1583 |
// the constant from stack. |
|
1584 |
const bool Matcher::rematerialize_float_constants = true; // XXX |
|
1585 |
||
1586 |
// If CPU can load and store mis-aligned doubles directly then no |
|
1587 |
// fixup is needed. Else we split the double into 2 integer pieces |
|
1588 |
// and move it piece-by-piece. Only happens when passing doubles into |
|
1589 |
// C code as the Java calling convention forces doubles to be aligned. |
|
1590 |
const bool Matcher::misaligned_doubles_ok = true; |
|
1591 |
||
1592 |
// No-op on amd64 |
|
1593 |
void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} |
|
1594 |
||
1595 |
// Advertise here if the CPU requires explicit rounding operations to |
|
1596 |
// implement the UseStrictFP mode. |
|
1597 |
const bool Matcher::strict_fp_requires_explicit_rounding = true; |
|
1598 |
||
5025
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4566
diff
changeset
|
1599 |
// Are floats conerted to double when stored to stack during deoptimization? |
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4566
diff
changeset
|
1600 |
// On x64 it is stored without convertion so we can use normal access. |
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4566
diff
changeset
|
1601 |
bool Matcher::float_in_double() { return false; } |
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4566
diff
changeset
|
1602 |
|
1 | 1603 |
// Do ints take an entire long register or just half? |
1604 |
const bool Matcher::int_in_long = true; |
|
1605 |
||
1606 |
// Return whether or not this register is ever used as an argument. |
|
1607 |
// This function is used on startup to build the trampoline stubs in |
|
1608 |
// generateOptoStub. Registers not mentioned will be killed by the VM |
|
1609 |
// call in the trampoline, and arguments in those registers not be |
|
1610 |
// available to the callee. |
|
1611 |
bool Matcher::can_be_java_arg(int reg) |
|
1612 |
{ |
|
1613 |
return |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1614 |
reg == RDI_num || reg == RDI_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1615 |
reg == RSI_num || reg == RSI_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1616 |
reg == RDX_num || reg == RDX_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1617 |
reg == RCX_num || reg == RCX_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1618 |
reg == R8_num || reg == R8_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1619 |
reg == R9_num || reg == R9_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1620 |
reg == R12_num || reg == R12_H_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1621 |
reg == XMM0_num || reg == XMM0b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1622 |
reg == XMM1_num || reg == XMM1b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1623 |
reg == XMM2_num || reg == XMM2b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1624 |
reg == XMM3_num || reg == XMM3b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1625 |
reg == XMM4_num || reg == XMM4b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1626 |
reg == XMM5_num || reg == XMM5b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1627 |
reg == XMM6_num || reg == XMM6b_num || |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1628 |
reg == XMM7_num || reg == XMM7b_num; |
1 | 1629 |
} |
1630 |
||
1631 |
bool Matcher::is_spillable_arg(int reg) |
|
1632 |
{ |
|
1633 |
return can_be_java_arg(reg); |
|
1634 |
} |
|
1635 |
||
7115
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1636 |
bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1637 |
// In 64 bit mode a code which use multiply when |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1638 |
// devisor is constant is faster than hardware |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1639 |
// DIV instruction (it uses MulHiL). |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1640 |
return false; |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1641 |
} |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6753
diff
changeset
|
1642 |
|
1 | 1643 |
// Register for DIVI projection of divmodI |
1644 |
RegMask Matcher::divI_proj_mask() { |
|
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
1645 |
return INT_RAX_REG_mask(); |
1 | 1646 |
} |
1647 |
||
1648 |
// Register for MODI projection of divmodI |
|
1649 |
RegMask Matcher::modI_proj_mask() { |
|
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
1650 |
return INT_RDX_REG_mask(); |
1 | 1651 |
} |
1652 |
||
1653 |
// Register for DIVL projection of divmodL |
|
1654 |
RegMask Matcher::divL_proj_mask() { |
|
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
1655 |
return LONG_RAX_REG_mask(); |
1 | 1656 |
} |
1657 |
||
1658 |
// Register for MODL projection of divmodL |
|
1659 |
RegMask Matcher::modL_proj_mask() { |
|
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
1660 |
return LONG_RDX_REG_mask(); |
1 | 1661 |
} |
1662 |
||
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
1663 |
const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
1664 |
return PTR_RBP_REG_mask(); |
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
1665 |
} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
1666 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1667 |
static Address build_address(int b, int i, int s, int d) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1668 |
Register index = as_Register(i); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1669 |
Address::ScaleFactor scale = (Address::ScaleFactor)s; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1670 |
if (index == rsp) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1671 |
index = noreg; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1672 |
scale = Address::no_scale; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1673 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1674 |
Address addr(as_Register(b), index, scale, d); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1675 |
return addr; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1676 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
1677 |
|
1 | 1678 |
%} |
1679 |
||
1680 |
//----------ENCODING BLOCK----------------------------------------------------- |
|
1681 |
// This block specifies the encoding classes used by the compiler to |
|
1682 |
// output byte streams. Encoding classes are parameterized macros |
|
1683 |
// used by Machine Instruction Nodes in order to generate the bit |
|
1684 |
// encoding of the instruction. Operands specify their base encoding |
|
1685 |
// interface with the interface keyword. There are currently |
|
1686 |
// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & |
|
1687 |
// COND_INTER. REG_INTER causes an operand to generate a function |
|
1688 |
// which returns its register number when queried. CONST_INTER causes |
|
1689 |
// an operand to generate a function which returns the value of the |
|
1690 |
// constant when queried. MEMORY_INTER causes an operand to generate |
|
1691 |
// four functions which return the Base Register, the Index Register, |
|
1692 |
// the Scale Value, and the Offset Value of the operand when queried. |
|
1693 |
// COND_INTER causes an operand to generate six functions which return |
|
1694 |
// the encoding code (ie - encoding bits for the instruction) |
|
1695 |
// associated with each basic boolean condition for a conditional |
|
1696 |
// instruction. |
|
1697 |
// |
|
1698 |
// Instructions specify two basic values for encoding. Again, a |
|
1699 |
// function is available to check if the constant displacement is an |
|
1700 |
// oop. They use the ins_encode keyword to specify their encoding |
|
1701 |
// classes (which must be a sequence of enc_class names, and their |
|
1702 |
// parameters, specified in the encoding block), and they use the |
|
1703 |
// opcode keyword to specify, in order, their primary, secondary, and |
|
1704 |
// tertiary opcode. Only the opcode sections which a particular |
|
1705 |
// instruction needs for encoding need to be specified. |
|
1706 |
encode %{ |
|
1707 |
// Build emit functions for each basic byte or larger field in the |
|
1708 |
// intel encoding scheme (opcode, rm, sib, immediate), and call them |
|
1709 |
// from C++ code in the enc_class source block. Emit functions will |
|
1710 |
// live in the main source block for now. In future, we can |
|
1711 |
// generalize this by adding a syntax that specifies the sizes of |
|
1712 |
// fields in an order, so that the adlc can build the emit functions |
|
1713 |
// automagically |
|
1714 |
||
1715 |
// Emit primary opcode |
|
1716 |
enc_class OpcP |
|
1717 |
%{ |
|
1718 |
emit_opcode(cbuf, $primary); |
|
1719 |
%} |
|
1720 |
||
1721 |
// Emit secondary opcode |
|
1722 |
enc_class OpcS |
|
1723 |
%{ |
|
1724 |
emit_opcode(cbuf, $secondary); |
|
1725 |
%} |
|
1726 |
||
1727 |
// Emit tertiary opcode |
|
1728 |
enc_class OpcT |
|
1729 |
%{ |
|
1730 |
emit_opcode(cbuf, $tertiary); |
|
1731 |
%} |
|
1732 |
||
1733 |
// Emit opcode directly |
|
1734 |
enc_class Opcode(immI d8) |
|
1735 |
%{ |
|
1736 |
emit_opcode(cbuf, $d8$$constant); |
|
1737 |
%} |
|
1738 |
||
1739 |
// Emit size prefix |
|
1740 |
enc_class SizePrefix |
|
1741 |
%{ |
|
1742 |
emit_opcode(cbuf, 0x66); |
|
1743 |
%} |
|
1744 |
||
1745 |
enc_class reg(rRegI reg) |
|
1746 |
%{ |
|
1747 |
emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); |
|
1748 |
%} |
|
1749 |
||
1750 |
enc_class reg_reg(rRegI dst, rRegI src) |
|
1751 |
%{ |
|
1752 |
emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); |
|
1753 |
%} |
|
1754 |
||
1755 |
enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) |
|
1756 |
%{ |
|
1757 |
emit_opcode(cbuf, $opcode$$constant); |
|
1758 |
emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); |
|
1759 |
%} |
|
1760 |
||
1761 |
enc_class cdql_enc(no_rax_rdx_RegI div) |
|
1762 |
%{ |
|
1763 |
// Full implementation of Java idiv and irem; checks for |
|
1764 |
// special case as described in JVM spec., p.243 & p.271. |
|
1765 |
// |
|
1766 |
// normal case special case |
|
1767 |
// |
|
1768 |
// input : rax: dividend min_int |
|
1769 |
// reg: divisor -1 |
|
1770 |
// |
|
1771 |
// output: rax: quotient (= rax idiv reg) min_int |
|
1772 |
// rdx: remainder (= rax irem reg) 0 |
|
1773 |
// |
|
1774 |
// Code sequnce: |
|
1775 |
// |
|
1776 |
// 0: 3d 00 00 00 80 cmp $0x80000000,%eax |
|
1777 |
// 5: 75 07/08 jne e <normal> |
|
1778 |
// 7: 33 d2 xor %edx,%edx |
|
1779 |
// [div >= 8 -> offset + 1] |
|
1780 |
// [REX_B] |
|
1781 |
// 9: 83 f9 ff cmp $0xffffffffffffffff,$div |
|
1782 |
// c: 74 03/04 je 11 <done> |
|
1783 |
// 000000000000000e <normal>: |
|
1784 |
// e: 99 cltd |
|
1785 |
// [div >= 8 -> offset + 1] |
|
1786 |
// [REX_B] |
|
1787 |
// f: f7 f9 idiv $div |
|
1788 |
// 0000000000000011 <done>: |
|
1789 |
||
1790 |
// cmp $0x80000000,%eax |
|
1791 |
emit_opcode(cbuf, 0x3d); |
|
1792 |
emit_d8(cbuf, 0x00); |
|
1793 |
emit_d8(cbuf, 0x00); |
|
1794 |
emit_d8(cbuf, 0x00); |
|
1795 |
emit_d8(cbuf, 0x80); |
|
1796 |
||
1797 |
// jne e <normal> |
|
1798 |
emit_opcode(cbuf, 0x75); |
|
1799 |
emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); |
|
1800 |
||
1801 |
// xor %edx,%edx |
|
1802 |
emit_opcode(cbuf, 0x33); |
|
1803 |
emit_d8(cbuf, 0xD2); |
|
1804 |
||
1805 |
// cmp $0xffffffffffffffff,%ecx |
|
1806 |
if ($div$$reg >= 8) { |
|
1807 |
emit_opcode(cbuf, Assembler::REX_B); |
|
1808 |
} |
|
1809 |
emit_opcode(cbuf, 0x83); |
|
1810 |
emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); |
|
1811 |
emit_d8(cbuf, 0xFF); |
|
1812 |
||
1813 |
// je 11 <done> |
|
1814 |
emit_opcode(cbuf, 0x74); |
|
1815 |
emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); |
|
1816 |
||
1817 |
// <normal> |
|
1818 |
// cltd |
|
1819 |
emit_opcode(cbuf, 0x99); |
|
1820 |
||
1821 |
// idivl (note: must be emitted by the user of this rule) |
|
1822 |
// <done> |
|
1823 |
%} |
|
1824 |
||
1825 |
enc_class cdqq_enc(no_rax_rdx_RegL div) |
|
1826 |
%{ |
|
1827 |
// Full implementation of Java ldiv and lrem; checks for |
|
1828 |
// special case as described in JVM spec., p.243 & p.271. |
|
1829 |
// |
|
1830 |
// normal case special case |
|
1831 |
// |
|
1832 |
// input : rax: dividend min_long |
|
1833 |
// reg: divisor -1 |
|
1834 |
// |
|
1835 |
// output: rax: quotient (= rax idiv reg) min_long |
|
1836 |
// rdx: remainder (= rax irem reg) 0 |
|
1837 |
// |
|
1838 |
// Code sequnce: |
|
1839 |
// |
|
1840 |
// 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx |
|
1841 |
// 7: 00 00 80 |
|
1842 |
// a: 48 39 d0 cmp %rdx,%rax |
|
1843 |
// d: 75 08 jne 17 <normal> |
|
1844 |
// f: 33 d2 xor %edx,%edx |
|
1845 |
// 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div |
|
1846 |
// 15: 74 05 je 1c <done> |
|
1847 |
// 0000000000000017 <normal>: |
|
1848 |
// 17: 48 99 cqto |
|
1849 |
// 19: 48 f7 f9 idiv $div |
|
1850 |
// 000000000000001c <done>: |
|
1851 |
||
1852 |
// mov $0x8000000000000000,%rdx |
|
1853 |
emit_opcode(cbuf, Assembler::REX_W); |
|
1854 |
emit_opcode(cbuf, 0xBA); |
|
1855 |
emit_d8(cbuf, 0x00); |
|
1856 |
emit_d8(cbuf, 0x00); |
|
1857 |
emit_d8(cbuf, 0x00); |
|
1858 |
emit_d8(cbuf, 0x00); |
|
1859 |
emit_d8(cbuf, 0x00); |
|
1860 |
emit_d8(cbuf, 0x00); |
|
1861 |
emit_d8(cbuf, 0x00); |
|
1862 |
emit_d8(cbuf, 0x80); |
|
1863 |
||
1864 |
// cmp %rdx,%rax |
|
1865 |
emit_opcode(cbuf, Assembler::REX_W); |
|
1866 |
emit_opcode(cbuf, 0x39); |
|
1867 |
emit_d8(cbuf, 0xD0); |
|
1868 |
||
1869 |
// jne 17 <normal> |
|
1870 |
emit_opcode(cbuf, 0x75); |
|
1871 |
emit_d8(cbuf, 0x08); |
|
1872 |
||
1873 |
// xor %edx,%edx |
|
1874 |
emit_opcode(cbuf, 0x33); |
|
1875 |
emit_d8(cbuf, 0xD2); |
|
1876 |
||
1877 |
// cmp $0xffffffffffffffff,$div |
|
1878 |
emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); |
|
1879 |
emit_opcode(cbuf, 0x83); |
|
1880 |
emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); |
|
1881 |
emit_d8(cbuf, 0xFF); |
|
1882 |
||
1883 |
// je 1e <done> |
|
1884 |
emit_opcode(cbuf, 0x74); |
|
1885 |
emit_d8(cbuf, 0x05); |
|
1886 |
||
1887 |
// <normal> |
|
1888 |
// cqto |
|
1889 |
emit_opcode(cbuf, Assembler::REX_W); |
|
1890 |
emit_opcode(cbuf, 0x99); |
|
1891 |
||
1892 |
// idivq (note: must be emitted by the user of this rule) |
|
1893 |
// <done> |
|
1894 |
%} |
|
1895 |
||
1896 |
// Opcde enc_class for 8/32 bit immediate instructions with sign-extension |
|
1897 |
enc_class OpcSE(immI imm) |
|
1898 |
%{ |
|
1899 |
// Emit primary opcode and set sign-extend bit |
|
1900 |
// Check for 8-bit immediate, and set sign extend bit in opcode |
|
1901 |
if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { |
|
1902 |
emit_opcode(cbuf, $primary | 0x02); |
|
1903 |
} else { |
|
1904 |
// 32-bit immediate |
|
1905 |
emit_opcode(cbuf, $primary); |
|
1906 |
} |
|
1907 |
%} |
|
1908 |
||
1909 |
enc_class OpcSErm(rRegI dst, immI imm) |
|
1910 |
%{ |
|
1911 |
// OpcSEr/m |
|
1912 |
int dstenc = $dst$$reg; |
|
1913 |
if (dstenc >= 8) { |
|
1914 |
emit_opcode(cbuf, Assembler::REX_B); |
|
1915 |
dstenc -= 8; |
|
1916 |
} |
|
1917 |
// Emit primary opcode and set sign-extend bit |
|
1918 |
// Check for 8-bit immediate, and set sign extend bit in opcode |
|
1919 |
if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { |
|
1920 |
emit_opcode(cbuf, $primary | 0x02); |
|
1921 |
} else { |
|
1922 |
// 32-bit immediate |
|
1923 |
emit_opcode(cbuf, $primary); |
|
1924 |
} |
|
1925 |
// Emit r/m byte with secondary opcode, after primary opcode. |
|
1926 |
emit_rm(cbuf, 0x3, $secondary, dstenc); |
|
1927 |
%} |
|
1928 |
||
1929 |
enc_class OpcSErm_wide(rRegL dst, immI imm) |
|
1930 |
%{ |
|
1931 |
// OpcSEr/m |
|
1932 |
int dstenc = $dst$$reg; |
|
1933 |
if (dstenc < 8) { |
|
1934 |
emit_opcode(cbuf, Assembler::REX_W); |
|
1935 |
} else { |
|
1936 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
1937 |
dstenc -= 8; |
|
1938 |
} |
|
1939 |
// Emit primary opcode and set sign-extend bit |
|
1940 |
// Check for 8-bit immediate, and set sign extend bit in opcode |
|
1941 |
if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { |
|
1942 |
emit_opcode(cbuf, $primary | 0x02); |
|
1943 |
} else { |
|
1944 |
// 32-bit immediate |
|
1945 |
emit_opcode(cbuf, $primary); |
|
1946 |
} |
|
1947 |
// Emit r/m byte with secondary opcode, after primary opcode. |
|
1948 |
emit_rm(cbuf, 0x3, $secondary, dstenc); |
|
1949 |
%} |
|
1950 |
||
1951 |
enc_class Con8or32(immI imm) |
|
1952 |
%{ |
|
1953 |
// Check for 8-bit immediate, and set sign extend bit in opcode |
|
1954 |
if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { |
|
1955 |
$$$emit8$imm$$constant; |
|
1956 |
} else { |
|
1957 |
// 32-bit immediate |
|
1958 |
$$$emit32$imm$$constant; |
|
1959 |
} |
|
1960 |
%} |
|
1961 |
||
1962 |
enc_class opc2_reg(rRegI dst) |
|
1963 |
%{ |
|
1964 |
// BSWAP |
|
1965 |
emit_cc(cbuf, $secondary, $dst$$reg); |
|
1966 |
%} |
|
1967 |
||
1968 |
enc_class opc3_reg(rRegI dst) |
|
1969 |
%{ |
|
1970 |
// BSWAP |
|
1971 |
emit_cc(cbuf, $tertiary, $dst$$reg); |
|
1972 |
%} |
|
1973 |
||
1974 |
enc_class reg_opc(rRegI div) |
|
1975 |
%{ |
|
1976 |
// INC, DEC, IDIV, IMOD, JMP indirect, ... |
|
1977 |
emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); |
|
1978 |
%} |
|
1979 |
||
1980 |
enc_class enc_cmov(cmpOp cop) |
|
1981 |
%{ |
|
1982 |
// CMOV |
|
1983 |
$$$emit8$primary; |
|
1984 |
emit_cc(cbuf, $secondary, $cop$$cmpcode); |
|
1985 |
%} |
|
1986 |
||
1987 |
enc_class enc_PartialSubtypeCheck() |
|
1988 |
%{ |
|
1989 |
Register Rrdi = as_Register(RDI_enc); // result register |
|
1990 |
Register Rrax = as_Register(RAX_enc); // super class |
|
1991 |
Register Rrcx = as_Register(RCX_enc); // killed |
|
1992 |
Register Rrsi = as_Register(RSI_enc); // sub class |
|
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
1993 |
Label miss; |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
1994 |
const bool set_cond_codes = true; |
1 | 1995 |
|
1996 |
MacroAssembler _masm(&cbuf); |
|
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
1997 |
__ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
1998 |
NULL, &miss, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
1999 |
/*set_cond_codes:*/ true); |
1 | 2000 |
if ($primary) { |
1066 | 2001 |
__ xorptr(Rrdi, Rrdi); |
1 | 2002 |
} |
2003 |
__ bind(miss); |
|
2004 |
%} |
|
2005 |
||
2006 |
enc_class Java_To_Interpreter(method meth) |
|
2007 |
%{ |
|
2008 |
// CALL Java_To_Interpreter |
|
2009 |
// This is the instruction starting address for relocation info. |
|
6418 | 2010 |
cbuf.set_insts_mark(); |
1 | 2011 |
$$$emit8$primary; |
2012 |
// CALL directly to the runtime |
|
2013 |
emit_d32_reloc(cbuf, |
|
6418 | 2014 |
(int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
1 | 2015 |
runtime_call_Relocation::spec(), |
2016 |
RELOC_DISP32); |
|
2017 |
%} |
|
2018 |
||
2019 |
enc_class Java_Static_Call(method meth) |
|
2020 |
%{ |
|
2021 |
// JAVA STATIC CALL |
|
2022 |
// CALL to fixup routine. Fixup routine uses ScopeDesc info to |
|
2023 |
// determine who we intended to call. |
|
6418 | 2024 |
cbuf.set_insts_mark(); |
1 | 2025 |
$$$emit8$primary; |
2026 |
||
2027 |
if (!_method) { |
|
2028 |
emit_d32_reloc(cbuf, |
|
6418 | 2029 |
(int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
1 | 2030 |
runtime_call_Relocation::spec(), |
2031 |
RELOC_DISP32); |
|
2032 |
} else if (_optimized_virtual) { |
|
2033 |
emit_d32_reloc(cbuf, |
|
6418 | 2034 |
(int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
1 | 2035 |
opt_virtual_call_Relocation::spec(), |
2036 |
RELOC_DISP32); |
|
2037 |
} else { |
|
2038 |
emit_d32_reloc(cbuf, |
|
6418 | 2039 |
(int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
1 | 2040 |
static_call_Relocation::spec(), |
2041 |
RELOC_DISP32); |
|
2042 |
} |
|
2043 |
if (_method) { |
|
2044 |
// Emit stub for static call |
|
2045 |
emit_java_to_interp(cbuf); |
|
2046 |
} |
|
2047 |
%} |
|
2048 |
||
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2049 |
enc_class Java_Dynamic_Call(method meth) %{ |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2050 |
MacroAssembler _masm(&cbuf); |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2051 |
__ ic_call((address)$meth$$method); |
1 | 2052 |
%} |
2053 |
||
2054 |
enc_class Java_Compiled_Call(method meth) |
|
2055 |
%{ |
|
2056 |
// JAVA COMPILED CALL |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2057 |
int disp = in_bytes(Method:: from_compiled_offset()); |
1 | 2058 |
|
2059 |
// XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! |
|
2060 |
// assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); |
|
2061 |
||
2062 |
// callq *disp(%rax) |
|
6418 | 2063 |
cbuf.set_insts_mark(); |
1 | 2064 |
$$$emit8$primary; |
2065 |
if (disp < 0x80) { |
|
2066 |
emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte |
|
2067 |
emit_d8(cbuf, disp); // Displacement |
|
2068 |
} else { |
|
2069 |
emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte |
|
2070 |
emit_d32(cbuf, disp); // Displacement |
|
2071 |
} |
|
2072 |
%} |
|
2073 |
||
2074 |
enc_class reg_opc_imm(rRegI dst, immI8 shift) |
|
2075 |
%{ |
|
2076 |
// SAL, SAR, SHR |
|
2077 |
int dstenc = $dst$$reg; |
|
2078 |
if (dstenc >= 8) { |
|
2079 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2080 |
dstenc -= 8; |
|
2081 |
} |
|
2082 |
$$$emit8$primary; |
|
2083 |
emit_rm(cbuf, 0x3, $secondary, dstenc); |
|
2084 |
$$$emit8$shift$$constant; |
|
2085 |
%} |
|
2086 |
||
2087 |
enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) |
|
2088 |
%{ |
|
2089 |
// SAL, SAR, SHR |
|
2090 |
int dstenc = $dst$$reg; |
|
2091 |
if (dstenc < 8) { |
|
2092 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2093 |
} else { |
|
2094 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2095 |
dstenc -= 8; |
|
2096 |
} |
|
2097 |
$$$emit8$primary; |
|
2098 |
emit_rm(cbuf, 0x3, $secondary, dstenc); |
|
2099 |
$$$emit8$shift$$constant; |
|
2100 |
%} |
|
2101 |
||
2102 |
enc_class load_immI(rRegI dst, immI src) |
|
2103 |
%{ |
|
2104 |
int dstenc = $dst$$reg; |
|
2105 |
if (dstenc >= 8) { |
|
2106 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2107 |
dstenc -= 8; |
|
2108 |
} |
|
2109 |
emit_opcode(cbuf, 0xB8 | dstenc); |
|
2110 |
$$$emit32$src$$constant; |
|
2111 |
%} |
|
2112 |
||
2113 |
enc_class load_immL(rRegL dst, immL src) |
|
2114 |
%{ |
|
2115 |
int dstenc = $dst$$reg; |
|
2116 |
if (dstenc < 8) { |
|
2117 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2118 |
} else { |
|
2119 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2120 |
dstenc -= 8; |
|
2121 |
} |
|
2122 |
emit_opcode(cbuf, 0xB8 | dstenc); |
|
2123 |
emit_d64(cbuf, $src$$constant); |
|
2124 |
%} |
|
2125 |
||
2126 |
enc_class load_immUL32(rRegL dst, immUL32 src) |
|
2127 |
%{ |
|
2128 |
// same as load_immI, but this time we care about zeroes in the high word |
|
2129 |
int dstenc = $dst$$reg; |
|
2130 |
if (dstenc >= 8) { |
|
2131 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2132 |
dstenc -= 8; |
|
2133 |
} |
|
2134 |
emit_opcode(cbuf, 0xB8 | dstenc); |
|
2135 |
$$$emit32$src$$constant; |
|
2136 |
%} |
|
2137 |
||
2138 |
enc_class load_immL32(rRegL dst, immL32 src) |
|
2139 |
%{ |
|
2140 |
int dstenc = $dst$$reg; |
|
2141 |
if (dstenc < 8) { |
|
2142 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2143 |
} else { |
|
2144 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2145 |
dstenc -= 8; |
|
2146 |
} |
|
2147 |
emit_opcode(cbuf, 0xC7); |
|
2148 |
emit_rm(cbuf, 0x03, 0x00, dstenc); |
|
2149 |
$$$emit32$src$$constant; |
|
2150 |
%} |
|
2151 |
||
2152 |
enc_class load_immP31(rRegP dst, immP32 src) |
|
2153 |
%{ |
|
2154 |
// same as load_immI, but this time we care about zeroes in the high word |
|
2155 |
int dstenc = $dst$$reg; |
|
2156 |
if (dstenc >= 8) { |
|
2157 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2158 |
dstenc -= 8; |
|
2159 |
} |
|
2160 |
emit_opcode(cbuf, 0xB8 | dstenc); |
|
2161 |
$$$emit32$src$$constant; |
|
2162 |
%} |
|
2163 |
||
2164 |
enc_class load_immP(rRegP dst, immP src) |
|
2165 |
%{ |
|
2166 |
int dstenc = $dst$$reg; |
|
2167 |
if (dstenc < 8) { |
|
2168 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2169 |
} else { |
|
2170 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2171 |
dstenc -= 8; |
|
2172 |
} |
|
2173 |
emit_opcode(cbuf, 0xB8 | dstenc); |
|
2174 |
// This next line should be generated from ADLC |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2175 |
if ($src->constant_reloc() != relocInfo::none) { |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2176 |
emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
1 | 2177 |
} else { |
2178 |
emit_d64(cbuf, $src$$constant); |
|
2179 |
} |
|
2180 |
%} |
|
2181 |
||
2182 |
enc_class Con32(immI src) |
|
2183 |
%{ |
|
2184 |
// Output immediate |
|
2185 |
$$$emit32$src$$constant; |
|
2186 |
%} |
|
2187 |
||
2188 |
enc_class Con64(immL src) |
|
2189 |
%{ |
|
2190 |
// Output immediate |
|
2191 |
emit_d64($src$$constant); |
|
2192 |
%} |
|
2193 |
||
2194 |
enc_class Con32F_as_bits(immF src) |
|
2195 |
%{ |
|
2196 |
// Output Float immediate bits |
|
2197 |
jfloat jf = $src$$constant; |
|
2198 |
jint jf_as_bits = jint_cast(jf); |
|
2199 |
emit_d32(cbuf, jf_as_bits); |
|
2200 |
%} |
|
2201 |
||
2202 |
enc_class Con16(immI src) |
|
2203 |
%{ |
|
2204 |
// Output immediate |
|
2205 |
$$$emit16$src$$constant; |
|
2206 |
%} |
|
2207 |
||
2208 |
// How is this different from Con32??? XXX |
|
2209 |
enc_class Con_d32(immI src) |
|
2210 |
%{ |
|
2211 |
emit_d32(cbuf,$src$$constant); |
|
2212 |
%} |
|
2213 |
||
2214 |
enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) |
|
2215 |
// Output immediate memory reference |
|
2216 |
emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); |
|
2217 |
emit_d32(cbuf, 0x00); |
|
2218 |
%} |
|
2219 |
||
2220 |
enc_class lock_prefix() |
|
2221 |
%{ |
|
2222 |
if (os::is_MP()) { |
|
2223 |
emit_opcode(cbuf, 0xF0); // lock |
|
2224 |
} |
|
2225 |
%} |
|
2226 |
||
2227 |
enc_class REX_mem(memory mem) |
|
2228 |
%{ |
|
2229 |
if ($mem$$base >= 8) { |
|
2230 |
if ($mem$$index < 8) { |
|
2231 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2232 |
} else { |
|
2233 |
emit_opcode(cbuf, Assembler::REX_XB); |
|
2234 |
} |
|
2235 |
} else { |
|
2236 |
if ($mem$$index >= 8) { |
|
2237 |
emit_opcode(cbuf, Assembler::REX_X); |
|
2238 |
} |
|
2239 |
} |
|
2240 |
%} |
|
2241 |
||
2242 |
enc_class REX_mem_wide(memory mem) |
|
2243 |
%{ |
|
2244 |
if ($mem$$base >= 8) { |
|
2245 |
if ($mem$$index < 8) { |
|
2246 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2247 |
} else { |
|
2248 |
emit_opcode(cbuf, Assembler::REX_WXB); |
|
2249 |
} |
|
2250 |
} else { |
|
2251 |
if ($mem$$index < 8) { |
|
2252 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2253 |
} else { |
|
2254 |
emit_opcode(cbuf, Assembler::REX_WX); |
|
2255 |
} |
|
2256 |
} |
|
2257 |
%} |
|
2258 |
||
2259 |
// for byte regs |
|
2260 |
enc_class REX_breg(rRegI reg) |
|
2261 |
%{ |
|
2262 |
if ($reg$$reg >= 4) { |
|
2263 |
emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); |
|
2264 |
} |
|
2265 |
%} |
|
2266 |
||
2267 |
// for byte regs |
|
2268 |
enc_class REX_reg_breg(rRegI dst, rRegI src) |
|
2269 |
%{ |
|
2270 |
if ($dst$$reg < 8) { |
|
2271 |
if ($src$$reg >= 4) { |
|
2272 |
emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); |
|
2273 |
} |
|
2274 |
} else { |
|
2275 |
if ($src$$reg < 8) { |
|
2276 |
emit_opcode(cbuf, Assembler::REX_R); |
|
2277 |
} else { |
|
2278 |
emit_opcode(cbuf, Assembler::REX_RB); |
|
2279 |
} |
|
2280 |
} |
|
2281 |
%} |
|
2282 |
||
2283 |
// for byte regs |
|
2284 |
enc_class REX_breg_mem(rRegI reg, memory mem) |
|
2285 |
%{ |
|
2286 |
if ($reg$$reg < 8) { |
|
2287 |
if ($mem$$base < 8) { |
|
2288 |
if ($mem$$index >= 8) { |
|
2289 |
emit_opcode(cbuf, Assembler::REX_X); |
|
2290 |
} else if ($reg$$reg >= 4) { |
|
2291 |
emit_opcode(cbuf, Assembler::REX); |
|
2292 |
} |
|
2293 |
} else { |
|
2294 |
if ($mem$$index < 8) { |
|
2295 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2296 |
} else { |
|
2297 |
emit_opcode(cbuf, Assembler::REX_XB); |
|
2298 |
} |
|
2299 |
} |
|
2300 |
} else { |
|
2301 |
if ($mem$$base < 8) { |
|
2302 |
if ($mem$$index < 8) { |
|
2303 |
emit_opcode(cbuf, Assembler::REX_R); |
|
2304 |
} else { |
|
2305 |
emit_opcode(cbuf, Assembler::REX_RX); |
|
2306 |
} |
|
2307 |
} else { |
|
2308 |
if ($mem$$index < 8) { |
|
2309 |
emit_opcode(cbuf, Assembler::REX_RB); |
|
2310 |
} else { |
|
2311 |
emit_opcode(cbuf, Assembler::REX_RXB); |
|
2312 |
} |
|
2313 |
} |
|
2314 |
} |
|
2315 |
%} |
|
2316 |
||
2317 |
enc_class REX_reg(rRegI reg) |
|
2318 |
%{ |
|
2319 |
if ($reg$$reg >= 8) { |
|
2320 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2321 |
} |
|
2322 |
%} |
|
2323 |
||
2324 |
enc_class REX_reg_wide(rRegI reg) |
|
2325 |
%{ |
|
2326 |
if ($reg$$reg < 8) { |
|
2327 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2328 |
} else { |
|
2329 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2330 |
} |
|
2331 |
%} |
|
2332 |
||
2333 |
enc_class REX_reg_reg(rRegI dst, rRegI src) |
|
2334 |
%{ |
|
2335 |
if ($dst$$reg < 8) { |
|
2336 |
if ($src$$reg >= 8) { |
|
2337 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2338 |
} |
|
2339 |
} else { |
|
2340 |
if ($src$$reg < 8) { |
|
2341 |
emit_opcode(cbuf, Assembler::REX_R); |
|
2342 |
} else { |
|
2343 |
emit_opcode(cbuf, Assembler::REX_RB); |
|
2344 |
} |
|
2345 |
} |
|
2346 |
%} |
|
2347 |
||
2348 |
enc_class REX_reg_reg_wide(rRegI dst, rRegI src) |
|
2349 |
%{ |
|
2350 |
if ($dst$$reg < 8) { |
|
2351 |
if ($src$$reg < 8) { |
|
2352 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2353 |
} else { |
|
2354 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2355 |
} |
|
2356 |
} else { |
|
2357 |
if ($src$$reg < 8) { |
|
2358 |
emit_opcode(cbuf, Assembler::REX_WR); |
|
2359 |
} else { |
|
2360 |
emit_opcode(cbuf, Assembler::REX_WRB); |
|
2361 |
} |
|
2362 |
} |
|
2363 |
%} |
|
2364 |
||
2365 |
enc_class REX_reg_mem(rRegI reg, memory mem) |
|
2366 |
%{ |
|
2367 |
if ($reg$$reg < 8) { |
|
2368 |
if ($mem$$base < 8) { |
|
2369 |
if ($mem$$index >= 8) { |
|
2370 |
emit_opcode(cbuf, Assembler::REX_X); |
|
2371 |
} |
|
2372 |
} else { |
|
2373 |
if ($mem$$index < 8) { |
|
2374 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2375 |
} else { |
|
2376 |
emit_opcode(cbuf, Assembler::REX_XB); |
|
2377 |
} |
|
2378 |
} |
|
2379 |
} else { |
|
2380 |
if ($mem$$base < 8) { |
|
2381 |
if ($mem$$index < 8) { |
|
2382 |
emit_opcode(cbuf, Assembler::REX_R); |
|
2383 |
} else { |
|
2384 |
emit_opcode(cbuf, Assembler::REX_RX); |
|
2385 |
} |
|
2386 |
} else { |
|
2387 |
if ($mem$$index < 8) { |
|
2388 |
emit_opcode(cbuf, Assembler::REX_RB); |
|
2389 |
} else { |
|
2390 |
emit_opcode(cbuf, Assembler::REX_RXB); |
|
2391 |
} |
|
2392 |
} |
|
2393 |
} |
|
2394 |
%} |
|
2395 |
||
2396 |
enc_class REX_reg_mem_wide(rRegL reg, memory mem) |
|
2397 |
%{ |
|
2398 |
if ($reg$$reg < 8) { |
|
2399 |
if ($mem$$base < 8) { |
|
2400 |
if ($mem$$index < 8) { |
|
2401 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2402 |
} else { |
|
2403 |
emit_opcode(cbuf, Assembler::REX_WX); |
|
2404 |
} |
|
2405 |
} else { |
|
2406 |
if ($mem$$index < 8) { |
|
2407 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2408 |
} else { |
|
2409 |
emit_opcode(cbuf, Assembler::REX_WXB); |
|
2410 |
} |
|
2411 |
} |
|
2412 |
} else { |
|
2413 |
if ($mem$$base < 8) { |
|
2414 |
if ($mem$$index < 8) { |
|
2415 |
emit_opcode(cbuf, Assembler::REX_WR); |
|
2416 |
} else { |
|
2417 |
emit_opcode(cbuf, Assembler::REX_WRX); |
|
2418 |
} |
|
2419 |
} else { |
|
2420 |
if ($mem$$index < 8) { |
|
2421 |
emit_opcode(cbuf, Assembler::REX_WRB); |
|
2422 |
} else { |
|
2423 |
emit_opcode(cbuf, Assembler::REX_WRXB); |
|
2424 |
} |
|
2425 |
} |
|
2426 |
} |
|
2427 |
%} |
|
2428 |
||
2429 |
enc_class reg_mem(rRegI ereg, memory mem) |
|
2430 |
%{ |
|
2431 |
// High registers handle in encode_RegMem |
|
2432 |
int reg = $ereg$$reg; |
|
2433 |
int base = $mem$$base; |
|
2434 |
int index = $mem$$index; |
|
2435 |
int scale = $mem$$scale; |
|
2436 |
int disp = $mem$$disp; |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2437 |
relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2438 |
|
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2439 |
encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
1 | 2440 |
%} |
2441 |
||
2442 |
enc_class RM_opc_mem(immI rm_opcode, memory mem) |
|
2443 |
%{ |
|
2444 |
int rm_byte_opcode = $rm_opcode$$constant; |
|
2445 |
||
2446 |
// High registers handle in encode_RegMem |
|
2447 |
int base = $mem$$base; |
|
2448 |
int index = $mem$$index; |
|
2449 |
int scale = $mem$$scale; |
|
2450 |
int displace = $mem$$disp; |
|
2451 |
||
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2452 |
relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
1 | 2453 |
// working with static |
2454 |
// globals |
|
2455 |
encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2456 |
disp_reloc); |
1 | 2457 |
%} |
2458 |
||
2459 |
enc_class reg_lea(rRegI dst, rRegI src0, immI src1) |
|
2460 |
%{ |
|
2461 |
int reg_encoding = $dst$$reg; |
|
2462 |
int base = $src0$$reg; // 0xFFFFFFFF indicates no base |
|
2463 |
int index = 0x04; // 0x04 indicates no index |
|
2464 |
int scale = 0x00; // 0x00 indicates no scale |
|
2465 |
int displace = $src1$$constant; // 0x00 indicates no displacement |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2466 |
relocInfo::relocType disp_reloc = relocInfo::none; |
1 | 2467 |
encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
2468 |
disp_reloc); |
1 | 2469 |
%} |
2470 |
||
2471 |
enc_class neg_reg(rRegI dst) |
|
2472 |
%{ |
|
2473 |
int dstenc = $dst$$reg; |
|
2474 |
if (dstenc >= 8) { |
|
2475 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2476 |
dstenc -= 8; |
|
2477 |
} |
|
2478 |
// NEG $dst |
|
2479 |
emit_opcode(cbuf, 0xF7); |
|
2480 |
emit_rm(cbuf, 0x3, 0x03, dstenc); |
|
2481 |
%} |
|
2482 |
||
2483 |
enc_class neg_reg_wide(rRegI dst) |
|
2484 |
%{ |
|
2485 |
int dstenc = $dst$$reg; |
|
2486 |
if (dstenc < 8) { |
|
2487 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2488 |
} else { |
|
2489 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2490 |
dstenc -= 8; |
|
2491 |
} |
|
2492 |
// NEG $dst |
|
2493 |
emit_opcode(cbuf, 0xF7); |
|
2494 |
emit_rm(cbuf, 0x3, 0x03, dstenc); |
|
2495 |
%} |
|
2496 |
||
2497 |
enc_class setLT_reg(rRegI dst) |
|
2498 |
%{ |
|
2499 |
int dstenc = $dst$$reg; |
|
2500 |
if (dstenc >= 8) { |
|
2501 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2502 |
dstenc -= 8; |
|
2503 |
} else if (dstenc >= 4) { |
|
2504 |
emit_opcode(cbuf, Assembler::REX); |
|
2505 |
} |
|
2506 |
// SETLT $dst |
|
2507 |
emit_opcode(cbuf, 0x0F); |
|
2508 |
emit_opcode(cbuf, 0x9C); |
|
2509 |
emit_rm(cbuf, 0x3, 0x0, dstenc); |
|
2510 |
%} |
|
2511 |
||
2512 |
enc_class setNZ_reg(rRegI dst) |
|
2513 |
%{ |
|
2514 |
int dstenc = $dst$$reg; |
|
2515 |
if (dstenc >= 8) { |
|
2516 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2517 |
dstenc -= 8; |
|
2518 |
} else if (dstenc >= 4) { |
|
2519 |
emit_opcode(cbuf, Assembler::REX); |
|
2520 |
} |
|
2521 |
// SETNZ $dst |
|
2522 |
emit_opcode(cbuf, 0x0F); |
|
2523 |
emit_opcode(cbuf, 0x95); |
|
2524 |
emit_rm(cbuf, 0x3, 0x0, dstenc); |
|
2525 |
%} |
|
2526 |
||
2527 |
||
2528 |
// Compare the lonogs and set -1, 0, or 1 into dst |
|
2529 |
enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) |
|
2530 |
%{ |
|
2531 |
int src1enc = $src1$$reg; |
|
2532 |
int src2enc = $src2$$reg; |
|
2533 |
int dstenc = $dst$$reg; |
|
2534 |
||
2535 |
// cmpq $src1, $src2 |
|
2536 |
if (src1enc < 8) { |
|
2537 |
if (src2enc < 8) { |
|
2538 |
emit_opcode(cbuf, Assembler::REX_W); |
|
2539 |
} else { |
|
2540 |
emit_opcode(cbuf, Assembler::REX_WB); |
|
2541 |
} |
|
2542 |
} else { |
|
2543 |
if (src2enc < 8) { |
|
2544 |
emit_opcode(cbuf, Assembler::REX_WR); |
|
2545 |
} else { |
|
2546 |
emit_opcode(cbuf, Assembler::REX_WRB); |
|
2547 |
} |
|
2548 |
} |
|
2549 |
emit_opcode(cbuf, 0x3B); |
|
2550 |
emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); |
|
2551 |
||
2552 |
// movl $dst, -1 |
|
2553 |
if (dstenc >= 8) { |
|
2554 |
emit_opcode(cbuf, Assembler::REX_B); |
|
2555 |
} |
|
2556 |
emit_opcode(cbuf, 0xB8 | (dstenc & 7)); |
|
2557 |
emit_d32(cbuf, -1); |
|
2558 |
||
2559 |
// jl,s done |
|
2560 |
emit_opcode(cbuf, 0x7C); |
|
2561 |
emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); |
|
2562 |
||
2563 |
// setne $dst |
|
2564 |
if (dstenc >= 4) { |
|
2565 |
emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); |
|
2566 |
} |
|
2567 |
emit_opcode(cbuf, 0x0F); |
|
2568 |
emit_opcode(cbuf, 0x95); |
|
2569 |
emit_opcode(cbuf, 0xC0 | (dstenc & 7)); |
|
2570 |
||
2571 |
// movzbl $dst, $dst |
|
2572 |
if (dstenc >= 4) { |
|
2573 |
emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); |
|
2574 |
} |
|
2575 |
emit_opcode(cbuf, 0x0F); |
|
2576 |
emit_opcode(cbuf, 0xB6); |
|
2577 |
emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); |
|
2578 |
%} |
|
2579 |
||
2580 |
enc_class Push_ResultXD(regD dst) %{ |
|
11427 | 2581 |
MacroAssembler _masm(&cbuf); |
2582 |
__ fstp_d(Address(rsp, 0)); |
|
2583 |
__ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
2584 |
__ addptr(rsp, 8); |
|
1 | 2585 |
%} |
2586 |
||
2587 |
enc_class Push_SrcXD(regD src) %{ |
|
2588 |
MacroAssembler _masm(&cbuf); |
|
11427 | 2589 |
__ subptr(rsp, 8); |
2590 |
__ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
2591 |
__ fld_d(Address(rsp, 0)); |
|
2592 |
%} |
|
2593 |
||
1 | 2594 |
|
2595 |
// obj: object to lock |
|
2596 |
// box: box address (header location) -- killed |
|
2597 |
// tmp: rax -- killed |
|
2598 |
// scr: rbx -- killed |
|
2599 |
// |
|
2600 |
// What follows is a direct transliteration of fast_lock() and fast_unlock() |
|
2601 |
// from i486.ad. See that file for comments. |
|
2602 |
// TODO: where possible switch from movq (r, 0) to movl(r,0) and |
|
2603 |
// use the shorter encoding. (Movl clears the high-order 32-bits). |
|
2604 |
||
2605 |
||
2606 |
enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) |
|
2607 |
%{ |
|
2608 |
Register objReg = as_Register((int)$obj$$reg); |
|
2609 |
Register boxReg = as_Register((int)$box$$reg); |
|
2610 |
Register tmpReg = as_Register($tmp$$reg); |
|
2611 |
Register scrReg = as_Register($scr$$reg); |
|
2612 |
MacroAssembler masm(&cbuf); |
|
2613 |
||
2614 |
// Verify uniqueness of register assignments -- necessary but not sufficient |
|
2615 |
assert (objReg != boxReg && objReg != tmpReg && |
|
2616 |
objReg != scrReg && tmpReg != scrReg, "invariant") ; |
|
2617 |
||
2618 |
if (_counters != NULL) { |
|
2619 |
masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); |
|
2620 |
} |
|
2621 |
if (EmitSync & 1) { |
|
1066 | 2622 |
// Without cast to int32_t a movptr will destroy r10 which is typically obj |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2623 |
masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2624 |
masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
1 | 2625 |
} else |
2626 |
if (EmitSync & 2) { |
|
2627 |
Label DONE_LABEL; |
|
2628 |
if (UseBiasedLocking) { |
|
2629 |
// Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. |
|
2630 |
masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
|
2631 |
} |
|
1066 | 2632 |
// QQQ was movl... |
2633 |
masm.movptr(tmpReg, 0x1); |
|
2634 |
masm.orptr(tmpReg, Address(objReg, 0)); |
|
2635 |
masm.movptr(Address(boxReg, 0), tmpReg); |
|
1 | 2636 |
if (os::is_MP()) { |
2637 |
masm.lock(); |
|
2638 |
} |
|
1066 | 2639 |
masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
1 | 2640 |
masm.jcc(Assembler::equal, DONE_LABEL); |
2641 |
||
2642 |
// Recursive locking |
|
1066 | 2643 |
masm.subptr(tmpReg, rsp); |
2644 |
masm.andptr(tmpReg, 7 - os::vm_page_size()); |
|
2645 |
masm.movptr(Address(boxReg, 0), tmpReg); |
|
1 | 2646 |
|
2647 |
masm.bind(DONE_LABEL); |
|
2648 |
masm.nop(); // avoid branch to branch |
|
2649 |
} else { |
|
2650 |
Label DONE_LABEL, IsInflated, Egress; |
|
2651 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2652 |
masm.movptr(tmpReg, Address(objReg, 0)) ; |
1066 | 2653 |
masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2654 |
masm.jcc (Assembler::notZero, IsInflated) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2655 |
|
1 | 2656 |
// it's stack-locked, biased or neutral |
2657 |
// TODO: optimize markword triage order to reduce the number of |
|
2658 |
// conditional branches in the most common cases. |
|
2659 |
// Beware -- there's a subtle invariant that fetch of the markword |
|
2660 |
// at [FETCH], below, will never observe a biased encoding (*101b). |
|
2661 |
// If this invariant is not held we'll suffer exclusion (safety) failure. |
|
2662 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
2663 |
if (UseBiasedLocking && !UseOptoBiasInlining) { |
1 | 2664 |
masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
1066 | 2665 |
masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
1 | 2666 |
} |
2667 |
||
1066 | 2668 |
// was q will it destroy high? |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2669 |
masm.orl (tmpReg, 1) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2670 |
masm.movptr(Address(boxReg, 0), tmpReg) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2671 |
if (os::is_MP()) { masm.lock(); } |
1066 | 2672 |
masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
1 | 2673 |
if (_counters != NULL) { |
2674 |
masm.cond_inc32(Assembler::equal, |
|
2675 |
ExternalAddress((address) _counters->fast_path_entry_count_addr())); |
|
2676 |
} |
|
2677 |
masm.jcc (Assembler::equal, DONE_LABEL); |
|
2678 |
||
2679 |
// Recursive locking |
|
1066 | 2680 |
masm.subptr(tmpReg, rsp); |
2681 |
masm.andptr(tmpReg, 7 - os::vm_page_size()); |
|
2682 |
masm.movptr(Address(boxReg, 0), tmpReg); |
|
1 | 2683 |
if (_counters != NULL) { |
2684 |
masm.cond_inc32(Assembler::equal, |
|
2685 |
ExternalAddress((address) _counters->fast_path_entry_count_addr())); |
|
2686 |
} |
|
2687 |
masm.jmp (DONE_LABEL) ; |
|
2688 |
||
2689 |
masm.bind (IsInflated) ; |
|
2690 |
// It's inflated |
|
2691 |
||
2692 |
// TODO: someday avoid the ST-before-CAS penalty by |
|
2693 |
// relocating (deferring) the following ST. |
|
2694 |
// We should also think about trying a CAS without having |
|
2695 |
// fetched _owner. If the CAS is successful we may |
|
2696 |
// avoid an RTO->RTS upgrade on the $line. |
|
1066 | 2697 |
// Without cast to int32_t a movptr will destroy r10 which is typically obj |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2698 |
masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2699 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2700 |
masm.mov (boxReg, tmpReg) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2701 |
masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2702 |
masm.testptr(tmpReg, tmpReg) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2703 |
masm.jcc (Assembler::notZero, DONE_LABEL) ; |
1 | 2704 |
|
2705 |
// It's inflated and appears unlocked |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2706 |
if (os::is_MP()) { masm.lock(); } |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2707 |
masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
1 | 2708 |
// Intentional fall-through into DONE_LABEL ... |
2709 |
||
2710 |
masm.bind (DONE_LABEL) ; |
|
2711 |
masm.nop () ; // avoid jmp to jmp |
|
2712 |
} |
|
2713 |
%} |
|
2714 |
||
2715 |
// obj: object to unlock |
|
2716 |
// box: box address (displaced header location), killed |
|
2717 |
// RBX: killed tmp; cannot be obj nor box |
|
2718 |
enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) |
|
2719 |
%{ |
|
2720 |
||
2721 |
Register objReg = as_Register($obj$$reg); |
|
2722 |
Register boxReg = as_Register($box$$reg); |
|
2723 |
Register tmpReg = as_Register($tmp$$reg); |
|
2724 |
MacroAssembler masm(&cbuf); |
|
2725 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2726 |
if (EmitSync & 4) { |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2727 |
masm.cmpptr(rsp, 0) ; |
1 | 2728 |
} else |
2729 |
if (EmitSync & 8) { |
|
2730 |
Label DONE_LABEL; |
|
2731 |
if (UseBiasedLocking) { |
|
2732 |
masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
|
2733 |
} |
|
2734 |
||
2735 |
// Check whether the displaced header is 0 |
|
2736 |
//(=> recursive unlock) |
|
1066 | 2737 |
masm.movptr(tmpReg, Address(boxReg, 0)); |
2738 |
masm.testptr(tmpReg, tmpReg); |
|
1 | 2739 |
masm.jcc(Assembler::zero, DONE_LABEL); |
2740 |
||
2741 |
// If not recursive lock, reset the header to displaced header |
|
2742 |
if (os::is_MP()) { |
|
2743 |
masm.lock(); |
|
2744 |
} |
|
1066 | 2745 |
masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
1 | 2746 |
masm.bind(DONE_LABEL); |
2747 |
masm.nop(); // avoid branch to branch |
|
2748 |
} else { |
|
2749 |
Label DONE_LABEL, Stacked, CheckSucc ; |
|
2750 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
2751 |
if (UseBiasedLocking && !UseOptoBiasInlining) { |
1 | 2752 |
masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
2753 |
} |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2754 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2755 |
masm.movptr(tmpReg, Address(objReg, 0)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2756 |
masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2757 |
masm.jcc (Assembler::zero, DONE_LABEL) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2758 |
masm.testl (tmpReg, 0x02) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2759 |
masm.jcc (Assembler::zero, Stacked) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2760 |
|
1 | 2761 |
// It's inflated |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2762 |
masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2763 |
masm.xorptr(boxReg, r15_thread) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2764 |
masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2765 |
masm.jcc (Assembler::notZero, DONE_LABEL) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2766 |
masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2767 |
masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2768 |
masm.jcc (Assembler::notZero, CheckSucc) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2769 |
masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2770 |
masm.jmp (DONE_LABEL) ; |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2771 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2772 |
if ((EmitSync & 65536) == 0) { |
1 | 2773 |
Label LSuccess, LGoSlowPath ; |
2774 |
masm.bind (CheckSucc) ; |
|
1066 | 2775 |
masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
1 | 2776 |
masm.jcc (Assembler::zero, LGoSlowPath) ; |
2777 |
||
2778 |
// I'd much rather use lock:andl m->_owner, 0 as it's faster than the |
|
2779 |
// the explicit ST;MEMBAR combination, but masm doesn't currently support |
|
2780 |
// "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc |
|
2781 |
// are all faster when the write buffer is populated. |
|
1066 | 2782 |
masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
1 | 2783 |
if (os::is_MP()) { |
1066 | 2784 |
masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
1 | 2785 |
} |
1066 | 2786 |
masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
1 | 2787 |
masm.jcc (Assembler::notZero, LSuccess) ; |
2788 |
||
1066 | 2789 |
masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
1 | 2790 |
if (os::is_MP()) { masm.lock(); } |
1066 | 2791 |
masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
1 | 2792 |
masm.jcc (Assembler::notEqual, LSuccess) ; |
2793 |
// Intentional fall-through into slow-path |
|
2794 |
||
2795 |
masm.bind (LGoSlowPath) ; |
|
2796 |
masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure |
|
2797 |
masm.jmp (DONE_LABEL) ; |
|
2798 |
||
2799 |
masm.bind (LSuccess) ; |
|
2800 |
masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success |
|
2801 |
masm.jmp (DONE_LABEL) ; |
|
2802 |
} |
|
2803 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2804 |
masm.bind (Stacked) ; |
1066 | 2805 |
masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
2806 |
if (os::is_MP()) { masm.lock(); } |
1066 | 2807 |
masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
1 | 2808 |
|
2809 |
if (EmitSync & 65536) { |
|
2810 |
masm.bind (CheckSucc) ; |
|
2811 |
} |
|
2812 |
masm.bind(DONE_LABEL); |
|
2813 |
if (EmitSync & 32768) { |
|
2814 |
masm.nop(); // avoid branch to branch |
|
2815 |
} |
|
2816 |
} |
|
2817 |
%} |
|
2818 |
||
595
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
2819 |
|
1 | 2820 |
enc_class enc_rethrow() |
2821 |
%{ |
|
6418 | 2822 |
cbuf.set_insts_mark(); |
1 | 2823 |
emit_opcode(cbuf, 0xE9); // jmp entry |
2824 |
emit_d32_reloc(cbuf, |
|
6418 | 2825 |
(int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
1 | 2826 |
runtime_call_Relocation::spec(), |
2827 |
RELOC_DISP32); |
|
2828 |
%} |
|
2829 |
||
2830 |
%} |
|
2831 |
||
2832 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
2833 |
|
1 | 2834 |
//----------FRAME-------------------------------------------------------------- |
2835 |
// Definition of frame structure and management information. |
|
2836 |
// |
|
2837 |
// S T A C K L A Y O U T Allocators stack-slot number |
|
2838 |
// | (to get allocators register number |
|
2839 |
// G Owned by | | v add OptoReg::stack0()) |
|
2840 |
// r CALLER | | |
|
2841 |
// o | +--------+ pad to even-align allocators stack-slot |
|
2842 |
// w V | pad0 | numbers; owned by CALLER |
|
2843 |
// t -----------+--------+----> Matcher::_in_arg_limit, unaligned |
|
2844 |
// h ^ | in | 5 |
|
2845 |
// | | args | 4 Holes in incoming args owned by SELF |
|
2846 |
// | | | | 3 |
|
2847 |
// | | +--------+ |
|
2848 |
// V | | old out| Empty on Intel, window on Sparc |
|
2849 |
// | old |preserve| Must be even aligned. |
|
2850 |
// | SP-+--------+----> Matcher::_old_SP, even aligned |
|
2851 |
// | | in | 3 area for Intel ret address |
|
2852 |
// Owned by |preserve| Empty on Sparc. |
|
2853 |
// SELF +--------+ |
|
2854 |
// | | pad2 | 2 pad to align old SP |
|
2855 |
// | +--------+ 1 |
|
2856 |
// | | locks | 0 |
|
2857 |
// | +--------+----> OptoReg::stack0(), even aligned |
|
2858 |
// | | pad1 | 11 pad to align new SP |
|
2859 |
// | +--------+ |
|
2860 |
// | | | 10 |
|
2861 |
// | | spills | 9 spills |
|
2862 |
// V | | 8 (pad0 slot for callee) |
|
2863 |
// -----------+--------+----> Matcher::_out_arg_limit, unaligned |
|
2864 |
// ^ | out | 7 |
|
2865 |
// | | args | 6 Holes in outgoing args owned by CALLEE |
|
2866 |
// Owned by +--------+ |
|
2867 |
// CALLEE | new out| 6 Empty on Intel, window on Sparc |
|
2868 |
// | new |preserve| Must be even-aligned. |
|
2869 |
// | SP-+--------+----> Matcher::_new_SP, even aligned |
|
2870 |
// | | | |
|
2871 |
// |
|
2872 |
// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is |
|
2873 |
// known from SELF's arguments and the Java calling convention. |
|
2874 |
// Region 6-7 is determined per call site. |
|
2875 |
// Note 2: If the calling convention leaves holes in the incoming argument |
|
2876 |
// area, those holes are owned by SELF. Holes in the outgoing area |
|
2877 |
// are owned by the CALLEE. Holes should not be nessecary in the |
|
2878 |
// incoming area, as the Java calling convention is completely under |
|
2879 |
// the control of the AD file. Doubles can be sorted and packed to |
|
2880 |
// avoid holes. Holes in the outgoing arguments may be nessecary for |
|
2881 |
// varargs C calling conventions. |
|
2882 |
// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is |
|
2883 |
// even aligned with pad0 as needed. |
|
2884 |
// Region 6 is even aligned. Region 6-7 is NOT even aligned; |
|
2885 |
// region 6-11 is even aligned; it may be padded out more so that |
|
2886 |
// the region from SP to FP meets the minimum stack alignment. |
|
2887 |
// Note 4: For I2C adapters, the incoming FP may not meet the minimum stack |
|
2888 |
// alignment. Region 11, pad1, may be dynamically extended so that |
|
2889 |
// SP meets the minimum alignment. |
|
2890 |
||
2891 |
frame |
|
2892 |
%{ |
|
2893 |
// What direction does stack grow in (assumed to be same for C & Java) |
|
2894 |
stack_direction(TOWARDS_LOW); |
|
2895 |
||
2896 |
// These three registers define part of the calling convention |
|
2897 |
// between compiled code and the interpreter. |
|
2898 |
inline_cache_reg(RAX); // Inline Cache Register |
|
2899 |
interpreter_method_oop_reg(RBX); // Method Oop Register when |
|
2900 |
// calling interpreter |
|
2901 |
||
2902 |
// Optional: name the operand used by cisc-spilling to access |
|
2903 |
// [stack_pointer + offset] |
|
2904 |
cisc_spilling_operand_name(indOffset32); |
|
2905 |
||
2906 |
// Number of stack slots consumed by locking an object |
|
2907 |
sync_stack_slots(2); |
|
2908 |
||
2909 |
// Compiled code's Frame Pointer |
|
2910 |
frame_pointer(RSP); |
|
2911 |
||
2912 |
// Interpreter stores its frame pointer in a register which is |
|
2913 |
// stored to the stack by I2CAdaptors. |
|
2914 |
// I2CAdaptors convert from interpreted java to compiled java. |
|
2915 |
interpreter_frame_pointer(RBP); |
|
2916 |
||
2917 |
// Stack alignment requirement |
|
2918 |
stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) |
|
2919 |
||
2920 |
// Number of stack slots between incoming argument block and the start of |
|
2921 |
// a new frame. The PROLOG must add this many slots to the stack. The |
|
2922 |
// EPILOG must remove this many slots. amd64 needs two slots for |
|
2923 |
// return address. |
|
2924 |
in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); |
|
2925 |
||
2926 |
// Number of outgoing stack slots killed above the out_preserve_stack_slots |
|
2927 |
// for calls to C. Supports the var-args backing area for register parms. |
|
2928 |
varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); |
|
2929 |
||
2930 |
// The after-PROLOG location of the return address. Location of |
|
2931 |
// return address specifies a type (REG or STACK) and a number |
|
2932 |
// representing the register number (i.e. - use a register name) or |
|
2933 |
// stack slot. |
|
2934 |
// Ret Addr is on stack in slot 0 if no locks or verification or alignment. |
|
2935 |
// Otherwise, it is above the locks and verification slot and alignment word |
|
2936 |
return_addr(STACK - 2 + |
|
11794 | 2937 |
round_to((Compile::current()->in_preserve_stack_slots() + |
2938 |
Compile::current()->fixed_slots()), |
|
2939 |
stack_alignment_in_slots())); |
|
1 | 2940 |
|
2941 |
// Body of function which returns an integer array locating |
|
2942 |
// arguments either in registers or in stack slots. Passed an array |
|
2943 |
// of ideal registers called "sig" and a "length" count. Stack-slot |
|
2944 |
// offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
2945 |
// arguments for a CALLEE. Incoming stack arguments are |
|
2946 |
// automatically biased by the preserve_stack_slots field above. |
|
2947 |
||
2948 |
calling_convention |
|
2949 |
%{ |
|
2950 |
// No difference between ingoing/outgoing just pass false |
|
2951 |
SharedRuntime::java_calling_convention(sig_bt, regs, length, false); |
|
2952 |
%} |
|
2953 |
||
2954 |
c_calling_convention |
|
2955 |
%{ |
|
2956 |
// This is obviously always outgoing |
|
2957 |
(void) SharedRuntime::c_calling_convention(sig_bt, regs, length); |
|
2958 |
%} |
|
2959 |
||
2960 |
// Location of compiled Java return values. Same as C for now. |
|
2961 |
return_value |
|
2962 |
%{ |
|
2963 |
assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, |
|
2964 |
"only return normal values"); |
|
2965 |
||
2966 |
static const int lo[Op_RegL + 1] = { |
|
2967 |
0, |
|
2968 |
0, |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
2969 |
RAX_num, // Op_RegN |
1 | 2970 |
RAX_num, // Op_RegI |
2971 |
RAX_num, // Op_RegP |
|
2972 |
XMM0_num, // Op_RegF |
|
2973 |
XMM0_num, // Op_RegD |
|
2974 |
RAX_num // Op_RegL |
|
2975 |
}; |
|
2976 |
static const int hi[Op_RegL + 1] = { |
|
2977 |
0, |
|
2978 |
0, |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
2979 |
OptoReg::Bad, // Op_RegN |
1 | 2980 |
OptoReg::Bad, // Op_RegI |
2981 |
RAX_H_num, // Op_RegP |
|
2982 |
OptoReg::Bad, // Op_RegF |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
2983 |
XMM0b_num, // Op_RegD |
1 | 2984 |
RAX_H_num // Op_RegL |
2985 |
}; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
2986 |
// Excluded flags and vector registers. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
2987 |
assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
1 | 2988 |
return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
2989 |
%} |
|
2990 |
%} |
|
2991 |
||
2992 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
2993 |
//----------Operand Attributes------------------------------------------------- |
|
2994 |
op_attrib op_cost(0); // Required cost attribute |
|
2995 |
||
2996 |
//----------Instruction Attributes--------------------------------------------- |
|
2997 |
ins_attrib ins_cost(100); // Required cost attribute |
|
2998 |
ins_attrib ins_size(8); // Required size attribute (in bits) |
|
2999 |
ins_attrib ins_short_branch(0); // Required flag: is this instruction |
|
3000 |
// a non-matching short branch variant |
|
3001 |
// of some long branch? |
|
3002 |
ins_attrib ins_alignment(1); // Required alignment attribute (must |
|
3003 |
// be a power of 2) specifies the |
|
3004 |
// alignment that some part of the |
|
3005 |
// instruction (not necessarily the |
|
3006 |
// start) requires. If > 1, a |
|
3007 |
// compute_padding() function must be |
|
3008 |
// provided for the instruction |
|
3009 |
||
3010 |
//----------OPERANDS----------------------------------------------------------- |
|
3011 |
// Operand definitions must precede instruction definitions for correct parsing |
|
3012 |
// in the ADLC because operands constitute user defined types which are used in |
|
3013 |
// instruction definitions. |
|
3014 |
||
3015 |
//----------Simple Operands---------------------------------------------------- |
|
3016 |
// Immediate Operands |
|
3017 |
// Integer Immediate |
|
3018 |
operand immI() |
|
3019 |
%{ |
|
3020 |
match(ConI); |
|
3021 |
||
3022 |
op_cost(10); |
|
3023 |
format %{ %} |
|
3024 |
interface(CONST_INTER); |
|
3025 |
%} |
|
3026 |
||
3027 |
// Constant for test vs zero |
|
3028 |
operand immI0() |
|
3029 |
%{ |
|
3030 |
predicate(n->get_int() == 0); |
|
3031 |
match(ConI); |
|
3032 |
||
3033 |
op_cost(0); |
|
3034 |
format %{ %} |
|
3035 |
interface(CONST_INTER); |
|
3036 |
%} |
|
3037 |
||
3038 |
// Constant for increment |
|
3039 |
operand immI1() |
|
3040 |
%{ |
|
3041 |
predicate(n->get_int() == 1); |
|
3042 |
match(ConI); |
|
3043 |
||
3044 |
op_cost(0); |
|
3045 |
format %{ %} |
|
3046 |
interface(CONST_INTER); |
|
3047 |
%} |
|
3048 |
||
3049 |
// Constant for decrement |
|
3050 |
operand immI_M1() |
|
3051 |
%{ |
|
3052 |
predicate(n->get_int() == -1); |
|
3053 |
match(ConI); |
|
3054 |
||
3055 |
op_cost(0); |
|
3056 |
format %{ %} |
|
3057 |
interface(CONST_INTER); |
|
3058 |
%} |
|
3059 |
||
3060 |
// Valid scale values for addressing modes |
|
3061 |
operand immI2() |
|
3062 |
%{ |
|
3063 |
predicate(0 <= n->get_int() && (n->get_int() <= 3)); |
|
3064 |
match(ConI); |
|
3065 |
||
3066 |
format %{ %} |
|
3067 |
interface(CONST_INTER); |
|
3068 |
%} |
|
3069 |
||
3070 |
operand immI8() |
|
3071 |
%{ |
|
3072 |
predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); |
|
3073 |
match(ConI); |
|
3074 |
||
3075 |
op_cost(5); |
|
3076 |
format %{ %} |
|
3077 |
interface(CONST_INTER); |
|
3078 |
%} |
|
3079 |
||
3080 |
operand immI16() |
|
3081 |
%{ |
|
3082 |
predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); |
|
3083 |
match(ConI); |
|
3084 |
||
3085 |
op_cost(10); |
|
3086 |
format %{ %} |
|
3087 |
interface(CONST_INTER); |
|
3088 |
%} |
|
3089 |
||
3090 |
// Constant for long shifts |
|
3091 |
operand immI_32() |
|
3092 |
%{ |
|
3093 |
predicate( n->get_int() == 32 ); |
|
3094 |
match(ConI); |
|
3095 |
||
3096 |
op_cost(0); |
|
3097 |
format %{ %} |
|
3098 |
interface(CONST_INTER); |
|
3099 |
%} |
|
3100 |
||
3101 |
// Constant for long shifts |
|
3102 |
operand immI_64() |
|
3103 |
%{ |
|
3104 |
predicate( n->get_int() == 64 ); |
|
3105 |
match(ConI); |
|
3106 |
||
3107 |
op_cost(0); |
|
3108 |
format %{ %} |
|
3109 |
interface(CONST_INTER); |
|
3110 |
%} |
|
3111 |
||
3112 |
// Pointer Immediate |
|
3113 |
operand immP() |
|
3114 |
%{ |
|
3115 |
match(ConP); |
|
3116 |
||
3117 |
op_cost(10); |
|
3118 |
format %{ %} |
|
3119 |
interface(CONST_INTER); |
|
3120 |
%} |
|
3121 |
||
3122 |
// NULL Pointer Immediate |
|
3123 |
operand immP0() |
|
3124 |
%{ |
|
3125 |
predicate(n->get_ptr() == 0); |
|
3126 |
match(ConP); |
|
3127 |
||
3128 |
op_cost(5); |
|
3129 |
format %{ %} |
|
3130 |
interface(CONST_INTER); |
|
3131 |
%} |
|
3132 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3133 |
// Pointer Immediate |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3134 |
operand immN() %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3135 |
match(ConN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3136 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3137 |
op_cost(10); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3138 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3139 |
interface(CONST_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3140 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3141 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3142 |
// NULL Pointer Immediate |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3143 |
operand immN0() %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3144 |
predicate(n->get_narrowcon() == 0); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3145 |
match(ConN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3146 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3147 |
op_cost(5); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3148 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3149 |
interface(CONST_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3150 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3151 |
|
1 | 3152 |
operand immP31() |
3153 |
%{ |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
3154 |
predicate(n->as_Type()->type()->reloc() == relocInfo::none |
1 | 3155 |
&& (n->get_ptr() >> 31) == 0); |
3156 |
match(ConP); |
|
3157 |
||
3158 |
op_cost(5); |
|
3159 |
format %{ %} |
|
3160 |
interface(CONST_INTER); |
|
3161 |
%} |
|
3162 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3163 |
|
1 | 3164 |
// Long Immediate |
3165 |
operand immL() |
|
3166 |
%{ |
|
3167 |
match(ConL); |
|
3168 |
||
3169 |
op_cost(20); |
|
3170 |
format %{ %} |
|
3171 |
interface(CONST_INTER); |
|
3172 |
%} |
|
3173 |
||
3174 |
// Long Immediate 8-bit |
|
3175 |
operand immL8() |
|
3176 |
%{ |
|
3177 |
predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); |
|
3178 |
match(ConL); |
|
3179 |
||
3180 |
op_cost(5); |
|
3181 |
format %{ %} |
|
3182 |
interface(CONST_INTER); |
|
3183 |
%} |
|
3184 |
||
3185 |
// Long Immediate 32-bit unsigned |
|
3186 |
operand immUL32() |
|
3187 |
%{ |
|
3188 |
predicate(n->get_long() == (unsigned int) (n->get_long())); |
|
3189 |
match(ConL); |
|
3190 |
||
3191 |
op_cost(10); |
|
3192 |
format %{ %} |
|
3193 |
interface(CONST_INTER); |
|
3194 |
%} |
|
3195 |
||
3196 |
// Long Immediate 32-bit signed |
|
3197 |
operand immL32() |
|
3198 |
%{ |
|
3199 |
predicate(n->get_long() == (int) (n->get_long())); |
|
3200 |
match(ConL); |
|
3201 |
||
3202 |
op_cost(15); |
|
3203 |
format %{ %} |
|
3204 |
interface(CONST_INTER); |
|
3205 |
%} |
|
3206 |
||
3207 |
// Long Immediate zero |
|
3208 |
operand immL0() |
|
3209 |
%{ |
|
3210 |
predicate(n->get_long() == 0L); |
|
3211 |
match(ConL); |
|
3212 |
||
3213 |
op_cost(10); |
|
3214 |
format %{ %} |
|
3215 |
interface(CONST_INTER); |
|
3216 |
%} |
|
3217 |
||
3218 |
// Constant for increment |
|
3219 |
operand immL1() |
|
3220 |
%{ |
|
3221 |
predicate(n->get_long() == 1); |
|
3222 |
match(ConL); |
|
3223 |
||
3224 |
format %{ %} |
|
3225 |
interface(CONST_INTER); |
|
3226 |
%} |
|
3227 |
||
3228 |
// Constant for decrement |
|
3229 |
operand immL_M1() |
|
3230 |
%{ |
|
3231 |
predicate(n->get_long() == -1); |
|
3232 |
match(ConL); |
|
3233 |
||
3234 |
format %{ %} |
|
3235 |
interface(CONST_INTER); |
|
3236 |
%} |
|
3237 |
||
3238 |
// Long Immediate: the value 10 |
|
3239 |
operand immL10() |
|
3240 |
%{ |
|
3241 |
predicate(n->get_long() == 10); |
|
3242 |
match(ConL); |
|
3243 |
||
3244 |
format %{ %} |
|
3245 |
interface(CONST_INTER); |
|
3246 |
%} |
|
3247 |
||
3248 |
// Long immediate from 0 to 127. |
|
3249 |
// Used for a shorter form of long mul by 10. |
|
3250 |
operand immL_127() |
|
3251 |
%{ |
|
3252 |
predicate(0 <= n->get_long() && n->get_long() < 0x80); |
|
3253 |
match(ConL); |
|
3254 |
||
3255 |
op_cost(10); |
|
3256 |
format %{ %} |
|
3257 |
interface(CONST_INTER); |
|
3258 |
%} |
|
3259 |
||
3260 |
// Long Immediate: low 32-bit mask |
|
3261 |
operand immL_32bits() |
|
3262 |
%{ |
|
3263 |
predicate(n->get_long() == 0xFFFFFFFFL); |
|
3264 |
match(ConL); |
|
3265 |
op_cost(20); |
|
3266 |
||
3267 |
format %{ %} |
|
3268 |
interface(CONST_INTER); |
|
3269 |
%} |
|
3270 |
||
3271 |
// Float Immediate zero |
|
3272 |
operand immF0() |
|
3273 |
%{ |
|
3274 |
predicate(jint_cast(n->getf()) == 0); |
|
3275 |
match(ConF); |
|
3276 |
||
3277 |
op_cost(5); |
|
3278 |
format %{ %} |
|
3279 |
interface(CONST_INTER); |
|
3280 |
%} |
|
3281 |
||
3282 |
// Float Immediate |
|
3283 |
operand immF() |
|
3284 |
%{ |
|
3285 |
match(ConF); |
|
3286 |
||
3287 |
op_cost(15); |
|
3288 |
format %{ %} |
|
3289 |
interface(CONST_INTER); |
|
3290 |
%} |
|
3291 |
||
3292 |
// Double Immediate zero |
|
3293 |
operand immD0() |
|
3294 |
%{ |
|
3295 |
predicate(jlong_cast(n->getd()) == 0); |
|
3296 |
match(ConD); |
|
3297 |
||
3298 |
op_cost(5); |
|
3299 |
format %{ %} |
|
3300 |
interface(CONST_INTER); |
|
3301 |
%} |
|
3302 |
||
3303 |
// Double Immediate |
|
3304 |
operand immD() |
|
3305 |
%{ |
|
3306 |
match(ConD); |
|
3307 |
||
3308 |
op_cost(15); |
|
3309 |
format %{ %} |
|
3310 |
interface(CONST_INTER); |
|
3311 |
%} |
|
3312 |
||
3313 |
// Immediates for special shifts (sign extend) |
|
3314 |
||
3315 |
// Constants for increment |
|
3316 |
operand immI_16() |
|
3317 |
%{ |
|
3318 |
predicate(n->get_int() == 16); |
|
3319 |
match(ConI); |
|
3320 |
||
3321 |
format %{ %} |
|
3322 |
interface(CONST_INTER); |
|
3323 |
%} |
|
3324 |
||
3325 |
operand immI_24() |
|
3326 |
%{ |
|
3327 |
predicate(n->get_int() == 24); |
|
3328 |
match(ConI); |
|
3329 |
||
3330 |
format %{ %} |
|
3331 |
interface(CONST_INTER); |
|
3332 |
%} |
|
3333 |
||
3334 |
// Constant for byte-wide masking |
|
3335 |
operand immI_255() |
|
3336 |
%{ |
|
3337 |
predicate(n->get_int() == 255); |
|
3338 |
match(ConI); |
|
3339 |
||
3340 |
format %{ %} |
|
3341 |
interface(CONST_INTER); |
|
3342 |
%} |
|
3343 |
||
3344 |
// Constant for short-wide masking |
|
3345 |
operand immI_65535() |
|
3346 |
%{ |
|
3347 |
predicate(n->get_int() == 65535); |
|
3348 |
match(ConI); |
|
3349 |
||
3350 |
format %{ %} |
|
3351 |
interface(CONST_INTER); |
|
3352 |
%} |
|
3353 |
||
3354 |
// Constant for byte-wide masking |
|
3355 |
operand immL_255() |
|
3356 |
%{ |
|
3357 |
predicate(n->get_long() == 255); |
|
3358 |
match(ConL); |
|
3359 |
||
3360 |
format %{ %} |
|
3361 |
interface(CONST_INTER); |
|
3362 |
%} |
|
3363 |
||
3364 |
// Constant for short-wide masking |
|
3365 |
operand immL_65535() |
|
3366 |
%{ |
|
3367 |
predicate(n->get_long() == 65535); |
|
3368 |
match(ConL); |
|
3369 |
||
3370 |
format %{ %} |
|
3371 |
interface(CONST_INTER); |
|
3372 |
%} |
|
3373 |
||
3374 |
// Register Operands |
|
3375 |
// Integer Register |
|
3376 |
operand rRegI() |
|
3377 |
%{ |
|
3378 |
constraint(ALLOC_IN_RC(int_reg)); |
|
3379 |
match(RegI); |
|
3380 |
||
3381 |
match(rax_RegI); |
|
3382 |
match(rbx_RegI); |
|
3383 |
match(rcx_RegI); |
|
3384 |
match(rdx_RegI); |
|
3385 |
match(rdi_RegI); |
|
3386 |
||
3387 |
format %{ %} |
|
3388 |
interface(REG_INTER); |
|
3389 |
%} |
|
3390 |
||
3391 |
// Special Registers |
|
3392 |
operand rax_RegI() |
|
3393 |
%{ |
|
3394 |
constraint(ALLOC_IN_RC(int_rax_reg)); |
|
3395 |
match(RegI); |
|
3396 |
match(rRegI); |
|
3397 |
||
3398 |
format %{ "RAX" %} |
|
3399 |
interface(REG_INTER); |
|
3400 |
%} |
|
3401 |
||
3402 |
// Special Registers |
|
3403 |
operand rbx_RegI() |
|
3404 |
%{ |
|
3405 |
constraint(ALLOC_IN_RC(int_rbx_reg)); |
|
3406 |
match(RegI); |
|
3407 |
match(rRegI); |
|
3408 |
||
3409 |
format %{ "RBX" %} |
|
3410 |
interface(REG_INTER); |
|
3411 |
%} |
|
3412 |
||
3413 |
operand rcx_RegI() |
|
3414 |
%{ |
|
3415 |
constraint(ALLOC_IN_RC(int_rcx_reg)); |
|
3416 |
match(RegI); |
|
3417 |
match(rRegI); |
|
3418 |
||
3419 |
format %{ "RCX" %} |
|
3420 |
interface(REG_INTER); |
|
3421 |
%} |
|
3422 |
||
3423 |
operand rdx_RegI() |
|
3424 |
%{ |
|
3425 |
constraint(ALLOC_IN_RC(int_rdx_reg)); |
|
3426 |
match(RegI); |
|
3427 |
match(rRegI); |
|
3428 |
||
3429 |
format %{ "RDX" %} |
|
3430 |
interface(REG_INTER); |
|
3431 |
%} |
|
3432 |
||
3433 |
operand rdi_RegI() |
|
3434 |
%{ |
|
3435 |
constraint(ALLOC_IN_RC(int_rdi_reg)); |
|
3436 |
match(RegI); |
|
3437 |
match(rRegI); |
|
3438 |
||
3439 |
format %{ "RDI" %} |
|
3440 |
interface(REG_INTER); |
|
3441 |
%} |
|
3442 |
||
3443 |
operand no_rcx_RegI() |
|
3444 |
%{ |
|
3445 |
constraint(ALLOC_IN_RC(int_no_rcx_reg)); |
|
3446 |
match(RegI); |
|
3447 |
match(rax_RegI); |
|
3448 |
match(rbx_RegI); |
|
3449 |
match(rdx_RegI); |
|
3450 |
match(rdi_RegI); |
|
3451 |
||
3452 |
format %{ %} |
|
3453 |
interface(REG_INTER); |
|
3454 |
%} |
|
3455 |
||
3456 |
operand no_rax_rdx_RegI() |
|
3457 |
%{ |
|
3458 |
constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); |
|
3459 |
match(RegI); |
|
3460 |
match(rbx_RegI); |
|
3461 |
match(rcx_RegI); |
|
3462 |
match(rdi_RegI); |
|
3463 |
||
3464 |
format %{ %} |
|
3465 |
interface(REG_INTER); |
|
3466 |
%} |
|
3467 |
||
3468 |
// Pointer Register |
|
3469 |
operand any_RegP() |
|
3470 |
%{ |
|
3471 |
constraint(ALLOC_IN_RC(any_reg)); |
|
3472 |
match(RegP); |
|
3473 |
match(rax_RegP); |
|
3474 |
match(rbx_RegP); |
|
3475 |
match(rdi_RegP); |
|
3476 |
match(rsi_RegP); |
|
3477 |
match(rbp_RegP); |
|
3478 |
match(r15_RegP); |
|
3479 |
match(rRegP); |
|
3480 |
||
3481 |
format %{ %} |
|
3482 |
interface(REG_INTER); |
|
3483 |
%} |
|
3484 |
||
3485 |
operand rRegP() |
|
3486 |
%{ |
|
3487 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3488 |
match(RegP); |
|
3489 |
match(rax_RegP); |
|
3490 |
match(rbx_RegP); |
|
3491 |
match(rdi_RegP); |
|
3492 |
match(rsi_RegP); |
|
3493 |
match(rbp_RegP); |
|
3494 |
match(r15_RegP); // See Q&A below about r15_RegP. |
|
3495 |
||
3496 |
format %{ %} |
|
3497 |
interface(REG_INTER); |
|
3498 |
%} |
|
3499 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3500 |
operand rRegN() %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3501 |
constraint(ALLOC_IN_RC(int_reg)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3502 |
match(RegN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3503 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3504 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3505 |
interface(REG_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3506 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3507 |
|
1 | 3508 |
// Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
3509 |
// Answer: Operand match rules govern the DFA as it processes instruction inputs. |
|
3510 |
// It's fine for an instruction input which expects rRegP to match a r15_RegP. |
|
3511 |
// The output of an instruction is controlled by the allocator, which respects |
|
3512 |
// register class masks, not match rules. Unless an instruction mentions |
|
3513 |
// r15_RegP or any_RegP explicitly as its output, r15 will not be considered |
|
3514 |
// by the allocator as an input. |
|
3515 |
||
3516 |
operand no_rax_RegP() |
|
3517 |
%{ |
|
3518 |
constraint(ALLOC_IN_RC(ptr_no_rax_reg)); |
|
3519 |
match(RegP); |
|
3520 |
match(rbx_RegP); |
|
3521 |
match(rsi_RegP); |
|
3522 |
match(rdi_RegP); |
|
3523 |
||
3524 |
format %{ %} |
|
3525 |
interface(REG_INTER); |
|
3526 |
%} |
|
3527 |
||
3528 |
operand no_rbp_RegP() |
|
3529 |
%{ |
|
3530 |
constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); |
|
3531 |
match(RegP); |
|
3532 |
match(rbx_RegP); |
|
3533 |
match(rsi_RegP); |
|
3534 |
match(rdi_RegP); |
|
3535 |
||
3536 |
format %{ %} |
|
3537 |
interface(REG_INTER); |
|
3538 |
%} |
|
3539 |
||
3540 |
operand no_rax_rbx_RegP() |
|
3541 |
%{ |
|
3542 |
constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); |
|
3543 |
match(RegP); |
|
3544 |
match(rsi_RegP); |
|
3545 |
match(rdi_RegP); |
|
3546 |
||
3547 |
format %{ %} |
|
3548 |
interface(REG_INTER); |
|
3549 |
%} |
|
3550 |
||
3551 |
// Special Registers |
|
3552 |
// Return a pointer value |
|
3553 |
operand rax_RegP() |
|
3554 |
%{ |
|
3555 |
constraint(ALLOC_IN_RC(ptr_rax_reg)); |
|
3556 |
match(RegP); |
|
3557 |
match(rRegP); |
|
3558 |
||
3559 |
format %{ %} |
|
3560 |
interface(REG_INTER); |
|
3561 |
%} |
|
3562 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3563 |
// Special Registers |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3564 |
// Return a compressed pointer value |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3565 |
operand rax_RegN() |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3566 |
%{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3567 |
constraint(ALLOC_IN_RC(int_rax_reg)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3568 |
match(RegN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3569 |
match(rRegN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3570 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3571 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3572 |
interface(REG_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3573 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
3574 |
|
1 | 3575 |
// Used in AtomicAdd |
3576 |
operand rbx_RegP() |
|
3577 |
%{ |
|
3578 |
constraint(ALLOC_IN_RC(ptr_rbx_reg)); |
|
3579 |
match(RegP); |
|
3580 |
match(rRegP); |
|
3581 |
||
3582 |
format %{ %} |
|
3583 |
interface(REG_INTER); |
|
3584 |
%} |
|
3585 |
||
3586 |
operand rsi_RegP() |
|
3587 |
%{ |
|
3588 |
constraint(ALLOC_IN_RC(ptr_rsi_reg)); |
|
3589 |
match(RegP); |
|
3590 |
match(rRegP); |
|
3591 |
||
3592 |
format %{ %} |
|
3593 |
interface(REG_INTER); |
|
3594 |
%} |
|
3595 |
||
3596 |
// Used in rep stosq |
|
3597 |
operand rdi_RegP() |
|
3598 |
%{ |
|
3599 |
constraint(ALLOC_IN_RC(ptr_rdi_reg)); |
|
3600 |
match(RegP); |
|
3601 |
match(rRegP); |
|
3602 |
||
3603 |
format %{ %} |
|
3604 |
interface(REG_INTER); |
|
3605 |
%} |
|
3606 |
||
3607 |
operand rbp_RegP() |
|
3608 |
%{ |
|
3609 |
constraint(ALLOC_IN_RC(ptr_rbp_reg)); |
|
3610 |
match(RegP); |
|
3611 |
match(rRegP); |
|
3612 |
||
3613 |
format %{ %} |
|
3614 |
interface(REG_INTER); |
|
3615 |
%} |
|
3616 |
||
3617 |
operand r15_RegP() |
|
3618 |
%{ |
|
3619 |
constraint(ALLOC_IN_RC(ptr_r15_reg)); |
|
3620 |
match(RegP); |
|
3621 |
match(rRegP); |
|
3622 |
||
3623 |
format %{ %} |
|
3624 |
interface(REG_INTER); |
|
3625 |
%} |
|
3626 |
||
3627 |
operand rRegL() |
|
3628 |
%{ |
|
3629 |
constraint(ALLOC_IN_RC(long_reg)); |
|
3630 |
match(RegL); |
|
3631 |
match(rax_RegL); |
|
3632 |
match(rdx_RegL); |
|
3633 |
||
3634 |
format %{ %} |
|
3635 |
interface(REG_INTER); |
|
3636 |
%} |
|
3637 |
||
3638 |
// Special Registers |
|
3639 |
operand no_rax_rdx_RegL() |
|
3640 |
%{ |
|
3641 |
constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); |
|
3642 |
match(RegL); |
|
3643 |
match(rRegL); |
|
3644 |
||
3645 |
format %{ %} |
|
3646 |
interface(REG_INTER); |
|
3647 |
%} |
|
3648 |
||
3649 |
operand no_rax_RegL() |
|
3650 |
%{ |
|
3651 |
constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); |
|
3652 |
match(RegL); |
|
3653 |
match(rRegL); |
|
3654 |
match(rdx_RegL); |
|
3655 |
||
3656 |
format %{ %} |
|
3657 |
interface(REG_INTER); |
|
3658 |
%} |
|
3659 |
||
3660 |
operand no_rcx_RegL() |
|
3661 |
%{ |
|
3662 |
constraint(ALLOC_IN_RC(long_no_rcx_reg)); |
|
3663 |
match(RegL); |
|
3664 |
match(rRegL); |
|
3665 |
||
3666 |
format %{ %} |
|
3667 |
interface(REG_INTER); |
|
3668 |
%} |
|
3669 |
||
3670 |
operand rax_RegL() |
|
3671 |
%{ |
|
3672 |
constraint(ALLOC_IN_RC(long_rax_reg)); |
|
3673 |
match(RegL); |
|
3674 |
match(rRegL); |
|
3675 |
||
3676 |
format %{ "RAX" %} |
|
3677 |
interface(REG_INTER); |
|
3678 |
%} |
|
3679 |
||
3680 |
operand rcx_RegL() |
|
3681 |
%{ |
|
3682 |
constraint(ALLOC_IN_RC(long_rcx_reg)); |
|
3683 |
match(RegL); |
|
3684 |
match(rRegL); |
|
3685 |
||
3686 |
format %{ %} |
|
3687 |
interface(REG_INTER); |
|
3688 |
%} |
|
3689 |
||
3690 |
operand rdx_RegL() |
|
3691 |
%{ |
|
3692 |
constraint(ALLOC_IN_RC(long_rdx_reg)); |
|
3693 |
match(RegL); |
|
3694 |
match(rRegL); |
|
3695 |
||
3696 |
format %{ %} |
|
3697 |
interface(REG_INTER); |
|
3698 |
%} |
|
3699 |
||
3700 |
// Flags register, used as output of compare instructions |
|
3701 |
operand rFlagsReg() |
|
3702 |
%{ |
|
3703 |
constraint(ALLOC_IN_RC(int_flags)); |
|
3704 |
match(RegFlags); |
|
3705 |
||
3706 |
format %{ "RFLAGS" %} |
|
3707 |
interface(REG_INTER); |
|
3708 |
%} |
|
3709 |
||
3710 |
// Flags register, used as output of FLOATING POINT compare instructions |
|
3711 |
operand rFlagsRegU() |
|
3712 |
%{ |
|
3713 |
constraint(ALLOC_IN_RC(int_flags)); |
|
3714 |
match(RegFlags); |
|
3715 |
||
3716 |
format %{ "RFLAGS_U" %} |
|
3717 |
interface(REG_INTER); |
|
3718 |
%} |
|
3719 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3720 |
operand rFlagsRegUCF() %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3721 |
constraint(ALLOC_IN_RC(int_flags)); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3722 |
match(RegFlags); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3723 |
predicate(false); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3724 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3725 |
format %{ "RFLAGS_U_CF" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3726 |
interface(REG_INTER); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3727 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
3728 |
|
1 | 3729 |
// Float register operands |
3730 |
operand regF() |
|
3731 |
%{ |
|
3732 |
constraint(ALLOC_IN_RC(float_reg)); |
|
3733 |
match(RegF); |
|
3734 |
||
3735 |
format %{ %} |
|
3736 |
interface(REG_INTER); |
|
3737 |
%} |
|
3738 |
||
3739 |
// Double register operands |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
3740 |
operand regD() |
1 | 3741 |
%{ |
3742 |
constraint(ALLOC_IN_RC(double_reg)); |
|
3743 |
match(RegD); |
|
3744 |
||
3745 |
format %{ %} |
|
3746 |
interface(REG_INTER); |
|
3747 |
%} |
|
3748 |
||
3749 |
//----------Memory Operands---------------------------------------------------- |
|
3750 |
// Direct Memory Operand |
|
3751 |
// operand direct(immP addr) |
|
3752 |
// %{ |
|
3753 |
// match(addr); |
|
3754 |
||
3755 |
// format %{ "[$addr]" %} |
|
3756 |
// interface(MEMORY_INTER) %{ |
|
3757 |
// base(0xFFFFFFFF); |
|
3758 |
// index(0x4); |
|
3759 |
// scale(0x0); |
|
3760 |
// disp($addr); |
|
3761 |
// %} |
|
3762 |
// %} |
|
3763 |
||
3764 |
// Indirect Memory Operand |
|
3765 |
operand indirect(any_RegP reg) |
|
3766 |
%{ |
|
3767 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3768 |
match(reg); |
|
3769 |
||
3770 |
format %{ "[$reg]" %} |
|
3771 |
interface(MEMORY_INTER) %{ |
|
3772 |
base($reg); |
|
3773 |
index(0x4); |
|
3774 |
scale(0x0); |
|
3775 |
disp(0x0); |
|
3776 |
%} |
|
3777 |
%} |
|
3778 |
||
3779 |
// Indirect Memory Plus Short Offset Operand |
|
3780 |
operand indOffset8(any_RegP reg, immL8 off) |
|
3781 |
%{ |
|
3782 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3783 |
match(AddP reg off); |
|
3784 |
||
3785 |
format %{ "[$reg + $off (8-bit)]" %} |
|
3786 |
interface(MEMORY_INTER) %{ |
|
3787 |
base($reg); |
|
3788 |
index(0x4); |
|
3789 |
scale(0x0); |
|
3790 |
disp($off); |
|
3791 |
%} |
|
3792 |
%} |
|
3793 |
||
3794 |
// Indirect Memory Plus Long Offset Operand |
|
3795 |
operand indOffset32(any_RegP reg, immL32 off) |
|
3796 |
%{ |
|
3797 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3798 |
match(AddP reg off); |
|
3799 |
||
3800 |
format %{ "[$reg + $off (32-bit)]" %} |
|
3801 |
interface(MEMORY_INTER) %{ |
|
3802 |
base($reg); |
|
3803 |
index(0x4); |
|
3804 |
scale(0x0); |
|
3805 |
disp($off); |
|
3806 |
%} |
|
3807 |
%} |
|
3808 |
||
3809 |
// Indirect Memory Plus Index Register Plus Offset Operand |
|
3810 |
operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) |
|
3811 |
%{ |
|
3812 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3813 |
match(AddP (AddP reg lreg) off); |
|
3814 |
||
3815 |
op_cost(10); |
|
3816 |
format %{"[$reg + $off + $lreg]" %} |
|
3817 |
interface(MEMORY_INTER) %{ |
|
3818 |
base($reg); |
|
3819 |
index($lreg); |
|
3820 |
scale(0x0); |
|
3821 |
disp($off); |
|
3822 |
%} |
|
3823 |
%} |
|
3824 |
||
3825 |
// Indirect Memory Plus Index Register Plus Offset Operand |
|
3826 |
operand indIndex(any_RegP reg, rRegL lreg) |
|
3827 |
%{ |
|
3828 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3829 |
match(AddP reg lreg); |
|
3830 |
||
3831 |
op_cost(10); |
|
3832 |
format %{"[$reg + $lreg]" %} |
|
3833 |
interface(MEMORY_INTER) %{ |
|
3834 |
base($reg); |
|
3835 |
index($lreg); |
|
3836 |
scale(0x0); |
|
3837 |
disp(0x0); |
|
3838 |
%} |
|
3839 |
%} |
|
3840 |
||
3841 |
// Indirect Memory Times Scale Plus Index Register |
|
3842 |
operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) |
|
3843 |
%{ |
|
3844 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3845 |
match(AddP reg (LShiftL lreg scale)); |
|
3846 |
||
3847 |
op_cost(10); |
|
3848 |
format %{"[$reg + $lreg << $scale]" %} |
|
3849 |
interface(MEMORY_INTER) %{ |
|
3850 |
base($reg); |
|
3851 |
index($lreg); |
|
3852 |
scale($scale); |
|
3853 |
disp(0x0); |
|
3854 |
%} |
|
3855 |
%} |
|
3856 |
||
3857 |
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
3858 |
operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) |
|
3859 |
%{ |
|
3860 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3861 |
match(AddP (AddP reg (LShiftL lreg scale)) off); |
|
3862 |
||
3863 |
op_cost(10); |
|
3864 |
format %{"[$reg + $off + $lreg << $scale]" %} |
|
3865 |
interface(MEMORY_INTER) %{ |
|
3866 |
base($reg); |
|
3867 |
index($lreg); |
|
3868 |
scale($scale); |
|
3869 |
disp($off); |
|
3870 |
%} |
|
3871 |
%} |
|
3872 |
||
3873 |
// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
3874 |
operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) |
|
3875 |
%{ |
|
3876 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3877 |
predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
3878 |
match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); |
|
3879 |
||
3880 |
op_cost(10); |
|
3881 |
format %{"[$reg + $off + $idx << $scale]" %} |
|
3882 |
interface(MEMORY_INTER) %{ |
|
3883 |
base($reg); |
|
3884 |
index($idx); |
|
3885 |
scale($scale); |
|
3886 |
disp($off); |
|
3887 |
%} |
|
3888 |
%} |
|
3889 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3890 |
// Indirect Narrow Oop Plus Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3891 |
// Note: x86 architecture doesn't support "scale * index + offset" without a base |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3892 |
// we can't free r12 even with Universe::narrow_oop_base() == NULL. |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3893 |
operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
3894 |
predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3895 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3896 |
match(AddP (DecodeN reg) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3897 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3898 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3899 |
format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3900 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3901 |
base(0xc); // R12 |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3902 |
index($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3903 |
scale(0x3); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3904 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3905 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3906 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3907 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3908 |
// Indirect Memory Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3909 |
operand indirectNarrow(rRegN reg) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3910 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3911 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3912 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3913 |
match(DecodeN reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3914 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3915 |
format %{ "[$reg]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3916 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3917 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3918 |
index(0x4); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3919 |
scale(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3920 |
disp(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3921 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3922 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3923 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3924 |
// Indirect Memory Plus Short Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3925 |
operand indOffset8Narrow(rRegN reg, immL8 off) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3926 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3927 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3928 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3929 |
match(AddP (DecodeN reg) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3930 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3931 |
format %{ "[$reg + $off (8-bit)]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3932 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3933 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3934 |
index(0x4); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3935 |
scale(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3936 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3937 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3938 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3939 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3940 |
// Indirect Memory Plus Long Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3941 |
operand indOffset32Narrow(rRegN reg, immL32 off) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3942 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3943 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3944 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3945 |
match(AddP (DecodeN reg) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3946 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3947 |
format %{ "[$reg + $off (32-bit)]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3948 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3949 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3950 |
index(0x4); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3951 |
scale(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3952 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3953 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3954 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3955 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3956 |
// Indirect Memory Plus Index Register Plus Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3957 |
operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3958 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3959 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3960 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3961 |
match(AddP (AddP (DecodeN reg) lreg) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3962 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3963 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3964 |
format %{"[$reg + $off + $lreg]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3965 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3966 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3967 |
index($lreg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3968 |
scale(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3969 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3970 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3971 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3972 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3973 |
// Indirect Memory Plus Index Register Plus Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3974 |
operand indIndexNarrow(rRegN reg, rRegL lreg) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3975 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3976 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3977 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3978 |
match(AddP (DecodeN reg) lreg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3979 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3980 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3981 |
format %{"[$reg + $lreg]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3982 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3983 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3984 |
index($lreg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3985 |
scale(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3986 |
disp(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3987 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3988 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3989 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3990 |
// Indirect Memory Times Scale Plus Index Register |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3991 |
operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3992 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3993 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3994 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3995 |
match(AddP (DecodeN reg) (LShiftL lreg scale)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3996 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3997 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3998 |
format %{"[$reg + $lreg << $scale]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
3999 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4000 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4001 |
index($lreg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4002 |
scale($scale); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4003 |
disp(0x0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4004 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4005 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4006 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4007 |
// Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4008 |
operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4009 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4010 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4011 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4012 |
match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4013 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4014 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4015 |
format %{"[$reg + $off + $lreg << $scale]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4016 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4017 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4018 |
index($lreg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4019 |
scale($scale); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4020 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4021 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4022 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4023 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4024 |
// Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4025 |
operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4026 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4027 |
constraint(ALLOC_IN_RC(ptr_reg)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4028 |
predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4029 |
match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4030 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4031 |
op_cost(10); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4032 |
format %{"[$reg + $off + $idx << $scale]" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4033 |
interface(MEMORY_INTER) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4034 |
base($reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4035 |
index($idx); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4036 |
scale($scale); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4037 |
disp($off); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4038 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4039 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4040 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4041 |
|
1 | 4042 |
//----------Special Memory Operands-------------------------------------------- |
4043 |
// Stack Slot Operand - This operand is used for loading and storing temporary |
|
4044 |
// values on the stack where a match requires a value to |
|
4045 |
// flow through memory. |
|
4046 |
operand stackSlotP(sRegP reg) |
|
4047 |
%{ |
|
4048 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4049 |
// No match rule because this operand is only generated in matching |
|
4050 |
||
4051 |
format %{ "[$reg]" %} |
|
4052 |
interface(MEMORY_INTER) %{ |
|
4053 |
base(0x4); // RSP |
|
4054 |
index(0x4); // No Index |
|
4055 |
scale(0x0); // No Scale |
|
4056 |
disp($reg); // Stack Offset |
|
4057 |
%} |
|
4058 |
%} |
|
4059 |
||
4060 |
operand stackSlotI(sRegI reg) |
|
4061 |
%{ |
|
4062 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4063 |
// No match rule because this operand is only generated in matching |
|
4064 |
||
4065 |
format %{ "[$reg]" %} |
|
4066 |
interface(MEMORY_INTER) %{ |
|
4067 |
base(0x4); // RSP |
|
4068 |
index(0x4); // No Index |
|
4069 |
scale(0x0); // No Scale |
|
4070 |
disp($reg); // Stack Offset |
|
4071 |
%} |
|
4072 |
%} |
|
4073 |
||
4074 |
operand stackSlotF(sRegF reg) |
|
4075 |
%{ |
|
4076 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4077 |
// No match rule because this operand is only generated in matching |
|
4078 |
||
4079 |
format %{ "[$reg]" %} |
|
4080 |
interface(MEMORY_INTER) %{ |
|
4081 |
base(0x4); // RSP |
|
4082 |
index(0x4); // No Index |
|
4083 |
scale(0x0); // No Scale |
|
4084 |
disp($reg); // Stack Offset |
|
4085 |
%} |
|
4086 |
%} |
|
4087 |
||
4088 |
operand stackSlotD(sRegD reg) |
|
4089 |
%{ |
|
4090 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4091 |
// No match rule because this operand is only generated in matching |
|
4092 |
||
4093 |
format %{ "[$reg]" %} |
|
4094 |
interface(MEMORY_INTER) %{ |
|
4095 |
base(0x4); // RSP |
|
4096 |
index(0x4); // No Index |
|
4097 |
scale(0x0); // No Scale |
|
4098 |
disp($reg); // Stack Offset |
|
4099 |
%} |
|
4100 |
%} |
|
4101 |
operand stackSlotL(sRegL reg) |
|
4102 |
%{ |
|
4103 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4104 |
// No match rule because this operand is only generated in matching |
|
4105 |
||
4106 |
format %{ "[$reg]" %} |
|
4107 |
interface(MEMORY_INTER) %{ |
|
4108 |
base(0x4); // RSP |
|
4109 |
index(0x4); // No Index |
|
4110 |
scale(0x0); // No Scale |
|
4111 |
disp($reg); // Stack Offset |
|
4112 |
%} |
|
4113 |
%} |
|
4114 |
||
4115 |
//----------Conditional Branch Operands---------------------------------------- |
|
4116 |
// Comparison Op - This is the operation of the comparison, and is limited to |
|
4117 |
// the following set of codes: |
|
4118 |
// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) |
|
4119 |
// |
|
4120 |
// Other attributes of the comparison, such as unsignedness, are specified |
|
4121 |
// by the comparison instruction that sets a condition code flags register. |
|
4122 |
// That result is represented by a flags operand whose subtype is appropriate |
|
4123 |
// to the unsignedness (etc.) of the comparison. |
|
4124 |
// |
|
4125 |
// Later, the instruction which matches both the Comparison Op (a Bool) and |
|
4126 |
// the flags (produced by the Cmp) specifies the coding of the comparison op |
|
4127 |
// by matching a specific subtype of Bool operand below, such as cmpOpU. |
|
4128 |
||
4129 |
// Comparision Code |
|
4130 |
operand cmpOp() |
|
4131 |
%{ |
|
4132 |
match(Bool); |
|
4133 |
||
4134 |
format %{ "" %} |
|
4135 |
interface(COND_INTER) %{ |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4136 |
equal(0x4, "e"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4137 |
not_equal(0x5, "ne"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4138 |
less(0xC, "l"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4139 |
greater_equal(0xD, "ge"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4140 |
less_equal(0xE, "le"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4141 |
greater(0xF, "g"); |
1 | 4142 |
%} |
4143 |
%} |
|
4144 |
||
4145 |
// Comparison Code, unsigned compare. Used by FP also, with |
|
4146 |
// C2 (unordered) turned into GT or LT already. The other bits |
|
4147 |
// C0 and C3 are turned into Carry & Zero flags. |
|
4148 |
operand cmpOpU() |
|
4149 |
%{ |
|
4150 |
match(Bool); |
|
4151 |
||
4152 |
format %{ "" %} |
|
4153 |
interface(COND_INTER) %{ |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4154 |
equal(0x4, "e"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4155 |
not_equal(0x5, "ne"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4156 |
less(0x2, "b"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4157 |
greater_equal(0x3, "nb"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4158 |
less_equal(0x6, "be"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4159 |
greater(0x7, "nbe"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4160 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4161 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4162 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4163 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4164 |
// Floating comparisons that don't require any fixup for the unordered case |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4165 |
operand cmpOpUCF() %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4166 |
match(Bool); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4167 |
predicate(n->as_Bool()->_test._test == BoolTest::lt || |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4168 |
n->as_Bool()->_test._test == BoolTest::ge || |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4169 |
n->as_Bool()->_test._test == BoolTest::le || |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4170 |
n->as_Bool()->_test._test == BoolTest::gt); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4171 |
format %{ "" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4172 |
interface(COND_INTER) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4173 |
equal(0x4, "e"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4174 |
not_equal(0x5, "ne"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4175 |
less(0x2, "b"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4176 |
greater_equal(0x3, "nb"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4177 |
less_equal(0x6, "be"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4178 |
greater(0x7, "nbe"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4179 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4180 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4181 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4182 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4183 |
// Floating comparisons that can be fixed up with extra conditional jumps |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4184 |
operand cmpOpUCF2() %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4185 |
match(Bool); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4186 |
predicate(n->as_Bool()->_test._test == BoolTest::ne || |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4187 |
n->as_Bool()->_test._test == BoolTest::eq); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4188 |
format %{ "" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4189 |
interface(COND_INTER) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4190 |
equal(0x4, "e"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4191 |
not_equal(0x5, "ne"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4192 |
less(0x2, "b"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4193 |
greater_equal(0x3, "nb"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4194 |
less_equal(0x6, "be"); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
4195 |
greater(0x7, "nbe"); |
1 | 4196 |
%} |
4197 |
%} |
|
4198 |
||
4199 |
||
4200 |
//----------OPERAND CLASSES---------------------------------------------------- |
|
4201 |
// Operand Classes are groups of operands that are used as to simplify |
|
2131 | 4202 |
// instruction definitions by not requiring the AD writer to specify separate |
1 | 4203 |
// instructions for every form of operand when the instruction accepts |
4204 |
// multiple operand types with the same basic encoding and format. The classic |
|
4205 |
// case of this is memory operands. |
|
4206 |
||
4207 |
opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
4208 |
indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4209 |
indCompressedOopOffset, |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4210 |
indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4211 |
indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
4212 |
indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
1 | 4213 |
|
4214 |
//----------PIPELINE----------------------------------------------------------- |
|
4215 |
// Rules which define the behavior of the target architectures pipeline. |
|
4216 |
pipeline %{ |
|
4217 |
||
4218 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
4219 |
attributes %{ |
|
4220 |
variable_size_instructions; // Fixed size instructions |
|
4221 |
max_instructions_per_bundle = 3; // Up to 3 instructions per bundle |
|
4222 |
instruction_unit_size = 1; // An instruction is 1 bytes long |
|
4223 |
instruction_fetch_unit_size = 16; // The processor fetches one line |
|
4224 |
instruction_fetch_units = 1; // of 16 bytes |
|
4225 |
||
4226 |
// List of nop instructions |
|
4227 |
nops( MachNop ); |
|
4228 |
%} |
|
4229 |
||
4230 |
//----------RESOURCES---------------------------------------------------------- |
|
4231 |
// Resources are the functional units available to the machine |
|
4232 |
||
4233 |
// Generic P2/P3 pipeline |
|
4234 |
// 3 decoders, only D0 handles big operands; a "bundle" is the limit of |
|
4235 |
// 3 instructions decoded per cycle. |
|
4236 |
// 2 load/store ops per cycle, 1 branch, 1 FPU, |
|
4237 |
// 3 ALU op, only ALU0 handles mul instructions. |
|
4238 |
resources( D0, D1, D2, DECODE = D0 | D1 | D2, |
|
4239 |
MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, |
|
4240 |
BR, FPU, |
|
4241 |
ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); |
|
4242 |
||
4243 |
//----------PIPELINE DESCRIPTION----------------------------------------------- |
|
4244 |
// Pipeline Description specifies the stages in the machine's pipeline |
|
4245 |
||
4246 |
// Generic P2/P3 pipeline |
|
4247 |
pipe_desc(S0, S1, S2, S3, S4, S5); |
|
4248 |
||
4249 |
//----------PIPELINE CLASSES--------------------------------------------------- |
|
4250 |
// Pipeline Classes describe the stages in which input and output are |
|
4251 |
// referenced by the hardware pipeline. |
|
4252 |
||
4253 |
// Naming convention: ialu or fpu |
|
4254 |
// Then: _reg |
|
4255 |
// Then: _reg if there is a 2nd register |
|
4256 |
// Then: _long if it's a pair of instructions implementing a long |
|
4257 |
// Then: _fat if it requires the big decoder |
|
4258 |
// Or: _mem if it requires the big decoder and a memory unit. |
|
4259 |
||
4260 |
// Integer ALU reg operation |
|
4261 |
pipe_class ialu_reg(rRegI dst) |
|
4262 |
%{ |
|
4263 |
single_instruction; |
|
4264 |
dst : S4(write); |
|
4265 |
dst : S3(read); |
|
4266 |
DECODE : S0; // any decoder |
|
4267 |
ALU : S3; // any alu |
|
4268 |
%} |
|
4269 |
||
4270 |
// Long ALU reg operation |
|
4271 |
pipe_class ialu_reg_long(rRegL dst) |
|
4272 |
%{ |
|
4273 |
instruction_count(2); |
|
4274 |
dst : S4(write); |
|
4275 |
dst : S3(read); |
|
4276 |
DECODE : S0(2); // any 2 decoders |
|
4277 |
ALU : S3(2); // both alus |
|
4278 |
%} |
|
4279 |
||
4280 |
// Integer ALU reg operation using big decoder |
|
4281 |
pipe_class ialu_reg_fat(rRegI dst) |
|
4282 |
%{ |
|
4283 |
single_instruction; |
|
4284 |
dst : S4(write); |
|
4285 |
dst : S3(read); |
|
4286 |
D0 : S0; // big decoder only |
|
4287 |
ALU : S3; // any alu |
|
4288 |
%} |
|
4289 |
||
4290 |
// Long ALU reg operation using big decoder |
|
4291 |
pipe_class ialu_reg_long_fat(rRegL dst) |
|
4292 |
%{ |
|
4293 |
instruction_count(2); |
|
4294 |
dst : S4(write); |
|
4295 |
dst : S3(read); |
|
4296 |
D0 : S0(2); // big decoder only; twice |
|
4297 |
ALU : S3(2); // any 2 alus |
|
4298 |
%} |
|
4299 |
||
4300 |
// Integer ALU reg-reg operation |
|
4301 |
pipe_class ialu_reg_reg(rRegI dst, rRegI src) |
|
4302 |
%{ |
|
4303 |
single_instruction; |
|
4304 |
dst : S4(write); |
|
4305 |
src : S3(read); |
|
4306 |
DECODE : S0; // any decoder |
|
4307 |
ALU : S3; // any alu |
|
4308 |
%} |
|
4309 |
||
4310 |
// Long ALU reg-reg operation |
|
4311 |
pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) |
|
4312 |
%{ |
|
4313 |
instruction_count(2); |
|
4314 |
dst : S4(write); |
|
4315 |
src : S3(read); |
|
4316 |
DECODE : S0(2); // any 2 decoders |
|
4317 |
ALU : S3(2); // both alus |
|
4318 |
%} |
|
4319 |
||
4320 |
// Integer ALU reg-reg operation |
|
4321 |
pipe_class ialu_reg_reg_fat(rRegI dst, memory src) |
|
4322 |
%{ |
|
4323 |
single_instruction; |
|
4324 |
dst : S4(write); |
|
4325 |
src : S3(read); |
|
4326 |
D0 : S0; // big decoder only |
|
4327 |
ALU : S3; // any alu |
|
4328 |
%} |
|
4329 |
||
4330 |
// Long ALU reg-reg operation |
|
4331 |
pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) |
|
4332 |
%{ |
|
4333 |
instruction_count(2); |
|
4334 |
dst : S4(write); |
|
4335 |
src : S3(read); |
|
4336 |
D0 : S0(2); // big decoder only; twice |
|
4337 |
ALU : S3(2); // both alus |
|
4338 |
%} |
|
4339 |
||
4340 |
// Integer ALU reg-mem operation |
|
4341 |
pipe_class ialu_reg_mem(rRegI dst, memory mem) |
|
4342 |
%{ |
|
4343 |
single_instruction; |
|
4344 |
dst : S5(write); |
|
4345 |
mem : S3(read); |
|
4346 |
D0 : S0; // big decoder only |
|
4347 |
ALU : S4; // any alu |
|
4348 |
MEM : S3; // any mem |
|
4349 |
%} |
|
4350 |
||
4351 |
// Integer mem operation (prefetch) |
|
4352 |
pipe_class ialu_mem(memory mem) |
|
4353 |
%{ |
|
4354 |
single_instruction; |
|
4355 |
mem : S3(read); |
|
4356 |
D0 : S0; // big decoder only |
|
4357 |
MEM : S3; // any mem |
|
4358 |
%} |
|
4359 |
||
4360 |
// Integer Store to Memory |
|
4361 |
pipe_class ialu_mem_reg(memory mem, rRegI src) |
|
4362 |
%{ |
|
4363 |
single_instruction; |
|
4364 |
mem : S3(read); |
|
4365 |
src : S5(read); |
|
4366 |
D0 : S0; // big decoder only |
|
4367 |
ALU : S4; // any alu |
|
4368 |
MEM : S3; |
|
4369 |
%} |
|
4370 |
||
4371 |
// // Long Store to Memory |
|
4372 |
// pipe_class ialu_mem_long_reg(memory mem, rRegL src) |
|
4373 |
// %{ |
|
4374 |
// instruction_count(2); |
|
4375 |
// mem : S3(read); |
|
4376 |
// src : S5(read); |
|
4377 |
// D0 : S0(2); // big decoder only; twice |
|
4378 |
// ALU : S4(2); // any 2 alus |
|
4379 |
// MEM : S3(2); // Both mems |
|
4380 |
// %} |
|
4381 |
||
4382 |
// Integer Store to Memory |
|
4383 |
pipe_class ialu_mem_imm(memory mem) |
|
4384 |
%{ |
|
4385 |
single_instruction; |
|
4386 |
mem : S3(read); |
|
4387 |
D0 : S0; // big decoder only |
|
4388 |
ALU : S4; // any alu |
|
4389 |
MEM : S3; |
|
4390 |
%} |
|
4391 |
||
4392 |
// Integer ALU0 reg-reg operation |
|
4393 |
pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) |
|
4394 |
%{ |
|
4395 |
single_instruction; |
|
4396 |
dst : S4(write); |
|
4397 |
src : S3(read); |
|
4398 |
D0 : S0; // Big decoder only |
|
4399 |
ALU0 : S3; // only alu0 |
|
4400 |
%} |
|
4401 |
||
4402 |
// Integer ALU0 reg-mem operation |
|
4403 |
pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) |
|
4404 |
%{ |
|
4405 |
single_instruction; |
|
4406 |
dst : S5(write); |
|
4407 |
mem : S3(read); |
|
4408 |
D0 : S0; // big decoder only |
|
4409 |
ALU0 : S4; // ALU0 only |
|
4410 |
MEM : S3; // any mem |
|
4411 |
%} |
|
4412 |
||
4413 |
// Integer ALU reg-reg operation |
|
4414 |
pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) |
|
4415 |
%{ |
|
4416 |
single_instruction; |
|
4417 |
cr : S4(write); |
|
4418 |
src1 : S3(read); |
|
4419 |
src2 : S3(read); |
|
4420 |
DECODE : S0; // any decoder |
|
4421 |
ALU : S3; // any alu |
|
4422 |
%} |
|
4423 |
||
4424 |
// Integer ALU reg-imm operation |
|
4425 |
pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) |
|
4426 |
%{ |
|
4427 |
single_instruction; |
|
4428 |
cr : S4(write); |
|
4429 |
src1 : S3(read); |
|
4430 |
DECODE : S0; // any decoder |
|
4431 |
ALU : S3; // any alu |
|
4432 |
%} |
|
4433 |
||
4434 |
// Integer ALU reg-mem operation |
|
4435 |
pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) |
|
4436 |
%{ |
|
4437 |
single_instruction; |
|
4438 |
cr : S4(write); |
|
4439 |
src1 : S3(read); |
|
4440 |
src2 : S3(read); |
|
4441 |
D0 : S0; // big decoder only |
|
4442 |
ALU : S4; // any alu |
|
4443 |
MEM : S3; |
|
4444 |
%} |
|
4445 |
||
4446 |
// Conditional move reg-reg |
|
4447 |
pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) |
|
4448 |
%{ |
|
4449 |
instruction_count(4); |
|
4450 |
y : S4(read); |
|
4451 |
q : S3(read); |
|
4452 |
p : S3(read); |
|
4453 |
DECODE : S0(4); // any decoder |
|
4454 |
%} |
|
4455 |
||
4456 |
// Conditional move reg-reg |
|
4457 |
pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) |
|
4458 |
%{ |
|
4459 |
single_instruction; |
|
4460 |
dst : S4(write); |
|
4461 |
src : S3(read); |
|
4462 |
cr : S3(read); |
|
4463 |
DECODE : S0; // any decoder |
|
4464 |
%} |
|
4465 |
||
4466 |
// Conditional move reg-mem |
|
4467 |
pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) |
|
4468 |
%{ |
|
4469 |
single_instruction; |
|
4470 |
dst : S4(write); |
|
4471 |
src : S3(read); |
|
4472 |
cr : S3(read); |
|
4473 |
DECODE : S0; // any decoder |
|
4474 |
MEM : S3; |
|
4475 |
%} |
|
4476 |
||
4477 |
// Conditional move reg-reg long |
|
4478 |
pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) |
|
4479 |
%{ |
|
4480 |
single_instruction; |
|
4481 |
dst : S4(write); |
|
4482 |
src : S3(read); |
|
4483 |
cr : S3(read); |
|
4484 |
DECODE : S0(2); // any 2 decoders |
|
4485 |
%} |
|
4486 |
||
4487 |
// XXX |
|
4488 |
// // Conditional move double reg-reg |
|
4489 |
// pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) |
|
4490 |
// %{ |
|
4491 |
// single_instruction; |
|
4492 |
// dst : S4(write); |
|
4493 |
// src : S3(read); |
|
4494 |
// cr : S3(read); |
|
4495 |
// DECODE : S0; // any decoder |
|
4496 |
// %} |
|
4497 |
||
4498 |
// Float reg-reg operation |
|
4499 |
pipe_class fpu_reg(regD dst) |
|
4500 |
%{ |
|
4501 |
instruction_count(2); |
|
4502 |
dst : S3(read); |
|
4503 |
DECODE : S0(2); // any 2 decoders |
|
4504 |
FPU : S3; |
|
4505 |
%} |
|
4506 |
||
4507 |
// Float reg-reg operation |
|
4508 |
pipe_class fpu_reg_reg(regD dst, regD src) |
|
4509 |
%{ |
|
4510 |
instruction_count(2); |
|
4511 |
dst : S4(write); |
|
4512 |
src : S3(read); |
|
4513 |
DECODE : S0(2); // any 2 decoders |
|
4514 |
FPU : S3; |
|
4515 |
%} |
|
4516 |
||
4517 |
// Float reg-reg operation |
|
4518 |
pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) |
|
4519 |
%{ |
|
4520 |
instruction_count(3); |
|
4521 |
dst : S4(write); |
|
4522 |
src1 : S3(read); |
|
4523 |
src2 : S3(read); |
|
4524 |
DECODE : S0(3); // any 3 decoders |
|
4525 |
FPU : S3(2); |
|
4526 |
%} |
|
4527 |
||
4528 |
// Float reg-reg operation |
|
4529 |
pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) |
|
4530 |
%{ |
|
4531 |
instruction_count(4); |
|
4532 |
dst : S4(write); |
|
4533 |
src1 : S3(read); |
|
4534 |
src2 : S3(read); |
|
4535 |
src3 : S3(read); |
|
4536 |
DECODE : S0(4); // any 3 decoders |
|
4537 |
FPU : S3(2); |
|
4538 |
%} |
|
4539 |
||
4540 |
// Float reg-reg operation |
|
4541 |
pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) |
|
4542 |
%{ |
|
4543 |
instruction_count(4); |
|
4544 |
dst : S4(write); |
|
4545 |
src1 : S3(read); |
|
4546 |
src2 : S3(read); |
|
4547 |
src3 : S3(read); |
|
4548 |
DECODE : S1(3); // any 3 decoders |
|
4549 |
D0 : S0; // Big decoder only |
|
4550 |
FPU : S3(2); |
|
4551 |
MEM : S3; |
|
4552 |
%} |
|
4553 |
||
4554 |
// Float reg-mem operation |
|
4555 |
pipe_class fpu_reg_mem(regD dst, memory mem) |
|
4556 |
%{ |
|
4557 |
instruction_count(2); |
|
4558 |
dst : S5(write); |
|
4559 |
mem : S3(read); |
|
4560 |
D0 : S0; // big decoder only |
|
4561 |
DECODE : S1; // any decoder for FPU POP |
|
4562 |
FPU : S4; |
|
4563 |
MEM : S3; // any mem |
|
4564 |
%} |
|
4565 |
||
4566 |
// Float reg-mem operation |
|
4567 |
pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) |
|
4568 |
%{ |
|
4569 |
instruction_count(3); |
|
4570 |
dst : S5(write); |
|
4571 |
src1 : S3(read); |
|
4572 |
mem : S3(read); |
|
4573 |
D0 : S0; // big decoder only |
|
4574 |
DECODE : S1(2); // any decoder for FPU POP |
|
4575 |
FPU : S4; |
|
4576 |
MEM : S3; // any mem |
|
4577 |
%} |
|
4578 |
||
4579 |
// Float mem-reg operation |
|
4580 |
pipe_class fpu_mem_reg(memory mem, regD src) |
|
4581 |
%{ |
|
4582 |
instruction_count(2); |
|
4583 |
src : S5(read); |
|
4584 |
mem : S3(read); |
|
4585 |
DECODE : S0; // any decoder for FPU PUSH |
|
4586 |
D0 : S1; // big decoder only |
|
4587 |
FPU : S4; |
|
4588 |
MEM : S3; // any mem |
|
4589 |
%} |
|
4590 |
||
4591 |
pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) |
|
4592 |
%{ |
|
4593 |
instruction_count(3); |
|
4594 |
src1 : S3(read); |
|
4595 |
src2 : S3(read); |
|
4596 |
mem : S3(read); |
|
4597 |
DECODE : S0(2); // any decoder for FPU PUSH |
|
4598 |
D0 : S1; // big decoder only |
|
4599 |
FPU : S4; |
|
4600 |
MEM : S3; // any mem |
|
4601 |
%} |
|
4602 |
||
4603 |
pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) |
|
4604 |
%{ |
|
4605 |
instruction_count(3); |
|
4606 |
src1 : S3(read); |
|
4607 |
src2 : S3(read); |
|
4608 |
mem : S4(read); |
|
4609 |
DECODE : S0; // any decoder for FPU PUSH |
|
4610 |
D0 : S0(2); // big decoder only |
|
4611 |
FPU : S4; |
|
4612 |
MEM : S3(2); // any mem |
|
4613 |
%} |
|
4614 |
||
4615 |
pipe_class fpu_mem_mem(memory dst, memory src1) |
|
4616 |
%{ |
|
4617 |
instruction_count(2); |
|
4618 |
src1 : S3(read); |
|
4619 |
dst : S4(read); |
|
4620 |
D0 : S0(2); // big decoder only |
|
4621 |
MEM : S3(2); // any mem |
|
4622 |
%} |
|
4623 |
||
4624 |
pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) |
|
4625 |
%{ |
|
4626 |
instruction_count(3); |
|
4627 |
src1 : S3(read); |
|
4628 |
src2 : S3(read); |
|
4629 |
dst : S4(read); |
|
4630 |
D0 : S0(3); // big decoder only |
|
4631 |
FPU : S4; |
|
4632 |
MEM : S3(3); // any mem |
|
4633 |
%} |
|
4634 |
||
4635 |
pipe_class fpu_mem_reg_con(memory mem, regD src1) |
|
4636 |
%{ |
|
4637 |
instruction_count(3); |
|
4638 |
src1 : S4(read); |
|
4639 |
mem : S4(read); |
|
4640 |
DECODE : S0; // any decoder for FPU PUSH |
|
4641 |
D0 : S0(2); // big decoder only |
|
4642 |
FPU : S4; |
|
4643 |
MEM : S3(2); // any mem |
|
4644 |
%} |
|
4645 |
||
4646 |
// Float load constant |
|
4647 |
pipe_class fpu_reg_con(regD dst) |
|
4648 |
%{ |
|
4649 |
instruction_count(2); |
|
4650 |
dst : S5(write); |
|
4651 |
D0 : S0; // big decoder only for the load |
|
4652 |
DECODE : S1; // any decoder for FPU POP |
|
4653 |
FPU : S4; |
|
4654 |
MEM : S3; // any mem |
|
4655 |
%} |
|
4656 |
||
4657 |
// Float load constant |
|
4658 |
pipe_class fpu_reg_reg_con(regD dst, regD src) |
|
4659 |
%{ |
|
4660 |
instruction_count(3); |
|
4661 |
dst : S5(write); |
|
4662 |
src : S3(read); |
|
4663 |
D0 : S0; // big decoder only for the load |
|
4664 |
DECODE : S1(2); // any decoder for FPU POP |
|
4665 |
FPU : S4; |
|
4666 |
MEM : S3; // any mem |
|
4667 |
%} |
|
4668 |
||
4669 |
// UnConditional branch |
|
4670 |
pipe_class pipe_jmp(label labl) |
|
4671 |
%{ |
|
4672 |
single_instruction; |
|
4673 |
BR : S3; |
|
4674 |
%} |
|
4675 |
||
4676 |
// Conditional branch |
|
4677 |
pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) |
|
4678 |
%{ |
|
4679 |
single_instruction; |
|
4680 |
cr : S1(read); |
|
4681 |
BR : S3; |
|
4682 |
%} |
|
4683 |
||
4684 |
// Allocation idiom |
|
4685 |
pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) |
|
4686 |
%{ |
|
4687 |
instruction_count(1); force_serialization; |
|
4688 |
fixed_latency(6); |
|
4689 |
heap_ptr : S3(read); |
|
4690 |
DECODE : S0(3); |
|
4691 |
D0 : S2; |
|
4692 |
MEM : S3; |
|
4693 |
ALU : S3(2); |
|
4694 |
dst : S5(write); |
|
4695 |
BR : S5; |
|
4696 |
%} |
|
4697 |
||
4698 |
// Generic big/slow expanded idiom |
|
4699 |
pipe_class pipe_slow() |
|
4700 |
%{ |
|
4701 |
instruction_count(10); multiple_bundles; force_serialization; |
|
4702 |
fixed_latency(100); |
|
4703 |
D0 : S0(2); |
|
4704 |
MEM : S3(2); |
|
4705 |
%} |
|
4706 |
||
4707 |
// The real do-nothing guy |
|
4708 |
pipe_class empty() |
|
4709 |
%{ |
|
4710 |
instruction_count(0); |
|
4711 |
%} |
|
4712 |
||
4713 |
// Define the class for the Nop node |
|
4714 |
define |
|
4715 |
%{ |
|
4716 |
MachNop = empty; |
|
4717 |
%} |
|
4718 |
||
4719 |
%} |
|
4720 |
||
4721 |
//----------INSTRUCTIONS------------------------------------------------------- |
|
4722 |
// |
|
4723 |
// match -- States which machine-independent subtree may be replaced |
|
4724 |
// by this instruction. |
|
4725 |
// ins_cost -- The estimated cost of this instruction is used by instruction |
|
4726 |
// selection to identify a minimum cost tree of machine |
|
4727 |
// instructions that matches a tree of machine-independent |
|
4728 |
// instructions. |
|
4729 |
// format -- A string providing the disassembly for this instruction. |
|
4730 |
// The value of an instruction's operand may be inserted |
|
4731 |
// by referring to it with a '$' prefix. |
|
4732 |
// opcode -- Three instruction opcodes may be provided. These are referred |
|
4733 |
// to within an encode class as $primary, $secondary, and $tertiary |
|
4734 |
// rrspectively. The primary opcode is commonly used to |
|
4735 |
// indicate the type of machine instruction, while secondary |
|
4736 |
// and tertiary are often used for prefix options or addressing |
|
4737 |
// modes. |
|
4738 |
// ins_encode -- A list of encode classes with parameters. The encode class |
|
4739 |
// name must have been defined in an 'enc_class' specification |
|
4740 |
// in the encode section of the architecture description. |
|
4741 |
||
4742 |
||
4743 |
//----------Load/Store/Move Instructions--------------------------------------- |
|
4744 |
//----------Load Instructions-------------------------------------------------- |
|
4745 |
||
4746 |
// Load Byte (8 bit signed) |
|
4747 |
instruct loadB(rRegI dst, memory mem) |
|
4748 |
%{ |
|
4749 |
match(Set dst (LoadB mem)); |
|
4750 |
||
4751 |
ins_cost(125); |
|
4752 |
format %{ "movsbl $dst, $mem\t# byte" %} |
|
2150 | 4753 |
|
4754 |
ins_encode %{ |
|
4755 |
__ movsbl($dst$$Register, $mem$$Address); |
|
4756 |
%} |
|
4757 |
||
1 | 4758 |
ins_pipe(ialu_reg_mem); |
4759 |
%} |
|
4760 |
||
2150 | 4761 |
// Load Byte (8 bit signed) into Long Register |
4762 |
instruct loadB2L(rRegL dst, memory mem) |
|
4763 |
%{ |
|
4764 |
match(Set dst (ConvI2L (LoadB mem))); |
|
4765 |
||
4766 |
ins_cost(125); |
|
4767 |
format %{ "movsbq $dst, $mem\t# byte -> long" %} |
|
4768 |
||
4769 |
ins_encode %{ |
|
4770 |
__ movsbq($dst$$Register, $mem$$Address); |
|
4771 |
%} |
|
4772 |
||
4773 |
ins_pipe(ialu_reg_mem); |
|
4774 |
%} |
|
4775 |
||
4776 |
// Load Unsigned Byte (8 bit UNsigned) |
|
4777 |
instruct loadUB(rRegI dst, memory mem) |
|
4778 |
%{ |
|
4779 |
match(Set dst (LoadUB mem)); |
|
1 | 4780 |
|
4781 |
ins_cost(125); |
|
4782 |
format %{ "movzbl $dst, $mem\t# ubyte" %} |
|
2150 | 4783 |
|
4784 |
ins_encode %{ |
|
4785 |
__ movzbl($dst$$Register, $mem$$Address); |
|
4786 |
%} |
|
4787 |
||
1 | 4788 |
ins_pipe(ialu_reg_mem); |
4789 |
%} |
|
4790 |
||
2150 | 4791 |
// Load Unsigned Byte (8 bit UNsigned) into Long Register |
4792 |
instruct loadUB2L(rRegL dst, memory mem) |
|
4793 |
%{ |
|
4794 |
match(Set dst (ConvI2L (LoadUB mem))); |
|
4795 |
||
4796 |
ins_cost(125); |
|
4797 |
format %{ "movzbq $dst, $mem\t# ubyte -> long" %} |
|
4798 |
||
4799 |
ins_encode %{ |
|
4800 |
__ movzbq($dst$$Register, $mem$$Address); |
|
4801 |
%} |
|
4802 |
||
4803 |
ins_pipe(ialu_reg_mem); |
|
4804 |
%} |
|
1 | 4805 |
|
3177 | 4806 |
// Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
4807 |
instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ |
|
4808 |
match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); |
|
4809 |
effect(KILL cr); |
|
4810 |
||
4811 |
format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" |
|
4812 |
"andl $dst, $mask" %} |
|
4813 |
ins_encode %{ |
|
4814 |
Register Rdst = $dst$$Register; |
|
4815 |
__ movzbq(Rdst, $mem$$Address); |
|
4816 |
__ andl(Rdst, $mask$$constant); |
|
4817 |
%} |
|
4818 |
ins_pipe(ialu_reg_mem); |
|
4819 |
%} |
|
4820 |
||
1 | 4821 |
// Load Short (16 bit signed) |
4822 |
instruct loadS(rRegI dst, memory mem) |
|
4823 |
%{ |
|
4824 |
match(Set dst (LoadS mem)); |
|
4825 |
||
2150 | 4826 |
ins_cost(125); |
1 | 4827 |
format %{ "movswl $dst, $mem\t# short" %} |
2150 | 4828 |
|
4829 |
ins_encode %{ |
|
4830 |
__ movswl($dst$$Register, $mem$$Address); |
|
4831 |
%} |
|
4832 |
||
1 | 4833 |
ins_pipe(ialu_reg_mem); |
4834 |
%} |
|
4835 |
||
2872 | 4836 |
// Load Short (16 bit signed) to Byte (8 bit signed) |
4837 |
instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
|
4838 |
match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
|
4839 |
||
4840 |
ins_cost(125); |
|
4841 |
format %{ "movsbl $dst, $mem\t# short -> byte" %} |
|
4842 |
ins_encode %{ |
|
4843 |
__ movsbl($dst$$Register, $mem$$Address); |
|
4844 |
%} |
|
4845 |
ins_pipe(ialu_reg_mem); |
|
4846 |
%} |
|
4847 |
||
2150 | 4848 |
// Load Short (16 bit signed) into Long Register |
4849 |
instruct loadS2L(rRegL dst, memory mem) |
|
4850 |
%{ |
|
4851 |
match(Set dst (ConvI2L (LoadS mem))); |
|
4852 |
||
4853 |
ins_cost(125); |
|
4854 |
format %{ "movswq $dst, $mem\t# short -> long" %} |
|
4855 |
||
4856 |
ins_encode %{ |
|
4857 |
__ movswq($dst$$Register, $mem$$Address); |
|
4858 |
%} |
|
4859 |
||
4860 |
ins_pipe(ialu_reg_mem); |
|
4861 |
%} |
|
1 | 4862 |
|
2022
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
1500
diff
changeset
|
4863 |
// Load Unsigned Short/Char (16 bit UNsigned) |
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
1500
diff
changeset
|
4864 |
instruct loadUS(rRegI dst, memory mem) |
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
1500
diff
changeset
|
4865 |
%{ |
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
1500
diff
changeset
|
4866 |
match(Set dst (LoadUS mem)); |
1 | 4867 |
|
4868 |
ins_cost(125); |
|
2022
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
1500
diff
changeset
|
4869 |
format %{ "movzwl $dst, $mem\t# ushort/char" %} |
2150 | 4870 |
|
4871 |
ins_encode %{ |
|
4872 |
__ movzwl($dst$$Register, $mem$$Address); |
|
4873 |
%} |
|
4874 |
||
1 | 4875 |
ins_pipe(ialu_reg_mem); |
4876 |
%} |
|
4877 |
||
2872 | 4878 |
// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
4879 |
instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
|
4880 |
match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
|
4881 |
||
4882 |
ins_cost(125); |
|
4883 |
format %{ "movsbl $dst, $mem\t# ushort -> byte" %} |
|
4884 |
ins_encode %{ |
|
4885 |
__ movsbl($dst$$Register, $mem$$Address); |
|
4886 |
%} |
|
4887 |
ins_pipe(ialu_reg_mem); |
|
4888 |
%} |
|
4889 |
||
2150 | 4890 |
// Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
4891 |
instruct loadUS2L(rRegL dst, memory mem) |
|
4892 |
%{ |
|
4893 |
match(Set dst (ConvI2L (LoadUS mem))); |
|
4894 |
||
4895 |
ins_cost(125); |
|
4896 |
format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} |
|
4897 |
||
4898 |
ins_encode %{ |
|
4899 |
__ movzwq($dst$$Register, $mem$$Address); |
|
4900 |
%} |
|
4901 |
||
4902 |
ins_pipe(ialu_reg_mem); |
|
4903 |
%} |
|
1 | 4904 |
|
3177 | 4905 |
// Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
4906 |
instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ |
|
4907 |
match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
|
4908 |
||
4909 |
format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} |
|
4910 |
ins_encode %{ |
|
4911 |
__ movzbq($dst$$Register, $mem$$Address); |
|
4912 |
%} |
|
4913 |
ins_pipe(ialu_reg_mem); |
|
4914 |
%} |
|
4915 |
||
4916 |
// Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register |
|
4917 |
instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ |
|
4918 |
match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
|
4919 |
effect(KILL cr); |
|
4920 |
||
4921 |
format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" |
|
4922 |
"andl $dst, $mask" %} |
|
4923 |
ins_encode %{ |
|
4924 |
Register Rdst = $dst$$Register; |
|
4925 |
__ movzwq(Rdst, $mem$$Address); |
|
4926 |
__ andl(Rdst, $mask$$constant); |
|
4927 |
%} |
|
4928 |
ins_pipe(ialu_reg_mem); |
|
4929 |
%} |
|
4930 |
||
1 | 4931 |
// Load Integer |
4932 |
instruct loadI(rRegI dst, memory mem) |
|
4933 |
%{ |
|
4934 |
match(Set dst (LoadI mem)); |
|
4935 |
||
2150 | 4936 |
ins_cost(125); |
1 | 4937 |
format %{ "movl $dst, $mem\t# int" %} |
2150 | 4938 |
|
4939 |
ins_encode %{ |
|
4940 |
__ movl($dst$$Register, $mem$$Address); |
|
4941 |
%} |
|
4942 |
||
4943 |
ins_pipe(ialu_reg_mem); |
|
4944 |
%} |
|
4945 |
||
2872 | 4946 |
// Load Integer (32 bit signed) to Byte (8 bit signed) |
4947 |
instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
|
4948 |
match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
|
4949 |
||
4950 |
ins_cost(125); |
|
4951 |
format %{ "movsbl $dst, $mem\t# int -> byte" %} |
|
4952 |
ins_encode %{ |
|
4953 |
__ movsbl($dst$$Register, $mem$$Address); |
|
4954 |
%} |
|
4955 |
ins_pipe(ialu_reg_mem); |
|
4956 |
%} |
|
4957 |
||
4958 |
// Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) |
|
4959 |
instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
|
4960 |
match(Set dst (AndI (LoadI mem) mask)); |
|
4961 |
||
4962 |
ins_cost(125); |
|
4963 |
format %{ "movzbl $dst, $mem\t# int -> ubyte" %} |
|
4964 |
ins_encode %{ |
|
4965 |
__ movzbl($dst$$Register, $mem$$Address); |
|
4966 |
%} |
|
4967 |
ins_pipe(ialu_reg_mem); |
|
4968 |
%} |
|
4969 |
||
4970 |
// Load Integer (32 bit signed) to Short (16 bit signed) |
|
4971 |
instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
|
4972 |
match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
|
4973 |
||
4974 |
ins_cost(125); |
|
4975 |
format %{ "movswl $dst, $mem\t# int -> short" %} |
|
4976 |
ins_encode %{ |
|
4977 |
__ movswl($dst$$Register, $mem$$Address); |
|
4978 |
%} |
|
4979 |
ins_pipe(ialu_reg_mem); |
|
4980 |
%} |
|
4981 |
||
4982 |
// Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) |
|
4983 |
instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
|
4984 |
match(Set dst (AndI (LoadI mem) mask)); |
|
4985 |
||
4986 |
ins_cost(125); |
|
4987 |
format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} |
|
4988 |
ins_encode %{ |
|
4989 |
__ movzwl($dst$$Register, $mem$$Address); |
|
4990 |
%} |
|
4991 |
ins_pipe(ialu_reg_mem); |
|
4992 |
%} |
|
4993 |
||
2150 | 4994 |
// Load Integer into Long Register |
4995 |
instruct loadI2L(rRegL dst, memory mem) |
|
4996 |
%{ |
|
4997 |
match(Set dst (ConvI2L (LoadI mem))); |
|
4998 |
||
4999 |
ins_cost(125); |
|
5000 |
format %{ "movslq $dst, $mem\t# int -> long" %} |
|
5001 |
||
5002 |
ins_encode %{ |
|
5003 |
__ movslq($dst$$Register, $mem$$Address); |
|
5004 |
%} |
|
5005 |
||
5006 |
ins_pipe(ialu_reg_mem); |
|
5007 |
%} |
|
5008 |
||
3177 | 5009 |
// Load Integer with mask 0xFF into Long Register |
5010 |
instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ |
|
5011 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
|
5012 |
||
5013 |
format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} |
|
5014 |
ins_encode %{ |
|
5015 |
__ movzbq($dst$$Register, $mem$$Address); |
|
5016 |
%} |
|
5017 |
ins_pipe(ialu_reg_mem); |
|
5018 |
%} |
|
5019 |
||
5020 |
// Load Integer with mask 0xFFFF into Long Register |
|
5021 |
instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ |
|
5022 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
|
5023 |
||
5024 |
format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} |
|
5025 |
ins_encode %{ |
|
5026 |
__ movzwq($dst$$Register, $mem$$Address); |
|
5027 |
%} |
|
5028 |
ins_pipe(ialu_reg_mem); |
|
5029 |
%} |
|
5030 |
||
5031 |
// Load Integer with a 32-bit mask into Long Register |
|
5032 |
instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ |
|
5033 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
|
5034 |
effect(KILL cr); |
|
5035 |
||
5036 |
format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" |
|
5037 |
"andl $dst, $mask" %} |
|
5038 |
ins_encode %{ |
|
5039 |
Register Rdst = $dst$$Register; |
|
5040 |
__ movl(Rdst, $mem$$Address); |
|
5041 |
__ andl(Rdst, $mask$$constant); |
|
5042 |
%} |
|
5043 |
ins_pipe(ialu_reg_mem); |
|
5044 |
%} |
|
5045 |
||
2150 | 5046 |
// Load Unsigned Integer into Long Register |
5047 |
instruct loadUI2L(rRegL dst, memory mem) |
|
5048 |
%{ |
|
5049 |
match(Set dst (LoadUI2L mem)); |
|
5050 |
||
5051 |
ins_cost(125); |
|
5052 |
format %{ "movl $dst, $mem\t# uint -> long" %} |
|
5053 |
||
5054 |
ins_encode %{ |
|
5055 |
__ movl($dst$$Register, $mem$$Address); |
|
5056 |
%} |
|
5057 |
||
1 | 5058 |
ins_pipe(ialu_reg_mem); |
5059 |
%} |
|
5060 |
||
5061 |
// Load Long |
|
5062 |
instruct loadL(rRegL dst, memory mem) |
|
5063 |
%{ |
|
5064 |
match(Set dst (LoadL mem)); |
|
5065 |
||
2150 | 5066 |
ins_cost(125); |
1 | 5067 |
format %{ "movq $dst, $mem\t# long" %} |
2150 | 5068 |
|
5069 |
ins_encode %{ |
|
5070 |
__ movq($dst$$Register, $mem$$Address); |
|
5071 |
%} |
|
5072 |
||
1 | 5073 |
ins_pipe(ialu_reg_mem); // XXX |
5074 |
%} |
|
5075 |
||
5076 |
// Load Range |
|
5077 |
instruct loadRange(rRegI dst, memory mem) |
|
5078 |
%{ |
|
5079 |
match(Set dst (LoadRange mem)); |
|
5080 |
||
5081 |
ins_cost(125); // XXX |
|
5082 |
format %{ "movl $dst, $mem\t# range" %} |
|
5083 |
opcode(0x8B); |
|
5084 |
ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5085 |
ins_pipe(ialu_reg_mem); |
|
5086 |
%} |
|
5087 |
||
5088 |
// Load Pointer |
|
5089 |
instruct loadP(rRegP dst, memory mem) |
|
5090 |
%{ |
|
5091 |
match(Set dst (LoadP mem)); |
|
5092 |
||
5093 |
ins_cost(125); // XXX |
|
5094 |
format %{ "movq $dst, $mem\t# ptr" %} |
|
5095 |
opcode(0x8B); |
|
5096 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5097 |
ins_pipe(ialu_reg_mem); // XXX |
|
5098 |
%} |
|
5099 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5100 |
// Load Compressed Pointer |
589 | 5101 |
instruct loadN(rRegN dst, memory mem) |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5102 |
%{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5103 |
match(Set dst (LoadN mem)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5104 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5105 |
ins_cost(125); // XXX |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5106 |
format %{ "movl $dst, $mem\t# compressed ptr" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5107 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5108 |
__ movl($dst$$Register, $mem$$Address); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5109 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5110 |
ins_pipe(ialu_reg_mem); // XXX |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5111 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5112 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5113 |
|
1 | 5114 |
// Load Klass Pointer |
5115 |
instruct loadKlass(rRegP dst, memory mem) |
|
5116 |
%{ |
|
5117 |
match(Set dst (LoadKlass mem)); |
|
5118 |
||
5119 |
ins_cost(125); // XXX |
|
5120 |
format %{ "movq $dst, $mem\t# class" %} |
|
5121 |
opcode(0x8B); |
|
5122 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5123 |
ins_pipe(ialu_reg_mem); // XXX |
|
5124 |
%} |
|
5125 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5126 |
// Load narrow Klass Pointer |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5127 |
instruct loadNKlass(rRegN dst, memory mem) |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5128 |
%{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5129 |
match(Set dst (LoadNKlass mem)); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5130 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5131 |
ins_cost(125); // XXX |
608
fe8c5fbbc54e
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
595
diff
changeset
|
5132 |
format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5133 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5134 |
__ movl($dst$$Register, $mem$$Address); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5135 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5136 |
ins_pipe(ialu_reg_mem); // XXX |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5137 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5138 |
|
1 | 5139 |
// Load Float |
5140 |
instruct loadF(regF dst, memory mem) |
|
5141 |
%{ |
|
5142 |
match(Set dst (LoadF mem)); |
|
5143 |
||
5144 |
ins_cost(145); // XXX |
|
5145 |
format %{ "movss $dst, $mem\t# float" %} |
|
11427 | 5146 |
ins_encode %{ |
5147 |
__ movflt($dst$$XMMRegister, $mem$$Address); |
|
5148 |
%} |
|
1 | 5149 |
ins_pipe(pipe_slow); // XXX |
5150 |
%} |
|
5151 |
||
5152 |
// Load Double |
|
5153 |
instruct loadD_partial(regD dst, memory mem) |
|
5154 |
%{ |
|
5155 |
predicate(!UseXmmLoadAndClearUpper); |
|
5156 |
match(Set dst (LoadD mem)); |
|
5157 |
||
5158 |
ins_cost(145); // XXX |
|
5159 |
format %{ "movlpd $dst, $mem\t# double" %} |
|
11427 | 5160 |
ins_encode %{ |
5161 |
__ movdbl($dst$$XMMRegister, $mem$$Address); |
|
5162 |
%} |
|
1 | 5163 |
ins_pipe(pipe_slow); // XXX |
5164 |
%} |
|
5165 |
||
5166 |
instruct loadD(regD dst, memory mem) |
|
5167 |
%{ |
|
5168 |
predicate(UseXmmLoadAndClearUpper); |
|
5169 |
match(Set dst (LoadD mem)); |
|
5170 |
||
5171 |
ins_cost(145); // XXX |
|
5172 |
format %{ "movsd $dst, $mem\t# double" %} |
|
11427 | 5173 |
ins_encode %{ |
5174 |
__ movdbl($dst$$XMMRegister, $mem$$Address); |
|
5175 |
%} |
|
1 | 5176 |
ins_pipe(pipe_slow); // XXX |
5177 |
%} |
|
5178 |
||
5179 |
// Load Effective Address |
|
5180 |
instruct leaP8(rRegP dst, indOffset8 mem) |
|
5181 |
%{ |
|
5182 |
match(Set dst mem); |
|
5183 |
||
5184 |
ins_cost(110); // XXX |
|
5185 |
format %{ "leaq $dst, $mem\t# ptr 8" %} |
|
5186 |
opcode(0x8D); |
|
5187 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5188 |
ins_pipe(ialu_reg_reg_fat); |
|
5189 |
%} |
|
5190 |
||
5191 |
instruct leaP32(rRegP dst, indOffset32 mem) |
|
5192 |
%{ |
|
5193 |
match(Set dst mem); |
|
5194 |
||
5195 |
ins_cost(110); |
|
5196 |
format %{ "leaq $dst, $mem\t# ptr 32" %} |
|
5197 |
opcode(0x8D); |
|
5198 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5199 |
ins_pipe(ialu_reg_reg_fat); |
|
5200 |
%} |
|
5201 |
||
5202 |
// instruct leaPIdx(rRegP dst, indIndex mem) |
|
5203 |
// %{ |
|
5204 |
// match(Set dst mem); |
|
5205 |
||
5206 |
// ins_cost(110); |
|
5207 |
// format %{ "leaq $dst, $mem\t# ptr idx" %} |
|
5208 |
// opcode(0x8D); |
|
5209 |
// ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5210 |
// ins_pipe(ialu_reg_reg_fat); |
|
5211 |
// %} |
|
5212 |
||
5213 |
instruct leaPIdxOff(rRegP dst, indIndexOffset mem) |
|
5214 |
%{ |
|
5215 |
match(Set dst mem); |
|
5216 |
||
5217 |
ins_cost(110); |
|
5218 |
format %{ "leaq $dst, $mem\t# ptr idxoff" %} |
|
5219 |
opcode(0x8D); |
|
5220 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5221 |
ins_pipe(ialu_reg_reg_fat); |
|
5222 |
%} |
|
5223 |
||
5224 |
instruct leaPIdxScale(rRegP dst, indIndexScale mem) |
|
5225 |
%{ |
|
5226 |
match(Set dst mem); |
|
5227 |
||
5228 |
ins_cost(110); |
|
5229 |
format %{ "leaq $dst, $mem\t# ptr idxscale" %} |
|
5230 |
opcode(0x8D); |
|
5231 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5232 |
ins_pipe(ialu_reg_reg_fat); |
|
5233 |
%} |
|
5234 |
||
5235 |
instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) |
|
5236 |
%{ |
|
5237 |
match(Set dst mem); |
|
5238 |
||
5239 |
ins_cost(110); |
|
5240 |
format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} |
|
5241 |
opcode(0x8D); |
|
5242 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
5243 |
ins_pipe(ialu_reg_reg_fat); |
|
5244 |
%} |
|
5245 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5246 |
instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5247 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5248 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5249 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5250 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5251 |
format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5252 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5253 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5254 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5255 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5256 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5257 |
// Load Effective Address which uses Narrow (32-bits) oop |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5258 |
instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5259 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5260 |
predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5261 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5262 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5263 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5264 |
format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5265 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5266 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5267 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5268 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5269 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5270 |
instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5271 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5272 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5273 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5274 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5275 |
ins_cost(110); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5276 |
format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5277 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5278 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5279 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5280 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5281 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5282 |
instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5283 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5284 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5285 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5286 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5287 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5288 |
format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5289 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5290 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5291 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5292 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5293 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5294 |
instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5295 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5296 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5297 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5298 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5299 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5300 |
format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5301 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5302 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5303 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5304 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5305 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5306 |
instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5307 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5308 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5309 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5310 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5311 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5312 |
format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5313 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5314 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5315 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5316 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5317 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5318 |
instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5319 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5320 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5321 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5322 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5323 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5324 |
format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5325 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5326 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5327 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5328 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5329 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5330 |
instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5331 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5332 |
predicate(Universe::narrow_oop_shift() == 0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5333 |
match(Set dst mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5334 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5335 |
ins_cost(110); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5336 |
format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5337 |
opcode(0x8D); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5338 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5339 |
ins_pipe(ialu_reg_reg_fat); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5340 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5341 |
|
1 | 5342 |
instruct loadConI(rRegI dst, immI src) |
5343 |
%{ |
|
5344 |
match(Set dst src); |
|
5345 |
||
5346 |
format %{ "movl $dst, $src\t# int" %} |
|
5347 |
ins_encode(load_immI(dst, src)); |
|
5348 |
ins_pipe(ialu_reg_fat); // XXX |
|
5349 |
%} |
|
5350 |
||
5351 |
instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) |
|
5352 |
%{ |
|
5353 |
match(Set dst src); |
|
5354 |
effect(KILL cr); |
|
5355 |
||
5356 |
ins_cost(50); |
|
5357 |
format %{ "xorl $dst, $dst\t# int" %} |
|
5358 |
opcode(0x33); /* + rd */ |
|
5359 |
ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); |
|
5360 |
ins_pipe(ialu_reg); |
|
5361 |
%} |
|
5362 |
||
5363 |
instruct loadConL(rRegL dst, immL src) |
|
5364 |
%{ |
|
5365 |
match(Set dst src); |
|
5366 |
||
5367 |
ins_cost(150); |
|
5368 |
format %{ "movq $dst, $src\t# long" %} |
|
5369 |
ins_encode(load_immL(dst, src)); |
|
5370 |
ins_pipe(ialu_reg); |
|
5371 |
%} |
|
5372 |
||
5373 |
instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) |
|
5374 |
%{ |
|
5375 |
match(Set dst src); |
|
5376 |
effect(KILL cr); |
|
5377 |
||
5378 |
ins_cost(50); |
|
5379 |
format %{ "xorl $dst, $dst\t# long" %} |
|
5380 |
opcode(0x33); /* + rd */ |
|
5381 |
ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); |
|
5382 |
ins_pipe(ialu_reg); // XXX |
|
5383 |
%} |
|
5384 |
||
5385 |
instruct loadConUL32(rRegL dst, immUL32 src) |
|
5386 |
%{ |
|
5387 |
match(Set dst src); |
|
5388 |
||
5389 |
ins_cost(60); |
|
5390 |
format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} |
|
5391 |
ins_encode(load_immUL32(dst, src)); |
|
5392 |
ins_pipe(ialu_reg); |
|
5393 |
%} |
|
5394 |
||
5395 |
instruct loadConL32(rRegL dst, immL32 src) |
|
5396 |
%{ |
|
5397 |
match(Set dst src); |
|
5398 |
||
5399 |
ins_cost(70); |
|
5400 |
format %{ "movq $dst, $src\t# long (32-bit)" %} |
|
5401 |
ins_encode(load_immL32(dst, src)); |
|
5402 |
ins_pipe(ialu_reg); |
|
5403 |
%} |
|
5404 |
||
7433 | 5405 |
instruct loadConP(rRegP dst, immP con) %{ |
5406 |
match(Set dst con); |
|
5407 |
||
5408 |
format %{ "movq $dst, $con\t# ptr" %} |
|
5409 |
ins_encode(load_immP(dst, con)); |
|
1 | 5410 |
ins_pipe(ialu_reg_fat); // XXX |
5411 |
%} |
|
5412 |
||
5413 |
instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) |
|
5414 |
%{ |
|
5415 |
match(Set dst src); |
|
5416 |
effect(KILL cr); |
|
5417 |
||
5418 |
ins_cost(50); |
|
5419 |
format %{ "xorl $dst, $dst\t# ptr" %} |
|
5420 |
opcode(0x33); /* + rd */ |
|
5421 |
ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); |
|
5422 |
ins_pipe(ialu_reg); |
|
5423 |
%} |
|
5424 |
||
5425 |
instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) |
|
5426 |
%{ |
|
5427 |
match(Set dst src); |
|
5428 |
effect(KILL cr); |
|
5429 |
||
5430 |
ins_cost(60); |
|
5431 |
format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} |
|
5432 |
ins_encode(load_immP31(dst, src)); |
|
5433 |
ins_pipe(ialu_reg); |
|
5434 |
%} |
|
5435 |
||
7433 | 5436 |
instruct loadConF(regF dst, immF con) %{ |
5437 |
match(Set dst con); |
|
1 | 5438 |
ins_cost(125); |
7433 | 5439 |
format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
5440 |
ins_encode %{ |
|
5441 |
__ movflt($dst$$XMMRegister, $constantaddress($con)); |
|
5442 |
%} |
|
1 | 5443 |
ins_pipe(pipe_slow); |
5444 |
%} |
|
5445 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5446 |
instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5447 |
match(Set dst src); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5448 |
effect(KILL cr); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
5449 |
format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5450 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5451 |
__ xorq($dst$$Register, $dst$$Register); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5452 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5453 |
ins_pipe(ialu_reg); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5454 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5455 |
|
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5456 |
instruct loadConN(rRegN dst, immN src) %{ |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5457 |
match(Set dst src); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5458 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5459 |
ins_cost(125); |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5460 |
format %{ "movl $dst, $src\t# compressed ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5461 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5462 |
address con = (address)$src$$constant; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5463 |
if (con == NULL) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5464 |
ShouldNotReachHere(); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5465 |
} else { |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5466 |
__ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5467 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5468 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5469 |
ins_pipe(ialu_reg_fat); // XXX |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5470 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5471 |
|
1 | 5472 |
instruct loadConF0(regF dst, immF0 src) |
5473 |
%{ |
|
5474 |
match(Set dst src); |
|
5475 |
ins_cost(100); |
|
5476 |
||
5477 |
format %{ "xorps $dst, $dst\t# float 0.0" %} |
|
11427 | 5478 |
ins_encode %{ |
5479 |
__ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
|
5480 |
%} |
|
1 | 5481 |
ins_pipe(pipe_slow); |
5482 |
%} |
|
5483 |
||
5484 |
// Use the same format since predicate() can not be used here. |
|
7433 | 5485 |
instruct loadConD(regD dst, immD con) %{ |
5486 |
match(Set dst con); |
|
1 | 5487 |
ins_cost(125); |
7433 | 5488 |
format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
5489 |
ins_encode %{ |
|
5490 |
__ movdbl($dst$$XMMRegister, $constantaddress($con)); |
|
5491 |
%} |
|
1 | 5492 |
ins_pipe(pipe_slow); |
5493 |
%} |
|
5494 |
||
5495 |
instruct loadConD0(regD dst, immD0 src) |
|
5496 |
%{ |
|
5497 |
match(Set dst src); |
|
5498 |
ins_cost(100); |
|
5499 |
||
5500 |
format %{ "xorpd $dst, $dst\t# double 0.0" %} |
|
11427 | 5501 |
ins_encode %{ |
5502 |
__ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); |
|
5503 |
%} |
|
1 | 5504 |
ins_pipe(pipe_slow); |
5505 |
%} |
|
5506 |
||
5507 |
instruct loadSSI(rRegI dst, stackSlotI src) |
|
5508 |
%{ |
|
5509 |
match(Set dst src); |
|
5510 |
||
5511 |
ins_cost(125); |
|
5512 |
format %{ "movl $dst, $src\t# int stk" %} |
|
5513 |
opcode(0x8B); |
|
5514 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
5515 |
ins_pipe(ialu_reg_mem); |
|
5516 |
%} |
|
5517 |
||
5518 |
instruct loadSSL(rRegL dst, stackSlotL src) |
|
5519 |
%{ |
|
5520 |
match(Set dst src); |
|
5521 |
||
5522 |
ins_cost(125); |
|
5523 |
format %{ "movq $dst, $src\t# long stk" %} |
|
5524 |
opcode(0x8B); |
|
5525 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
5526 |
ins_pipe(ialu_reg_mem); |
|
5527 |
%} |
|
5528 |
||
5529 |
instruct loadSSP(rRegP dst, stackSlotP src) |
|
5530 |
%{ |
|
5531 |
match(Set dst src); |
|
5532 |
||
5533 |
ins_cost(125); |
|
5534 |
format %{ "movq $dst, $src\t# ptr stk" %} |
|
5535 |
opcode(0x8B); |
|
5536 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
5537 |
ins_pipe(ialu_reg_mem); |
|
5538 |
%} |
|
5539 |
||
5540 |
instruct loadSSF(regF dst, stackSlotF src) |
|
5541 |
%{ |
|
5542 |
match(Set dst src); |
|
5543 |
||
5544 |
ins_cost(125); |
|
5545 |
format %{ "movss $dst, $src\t# float stk" %} |
|
11427 | 5546 |
ins_encode %{ |
5547 |
__ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); |
|
5548 |
%} |
|
1 | 5549 |
ins_pipe(pipe_slow); // XXX |
5550 |
%} |
|
5551 |
||
5552 |
// Use the same format since predicate() can not be used here. |
|
5553 |
instruct loadSSD(regD dst, stackSlotD src) |
|
5554 |
%{ |
|
5555 |
match(Set dst src); |
|
5556 |
||
5557 |
ins_cost(125); |
|
5558 |
format %{ "movsd $dst, $src\t# double stk" %} |
|
5559 |
ins_encode %{ |
|
5560 |
__ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); |
|
5561 |
%} |
|
5562 |
ins_pipe(pipe_slow); // XXX |
|
5563 |
%} |
|
5564 |
||
5565 |
// Prefetch instructions. |
|
5566 |
// Must be safe to execute with invalid address (cannot fault). |
|
5567 |
||
5568 |
instruct prefetchr( memory mem ) %{ |
|
5569 |
predicate(ReadPrefetchInstr==3); |
|
5570 |
match(PrefetchRead mem); |
|
5571 |
ins_cost(125); |
|
5572 |
||
5573 |
format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} |
|
10267 | 5574 |
ins_encode %{ |
5575 |
__ prefetchr($mem$$Address); |
|
5576 |
%} |
|
1 | 5577 |
ins_pipe(ialu_mem); |
5578 |
%} |
|
5579 |
||
5580 |
instruct prefetchrNTA( memory mem ) %{ |
|
5581 |
predicate(ReadPrefetchInstr==0); |
|
5582 |
match(PrefetchRead mem); |
|
5583 |
ins_cost(125); |
|
5584 |
||
5585 |
format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} |
|
10267 | 5586 |
ins_encode %{ |
5587 |
__ prefetchnta($mem$$Address); |
|
5588 |
%} |
|
1 | 5589 |
ins_pipe(ialu_mem); |
5590 |
%} |
|
5591 |
||
5592 |
instruct prefetchrT0( memory mem ) %{ |
|
5593 |
predicate(ReadPrefetchInstr==1); |
|
5594 |
match(PrefetchRead mem); |
|
5595 |
ins_cost(125); |
|
5596 |
||
5597 |
format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} |
|
10267 | 5598 |
ins_encode %{ |
5599 |
__ prefetcht0($mem$$Address); |
|
5600 |
%} |
|
1 | 5601 |
ins_pipe(ialu_mem); |
5602 |
%} |
|
5603 |
||
5604 |
instruct prefetchrT2( memory mem ) %{ |
|
5605 |
predicate(ReadPrefetchInstr==2); |
|
5606 |
match(PrefetchRead mem); |
|
5607 |
ins_cost(125); |
|
5608 |
||
5609 |
format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} |
|
10267 | 5610 |
ins_encode %{ |
5611 |
__ prefetcht2($mem$$Address); |
|
5612 |
%} |
|
1 | 5613 |
ins_pipe(ialu_mem); |
5614 |
%} |
|
5615 |
||
5616 |
instruct prefetchwNTA( memory mem ) %{ |
|
5617 |
match(PrefetchWrite mem); |
|
5618 |
ins_cost(125); |
|
5619 |
||
5620 |
format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} |
|
10267 | 5621 |
ins_encode %{ |
5622 |
__ prefetchnta($mem$$Address); |
|
5623 |
%} |
|
1 | 5624 |
ins_pipe(ialu_mem); |
5625 |
%} |
|
5626 |
||
10267 | 5627 |
// Prefetch instructions for allocation. |
5628 |
||
5629 |
instruct prefetchAlloc( memory mem ) %{ |
|
5630 |
predicate(AllocatePrefetchInstr==3); |
|
5631 |
match(PrefetchAllocation mem); |
|
5632 |
ins_cost(125); |
|
5633 |
||
5634 |
format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} |
|
5635 |
ins_encode %{ |
|
5636 |
__ prefetchw($mem$$Address); |
|
5637 |
%} |
|
5638 |
ins_pipe(ialu_mem); |
|
5639 |
%} |
|
5640 |
||
5641 |
instruct prefetchAllocNTA( memory mem ) %{ |
|
5642 |
predicate(AllocatePrefetchInstr==0); |
|
5643 |
match(PrefetchAllocation mem); |
|
1 | 5644 |
ins_cost(125); |
5645 |
||
10267 | 5646 |
format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
5647 |
ins_encode %{ |
|
5648 |
__ prefetchnta($mem$$Address); |
|
5649 |
%} |
|
1 | 5650 |
ins_pipe(ialu_mem); |
5651 |
%} |
|
5652 |
||
10267 | 5653 |
instruct prefetchAllocT0( memory mem ) %{ |
5654 |
predicate(AllocatePrefetchInstr==1); |
|
5655 |
match(PrefetchAllocation mem); |
|
1 | 5656 |
ins_cost(125); |
5657 |
||
10267 | 5658 |
format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
5659 |
ins_encode %{ |
|
5660 |
__ prefetcht0($mem$$Address); |
|
5661 |
%} |
|
5662 |
ins_pipe(ialu_mem); |
|
5663 |
%} |
|
5664 |
||
5665 |
instruct prefetchAllocT2( memory mem ) %{ |
|
5666 |
predicate(AllocatePrefetchInstr==2); |
|
5667 |
match(PrefetchAllocation mem); |
|
5668 |
ins_cost(125); |
|
5669 |
||
5670 |
format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} |
|
5671 |
ins_encode %{ |
|
5672 |
__ prefetcht2($mem$$Address); |
|
5673 |
%} |
|
1 | 5674 |
ins_pipe(ialu_mem); |
5675 |
%} |
|
5676 |
||
5677 |
//----------Store Instructions------------------------------------------------- |
|
5678 |
||
5679 |
// Store Byte |
|
5680 |
instruct storeB(memory mem, rRegI src) |
|
5681 |
%{ |
|
5682 |
match(Set mem (StoreB mem src)); |
|
5683 |
||
5684 |
ins_cost(125); // XXX |
|
5685 |
format %{ "movb $mem, $src\t# byte" %} |
|
5686 |
opcode(0x88); |
|
5687 |
ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); |
|
5688 |
ins_pipe(ialu_mem_reg); |
|
5689 |
%} |
|
5690 |
||
5691 |
// Store Char/Short |
|
5692 |
instruct storeC(memory mem, rRegI src) |
|
5693 |
%{ |
|
5694 |
match(Set mem (StoreC mem src)); |
|
5695 |
||
5696 |
ins_cost(125); // XXX |
|
5697 |
format %{ "movw $mem, $src\t# char/short" %} |
|
5698 |
opcode(0x89); |
|
5699 |
ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); |
|
5700 |
ins_pipe(ialu_mem_reg); |
|
5701 |
%} |
|
5702 |
||
5703 |
// Store Integer |
|
5704 |
instruct storeI(memory mem, rRegI src) |
|
5705 |
%{ |
|
5706 |
match(Set mem (StoreI mem src)); |
|
5707 |
||
5708 |
ins_cost(125); // XXX |
|
5709 |
format %{ "movl $mem, $src\t# int" %} |
|
5710 |
opcode(0x89); |
|
5711 |
ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); |
|
5712 |
ins_pipe(ialu_mem_reg); |
|
5713 |
%} |
|
5714 |
||
5715 |
// Store Long |
|
5716 |
instruct storeL(memory mem, rRegL src) |
|
5717 |
%{ |
|
5718 |
match(Set mem (StoreL mem src)); |
|
5719 |
||
5720 |
ins_cost(125); // XXX |
|
5721 |
format %{ "movq $mem, $src\t# long" %} |
|
5722 |
opcode(0x89); |
|
5723 |
ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); |
|
5724 |
ins_pipe(ialu_mem_reg); // XXX |
|
5725 |
%} |
|
5726 |
||
5727 |
// Store Pointer |
|
5728 |
instruct storeP(memory mem, any_RegP src) |
|
5729 |
%{ |
|
5730 |
match(Set mem (StoreP mem src)); |
|
5731 |
||
5732 |
ins_cost(125); // XXX |
|
5733 |
format %{ "movq $mem, $src\t# ptr" %} |
|
5734 |
opcode(0x89); |
|
5735 |
ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); |
|
5736 |
ins_pipe(ialu_mem_reg); |
|
5737 |
%} |
|
5738 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5739 |
instruct storeImmP0(memory mem, immP0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5740 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5741 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5742 |
match(Set mem (StoreP mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5743 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5744 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5745 |
format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5746 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5747 |
__ movq($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5748 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5749 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5750 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5751 |
|
1 | 5752 |
// Store NULL Pointer, mark word, or other simple pointer constant. |
5753 |
instruct storeImmP(memory mem, immP31 src) |
|
5754 |
%{ |
|
5755 |
match(Set mem (StoreP mem src)); |
|
5756 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5757 |
ins_cost(150); // XXX |
1 | 5758 |
format %{ "movq $mem, $src\t# ptr" %} |
5759 |
opcode(0xC7); /* C7 /0 */ |
|
5760 |
ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
|
5761 |
ins_pipe(ialu_mem_imm); |
|
5762 |
%} |
|
5763 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5764 |
// Store Compressed Pointer |
589 | 5765 |
instruct storeN(memory mem, rRegN src) |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5766 |
%{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5767 |
match(Set mem (StoreN mem src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5768 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5769 |
ins_cost(125); // XXX |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
5770 |
format %{ "movl $mem, $src\t# compressed ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5771 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5772 |
__ movl($mem$$Address, $src$$Register); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5773 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5774 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5775 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5776 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5777 |
instruct storeImmN0(memory mem, immN0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5778 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5779 |
predicate(Universe::narrow_oop_base() == NULL); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5780 |
match(Set mem (StoreN mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5781 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5782 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5783 |
format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5784 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5785 |
__ movl($mem$$Address, r12); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5786 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5787 |
ins_pipe(ialu_mem_reg); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5788 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
5789 |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5790 |
instruct storeImmN(memory mem, immN src) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5791 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5792 |
match(Set mem (StoreN mem src)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5793 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5794 |
ins_cost(150); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5795 |
format %{ "movl $mem, $src\t# compressed ptr" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5796 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5797 |
address con = (address)$src$$constant; |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5798 |
if (con == NULL) { |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5799 |
__ movl($mem$$Address, (int32_t)0); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5800 |
} else { |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5801 |
__ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5802 |
} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5803 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5804 |
ins_pipe(ialu_mem_imm); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5805 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5806 |
|
1 | 5807 |
// Store Integer Immediate |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5808 |
instruct storeImmI0(memory mem, immI0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5809 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5810 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5811 |
match(Set mem (StoreI mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5812 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5813 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5814 |
format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5815 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5816 |
__ movl($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5817 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5818 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5819 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5820 |
|
1 | 5821 |
instruct storeImmI(memory mem, immI src) |
5822 |
%{ |
|
5823 |
match(Set mem (StoreI mem src)); |
|
5824 |
||
5825 |
ins_cost(150); |
|
5826 |
format %{ "movl $mem, $src\t# int" %} |
|
5827 |
opcode(0xC7); /* C7 /0 */ |
|
5828 |
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
|
5829 |
ins_pipe(ialu_mem_imm); |
|
5830 |
%} |
|
5831 |
||
5832 |
// Store Long Immediate |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5833 |
instruct storeImmL0(memory mem, immL0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5834 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5835 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5836 |
match(Set mem (StoreL mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5837 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5838 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5839 |
format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5840 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5841 |
__ movq($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5842 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5843 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5844 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5845 |
|
1 | 5846 |
instruct storeImmL(memory mem, immL32 src) |
5847 |
%{ |
|
5848 |
match(Set mem (StoreL mem src)); |
|
5849 |
||
5850 |
ins_cost(150); |
|
5851 |
format %{ "movq $mem, $src\t# long" %} |
|
5852 |
opcode(0xC7); /* C7 /0 */ |
|
5853 |
ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); |
|
5854 |
ins_pipe(ialu_mem_imm); |
|
5855 |
%} |
|
5856 |
||
5857 |
// Store Short/Char Immediate |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5858 |
instruct storeImmC0(memory mem, immI0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5859 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5860 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5861 |
match(Set mem (StoreC mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5862 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5863 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5864 |
format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5865 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5866 |
__ movw($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5867 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5868 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5869 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5870 |
|
1 | 5871 |
instruct storeImmI16(memory mem, immI16 src) |
5872 |
%{ |
|
5873 |
predicate(UseStoreImmI16); |
|
5874 |
match(Set mem (StoreC mem src)); |
|
5875 |
||
5876 |
ins_cost(150); |
|
5877 |
format %{ "movw $mem, $src\t# short/char" %} |
|
5878 |
opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ |
|
5879 |
ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); |
|
5880 |
ins_pipe(ialu_mem_imm); |
|
5881 |
%} |
|
5882 |
||
5883 |
// Store Byte Immediate |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5884 |
instruct storeImmB0(memory mem, immI0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5885 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5886 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5887 |
match(Set mem (StoreB mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5888 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5889 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5890 |
format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5891 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5892 |
__ movb($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5893 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5894 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5895 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5896 |
|
1 | 5897 |
instruct storeImmB(memory mem, immI8 src) |
5898 |
%{ |
|
5899 |
match(Set mem (StoreB mem src)); |
|
5900 |
||
5901 |
ins_cost(150); // XXX |
|
5902 |
format %{ "movb $mem, $src\t# byte" %} |
|
5903 |
opcode(0xC6); /* C6 /0 */ |
|
5904 |
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); |
|
5905 |
ins_pipe(ialu_mem_imm); |
|
5906 |
%} |
|
5907 |
||
5908 |
// Store CMS card-mark Immediate |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5909 |
instruct storeImmCM0_reg(memory mem, immI0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5910 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5911 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5912 |
match(Set mem (StoreCM mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5913 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5914 |
ins_cost(125); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5915 |
format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5916 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5917 |
__ movb($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5918 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5919 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5920 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5921 |
|
1 | 5922 |
instruct storeImmCM0(memory mem, immI0 src) |
5923 |
%{ |
|
5924 |
match(Set mem (StoreCM mem src)); |
|
5925 |
||
5926 |
ins_cost(150); // XXX |
|
5927 |
format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} |
|
5928 |
opcode(0xC6); /* C6 /0 */ |
|
5929 |
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); |
|
5930 |
ins_pipe(ialu_mem_imm); |
|
5931 |
%} |
|
5932 |
||
5933 |
// Store Float |
|
5934 |
instruct storeF(memory mem, regF src) |
|
5935 |
%{ |
|
5936 |
match(Set mem (StoreF mem src)); |
|
5937 |
||
5938 |
ins_cost(95); // XXX |
|
5939 |
format %{ "movss $mem, $src\t# float" %} |
|
11427 | 5940 |
ins_encode %{ |
5941 |
__ movflt($mem$$Address, $src$$XMMRegister); |
|
5942 |
%} |
|
1 | 5943 |
ins_pipe(pipe_slow); // XXX |
5944 |
%} |
|
5945 |
||
5946 |
// Store immediate Float value (it is faster than store from XMM register) |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5947 |
instruct storeF0(memory mem, immF0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5948 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5949 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5950 |
match(Set mem (StoreF mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5951 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5952 |
ins_cost(25); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5953 |
format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5954 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5955 |
__ movl($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5956 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5957 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5958 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5959 |
|
1 | 5960 |
instruct storeF_imm(memory mem, immF src) |
5961 |
%{ |
|
5962 |
match(Set mem (StoreF mem src)); |
|
5963 |
||
5964 |
ins_cost(50); |
|
5965 |
format %{ "movl $mem, $src\t# float" %} |
|
5966 |
opcode(0xC7); /* C7 /0 */ |
|
5967 |
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); |
|
5968 |
ins_pipe(ialu_mem_imm); |
|
5969 |
%} |
|
5970 |
||
5971 |
// Store Double |
|
5972 |
instruct storeD(memory mem, regD src) |
|
5973 |
%{ |
|
5974 |
match(Set mem (StoreD mem src)); |
|
5975 |
||
5976 |
ins_cost(95); // XXX |
|
5977 |
format %{ "movsd $mem, $src\t# double" %} |
|
11427 | 5978 |
ins_encode %{ |
5979 |
__ movdbl($mem$$Address, $src$$XMMRegister); |
|
5980 |
%} |
|
1 | 5981 |
ins_pipe(pipe_slow); // XXX |
5982 |
%} |
|
5983 |
||
5984 |
// Store immediate double 0.0 (it is faster than store from XMM register) |
|
5985 |
instruct storeD0_imm(memory mem, immD0 src) |
|
5986 |
%{ |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5987 |
predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
1 | 5988 |
match(Set mem (StoreD mem src)); |
5989 |
||
5990 |
ins_cost(50); |
|
5991 |
format %{ "movq $mem, $src\t# double 0." %} |
|
5992 |
opcode(0xC7); /* C7 /0 */ |
|
5993 |
ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); |
|
5994 |
ins_pipe(ialu_mem_imm); |
|
5995 |
%} |
|
5996 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5997 |
instruct storeD0(memory mem, immD0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5998 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
5999 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6000 |
match(Set mem (StoreD mem zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6001 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6002 |
ins_cost(25); // XXX |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6003 |
format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6004 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6005 |
__ movq($mem$$Address, r12); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6006 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6007 |
ins_pipe(ialu_mem_reg); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6008 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6009 |
|
1 | 6010 |
instruct storeSSI(stackSlotI dst, rRegI src) |
6011 |
%{ |
|
6012 |
match(Set dst src); |
|
6013 |
||
6014 |
ins_cost(100); |
|
6015 |
format %{ "movl $dst, $src\t# int stk" %} |
|
6016 |
opcode(0x89); |
|
6017 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
6018 |
ins_pipe( ialu_mem_reg ); |
|
6019 |
%} |
|
6020 |
||
6021 |
instruct storeSSL(stackSlotL dst, rRegL src) |
|
6022 |
%{ |
|
6023 |
match(Set dst src); |
|
6024 |
||
6025 |
ins_cost(100); |
|
6026 |
format %{ "movq $dst, $src\t# long stk" %} |
|
6027 |
opcode(0x89); |
|
6028 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
6029 |
ins_pipe(ialu_mem_reg); |
|
6030 |
%} |
|
6031 |
||
6032 |
instruct storeSSP(stackSlotP dst, rRegP src) |
|
6033 |
%{ |
|
6034 |
match(Set dst src); |
|
6035 |
||
6036 |
ins_cost(100); |
|
6037 |
format %{ "movq $dst, $src\t# ptr stk" %} |
|
6038 |
opcode(0x89); |
|
6039 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
6040 |
ins_pipe(ialu_mem_reg); |
|
6041 |
%} |
|
6042 |
||
6043 |
instruct storeSSF(stackSlotF dst, regF src) |
|
6044 |
%{ |
|
6045 |
match(Set dst src); |
|
6046 |
||
6047 |
ins_cost(95); // XXX |
|
6048 |
format %{ "movss $dst, $src\t# float stk" %} |
|
11427 | 6049 |
ins_encode %{ |
6050 |
__ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); |
|
6051 |
%} |
|
1 | 6052 |
ins_pipe(pipe_slow); // XXX |
6053 |
%} |
|
6054 |
||
6055 |
instruct storeSSD(stackSlotD dst, regD src) |
|
6056 |
%{ |
|
6057 |
match(Set dst src); |
|
6058 |
||
6059 |
ins_cost(95); // XXX |
|
6060 |
format %{ "movsd $dst, $src\t# double stk" %} |
|
11427 | 6061 |
ins_encode %{ |
6062 |
__ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
|
6063 |
%} |
|
1 | 6064 |
ins_pipe(pipe_slow); // XXX |
6065 |
%} |
|
6066 |
||
6067 |
//----------BSWAP Instructions------------------------------------------------- |
|
6068 |
instruct bytes_reverse_int(rRegI dst) %{ |
|
6069 |
match(Set dst (ReverseBytesI dst)); |
|
6070 |
||
6071 |
format %{ "bswapl $dst" %} |
|
6072 |
opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ |
|
6073 |
ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); |
|
6074 |
ins_pipe( ialu_reg ); |
|
6075 |
%} |
|
6076 |
||
6077 |
instruct bytes_reverse_long(rRegL dst) %{ |
|
6078 |
match(Set dst (ReverseBytesL dst)); |
|
6079 |
||
6080 |
format %{ "bswapq $dst" %} |
|
6081 |
opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ |
|
6082 |
ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); |
|
6083 |
ins_pipe( ialu_reg); |
|
6084 |
%} |
|
6085 |
||
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6086 |
instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6087 |
match(Set dst (ReverseBytesUS dst)); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6088 |
effect(KILL cr); |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6089 |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
6090 |
format %{ "bswapl $dst\n\t" |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6091 |
"shrl $dst,16\n\t" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6092 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6093 |
__ bswapl($dst$$Register); |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
6094 |
__ shrl($dst$$Register, 16); |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6095 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6096 |
ins_pipe( ialu_reg ); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6097 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6098 |
|
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6099 |
instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6100 |
match(Set dst (ReverseBytesS dst)); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6101 |
effect(KILL cr); |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6102 |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
6103 |
format %{ "bswapl $dst\n\t" |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6104 |
"sar $dst,16\n\t" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6105 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6106 |
__ bswapl($dst$$Register); |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
6107 |
__ sarl($dst$$Register, 16); |
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6108 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6109 |
ins_pipe( ialu_reg ); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6110 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5025
diff
changeset
|
6111 |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6112 |
//---------- Zeros Count Instructions ------------------------------------------ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6113 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6114 |
instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6115 |
predicate(UseCountLeadingZerosInstruction); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6116 |
match(Set dst (CountLeadingZerosI src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6117 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6118 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6119 |
format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6120 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6121 |
__ lzcntl($dst$$Register, $src$$Register); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6122 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6123 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6124 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6125 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6126 |
instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6127 |
predicate(!UseCountLeadingZerosInstruction); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6128 |
match(Set dst (CountLeadingZerosI src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6129 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6130 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6131 |
format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6132 |
"jnz skip\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6133 |
"movl $dst, -1\n" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6134 |
"skip:\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6135 |
"negl $dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6136 |
"addl $dst, 31" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6137 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6138 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6139 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6140 |
Label skip; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6141 |
__ bsrl(Rdst, Rsrc); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6142 |
__ jccb(Assembler::notZero, skip); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6143 |
__ movl(Rdst, -1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6144 |
__ bind(skip); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6145 |
__ negl(Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6146 |
__ addl(Rdst, BitsPerInt - 1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6147 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6148 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6149 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6150 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6151 |
instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6152 |
predicate(UseCountLeadingZerosInstruction); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6153 |
match(Set dst (CountLeadingZerosL src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6154 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6155 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6156 |
format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6157 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6158 |
__ lzcntq($dst$$Register, $src$$Register); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6159 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6160 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6161 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6162 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6163 |
instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6164 |
predicate(!UseCountLeadingZerosInstruction); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6165 |
match(Set dst (CountLeadingZerosL src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6166 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6167 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6168 |
format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6169 |
"jnz skip\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6170 |
"movl $dst, -1\n" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6171 |
"skip:\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6172 |
"negl $dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6173 |
"addl $dst, 63" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6174 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6175 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6176 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6177 |
Label skip; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6178 |
__ bsrq(Rdst, Rsrc); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6179 |
__ jccb(Assembler::notZero, skip); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6180 |
__ movl(Rdst, -1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6181 |
__ bind(skip); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6182 |
__ negl(Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6183 |
__ addl(Rdst, BitsPerLong - 1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6184 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6185 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6186 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6187 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6188 |
instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6189 |
match(Set dst (CountTrailingZerosI src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6190 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6191 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6192 |
format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6193 |
"jnz done\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6194 |
"movl $dst, 32\n" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6195 |
"done:" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6196 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6197 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6198 |
Label done; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6199 |
__ bsfl(Rdst, $src$$Register); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6200 |
__ jccb(Assembler::notZero, done); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6201 |
__ movl(Rdst, BitsPerInt); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6202 |
__ bind(done); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6203 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6204 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6205 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6206 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6207 |
instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6208 |
match(Set dst (CountTrailingZerosL src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6209 |
effect(KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6210 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6211 |
format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6212 |
"jnz done\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6213 |
"movl $dst, 64\n" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6214 |
"done:" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6215 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6216 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6217 |
Label done; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6218 |
__ bsfq(Rdst, $src$$Register); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6219 |
__ jccb(Assembler::notZero, done); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6220 |
__ movl(Rdst, BitsPerLong); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6221 |
__ bind(done); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6222 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6223 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6224 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6225 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
6226 |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6227 |
//---------- Population Count Instructions ------------------------------------- |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6228 |
|
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6229 |
instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6230 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6231 |
match(Set dst (PopCountI src)); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6232 |
effect(KILL cr); |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6233 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6234 |
format %{ "popcnt $dst, $src" %} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6235 |
ins_encode %{ |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6236 |
__ popcntl($dst$$Register, $src$$Register); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6237 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6238 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6239 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6240 |
|
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6241 |
instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6242 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6243 |
match(Set dst (PopCountI (LoadI mem))); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6244 |
effect(KILL cr); |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6245 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6246 |
format %{ "popcnt $dst, $mem" %} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6247 |
ins_encode %{ |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6248 |
__ popcntl($dst$$Register, $mem$$Address); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6249 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6250 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6251 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6252 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6253 |
// Note: Long.bitCount(long) returns an int. |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6254 |
instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6255 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6256 |
match(Set dst (PopCountL src)); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6257 |
effect(KILL cr); |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6258 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6259 |
format %{ "popcnt $dst, $src" %} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6260 |
ins_encode %{ |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6261 |
__ popcntq($dst$$Register, $src$$Register); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6262 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6263 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6264 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6265 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6266 |
// Note: Long.bitCount(long) returns an int. |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6267 |
instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6268 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6269 |
match(Set dst (PopCountL (LoadL mem))); |
12952
a1f3ff3a89e1
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
12739
diff
changeset
|
6270 |
effect(KILL cr); |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6271 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6272 |
format %{ "popcnt $dst, $mem" %} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6273 |
ins_encode %{ |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6274 |
__ popcntq($dst$$Register, $mem$$Address); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6275 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6276 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6277 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6278 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
6279 |
|
1 | 6280 |
//----------MemBar Instructions----------------------------------------------- |
6281 |
// Memory barrier flavors |
|
6282 |
||
6283 |
instruct membar_acquire() |
|
6284 |
%{ |
|
6285 |
match(MemBarAcquire); |
|
6286 |
ins_cost(0); |
|
6287 |
||
6288 |
size(0); |
|
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6289 |
format %{ "MEMBAR-acquire ! (empty encoding)" %} |
1 | 6290 |
ins_encode(); |
6291 |
ins_pipe(empty); |
|
6292 |
%} |
|
6293 |
||
6294 |
instruct membar_acquire_lock() |
|
6295 |
%{ |
|
10262
c5f62d314bee
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
10255
diff
changeset
|
6296 |
match(MemBarAcquireLock); |
1 | 6297 |
ins_cost(0); |
6298 |
||
6299 |
size(0); |
|
6300 |
format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} |
|
6301 |
ins_encode(); |
|
6302 |
ins_pipe(empty); |
|
6303 |
%} |
|
6304 |
||
6305 |
instruct membar_release() |
|
6306 |
%{ |
|
6307 |
match(MemBarRelease); |
|
6308 |
ins_cost(0); |
|
6309 |
||
6310 |
size(0); |
|
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6311 |
format %{ "MEMBAR-release ! (empty encoding)" %} |
1 | 6312 |
ins_encode(); |
6313 |
ins_pipe(empty); |
|
6314 |
%} |
|
6315 |
||
6316 |
instruct membar_release_lock() |
|
6317 |
%{ |
|
10262
c5f62d314bee
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
10255
diff
changeset
|
6318 |
match(MemBarReleaseLock); |
1 | 6319 |
ins_cost(0); |
6320 |
||
6321 |
size(0); |
|
6322 |
format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} |
|
6323 |
ins_encode(); |
|
6324 |
ins_pipe(empty); |
|
6325 |
%} |
|
6326 |
||
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6327 |
instruct membar_volatile(rFlagsReg cr) %{ |
1 | 6328 |
match(MemBarVolatile); |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6329 |
effect(KILL cr); |
1 | 6330 |
ins_cost(400); |
6331 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
6332 |
format %{ |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6333 |
$$template |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6334 |
if (os::is_MP()) { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6335 |
$$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6336 |
} else { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6337 |
$$emit$$"MEMBAR-volatile ! (empty encoding)" |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6338 |
} |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6339 |
%} |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6340 |
ins_encode %{ |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6341 |
__ membar(Assembler::StoreLoad); |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
6342 |
%} |
1 | 6343 |
ins_pipe(pipe_slow); |
6344 |
%} |
|
6345 |
||
6346 |
instruct unnecessary_membar_volatile() |
|
6347 |
%{ |
|
6348 |
match(MemBarVolatile); |
|
6349 |
predicate(Matcher::post_store_load_barrier(n)); |
|
6350 |
ins_cost(0); |
|
6351 |
||
6352 |
size(0); |
|
6353 |
format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} |
|
6354 |
ins_encode(); |
|
6355 |
ins_pipe(empty); |
|
6356 |
%} |
|
6357 |
||
11431
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6358 |
instruct membar_storestore() %{ |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6359 |
match(MemBarStoreStore); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6360 |
ins_cost(0); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6361 |
|
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6362 |
size(0); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6363 |
format %{ "MEMBAR-storestore (empty encoding)" %} |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6364 |
ins_encode( ); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6365 |
ins_pipe(empty); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6366 |
%} |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11430
diff
changeset
|
6367 |
|
1 | 6368 |
//----------Move Instructions-------------------------------------------------- |
6369 |
||
6370 |
instruct castX2P(rRegP dst, rRegL src) |
|
6371 |
%{ |
|
6372 |
match(Set dst (CastX2P src)); |
|
6373 |
||
6374 |
format %{ "movq $dst, $src\t# long->ptr" %} |
|
11427 | 6375 |
ins_encode %{ |
6376 |
if ($dst$$reg != $src$$reg) { |
|
6377 |
__ movptr($dst$$Register, $src$$Register); |
|
6378 |
} |
|
6379 |
%} |
|
1 | 6380 |
ins_pipe(ialu_reg_reg); // XXX |
6381 |
%} |
|
6382 |
||
6383 |
instruct castP2X(rRegL dst, rRegP src) |
|
6384 |
%{ |
|
6385 |
match(Set dst (CastP2X src)); |
|
6386 |
||
6387 |
format %{ "movq $dst, $src\t# ptr -> long" %} |
|
11427 | 6388 |
ins_encode %{ |
6389 |
if ($dst$$reg != $src$$reg) { |
|
6390 |
__ movptr($dst$$Register, $src$$Register); |
|
6391 |
} |
|
6392 |
%} |
|
1 | 6393 |
ins_pipe(ialu_reg_reg); // XXX |
6394 |
%} |
|
6395 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6396 |
// Convert oop into int for vectors alignment masking |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6397 |
instruct convP2I(rRegI dst, rRegP src) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6398 |
%{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6399 |
match(Set dst (ConvL2I (CastP2X src))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6400 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6401 |
format %{ "movl $dst, $src\t# ptr -> int" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6402 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6403 |
__ movl($dst$$Register, $src$$Register); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6404 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6405 |
ins_pipe(ialu_reg_reg); // XXX |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6406 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6407 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6408 |
// Convert compressed oop into int for vectors alignment masking |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6409 |
// in case of 32bit oops (heap < 4Gb). |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6410 |
instruct convN2I(rRegI dst, rRegN src) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6411 |
%{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6412 |
predicate(Universe::narrow_oop_shift() == 0); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6413 |
match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6414 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6415 |
format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6416 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6417 |
__ movl($dst$$Register, $src$$Register); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6418 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6419 |
ins_pipe(ialu_reg_reg); // XXX |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
6420 |
%} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6421 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6422 |
// Convert oop pointer into compressed form |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6423 |
instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
767
64fb1fd7186d
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
608
diff
changeset
|
6424 |
predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6425 |
match(Set dst (EncodeP src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6426 |
effect(KILL cr); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6427 |
format %{ "encode_heap_oop $dst,$src" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6428 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6429 |
Register s = $src$$Register; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6430 |
Register d = $dst$$Register; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6431 |
if (s != d) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6432 |
__ movq(d, s); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6433 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6434 |
__ encode_heap_oop(d); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6435 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6436 |
ins_pipe(ialu_reg_long); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6437 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6438 |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6439 |
instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
767
64fb1fd7186d
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
608
diff
changeset
|
6440 |
predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6441 |
match(Set dst (EncodeP src)); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6442 |
effect(KILL cr); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6443 |
format %{ "encode_heap_oop_not_null $dst,$src" %} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6444 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6445 |
__ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6446 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6447 |
ins_pipe(ialu_reg_long); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6448 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6449 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6450 |
instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
6451 |
predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
6452 |
n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6453 |
match(Set dst (DecodeN src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6454 |
effect(KILL cr); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6455 |
format %{ "decode_heap_oop $dst,$src" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6456 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6457 |
Register s = $src$$Register; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6458 |
Register d = $dst$$Register; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6459 |
if (s != d) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6460 |
__ movq(d, s); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6461 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6462 |
__ decode_heap_oop(d); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6463 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6464 |
ins_pipe(ialu_reg_long); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6465 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6466 |
|
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
6467 |
instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
6468 |
predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
6469 |
n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6470 |
match(Set dst (DecodeN src)); |
5694
1e0532a6abff
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
5690
diff
changeset
|
6471 |
effect(KILL cr); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6472 |
format %{ "decode_heap_oop_not_null $dst,$src" %} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6473 |
ins_encode %{ |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6474 |
Register s = $src$$Register; |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6475 |
Register d = $dst$$Register; |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6476 |
if (s != d) { |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6477 |
__ decode_heap_oop_not_null(d, s); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6478 |
} else { |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6479 |
__ decode_heap_oop_not_null(d); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
6480 |
} |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6481 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6482 |
ins_pipe(ialu_reg_long); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6483 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6484 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
6485 |
|
1 | 6486 |
//----------Conditional Move--------------------------------------------------- |
6487 |
// Jump |
|
6488 |
// dummy instruction for generating temp registers |
|
6489 |
instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ |
|
6490 |
match(Jump (LShiftL switch_val shift)); |
|
6491 |
ins_cost(350); |
|
6492 |
predicate(false); |
|
6493 |
effect(TEMP dest); |
|
6494 |
||
7433 | 6495 |
format %{ "leaq $dest, [$constantaddress]\n\t" |
1 | 6496 |
"jmp [$dest + $switch_val << $shift]\n\t" %} |
7433 | 6497 |
ins_encode %{ |
6498 |
// We could use jump(ArrayAddress) except that the macro assembler needs to use r10 |
|
6499 |
// to do that and the compiler is using that register as one it can allocate. |
|
6500 |
// So we build it all by hand. |
|
6501 |
// Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); |
|
6502 |
// ArrayAddress dispatch(table, index); |
|
6503 |
Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); |
|
6504 |
__ lea($dest$$Register, $constantaddress); |
|
6505 |
__ jmp(dispatch); |
|
6506 |
%} |
|
1 | 6507 |
ins_pipe(pipe_jmp); |
6508 |
%} |
|
6509 |
||
6510 |
instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ |
|
6511 |
match(Jump (AddL (LShiftL switch_val shift) offset)); |
|
6512 |
ins_cost(350); |
|
6513 |
effect(TEMP dest); |
|
6514 |
||
7433 | 6515 |
format %{ "leaq $dest, [$constantaddress]\n\t" |
1 | 6516 |
"jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
7433 | 6517 |
ins_encode %{ |
6518 |
// We could use jump(ArrayAddress) except that the macro assembler needs to use r10 |
|
6519 |
// to do that and the compiler is using that register as one it can allocate. |
|
6520 |
// So we build it all by hand. |
|
6521 |
// Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); |
|
6522 |
// ArrayAddress dispatch(table, index); |
|
6523 |
Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); |
|
6524 |
__ lea($dest$$Register, $constantaddress); |
|
6525 |
__ jmp(dispatch); |
|
6526 |
%} |
|
1 | 6527 |
ins_pipe(pipe_jmp); |
6528 |
%} |
|
6529 |
||
6530 |
instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ |
|
6531 |
match(Jump switch_val); |
|
6532 |
ins_cost(350); |
|
6533 |
effect(TEMP dest); |
|
6534 |
||
7433 | 6535 |
format %{ "leaq $dest, [$constantaddress]\n\t" |
1 | 6536 |
"jmp [$dest + $switch_val]\n\t" %} |
7433 | 6537 |
ins_encode %{ |
6538 |
// We could use jump(ArrayAddress) except that the macro assembler needs to use r10 |
|
6539 |
// to do that and the compiler is using that register as one it can allocate. |
|
6540 |
// So we build it all by hand. |
|
6541 |
// Address index(noreg, switch_reg, Address::times_1); |
|
6542 |
// ArrayAddress dispatch(table, index); |
|
6543 |
Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); |
|
6544 |
__ lea($dest$$Register, $constantaddress); |
|
6545 |
__ jmp(dispatch); |
|
6546 |
%} |
|
1 | 6547 |
ins_pipe(pipe_jmp); |
6548 |
%} |
|
6549 |
||
6550 |
// Conditional move |
|
6551 |
instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) |
|
6552 |
%{ |
|
6553 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
6554 |
||
6555 |
ins_cost(200); // XXX |
|
6556 |
format %{ "cmovl$cop $dst, $src\t# signed, int" %} |
|
6557 |
opcode(0x0F, 0x40); |
|
6558 |
ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6559 |
ins_pipe(pipe_cmov_reg); |
|
6560 |
%} |
|
6561 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6562 |
instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
1 | 6563 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
6564 |
||
6565 |
ins_cost(200); // XXX |
|
6566 |
format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} |
|
6567 |
opcode(0x0F, 0x40); |
|
6568 |
ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6569 |
ins_pipe(pipe_cmov_reg); |
|
6570 |
%} |
|
6571 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6572 |
instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6573 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6574 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6575 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6576 |
cmovI_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6577 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6578 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6579 |
|
1 | 6580 |
// Conditional move |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6581 |
instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
1 | 6582 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
6583 |
||
6584 |
ins_cost(250); // XXX |
|
6585 |
format %{ "cmovl$cop $dst, $src\t# signed, int" %} |
|
6586 |
opcode(0x0F, 0x40); |
|
6587 |
ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); |
|
6588 |
ins_pipe(pipe_cmov_mem); |
|
6589 |
%} |
|
6590 |
||
6591 |
// Conditional move |
|
6592 |
instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) |
|
6593 |
%{ |
|
6594 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
6595 |
||
6596 |
ins_cost(250); // XXX |
|
6597 |
format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} |
|
6598 |
opcode(0x0F, 0x40); |
|
6599 |
ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); |
|
6600 |
ins_pipe(pipe_cmov_mem); |
|
6601 |
%} |
|
6602 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6603 |
instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6604 |
match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6605 |
ins_cost(250); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6606 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6607 |
cmovI_memU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6608 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6609 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6610 |
|
1 | 6611 |
// Conditional move |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6612 |
instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6613 |
%{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6614 |
match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6615 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6616 |
ins_cost(200); // XXX |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6617 |
format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6618 |
opcode(0x0F, 0x40); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6619 |
ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6620 |
ins_pipe(pipe_cmov_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6621 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6622 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6623 |
// Conditional move |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6624 |
instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6625 |
%{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6626 |
match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6627 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6628 |
ins_cost(200); // XXX |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6629 |
format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6630 |
opcode(0x0F, 0x40); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6631 |
ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6632 |
ins_pipe(pipe_cmov_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6633 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6634 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6635 |
instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6636 |
match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6637 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6638 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6639 |
cmovN_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6640 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6641 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6642 |
|
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6643 |
// Conditional move |
1 | 6644 |
instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
6645 |
%{ |
|
6646 |
match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
6647 |
||
6648 |
ins_cost(200); // XXX |
|
6649 |
format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} |
|
6650 |
opcode(0x0F, 0x40); |
|
6651 |
ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6652 |
ins_pipe(pipe_cmov_reg); // XXX |
|
6653 |
%} |
|
6654 |
||
6655 |
// Conditional move |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6656 |
instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
1 | 6657 |
%{ |
6658 |
match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
6659 |
||
6660 |
ins_cost(200); // XXX |
|
6661 |
format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} |
|
6662 |
opcode(0x0F, 0x40); |
|
6663 |
ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6664 |
ins_pipe(pipe_cmov_reg); // XXX |
|
6665 |
%} |
|
6666 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6667 |
instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6668 |
match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6669 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6670 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6671 |
cmovP_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6672 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6673 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6674 |
|
1 | 6675 |
// DISABLED: Requires the ADLC to emit a bottom_type call that |
6676 |
// correctly meets the two pointer arguments; one is an incoming |
|
6677 |
// register but the other is a memory operand. ALSO appears to |
|
6678 |
// be buggy with implicit null checks. |
|
6679 |
// |
|
6680 |
//// Conditional move |
|
6681 |
//instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) |
|
6682 |
//%{ |
|
6683 |
// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); |
|
6684 |
// ins_cost(250); |
|
6685 |
// format %{ "CMOV$cop $dst,$src\t# ptr" %} |
|
6686 |
// opcode(0x0F,0x40); |
|
6687 |
// ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); |
|
6688 |
// ins_pipe( pipe_cmov_mem ); |
|
6689 |
//%} |
|
6690 |
// |
|
6691 |
//// Conditional move |
|
6692 |
//instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) |
|
6693 |
//%{ |
|
6694 |
// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); |
|
6695 |
// ins_cost(250); |
|
6696 |
// format %{ "CMOV$cop $dst,$src\t# ptr" %} |
|
6697 |
// opcode(0x0F,0x40); |
|
6698 |
// ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); |
|
6699 |
// ins_pipe( pipe_cmov_mem ); |
|
6700 |
//%} |
|
6701 |
||
6702 |
instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) |
|
6703 |
%{ |
|
6704 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
6705 |
||
6706 |
ins_cost(200); // XXX |
|
6707 |
format %{ "cmovq$cop $dst, $src\t# signed, long" %} |
|
6708 |
opcode(0x0F, 0x40); |
|
6709 |
ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6710 |
ins_pipe(pipe_cmov_reg); // XXX |
|
6711 |
%} |
|
6712 |
||
6713 |
instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) |
|
6714 |
%{ |
|
6715 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
6716 |
||
6717 |
ins_cost(200); // XXX |
|
6718 |
format %{ "cmovq$cop $dst, $src\t# signed, long" %} |
|
6719 |
opcode(0x0F, 0x40); |
|
6720 |
ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); |
|
6721 |
ins_pipe(pipe_cmov_mem); // XXX |
|
6722 |
%} |
|
6723 |
||
6724 |
instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) |
|
6725 |
%{ |
|
6726 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
6727 |
||
6728 |
ins_cost(200); // XXX |
|
6729 |
format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} |
|
6730 |
opcode(0x0F, 0x40); |
|
6731 |
ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
6732 |
ins_pipe(pipe_cmov_reg); // XXX |
|
6733 |
%} |
|
6734 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6735 |
instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6736 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6737 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6738 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6739 |
cmovL_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6740 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6741 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6742 |
|
1 | 6743 |
instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
6744 |
%{ |
|
6745 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
6746 |
||
6747 |
ins_cost(200); // XXX |
|
6748 |
format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} |
|
6749 |
opcode(0x0F, 0x40); |
|
6750 |
ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); |
|
6751 |
ins_pipe(pipe_cmov_mem); // XXX |
|
6752 |
%} |
|
6753 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6754 |
instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6755 |
match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6756 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6757 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6758 |
cmovL_memU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6759 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6760 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6761 |
|
1 | 6762 |
instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
6763 |
%{ |
|
6764 |
match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
6765 |
||
6766 |
ins_cost(200); // XXX |
|
6767 |
format %{ "jn$cop skip\t# signed cmove float\n\t" |
|
6768 |
"movss $dst, $src\n" |
|
6769 |
"skip:" %} |
|
11427 | 6770 |
ins_encode %{ |
6771 |
Label Lskip; |
|
6772 |
// Invert sense of branch from sense of CMOV |
|
6773 |
__ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); |
|
6774 |
__ movflt($dst$$XMMRegister, $src$$XMMRegister); |
|
6775 |
__ bind(Lskip); |
|
6776 |
%} |
|
1 | 6777 |
ins_pipe(pipe_slow); |
6778 |
%} |
|
6779 |
||
6780 |
// instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) |
|
6781 |
// %{ |
|
6782 |
// match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); |
|
6783 |
||
6784 |
// ins_cost(200); // XXX |
|
6785 |
// format %{ "jn$cop skip\t# signed cmove float\n\t" |
|
6786 |
// "movss $dst, $src\n" |
|
6787 |
// "skip:" %} |
|
6788 |
// ins_encode(enc_cmovf_mem_branch(cop, dst, src)); |
|
6789 |
// ins_pipe(pipe_slow); |
|
6790 |
// %} |
|
6791 |
||
6792 |
instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) |
|
6793 |
%{ |
|
6794 |
match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
6795 |
||
6796 |
ins_cost(200); // XXX |
|
6797 |
format %{ "jn$cop skip\t# unsigned cmove float\n\t" |
|
6798 |
"movss $dst, $src\n" |
|
6799 |
"skip:" %} |
|
11427 | 6800 |
ins_encode %{ |
6801 |
Label Lskip; |
|
6802 |
// Invert sense of branch from sense of CMOV |
|
6803 |
__ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); |
|
6804 |
__ movflt($dst$$XMMRegister, $src$$XMMRegister); |
|
6805 |
__ bind(Lskip); |
|
6806 |
%} |
|
1 | 6807 |
ins_pipe(pipe_slow); |
6808 |
%} |
|
6809 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6810 |
instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6811 |
match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6812 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6813 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6814 |
cmovF_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6815 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6816 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6817 |
|
1 | 6818 |
instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
6819 |
%{ |
|
6820 |
match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
6821 |
||
6822 |
ins_cost(200); // XXX |
|
6823 |
format %{ "jn$cop skip\t# signed cmove double\n\t" |
|
6824 |
"movsd $dst, $src\n" |
|
6825 |
"skip:" %} |
|
11427 | 6826 |
ins_encode %{ |
6827 |
Label Lskip; |
|
6828 |
// Invert sense of branch from sense of CMOV |
|
6829 |
__ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); |
|
6830 |
__ movdbl($dst$$XMMRegister, $src$$XMMRegister); |
|
6831 |
__ bind(Lskip); |
|
6832 |
%} |
|
1 | 6833 |
ins_pipe(pipe_slow); |
6834 |
%} |
|
6835 |
||
6836 |
instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) |
|
6837 |
%{ |
|
6838 |
match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
6839 |
||
6840 |
ins_cost(200); // XXX |
|
6841 |
format %{ "jn$cop skip\t# unsigned cmove double\n\t" |
|
6842 |
"movsd $dst, $src\n" |
|
6843 |
"skip:" %} |
|
11427 | 6844 |
ins_encode %{ |
6845 |
Label Lskip; |
|
6846 |
// Invert sense of branch from sense of CMOV |
|
6847 |
__ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); |
|
6848 |
__ movdbl($dst$$XMMRegister, $src$$XMMRegister); |
|
6849 |
__ bind(Lskip); |
|
6850 |
%} |
|
1 | 6851 |
ins_pipe(pipe_slow); |
6852 |
%} |
|
6853 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6854 |
instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6855 |
match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6856 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6857 |
expand %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6858 |
cmovD_regU(cop, cr, dst, src); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6859 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6860 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
6861 |
|
1 | 6862 |
//----------Arithmetic Instructions-------------------------------------------- |
6863 |
//----------Addition Instructions---------------------------------------------- |
|
6864 |
||
6865 |
instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
6866 |
%{ |
|
6867 |
match(Set dst (AddI dst src)); |
|
6868 |
effect(KILL cr); |
|
6869 |
||
6870 |
format %{ "addl $dst, $src\t# int" %} |
|
6871 |
opcode(0x03); |
|
6872 |
ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); |
|
6873 |
ins_pipe(ialu_reg_reg); |
|
6874 |
%} |
|
6875 |
||
6876 |
instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) |
|
6877 |
%{ |
|
6878 |
match(Set dst (AddI dst src)); |
|
6879 |
effect(KILL cr); |
|
6880 |
||
6881 |
format %{ "addl $dst, $src\t# int" %} |
|
6882 |
opcode(0x81, 0x00); /* /0 id */ |
|
6883 |
ins_encode(OpcSErm(dst, src), Con8or32(src)); |
|
6884 |
ins_pipe( ialu_reg ); |
|
6885 |
%} |
|
6886 |
||
6887 |
instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) |
|
6888 |
%{ |
|
6889 |
match(Set dst (AddI dst (LoadI src))); |
|
6890 |
effect(KILL cr); |
|
6891 |
||
6892 |
ins_cost(125); // XXX |
|
6893 |
format %{ "addl $dst, $src\t# int" %} |
|
6894 |
opcode(0x03); |
|
6895 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
6896 |
ins_pipe(ialu_reg_mem); |
|
6897 |
%} |
|
6898 |
||
6899 |
instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) |
|
6900 |
%{ |
|
6901 |
match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
|
6902 |
effect(KILL cr); |
|
6903 |
||
6904 |
ins_cost(150); // XXX |
|
6905 |
format %{ "addl $dst, $src\t# int" %} |
|
6906 |
opcode(0x01); /* Opcode 01 /r */ |
|
6907 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
6908 |
ins_pipe(ialu_mem_reg); |
|
6909 |
%} |
|
6910 |
||
6911 |
instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) |
|
6912 |
%{ |
|
6913 |
match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
|
6914 |
effect(KILL cr); |
|
6915 |
||
6916 |
ins_cost(125); // XXX |
|
6917 |
format %{ "addl $dst, $src\t# int" %} |
|
6918 |
opcode(0x81); /* Opcode 81 /0 id */ |
|
6919 |
ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); |
|
6920 |
ins_pipe(ialu_mem_imm); |
|
6921 |
%} |
|
6922 |
||
6923 |
instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) |
|
6924 |
%{ |
|
6925 |
predicate(UseIncDec); |
|
6926 |
match(Set dst (AddI dst src)); |
|
6927 |
effect(KILL cr); |
|
6928 |
||
6929 |
format %{ "incl $dst\t# int" %} |
|
6930 |
opcode(0xFF, 0x00); // FF /0 |
|
6931 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
6932 |
ins_pipe(ialu_reg); |
|
6933 |
%} |
|
6934 |
||
6935 |
instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) |
|
6936 |
%{ |
|
6937 |
predicate(UseIncDec); |
|
6938 |
match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
|
6939 |
effect(KILL cr); |
|
6940 |
||
6941 |
ins_cost(125); // XXX |
|
6942 |
format %{ "incl $dst\t# int" %} |
|
6943 |
opcode(0xFF); /* Opcode FF /0 */ |
|
6944 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); |
|
6945 |
ins_pipe(ialu_mem_imm); |
|
6946 |
%} |
|
6947 |
||
6948 |
// XXX why does that use AddI |
|
6949 |
instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) |
|
6950 |
%{ |
|
6951 |
predicate(UseIncDec); |
|
6952 |
match(Set dst (AddI dst src)); |
|
6953 |
effect(KILL cr); |
|
6954 |
||
6955 |
format %{ "decl $dst\t# int" %} |
|
6956 |
opcode(0xFF, 0x01); // FF /1 |
|
6957 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
6958 |
ins_pipe(ialu_reg); |
|
6959 |
%} |
|
6960 |
||
6961 |
// XXX why does that use AddI |
|
6962 |
instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) |
|
6963 |
%{ |
|
6964 |
predicate(UseIncDec); |
|
6965 |
match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
|
6966 |
effect(KILL cr); |
|
6967 |
||
6968 |
ins_cost(125); // XXX |
|
6969 |
format %{ "decl $dst\t# int" %} |
|
6970 |
opcode(0xFF); /* Opcode FF /1 */ |
|
6971 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); |
|
6972 |
ins_pipe(ialu_mem_imm); |
|
6973 |
%} |
|
6974 |
||
6975 |
instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) |
|
6976 |
%{ |
|
6977 |
match(Set dst (AddI src0 src1)); |
|
6978 |
||
6979 |
ins_cost(110); |
|
6980 |
format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} |
|
6981 |
opcode(0x8D); /* 0x8D /r */ |
|
6982 |
ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX |
|
6983 |
ins_pipe(ialu_reg_reg); |
|
6984 |
%} |
|
6985 |
||
6986 |
instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
6987 |
%{ |
|
6988 |
match(Set dst (AddL dst src)); |
|
6989 |
effect(KILL cr); |
|
6990 |
||
6991 |
format %{ "addq $dst, $src\t# long" %} |
|
6992 |
opcode(0x03); |
|
6993 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
6994 |
ins_pipe(ialu_reg_reg); |
|
6995 |
%} |
|
6996 |
||
6997 |
instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) |
|
6998 |
%{ |
|
6999 |
match(Set dst (AddL dst src)); |
|
7000 |
effect(KILL cr); |
|
7001 |
||
7002 |
format %{ "addq $dst, $src\t# long" %} |
|
7003 |
opcode(0x81, 0x00); /* /0 id */ |
|
7004 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
7005 |
ins_pipe( ialu_reg ); |
|
7006 |
%} |
|
7007 |
||
7008 |
instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) |
|
7009 |
%{ |
|
7010 |
match(Set dst (AddL dst (LoadL src))); |
|
7011 |
effect(KILL cr); |
|
7012 |
||
7013 |
ins_cost(125); // XXX |
|
7014 |
format %{ "addq $dst, $src\t# long" %} |
|
7015 |
opcode(0x03); |
|
7016 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
7017 |
ins_pipe(ialu_reg_mem); |
|
7018 |
%} |
|
7019 |
||
7020 |
instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) |
|
7021 |
%{ |
|
7022 |
match(Set dst (StoreL dst (AddL (LoadL dst) src))); |
|
7023 |
effect(KILL cr); |
|
7024 |
||
7025 |
ins_cost(150); // XXX |
|
7026 |
format %{ "addq $dst, $src\t# long" %} |
|
7027 |
opcode(0x01); /* Opcode 01 /r */ |
|
7028 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
7029 |
ins_pipe(ialu_mem_reg); |
|
7030 |
%} |
|
7031 |
||
7032 |
instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) |
|
7033 |
%{ |
|
7034 |
match(Set dst (StoreL dst (AddL (LoadL dst) src))); |
|
7035 |
effect(KILL cr); |
|
7036 |
||
7037 |
ins_cost(125); // XXX |
|
7038 |
format %{ "addq $dst, $src\t# long" %} |
|
7039 |
opcode(0x81); /* Opcode 81 /0 id */ |
|
7040 |
ins_encode(REX_mem_wide(dst), |
|
7041 |
OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); |
|
7042 |
ins_pipe(ialu_mem_imm); |
|
7043 |
%} |
|
7044 |
||
7045 |
instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) |
|
7046 |
%{ |
|
7047 |
predicate(UseIncDec); |
|
7048 |
match(Set dst (AddL dst src)); |
|
7049 |
effect(KILL cr); |
|
7050 |
||
7051 |
format %{ "incq $dst\t# long" %} |
|
7052 |
opcode(0xFF, 0x00); // FF /0 |
|
7053 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
7054 |
ins_pipe(ialu_reg); |
|
7055 |
%} |
|
7056 |
||
7057 |
instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) |
|
7058 |
%{ |
|
7059 |
predicate(UseIncDec); |
|
7060 |
match(Set dst (StoreL dst (AddL (LoadL dst) src))); |
|
7061 |
effect(KILL cr); |
|
7062 |
||
7063 |
ins_cost(125); // XXX |
|
7064 |
format %{ "incq $dst\t# long" %} |
|
7065 |
opcode(0xFF); /* Opcode FF /0 */ |
|
7066 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); |
|
7067 |
ins_pipe(ialu_mem_imm); |
|
7068 |
%} |
|
7069 |
||
7070 |
// XXX why does that use AddL |
|
7071 |
instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) |
|
7072 |
%{ |
|
7073 |
predicate(UseIncDec); |
|
7074 |
match(Set dst (AddL dst src)); |
|
7075 |
effect(KILL cr); |
|
7076 |
||
7077 |
format %{ "decq $dst\t# long" %} |
|
7078 |
opcode(0xFF, 0x01); // FF /1 |
|
7079 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
7080 |
ins_pipe(ialu_reg); |
|
7081 |
%} |
|
7082 |
||
7083 |
// XXX why does that use AddL |
|
7084 |
instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) |
|
7085 |
%{ |
|
7086 |
predicate(UseIncDec); |
|
7087 |
match(Set dst (StoreL dst (AddL (LoadL dst) src))); |
|
7088 |
effect(KILL cr); |
|
7089 |
||
7090 |
ins_cost(125); // XXX |
|
7091 |
format %{ "decq $dst\t# long" %} |
|
7092 |
opcode(0xFF); /* Opcode FF /1 */ |
|
7093 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); |
|
7094 |
ins_pipe(ialu_mem_imm); |
|
7095 |
%} |
|
7096 |
||
7097 |
instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) |
|
7098 |
%{ |
|
7099 |
match(Set dst (AddL src0 src1)); |
|
7100 |
||
7101 |
ins_cost(110); |
|
7102 |
format %{ "leaq $dst, [$src0 + $src1]\t# long" %} |
|
7103 |
opcode(0x8D); /* 0x8D /r */ |
|
7104 |
ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX |
|
7105 |
ins_pipe(ialu_reg_reg); |
|
7106 |
%} |
|
7107 |
||
7108 |
instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) |
|
7109 |
%{ |
|
7110 |
match(Set dst (AddP dst src)); |
|
7111 |
effect(KILL cr); |
|
7112 |
||
7113 |
format %{ "addq $dst, $src\t# ptr" %} |
|
7114 |
opcode(0x03); |
|
7115 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
7116 |
ins_pipe(ialu_reg_reg); |
|
7117 |
%} |
|
7118 |
||
7119 |
instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) |
|
7120 |
%{ |
|
7121 |
match(Set dst (AddP dst src)); |
|
7122 |
effect(KILL cr); |
|
7123 |
||
7124 |
format %{ "addq $dst, $src\t# ptr" %} |
|
7125 |
opcode(0x81, 0x00); /* /0 id */ |
|
7126 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
7127 |
ins_pipe( ialu_reg ); |
|
7128 |
%} |
|
7129 |
||
7130 |
// XXX addP mem ops ???? |
|
7131 |
||
7132 |
instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) |
|
7133 |
%{ |
|
7134 |
match(Set dst (AddP src0 src1)); |
|
7135 |
||
7136 |
ins_cost(110); |
|
7137 |
format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} |
|
7138 |
opcode(0x8D); /* 0x8D /r */ |
|
7139 |
ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX |
|
7140 |
ins_pipe(ialu_reg_reg); |
|
7141 |
%} |
|
7142 |
||
7143 |
instruct checkCastPP(rRegP dst) |
|
7144 |
%{ |
|
7145 |
match(Set dst (CheckCastPP dst)); |
|
7146 |
||
7147 |
size(0); |
|
7148 |
format %{ "# checkcastPP of $dst" %} |
|
7149 |
ins_encode(/* empty encoding */); |
|
7150 |
ins_pipe(empty); |
|
7151 |
%} |
|
7152 |
||
7153 |
instruct castPP(rRegP dst) |
|
7154 |
%{ |
|
7155 |
match(Set dst (CastPP dst)); |
|
7156 |
||
7157 |
size(0); |
|
7158 |
format %{ "# castPP of $dst" %} |
|
7159 |
ins_encode(/* empty encoding */); |
|
7160 |
ins_pipe(empty); |
|
7161 |
%} |
|
7162 |
||
7163 |
instruct castII(rRegI dst) |
|
7164 |
%{ |
|
7165 |
match(Set dst (CastII dst)); |
|
7166 |
||
7167 |
size(0); |
|
7168 |
format %{ "# castII of $dst" %} |
|
7169 |
ins_encode(/* empty encoding */); |
|
7170 |
ins_cost(0); |
|
7171 |
ins_pipe(empty); |
|
7172 |
%} |
|
7173 |
||
7174 |
// LoadP-locked same as a regular LoadP when used with compare-swap |
|
7175 |
instruct loadPLocked(rRegP dst, memory mem) |
|
7176 |
%{ |
|
7177 |
match(Set dst (LoadPLocked mem)); |
|
7178 |
||
7179 |
ins_cost(125); // XXX |
|
7180 |
format %{ "movq $dst, $mem\t# ptr locked" %} |
|
7181 |
opcode(0x8B); |
|
7182 |
ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
7183 |
ins_pipe(ialu_reg_mem); // XXX |
|
7184 |
%} |
|
7185 |
||
7186 |
// Conditional-store of the updated heap-top. |
|
7187 |
// Used during allocation of the shared heap. |
|
7188 |
// Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. |
|
7189 |
||
7190 |
instruct storePConditional(memory heap_top_ptr, |
|
7191 |
rax_RegP oldval, rRegP newval, |
|
7192 |
rFlagsReg cr) |
|
7193 |
%{ |
|
7194 |
match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
7195 |
|
1 | 7196 |
format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
7197 |
"If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} |
|
7198 |
opcode(0x0F, 0xB1); |
|
7199 |
ins_encode(lock_prefix, |
|
7200 |
REX_reg_mem_wide(newval, heap_top_ptr), |
|
7201 |
OpcP, OpcS, |
|
7202 |
reg_mem(newval, heap_top_ptr)); |
|
7203 |
ins_pipe(pipe_cmpxchg); |
|
7204 |
%} |
|
7205 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7206 |
// Conditional-store of an int value. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7207 |
// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7208 |
instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7209 |
%{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7210 |
match(Set cr (StoreIConditional mem (Binary oldval newval))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7211 |
effect(KILL oldval); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7212 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7213 |
format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
1 | 7214 |
opcode(0x0F, 0xB1); |
7215 |
ins_encode(lock_prefix, |
|
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7216 |
REX_reg_mem(newval, mem), |
1 | 7217 |
OpcP, OpcS, |
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7218 |
reg_mem(newval, mem)); |
1 | 7219 |
ins_pipe(pipe_cmpxchg); |
7220 |
%} |
|
7221 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7222 |
// Conditional-store of a long value. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7223 |
// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7224 |
instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7225 |
%{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7226 |
match(Set cr (StoreLConditional mem (Binary oldval newval))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7227 |
effect(KILL oldval); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7228 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7229 |
format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
1 | 7230 |
opcode(0x0F, 0xB1); |
7231 |
ins_encode(lock_prefix, |
|
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7232 |
REX_reg_mem_wide(newval, mem), |
1 | 7233 |
OpcP, OpcS, |
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7234 |
reg_mem(newval, mem)); |
1 | 7235 |
ins_pipe(pipe_cmpxchg); |
7236 |
%} |
|
7237 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7238 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7239 |
// XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
1 | 7240 |
instruct compareAndSwapP(rRegI res, |
7241 |
memory mem_ptr, |
|
7242 |
rax_RegP oldval, rRegP newval, |
|
7243 |
rFlagsReg cr) |
|
7244 |
%{ |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7245 |
predicate(VM_Version::supports_cx8()); |
1 | 7246 |
match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7247 |
effect(KILL cr, KILL oldval); |
|
7248 |
||
7249 |
format %{ "cmpxchgq $mem_ptr,$newval\t# " |
|
7250 |
"If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
7251 |
"sete $res\n\t" |
|
7252 |
"movzbl $res, $res" %} |
|
7253 |
opcode(0x0F, 0xB1); |
|
7254 |
ins_encode(lock_prefix, |
|
7255 |
REX_reg_mem_wide(newval, mem_ptr), |
|
7256 |
OpcP, OpcS, |
|
7257 |
reg_mem(newval, mem_ptr), |
|
7258 |
REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
7259 |
REX_reg_breg(res, res), // movzbl |
|
7260 |
Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
7261 |
ins_pipe( pipe_cmpxchg ); |
|
7262 |
%} |
|
7263 |
||
7264 |
instruct compareAndSwapL(rRegI res, |
|
7265 |
memory mem_ptr, |
|
7266 |
rax_RegL oldval, rRegL newval, |
|
7267 |
rFlagsReg cr) |
|
7268 |
%{ |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7269 |
predicate(VM_Version::supports_cx8()); |
1 | 7270 |
match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7271 |
effect(KILL cr, KILL oldval); |
|
7272 |
||
7273 |
format %{ "cmpxchgq $mem_ptr,$newval\t# " |
|
7274 |
"If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
7275 |
"sete $res\n\t" |
|
7276 |
"movzbl $res, $res" %} |
|
7277 |
opcode(0x0F, 0xB1); |
|
7278 |
ins_encode(lock_prefix, |
|
7279 |
REX_reg_mem_wide(newval, mem_ptr), |
|
7280 |
OpcP, OpcS, |
|
7281 |
reg_mem(newval, mem_ptr), |
|
7282 |
REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
7283 |
REX_reg_breg(res, res), // movzbl |
|
7284 |
Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
7285 |
ins_pipe( pipe_cmpxchg ); |
|
7286 |
%} |
|
7287 |
||
7288 |
instruct compareAndSwapI(rRegI res, |
|
7289 |
memory mem_ptr, |
|
7290 |
rax_RegI oldval, rRegI newval, |
|
7291 |
rFlagsReg cr) |
|
7292 |
%{ |
|
7293 |
match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
|
7294 |
effect(KILL cr, KILL oldval); |
|
7295 |
||
7296 |
format %{ "cmpxchgl $mem_ptr,$newval\t# " |
|
7297 |
"If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
7298 |
"sete $res\n\t" |
|
7299 |
"movzbl $res, $res" %} |
|
7300 |
opcode(0x0F, 0xB1); |
|
7301 |
ins_encode(lock_prefix, |
|
7302 |
REX_reg_mem(newval, mem_ptr), |
|
7303 |
OpcP, OpcS, |
|
7304 |
reg_mem(newval, mem_ptr), |
|
7305 |
REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
7306 |
REX_reg_breg(res, res), // movzbl |
|
7307 |
Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
7308 |
ins_pipe( pipe_cmpxchg ); |
|
7309 |
%} |
|
7310 |
||
7311 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7312 |
instruct compareAndSwapN(rRegI res, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7313 |
memory mem_ptr, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7314 |
rax_RegN oldval, rRegN newval, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7315 |
rFlagsReg cr) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7316 |
match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7317 |
effect(KILL cr, KILL oldval); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7318 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7319 |
format %{ "cmpxchgl $mem_ptr,$newval\t# " |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7320 |
"If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7321 |
"sete $res\n\t" |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7322 |
"movzbl $res, $res" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7323 |
opcode(0x0F, 0xB1); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7324 |
ins_encode(lock_prefix, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7325 |
REX_reg_mem(newval, mem_ptr), |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7326 |
OpcP, OpcS, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7327 |
reg_mem(newval, mem_ptr), |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7328 |
REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7329 |
REX_reg_breg(res, res), // movzbl |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7330 |
Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7331 |
ins_pipe( pipe_cmpxchg ); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7332 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
7333 |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7334 |
instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7335 |
predicate(n->as_LoadStore()->result_not_used()); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7336 |
match(Set dummy (GetAndAddI mem add)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7337 |
effect(KILL cr); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7338 |
format %{ "ADDL [$mem],$add" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7339 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7340 |
if (os::is_MP()) { __ lock(); } |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7341 |
__ addl($mem$$Address, $add$$constant); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7342 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7343 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7344 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7345 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7346 |
instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7347 |
match(Set newval (GetAndAddI mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7348 |
effect(KILL cr); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7349 |
format %{ "XADDL [$mem],$newval" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7350 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7351 |
if (os::is_MP()) { __ lock(); } |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7352 |
__ xaddl($mem$$Address, $newval$$Register); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7353 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7354 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7355 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7356 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7357 |
instruct xaddL_no_res( memory mem, Universe dummy, immL add, rFlagsReg cr) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7358 |
predicate(n->as_LoadStore()->result_not_used()); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7359 |
match(Set dummy (GetAndAddL mem add)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7360 |
effect(KILL cr); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7361 |
format %{ "ADDQ [$mem],$add" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7362 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7363 |
if (os::is_MP()) { __ lock(); } |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7364 |
__ addq($mem$$Address, $add$$constant); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7365 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7366 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7367 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7368 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7369 |
instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7370 |
match(Set newval (GetAndAddL mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7371 |
effect(KILL cr); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7372 |
format %{ "XADDQ [$mem],$newval" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7373 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7374 |
if (os::is_MP()) { __ lock(); } |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7375 |
__ xaddq($mem$$Address, $newval$$Register); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7376 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7377 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7378 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7379 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7380 |
instruct xchgI( memory mem, rRegI newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7381 |
match(Set newval (GetAndSetI mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7382 |
format %{ "XCHGL $newval,[$mem]" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7383 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7384 |
__ xchgl($newval$$Register, $mem$$Address); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7385 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7386 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7387 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7388 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7389 |
instruct xchgL( memory mem, rRegL newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7390 |
match(Set newval (GetAndSetL mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7391 |
format %{ "XCHGL $newval,[$mem]" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7392 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7393 |
__ xchgq($newval$$Register, $mem$$Address); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7394 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7395 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7396 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7397 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7398 |
instruct xchgP( memory mem, rRegP newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7399 |
match(Set newval (GetAndSetP mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7400 |
format %{ "XCHGQ $newval,[$mem]" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7401 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7402 |
__ xchgq($newval$$Register, $mem$$Address); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7403 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7404 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7405 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7406 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7407 |
instruct xchgN( memory mem, rRegN newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7408 |
match(Set newval (GetAndSetN mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7409 |
format %{ "XCHGL $newval,$mem]" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7410 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7411 |
__ xchgl($newval$$Register, $mem$$Address); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7412 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7413 |
ins_pipe( pipe_cmpxchg ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7414 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7415 |
|
1 | 7416 |
//----------Subtraction Instructions------------------------------------------- |
7417 |
||
7418 |
// Integer Subtraction Instructions |
|
7419 |
instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
7420 |
%{ |
|
7421 |
match(Set dst (SubI dst src)); |
|
7422 |
effect(KILL cr); |
|
7423 |
||
7424 |
format %{ "subl $dst, $src\t# int" %} |
|
7425 |
opcode(0x2B); |
|
7426 |
ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); |
|
7427 |
ins_pipe(ialu_reg_reg); |
|
7428 |
%} |
|
7429 |
||
7430 |
instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) |
|
7431 |
%{ |
|
7432 |
match(Set dst (SubI dst src)); |
|
7433 |
effect(KILL cr); |
|
7434 |
||
7435 |
format %{ "subl $dst, $src\t# int" %} |
|
7436 |
opcode(0x81, 0x05); /* Opcode 81 /5 */ |
|
7437 |
ins_encode(OpcSErm(dst, src), Con8or32(src)); |
|
7438 |
ins_pipe(ialu_reg); |
|
7439 |
%} |
|
7440 |
||
7441 |
instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) |
|
7442 |
%{ |
|
7443 |
match(Set dst (SubI dst (LoadI src))); |
|
7444 |
effect(KILL cr); |
|
7445 |
||
7446 |
ins_cost(125); |
|
7447 |
format %{ "subl $dst, $src\t# int" %} |
|
7448 |
opcode(0x2B); |
|
7449 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
7450 |
ins_pipe(ialu_reg_mem); |
|
7451 |
%} |
|
7452 |
||
7453 |
instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) |
|
7454 |
%{ |
|
7455 |
match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
|
7456 |
effect(KILL cr); |
|
7457 |
||
7458 |
ins_cost(150); |
|
7459 |
format %{ "subl $dst, $src\t# int" %} |
|
7460 |
opcode(0x29); /* Opcode 29 /r */ |
|
7461 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
7462 |
ins_pipe(ialu_mem_reg); |
|
7463 |
%} |
|
7464 |
||
7465 |
instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) |
|
7466 |
%{ |
|
7467 |
match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
|
7468 |
effect(KILL cr); |
|
7469 |
||
7470 |
ins_cost(125); // XXX |
|
7471 |
format %{ "subl $dst, $src\t# int" %} |
|
7472 |
opcode(0x81); /* Opcode 81 /5 id */ |
|
7473 |
ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
|
7474 |
ins_pipe(ialu_mem_imm); |
|
7475 |
%} |
|
7476 |
||
7477 |
instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
7478 |
%{ |
|
7479 |
match(Set dst (SubL dst src)); |
|
7480 |
effect(KILL cr); |
|
7481 |
||
7482 |
format %{ "subq $dst, $src\t# long" %} |
|
7483 |
opcode(0x2B); |
|
7484 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
7485 |
ins_pipe(ialu_reg_reg); |
|
7486 |
%} |
|
7487 |
||
7488 |
instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) |
|
7489 |
%{ |
|
7490 |
match(Set dst (SubL dst src)); |
|
7491 |
effect(KILL cr); |
|
7492 |
||
7493 |
format %{ "subq $dst, $src\t# long" %} |
|
7494 |
opcode(0x81, 0x05); /* Opcode 81 /5 */ |
|
7495 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
7496 |
ins_pipe(ialu_reg); |
|
7497 |
%} |
|
7498 |
||
7499 |
instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) |
|
7500 |
%{ |
|
7501 |
match(Set dst (SubL dst (LoadL src))); |
|
7502 |
effect(KILL cr); |
|
7503 |
||
7504 |
ins_cost(125); |
|
7505 |
format %{ "subq $dst, $src\t# long" %} |
|
7506 |
opcode(0x2B); |
|
7507 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
7508 |
ins_pipe(ialu_reg_mem); |
|
7509 |
%} |
|
7510 |
||
7511 |
instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) |
|
7512 |
%{ |
|
7513 |
match(Set dst (StoreL dst (SubL (LoadL dst) src))); |
|
7514 |
effect(KILL cr); |
|
7515 |
||
7516 |
ins_cost(150); |
|
7517 |
format %{ "subq $dst, $src\t# long" %} |
|
7518 |
opcode(0x29); /* Opcode 29 /r */ |
|
7519 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
7520 |
ins_pipe(ialu_mem_reg); |
|
7521 |
%} |
|
7522 |
||
7523 |
instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) |
|
7524 |
%{ |
|
7525 |
match(Set dst (StoreL dst (SubL (LoadL dst) src))); |
|
7526 |
effect(KILL cr); |
|
7527 |
||
7528 |
ins_cost(125); // XXX |
|
7529 |
format %{ "subq $dst, $src\t# long" %} |
|
7530 |
opcode(0x81); /* Opcode 81 /5 id */ |
|
7531 |
ins_encode(REX_mem_wide(dst), |
|
7532 |
OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
|
7533 |
ins_pipe(ialu_mem_imm); |
|
7534 |
%} |
|
7535 |
||
7536 |
// Subtract from a pointer |
|
7537 |
// XXX hmpf??? |
|
7538 |
instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) |
|
7539 |
%{ |
|
7540 |
match(Set dst (AddP dst (SubI zero src))); |
|
7541 |
effect(KILL cr); |
|
7542 |
||
7543 |
format %{ "subq $dst, $src\t# ptr - int" %} |
|
7544 |
opcode(0x2B); |
|
7545 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
7546 |
ins_pipe(ialu_reg_reg); |
|
7547 |
%} |
|
7548 |
||
7549 |
instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) |
|
7550 |
%{ |
|
7551 |
match(Set dst (SubI zero dst)); |
|
7552 |
effect(KILL cr); |
|
7553 |
||
7554 |
format %{ "negl $dst\t# int" %} |
|
7555 |
opcode(0xF7, 0x03); // Opcode F7 /3 |
|
7556 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
7557 |
ins_pipe(ialu_reg); |
|
7558 |
%} |
|
7559 |
||
7560 |
instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) |
|
7561 |
%{ |
|
7562 |
match(Set dst (StoreI dst (SubI zero (LoadI dst)))); |
|
7563 |
effect(KILL cr); |
|
7564 |
||
7565 |
format %{ "negl $dst\t# int" %} |
|
7566 |
opcode(0xF7, 0x03); // Opcode F7 /3 |
|
7567 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
7568 |
ins_pipe(ialu_reg); |
|
7569 |
%} |
|
7570 |
||
7571 |
instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) |
|
7572 |
%{ |
|
7573 |
match(Set dst (SubL zero dst)); |
|
7574 |
effect(KILL cr); |
|
7575 |
||
7576 |
format %{ "negq $dst\t# long" %} |
|
7577 |
opcode(0xF7, 0x03); // Opcode F7 /3 |
|
7578 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
7579 |
ins_pipe(ialu_reg); |
|
7580 |
%} |
|
7581 |
||
7582 |
instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) |
|
7583 |
%{ |
|
7584 |
match(Set dst (StoreL dst (SubL zero (LoadL dst)))); |
|
7585 |
effect(KILL cr); |
|
7586 |
||
7587 |
format %{ "negq $dst\t# long" %} |
|
7588 |
opcode(0xF7, 0x03); // Opcode F7 /3 |
|
7589 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
7590 |
ins_pipe(ialu_reg); |
|
7591 |
%} |
|
7592 |
||
7593 |
||
7594 |
//----------Multiplication/Division Instructions------------------------------- |
|
7595 |
// Integer Multiplication Instructions |
|
7596 |
// Multiply Register |
|
7597 |
||
7598 |
instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
7599 |
%{ |
|
7600 |
match(Set dst (MulI dst src)); |
|
7601 |
effect(KILL cr); |
|
7602 |
||
7603 |
ins_cost(300); |
|
7604 |
format %{ "imull $dst, $src\t# int" %} |
|
7605 |
opcode(0x0F, 0xAF); |
|
7606 |
ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
7607 |
ins_pipe(ialu_reg_reg_alu0); |
|
7608 |
%} |
|
7609 |
||
7610 |
instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) |
|
7611 |
%{ |
|
7612 |
match(Set dst (MulI src imm)); |
|
7613 |
effect(KILL cr); |
|
7614 |
||
7615 |
ins_cost(300); |
|
7616 |
format %{ "imull $dst, $src, $imm\t# int" %} |
|
7617 |
opcode(0x69); /* 69 /r id */ |
|
7618 |
ins_encode(REX_reg_reg(dst, src), |
|
7619 |
OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); |
|
7620 |
ins_pipe(ialu_reg_reg_alu0); |
|
7621 |
%} |
|
7622 |
||
7623 |
instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) |
|
7624 |
%{ |
|
7625 |
match(Set dst (MulI dst (LoadI src))); |
|
7626 |
effect(KILL cr); |
|
7627 |
||
7628 |
ins_cost(350); |
|
7629 |
format %{ "imull $dst, $src\t# int" %} |
|
7630 |
opcode(0x0F, 0xAF); |
|
7631 |
ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); |
|
7632 |
ins_pipe(ialu_reg_mem_alu0); |
|
7633 |
%} |
|
7634 |
||
7635 |
instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) |
|
7636 |
%{ |
|
7637 |
match(Set dst (MulI (LoadI src) imm)); |
|
7638 |
effect(KILL cr); |
|
7639 |
||
7640 |
ins_cost(300); |
|
7641 |
format %{ "imull $dst, $src, $imm\t# int" %} |
|
7642 |
opcode(0x69); /* 69 /r id */ |
|
7643 |
ins_encode(REX_reg_mem(dst, src), |
|
7644 |
OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); |
|
7645 |
ins_pipe(ialu_reg_mem_alu0); |
|
7646 |
%} |
|
7647 |
||
7648 |
instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
7649 |
%{ |
|
7650 |
match(Set dst (MulL dst src)); |
|
7651 |
effect(KILL cr); |
|
7652 |
||
7653 |
ins_cost(300); |
|
7654 |
format %{ "imulq $dst, $src\t# long" %} |
|
7655 |
opcode(0x0F, 0xAF); |
|
7656 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
7657 |
ins_pipe(ialu_reg_reg_alu0); |
|
7658 |
%} |
|
7659 |
||
7660 |
instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) |
|
7661 |
%{ |
|
7662 |
match(Set dst (MulL src imm)); |
|
7663 |
effect(KILL cr); |
|
7664 |
||
7665 |
ins_cost(300); |
|
7666 |
format %{ "imulq $dst, $src, $imm\t# long" %} |
|
7667 |
opcode(0x69); /* 69 /r id */ |
|
7668 |
ins_encode(REX_reg_reg_wide(dst, src), |
|
7669 |
OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); |
|
7670 |
ins_pipe(ialu_reg_reg_alu0); |
|
7671 |
%} |
|
7672 |
||
7673 |
instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) |
|
7674 |
%{ |
|
7675 |
match(Set dst (MulL dst (LoadL src))); |
|
7676 |
effect(KILL cr); |
|
7677 |
||
7678 |
ins_cost(350); |
|
7679 |
format %{ "imulq $dst, $src\t# long" %} |
|
7680 |
opcode(0x0F, 0xAF); |
|
7681 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); |
|
7682 |
ins_pipe(ialu_reg_mem_alu0); |
|
7683 |
%} |
|
7684 |
||
7685 |
instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) |
|
7686 |
%{ |
|
7687 |
match(Set dst (MulL (LoadL src) imm)); |
|
7688 |
effect(KILL cr); |
|
7689 |
||
7690 |
ins_cost(300); |
|
7691 |
format %{ "imulq $dst, $src, $imm\t# long" %} |
|
7692 |
opcode(0x69); /* 69 /r id */ |
|
7693 |
ins_encode(REX_reg_mem_wide(dst, src), |
|
7694 |
OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); |
|
7695 |
ins_pipe(ialu_reg_mem_alu0); |
|
7696 |
%} |
|
7697 |
||
392 | 7698 |
instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
7699 |
%{ |
|
7700 |
match(Set dst (MulHiL src rax)); |
|
7701 |
effect(USE_KILL rax, KILL cr); |
|
7702 |
||
7703 |
ins_cost(300); |
|
7704 |
format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
|
7705 |
opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
|
7706 |
ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
|
7707 |
ins_pipe(ialu_reg_reg_alu0); |
|
7708 |
%} |
|
7709 |
||
1 | 7710 |
instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
7711 |
rFlagsReg cr) |
|
7712 |
%{ |
|
7713 |
match(Set rax (DivI rax div)); |
|
7714 |
effect(KILL rdx, KILL cr); |
|
7715 |
||
7716 |
ins_cost(30*100+10*100); // XXX |
|
7717 |
format %{ "cmpl rax, 0x80000000\t# idiv\n\t" |
|
7718 |
"jne,s normal\n\t" |
|
7719 |
"xorl rdx, rdx\n\t" |
|
7720 |
"cmpl $div, -1\n\t" |
|
7721 |
"je,s done\n" |
|
7722 |
"normal: cdql\n\t" |
|
7723 |
"idivl $div\n" |
|
7724 |
"done:" %} |
|
7725 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7726 |
ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); |
|
7727 |
ins_pipe(ialu_reg_reg_alu0); |
|
7728 |
%} |
|
7729 |
||
7730 |
instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, |
|
7731 |
rFlagsReg cr) |
|
7732 |
%{ |
|
7733 |
match(Set rax (DivL rax div)); |
|
7734 |
effect(KILL rdx, KILL cr); |
|
7735 |
||
7736 |
ins_cost(30*100+10*100); // XXX |
|
7737 |
format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" |
|
7738 |
"cmpq rax, rdx\n\t" |
|
7739 |
"jne,s normal\n\t" |
|
7740 |
"xorl rdx, rdx\n\t" |
|
7741 |
"cmpq $div, -1\n\t" |
|
7742 |
"je,s done\n" |
|
7743 |
"normal: cdqq\n\t" |
|
7744 |
"idivq $div\n" |
|
7745 |
"done:" %} |
|
7746 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7747 |
ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); |
|
7748 |
ins_pipe(ialu_reg_reg_alu0); |
|
7749 |
%} |
|
7750 |
||
7751 |
// Integer DIVMOD with Register, both quotient and mod results |
|
7752 |
instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
|
7753 |
rFlagsReg cr) |
|
7754 |
%{ |
|
7755 |
match(DivModI rax div); |
|
7756 |
effect(KILL cr); |
|
7757 |
||
7758 |
ins_cost(30*100+10*100); // XXX |
|
7759 |
format %{ "cmpl rax, 0x80000000\t# idiv\n\t" |
|
7760 |
"jne,s normal\n\t" |
|
7761 |
"xorl rdx, rdx\n\t" |
|
7762 |
"cmpl $div, -1\n\t" |
|
7763 |
"je,s done\n" |
|
7764 |
"normal: cdql\n\t" |
|
7765 |
"idivl $div\n" |
|
7766 |
"done:" %} |
|
7767 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7768 |
ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); |
|
7769 |
ins_pipe(pipe_slow); |
|
7770 |
%} |
|
7771 |
||
7772 |
// Long DIVMOD with Register, both quotient and mod results |
|
7773 |
instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, |
|
7774 |
rFlagsReg cr) |
|
7775 |
%{ |
|
7776 |
match(DivModL rax div); |
|
7777 |
effect(KILL cr); |
|
7778 |
||
7779 |
ins_cost(30*100+10*100); // XXX |
|
7780 |
format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" |
|
7781 |
"cmpq rax, rdx\n\t" |
|
7782 |
"jne,s normal\n\t" |
|
7783 |
"xorl rdx, rdx\n\t" |
|
7784 |
"cmpq $div, -1\n\t" |
|
7785 |
"je,s done\n" |
|
7786 |
"normal: cdqq\n\t" |
|
7787 |
"idivq $div\n" |
|
7788 |
"done:" %} |
|
7789 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7790 |
ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); |
|
7791 |
ins_pipe(pipe_slow); |
|
7792 |
%} |
|
7793 |
||
7794 |
//----------- DivL-By-Constant-Expansions-------------------------------------- |
|
7795 |
// DivI cases are handled by the compiler |
|
7796 |
||
2131 | 7797 |
// Magic constant, reciprocal of 10 |
1 | 7798 |
instruct loadConL_0x6666666666666667(rRegL dst) |
7799 |
%{ |
|
7800 |
effect(DEF dst); |
|
7801 |
||
7802 |
format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} |
|
7803 |
ins_encode(load_immL(dst, 0x6666666666666667)); |
|
7804 |
ins_pipe(ialu_reg); |
|
7805 |
%} |
|
7806 |
||
7807 |
instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
|
7808 |
%{ |
|
7809 |
effect(DEF dst, USE src, USE_KILL rax, KILL cr); |
|
7810 |
||
7811 |
format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} |
|
7812 |
opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
|
7813 |
ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
|
7814 |
ins_pipe(ialu_reg_reg_alu0); |
|
7815 |
%} |
|
7816 |
||
7817 |
instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) |
|
7818 |
%{ |
|
7819 |
effect(USE_DEF dst, KILL cr); |
|
7820 |
||
7821 |
format %{ "sarq $dst, #63\t# Used in div-by-10" %} |
|
7822 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
7823 |
ins_encode(reg_opc_imm_wide(dst, 0x3F)); |
|
7824 |
ins_pipe(ialu_reg); |
|
7825 |
%} |
|
7826 |
||
7827 |
instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) |
|
7828 |
%{ |
|
7829 |
effect(USE_DEF dst, KILL cr); |
|
7830 |
||
7831 |
format %{ "sarq $dst, #2\t# Used in div-by-10" %} |
|
7832 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
7833 |
ins_encode(reg_opc_imm_wide(dst, 0x2)); |
|
7834 |
ins_pipe(ialu_reg); |
|
7835 |
%} |
|
7836 |
||
7837 |
instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) |
|
7838 |
%{ |
|
7839 |
match(Set dst (DivL src div)); |
|
7840 |
||
7841 |
ins_cost((5+8)*100); |
|
7842 |
expand %{ |
|
7843 |
rax_RegL rax; // Killed temp |
|
7844 |
rFlagsReg cr; // Killed |
|
7845 |
loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 |
|
7846 |
mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src |
|
7847 |
sarL_rReg_63(src, cr); // sarq src, 63 |
|
7848 |
sarL_rReg_2(dst, cr); // sarq rdx, 2 |
|
7849 |
subL_rReg(dst, src, cr); // subl rdx, src |
|
7850 |
%} |
|
7851 |
%} |
|
7852 |
||
7853 |
//----------------------------------------------------------------------------- |
|
7854 |
||
7855 |
instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, |
|
7856 |
rFlagsReg cr) |
|
7857 |
%{ |
|
7858 |
match(Set rdx (ModI rax div)); |
|
7859 |
effect(KILL rax, KILL cr); |
|
7860 |
||
7861 |
ins_cost(300); // XXX |
|
7862 |
format %{ "cmpl rax, 0x80000000\t# irem\n\t" |
|
7863 |
"jne,s normal\n\t" |
|
7864 |
"xorl rdx, rdx\n\t" |
|
7865 |
"cmpl $div, -1\n\t" |
|
7866 |
"je,s done\n" |
|
7867 |
"normal: cdql\n\t" |
|
7868 |
"idivl $div\n" |
|
7869 |
"done:" %} |
|
7870 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7871 |
ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); |
|
7872 |
ins_pipe(ialu_reg_reg_alu0); |
|
7873 |
%} |
|
7874 |
||
7875 |
instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, |
|
7876 |
rFlagsReg cr) |
|
7877 |
%{ |
|
7878 |
match(Set rdx (ModL rax div)); |
|
7879 |
effect(KILL rax, KILL cr); |
|
7880 |
||
7881 |
ins_cost(300); // XXX |
|
7882 |
format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" |
|
7883 |
"cmpq rax, rdx\n\t" |
|
7884 |
"jne,s normal\n\t" |
|
7885 |
"xorl rdx, rdx\n\t" |
|
7886 |
"cmpq $div, -1\n\t" |
|
7887 |
"je,s done\n" |
|
7888 |
"normal: cdqq\n\t" |
|
7889 |
"idivq $div\n" |
|
7890 |
"done:" %} |
|
7891 |
opcode(0xF7, 0x7); /* Opcode F7 /7 */ |
|
7892 |
ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); |
|
7893 |
ins_pipe(ialu_reg_reg_alu0); |
|
7894 |
%} |
|
7895 |
||
7896 |
// Integer Shift Instructions |
|
7897 |
// Shift Left by one |
|
7898 |
instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) |
|
7899 |
%{ |
|
7900 |
match(Set dst (LShiftI dst shift)); |
|
7901 |
effect(KILL cr); |
|
7902 |
||
7903 |
format %{ "sall $dst, $shift" %} |
|
7904 |
opcode(0xD1, 0x4); /* D1 /4 */ |
|
7905 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
7906 |
ins_pipe(ialu_reg); |
|
7907 |
%} |
|
7908 |
||
7909 |
// Shift Left by one |
|
7910 |
instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
7911 |
%{ |
|
7912 |
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); |
|
7913 |
effect(KILL cr); |
|
7914 |
||
7915 |
format %{ "sall $dst, $shift\t" %} |
|
7916 |
opcode(0xD1, 0x4); /* D1 /4 */ |
|
7917 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
7918 |
ins_pipe(ialu_mem_imm); |
|
7919 |
%} |
|
7920 |
||
7921 |
// Shift Left by 8-bit immediate |
|
7922 |
instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) |
|
7923 |
%{ |
|
7924 |
match(Set dst (LShiftI dst shift)); |
|
7925 |
effect(KILL cr); |
|
7926 |
||
7927 |
format %{ "sall $dst, $shift" %} |
|
7928 |
opcode(0xC1, 0x4); /* C1 /4 ib */ |
|
7929 |
ins_encode(reg_opc_imm(dst, shift)); |
|
7930 |
ins_pipe(ialu_reg); |
|
7931 |
%} |
|
7932 |
||
7933 |
// Shift Left by 8-bit immediate |
|
7934 |
instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
7935 |
%{ |
|
7936 |
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); |
|
7937 |
effect(KILL cr); |
|
7938 |
||
7939 |
format %{ "sall $dst, $shift" %} |
|
7940 |
opcode(0xC1, 0x4); /* C1 /4 ib */ |
|
7941 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
7942 |
ins_pipe(ialu_mem_imm); |
|
7943 |
%} |
|
7944 |
||
7945 |
// Shift Left by variable |
|
7946 |
instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) |
|
7947 |
%{ |
|
7948 |
match(Set dst (LShiftI dst shift)); |
|
7949 |
effect(KILL cr); |
|
7950 |
||
7951 |
format %{ "sall $dst, $shift" %} |
|
7952 |
opcode(0xD3, 0x4); /* D3 /4 */ |
|
7953 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
7954 |
ins_pipe(ialu_reg_reg); |
|
7955 |
%} |
|
7956 |
||
7957 |
// Shift Left by variable |
|
7958 |
instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
7959 |
%{ |
|
7960 |
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); |
|
7961 |
effect(KILL cr); |
|
7962 |
||
7963 |
format %{ "sall $dst, $shift" %} |
|
7964 |
opcode(0xD3, 0x4); /* D3 /4 */ |
|
7965 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
7966 |
ins_pipe(ialu_mem_reg); |
|
7967 |
%} |
|
7968 |
||
7969 |
// Arithmetic shift right by one |
|
7970 |
instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) |
|
7971 |
%{ |
|
7972 |
match(Set dst (RShiftI dst shift)); |
|
7973 |
effect(KILL cr); |
|
7974 |
||
7975 |
format %{ "sarl $dst, $shift" %} |
|
7976 |
opcode(0xD1, 0x7); /* D1 /7 */ |
|
7977 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
7978 |
ins_pipe(ialu_reg); |
|
7979 |
%} |
|
7980 |
||
7981 |
// Arithmetic shift right by one |
|
7982 |
instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
7983 |
%{ |
|
7984 |
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); |
|
7985 |
effect(KILL cr); |
|
7986 |
||
7987 |
format %{ "sarl $dst, $shift" %} |
|
7988 |
opcode(0xD1, 0x7); /* D1 /7 */ |
|
7989 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
7990 |
ins_pipe(ialu_mem_imm); |
|
7991 |
%} |
|
7992 |
||
7993 |
// Arithmetic Shift Right by 8-bit immediate |
|
7994 |
instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) |
|
7995 |
%{ |
|
7996 |
match(Set dst (RShiftI dst shift)); |
|
7997 |
effect(KILL cr); |
|
7998 |
||
7999 |
format %{ "sarl $dst, $shift" %} |
|
8000 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
8001 |
ins_encode(reg_opc_imm(dst, shift)); |
|
8002 |
ins_pipe(ialu_mem_imm); |
|
8003 |
%} |
|
8004 |
||
8005 |
// Arithmetic Shift Right by 8-bit immediate |
|
8006 |
instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
8007 |
%{ |
|
8008 |
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); |
|
8009 |
effect(KILL cr); |
|
8010 |
||
8011 |
format %{ "sarl $dst, $shift" %} |
|
8012 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
8013 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
8014 |
ins_pipe(ialu_mem_imm); |
|
8015 |
%} |
|
8016 |
||
8017 |
// Arithmetic Shift Right by variable |
|
8018 |
instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) |
|
8019 |
%{ |
|
8020 |
match(Set dst (RShiftI dst shift)); |
|
8021 |
effect(KILL cr); |
|
8022 |
||
8023 |
format %{ "sarl $dst, $shift" %} |
|
8024 |
opcode(0xD3, 0x7); /* D3 /7 */ |
|
8025 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8026 |
ins_pipe(ialu_reg_reg); |
|
8027 |
%} |
|
8028 |
||
8029 |
// Arithmetic Shift Right by variable |
|
8030 |
instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
8031 |
%{ |
|
8032 |
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); |
|
8033 |
effect(KILL cr); |
|
8034 |
||
8035 |
format %{ "sarl $dst, $shift" %} |
|
8036 |
opcode(0xD3, 0x7); /* D3 /7 */ |
|
8037 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8038 |
ins_pipe(ialu_mem_reg); |
|
8039 |
%} |
|
8040 |
||
8041 |
// Logical shift right by one |
|
8042 |
instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) |
|
8043 |
%{ |
|
8044 |
match(Set dst (URShiftI dst shift)); |
|
8045 |
effect(KILL cr); |
|
8046 |
||
8047 |
format %{ "shrl $dst, $shift" %} |
|
8048 |
opcode(0xD1, 0x5); /* D1 /5 */ |
|
8049 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8050 |
ins_pipe(ialu_reg); |
|
8051 |
%} |
|
8052 |
||
8053 |
// Logical shift right by one |
|
8054 |
instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
8055 |
%{ |
|
8056 |
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); |
|
8057 |
effect(KILL cr); |
|
8058 |
||
8059 |
format %{ "shrl $dst, $shift" %} |
|
8060 |
opcode(0xD1, 0x5); /* D1 /5 */ |
|
8061 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8062 |
ins_pipe(ialu_mem_imm); |
|
8063 |
%} |
|
8064 |
||
8065 |
// Logical Shift Right by 8-bit immediate |
|
8066 |
instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) |
|
8067 |
%{ |
|
8068 |
match(Set dst (URShiftI dst shift)); |
|
8069 |
effect(KILL cr); |
|
8070 |
||
8071 |
format %{ "shrl $dst, $shift" %} |
|
8072 |
opcode(0xC1, 0x5); /* C1 /5 ib */ |
|
8073 |
ins_encode(reg_opc_imm(dst, shift)); |
|
8074 |
ins_pipe(ialu_reg); |
|
8075 |
%} |
|
8076 |
||
8077 |
// Logical Shift Right by 8-bit immediate |
|
8078 |
instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
8079 |
%{ |
|
8080 |
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); |
|
8081 |
effect(KILL cr); |
|
8082 |
||
8083 |
format %{ "shrl $dst, $shift" %} |
|
8084 |
opcode(0xC1, 0x5); /* C1 /5 ib */ |
|
8085 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
8086 |
ins_pipe(ialu_mem_imm); |
|
8087 |
%} |
|
8088 |
||
8089 |
// Logical Shift Right by variable |
|
8090 |
instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) |
|
8091 |
%{ |
|
8092 |
match(Set dst (URShiftI dst shift)); |
|
8093 |
effect(KILL cr); |
|
8094 |
||
8095 |
format %{ "shrl $dst, $shift" %} |
|
8096 |
opcode(0xD3, 0x5); /* D3 /5 */ |
|
8097 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8098 |
ins_pipe(ialu_reg_reg); |
|
8099 |
%} |
|
8100 |
||
8101 |
// Logical Shift Right by variable |
|
8102 |
instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
8103 |
%{ |
|
8104 |
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); |
|
8105 |
effect(KILL cr); |
|
8106 |
||
8107 |
format %{ "shrl $dst, $shift" %} |
|
8108 |
opcode(0xD3, 0x5); /* D3 /5 */ |
|
8109 |
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8110 |
ins_pipe(ialu_mem_reg); |
|
8111 |
%} |
|
8112 |
||
8113 |
// Long Shift Instructions |
|
8114 |
// Shift Left by one |
|
8115 |
instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) |
|
8116 |
%{ |
|
8117 |
match(Set dst (LShiftL dst shift)); |
|
8118 |
effect(KILL cr); |
|
8119 |
||
8120 |
format %{ "salq $dst, $shift" %} |
|
8121 |
opcode(0xD1, 0x4); /* D1 /4 */ |
|
8122 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8123 |
ins_pipe(ialu_reg); |
|
8124 |
%} |
|
8125 |
||
8126 |
// Shift Left by one |
|
8127 |
instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
8128 |
%{ |
|
8129 |
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); |
|
8130 |
effect(KILL cr); |
|
8131 |
||
8132 |
format %{ "salq $dst, $shift" %} |
|
8133 |
opcode(0xD1, 0x4); /* D1 /4 */ |
|
8134 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8135 |
ins_pipe(ialu_mem_imm); |
|
8136 |
%} |
|
8137 |
||
8138 |
// Shift Left by 8-bit immediate |
|
8139 |
instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) |
|
8140 |
%{ |
|
8141 |
match(Set dst (LShiftL dst shift)); |
|
8142 |
effect(KILL cr); |
|
8143 |
||
8144 |
format %{ "salq $dst, $shift" %} |
|
8145 |
opcode(0xC1, 0x4); /* C1 /4 ib */ |
|
8146 |
ins_encode(reg_opc_imm_wide(dst, shift)); |
|
8147 |
ins_pipe(ialu_reg); |
|
8148 |
%} |
|
8149 |
||
8150 |
// Shift Left by 8-bit immediate |
|
8151 |
instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
8152 |
%{ |
|
8153 |
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); |
|
8154 |
effect(KILL cr); |
|
8155 |
||
8156 |
format %{ "salq $dst, $shift" %} |
|
8157 |
opcode(0xC1, 0x4); /* C1 /4 ib */ |
|
8158 |
ins_encode(REX_mem_wide(dst), OpcP, |
|
8159 |
RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
8160 |
ins_pipe(ialu_mem_imm); |
|
8161 |
%} |
|
8162 |
||
8163 |
// Shift Left by variable |
|
8164 |
instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) |
|
8165 |
%{ |
|
8166 |
match(Set dst (LShiftL dst shift)); |
|
8167 |
effect(KILL cr); |
|
8168 |
||
8169 |
format %{ "salq $dst, $shift" %} |
|
8170 |
opcode(0xD3, 0x4); /* D3 /4 */ |
|
8171 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8172 |
ins_pipe(ialu_reg_reg); |
|
8173 |
%} |
|
8174 |
||
8175 |
// Shift Left by variable |
|
8176 |
instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
8177 |
%{ |
|
8178 |
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); |
|
8179 |
effect(KILL cr); |
|
8180 |
||
8181 |
format %{ "salq $dst, $shift" %} |
|
8182 |
opcode(0xD3, 0x4); /* D3 /4 */ |
|
8183 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8184 |
ins_pipe(ialu_mem_reg); |
|
8185 |
%} |
|
8186 |
||
8187 |
// Arithmetic shift right by one |
|
8188 |
instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) |
|
8189 |
%{ |
|
8190 |
match(Set dst (RShiftL dst shift)); |
|
8191 |
effect(KILL cr); |
|
8192 |
||
8193 |
format %{ "sarq $dst, $shift" %} |
|
8194 |
opcode(0xD1, 0x7); /* D1 /7 */ |
|
8195 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8196 |
ins_pipe(ialu_reg); |
|
8197 |
%} |
|
8198 |
||
8199 |
// Arithmetic shift right by one |
|
8200 |
instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
8201 |
%{ |
|
8202 |
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); |
|
8203 |
effect(KILL cr); |
|
8204 |
||
8205 |
format %{ "sarq $dst, $shift" %} |
|
8206 |
opcode(0xD1, 0x7); /* D1 /7 */ |
|
8207 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8208 |
ins_pipe(ialu_mem_imm); |
|
8209 |
%} |
|
8210 |
||
8211 |
// Arithmetic Shift Right by 8-bit immediate |
|
8212 |
instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) |
|
8213 |
%{ |
|
8214 |
match(Set dst (RShiftL dst shift)); |
|
8215 |
effect(KILL cr); |
|
8216 |
||
8217 |
format %{ "sarq $dst, $shift" %} |
|
8218 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
8219 |
ins_encode(reg_opc_imm_wide(dst, shift)); |
|
8220 |
ins_pipe(ialu_mem_imm); |
|
8221 |
%} |
|
8222 |
||
8223 |
// Arithmetic Shift Right by 8-bit immediate |
|
8224 |
instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
8225 |
%{ |
|
8226 |
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); |
|
8227 |
effect(KILL cr); |
|
8228 |
||
8229 |
format %{ "sarq $dst, $shift" %} |
|
8230 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
8231 |
ins_encode(REX_mem_wide(dst), OpcP, |
|
8232 |
RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
8233 |
ins_pipe(ialu_mem_imm); |
|
8234 |
%} |
|
8235 |
||
8236 |
// Arithmetic Shift Right by variable |
|
8237 |
instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) |
|
8238 |
%{ |
|
8239 |
match(Set dst (RShiftL dst shift)); |
|
8240 |
effect(KILL cr); |
|
8241 |
||
8242 |
format %{ "sarq $dst, $shift" %} |
|
8243 |
opcode(0xD3, 0x7); /* D3 /7 */ |
|
8244 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8245 |
ins_pipe(ialu_reg_reg); |
|
8246 |
%} |
|
8247 |
||
8248 |
// Arithmetic Shift Right by variable |
|
8249 |
instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
8250 |
%{ |
|
8251 |
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); |
|
8252 |
effect(KILL cr); |
|
8253 |
||
8254 |
format %{ "sarq $dst, $shift" %} |
|
8255 |
opcode(0xD3, 0x7); /* D3 /7 */ |
|
8256 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8257 |
ins_pipe(ialu_mem_reg); |
|
8258 |
%} |
|
8259 |
||
8260 |
// Logical shift right by one |
|
8261 |
instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) |
|
8262 |
%{ |
|
8263 |
match(Set dst (URShiftL dst shift)); |
|
8264 |
effect(KILL cr); |
|
8265 |
||
8266 |
format %{ "shrq $dst, $shift" %} |
|
8267 |
opcode(0xD1, 0x5); /* D1 /5 */ |
|
8268 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); |
|
8269 |
ins_pipe(ialu_reg); |
|
8270 |
%} |
|
8271 |
||
8272 |
// Logical shift right by one |
|
8273 |
instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) |
|
8274 |
%{ |
|
8275 |
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); |
|
8276 |
effect(KILL cr); |
|
8277 |
||
8278 |
format %{ "shrq $dst, $shift" %} |
|
8279 |
opcode(0xD1, 0x5); /* D1 /5 */ |
|
8280 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8281 |
ins_pipe(ialu_mem_imm); |
|
8282 |
%} |
|
8283 |
||
8284 |
// Logical Shift Right by 8-bit immediate |
|
8285 |
instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) |
|
8286 |
%{ |
|
8287 |
match(Set dst (URShiftL dst shift)); |
|
8288 |
effect(KILL cr); |
|
8289 |
||
8290 |
format %{ "shrq $dst, $shift" %} |
|
8291 |
opcode(0xC1, 0x5); /* C1 /5 ib */ |
|
8292 |
ins_encode(reg_opc_imm_wide(dst, shift)); |
|
8293 |
ins_pipe(ialu_reg); |
|
8294 |
%} |
|
8295 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8296 |
|
1 | 8297 |
// Logical Shift Right by 8-bit immediate |
8298 |
instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) |
|
8299 |
%{ |
|
8300 |
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); |
|
8301 |
effect(KILL cr); |
|
8302 |
||
8303 |
format %{ "shrq $dst, $shift" %} |
|
8304 |
opcode(0xC1, 0x5); /* C1 /5 ib */ |
|
8305 |
ins_encode(REX_mem_wide(dst), OpcP, |
|
8306 |
RM_opc_mem(secondary, dst), Con8or32(shift)); |
|
8307 |
ins_pipe(ialu_mem_imm); |
|
8308 |
%} |
|
8309 |
||
8310 |
// Logical Shift Right by variable |
|
8311 |
instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) |
|
8312 |
%{ |
|
8313 |
match(Set dst (URShiftL dst shift)); |
|
8314 |
effect(KILL cr); |
|
8315 |
||
8316 |
format %{ "shrq $dst, $shift" %} |
|
8317 |
opcode(0xD3, 0x5); /* D3 /5 */ |
|
8318 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8319 |
ins_pipe(ialu_reg_reg); |
|
8320 |
%} |
|
8321 |
||
8322 |
// Logical Shift Right by variable |
|
8323 |
instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) |
|
8324 |
%{ |
|
8325 |
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); |
|
8326 |
effect(KILL cr); |
|
8327 |
||
8328 |
format %{ "shrq $dst, $shift" %} |
|
8329 |
opcode(0xD3, 0x5); /* D3 /5 */ |
|
8330 |
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
|
8331 |
ins_pipe(ialu_mem_reg); |
|
8332 |
%} |
|
8333 |
||
8334 |
// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
|
8335 |
// This idiom is used by the compiler for the i2b bytecode. |
|
8336 |
instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) |
|
8337 |
%{ |
|
8338 |
match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
|
8339 |
||
8340 |
format %{ "movsbl $dst, $src\t# i2b" %} |
|
8341 |
opcode(0x0F, 0xBE); |
|
8342 |
ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
8343 |
ins_pipe(ialu_reg_reg); |
|
8344 |
%} |
|
8345 |
||
8346 |
// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. |
|
8347 |
// This idiom is used by the compiler the i2s bytecode. |
|
8348 |
instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) |
|
8349 |
%{ |
|
8350 |
match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
|
8351 |
||
8352 |
format %{ "movswl $dst, $src\t# i2s" %} |
|
8353 |
opcode(0x0F, 0xBF); |
|
8354 |
ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
8355 |
ins_pipe(ialu_reg_reg); |
|
8356 |
%} |
|
8357 |
||
8358 |
// ROL/ROR instructions |
|
8359 |
||
8360 |
// ROL expand |
|
8361 |
instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ |
|
8362 |
effect(KILL cr, USE_DEF dst); |
|
8363 |
||
8364 |
format %{ "roll $dst" %} |
|
8365 |
opcode(0xD1, 0x0); /* Opcode D1 /0 */ |
|
8366 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8367 |
ins_pipe(ialu_reg); |
|
8368 |
%} |
|
8369 |
||
8370 |
instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ |
|
8371 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8372 |
||
8373 |
format %{ "roll $dst, $shift" %} |
|
8374 |
opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ |
|
8375 |
ins_encode( reg_opc_imm(dst, shift) ); |
|
8376 |
ins_pipe(ialu_reg); |
|
8377 |
%} |
|
8378 |
||
8379 |
instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) |
|
8380 |
%{ |
|
8381 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8382 |
||
8383 |
format %{ "roll $dst, $shift" %} |
|
8384 |
opcode(0xD3, 0x0); /* Opcode D3 /0 */ |
|
8385 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8386 |
ins_pipe(ialu_reg_reg); |
|
8387 |
%} |
|
8388 |
// end of ROL expand |
|
8389 |
||
8390 |
// Rotate Left by one |
|
8391 |
instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) |
|
8392 |
%{ |
|
8393 |
match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
|
8394 |
||
8395 |
expand %{ |
|
8396 |
rolI_rReg_imm1(dst, cr); |
|
8397 |
%} |
|
8398 |
%} |
|
8399 |
||
8400 |
// Rotate Left by 8-bit immediate |
|
8401 |
instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) |
|
8402 |
%{ |
|
8403 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8404 |
match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
|
8405 |
||
8406 |
expand %{ |
|
8407 |
rolI_rReg_imm8(dst, lshift, cr); |
|
8408 |
%} |
|
8409 |
%} |
|
8410 |
||
8411 |
// Rotate Left by variable |
|
8412 |
instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) |
|
8413 |
%{ |
|
8414 |
match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); |
|
8415 |
||
8416 |
expand %{ |
|
8417 |
rolI_rReg_CL(dst, shift, cr); |
|
8418 |
%} |
|
8419 |
%} |
|
8420 |
||
8421 |
// Rotate Left by variable |
|
8422 |
instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) |
|
8423 |
%{ |
|
8424 |
match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); |
|
8425 |
||
8426 |
expand %{ |
|
8427 |
rolI_rReg_CL(dst, shift, cr); |
|
8428 |
%} |
|
8429 |
%} |
|
8430 |
||
8431 |
// ROR expand |
|
8432 |
instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) |
|
8433 |
%{ |
|
8434 |
effect(USE_DEF dst, KILL cr); |
|
8435 |
||
8436 |
format %{ "rorl $dst" %} |
|
8437 |
opcode(0xD1, 0x1); /* D1 /1 */ |
|
8438 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8439 |
ins_pipe(ialu_reg); |
|
8440 |
%} |
|
8441 |
||
8442 |
instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) |
|
8443 |
%{ |
|
8444 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8445 |
||
8446 |
format %{ "rorl $dst, $shift" %} |
|
8447 |
opcode(0xC1, 0x1); /* C1 /1 ib */ |
|
8448 |
ins_encode(reg_opc_imm(dst, shift)); |
|
8449 |
ins_pipe(ialu_reg); |
|
8450 |
%} |
|
8451 |
||
8452 |
instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) |
|
8453 |
%{ |
|
8454 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8455 |
||
8456 |
format %{ "rorl $dst, $shift" %} |
|
8457 |
opcode(0xD3, 0x1); /* D3 /1 */ |
|
8458 |
ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); |
|
8459 |
ins_pipe(ialu_reg_reg); |
|
8460 |
%} |
|
8461 |
// end of ROR expand |
|
8462 |
||
8463 |
// Rotate Right by one |
|
8464 |
instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) |
|
8465 |
%{ |
|
8466 |
match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
|
8467 |
||
8468 |
expand %{ |
|
8469 |
rorI_rReg_imm1(dst, cr); |
|
8470 |
%} |
|
8471 |
%} |
|
8472 |
||
8473 |
// Rotate Right by 8-bit immediate |
|
8474 |
instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) |
|
8475 |
%{ |
|
8476 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8477 |
match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
|
8478 |
||
8479 |
expand %{ |
|
8480 |
rorI_rReg_imm8(dst, rshift, cr); |
|
8481 |
%} |
|
8482 |
%} |
|
8483 |
||
8484 |
// Rotate Right by variable |
|
8485 |
instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) |
|
8486 |
%{ |
|
8487 |
match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); |
|
8488 |
||
8489 |
expand %{ |
|
8490 |
rorI_rReg_CL(dst, shift, cr); |
|
8491 |
%} |
|
8492 |
%} |
|
8493 |
||
8494 |
// Rotate Right by variable |
|
8495 |
instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) |
|
8496 |
%{ |
|
8497 |
match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); |
|
8498 |
||
8499 |
expand %{ |
|
8500 |
rorI_rReg_CL(dst, shift, cr); |
|
8501 |
%} |
|
8502 |
%} |
|
8503 |
||
8504 |
// for long rotate |
|
8505 |
// ROL expand |
|
8506 |
instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ |
|
8507 |
effect(USE_DEF dst, KILL cr); |
|
8508 |
||
8509 |
format %{ "rolq $dst" %} |
|
8510 |
opcode(0xD1, 0x0); /* Opcode D1 /0 */ |
|
8511 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8512 |
ins_pipe(ialu_reg); |
|
8513 |
%} |
|
8514 |
||
8515 |
instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ |
|
8516 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8517 |
||
8518 |
format %{ "rolq $dst, $shift" %} |
|
8519 |
opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ |
|
8520 |
ins_encode( reg_opc_imm_wide(dst, shift) ); |
|
8521 |
ins_pipe(ialu_reg); |
|
8522 |
%} |
|
8523 |
||
8524 |
instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) |
|
8525 |
%{ |
|
8526 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8527 |
||
8528 |
format %{ "rolq $dst, $shift" %} |
|
8529 |
opcode(0xD3, 0x0); /* Opcode D3 /0 */ |
|
8530 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8531 |
ins_pipe(ialu_reg_reg); |
|
8532 |
%} |
|
8533 |
// end of ROL expand |
|
8534 |
||
8535 |
// Rotate Left by one |
|
8536 |
instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) |
|
8537 |
%{ |
|
8538 |
match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); |
|
8539 |
||
8540 |
expand %{ |
|
8541 |
rolL_rReg_imm1(dst, cr); |
|
8542 |
%} |
|
8543 |
%} |
|
8544 |
||
8545 |
// Rotate Left by 8-bit immediate |
|
8546 |
instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) |
|
8547 |
%{ |
|
8548 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); |
|
8549 |
match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); |
|
8550 |
||
8551 |
expand %{ |
|
8552 |
rolL_rReg_imm8(dst, lshift, cr); |
|
8553 |
%} |
|
8554 |
%} |
|
8555 |
||
8556 |
// Rotate Left by variable |
|
8557 |
instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) |
|
8558 |
%{ |
|
8559 |
match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); |
|
8560 |
||
8561 |
expand %{ |
|
8562 |
rolL_rReg_CL(dst, shift, cr); |
|
8563 |
%} |
|
8564 |
%} |
|
8565 |
||
8566 |
// Rotate Left by variable |
|
8567 |
instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) |
|
8568 |
%{ |
|
8569 |
match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); |
|
8570 |
||
8571 |
expand %{ |
|
8572 |
rolL_rReg_CL(dst, shift, cr); |
|
8573 |
%} |
|
8574 |
%} |
|
8575 |
||
8576 |
// ROR expand |
|
8577 |
instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) |
|
8578 |
%{ |
|
8579 |
effect(USE_DEF dst, KILL cr); |
|
8580 |
||
8581 |
format %{ "rorq $dst" %} |
|
8582 |
opcode(0xD1, 0x1); /* D1 /1 */ |
|
8583 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8584 |
ins_pipe(ialu_reg); |
|
8585 |
%} |
|
8586 |
||
8587 |
instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) |
|
8588 |
%{ |
|
8589 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8590 |
||
8591 |
format %{ "rorq $dst, $shift" %} |
|
8592 |
opcode(0xC1, 0x1); /* C1 /1 ib */ |
|
8593 |
ins_encode(reg_opc_imm_wide(dst, shift)); |
|
8594 |
ins_pipe(ialu_reg); |
|
8595 |
%} |
|
8596 |
||
8597 |
instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) |
|
8598 |
%{ |
|
8599 |
effect(USE_DEF dst, USE shift, KILL cr); |
|
8600 |
||
8601 |
format %{ "rorq $dst, $shift" %} |
|
8602 |
opcode(0xD3, 0x1); /* D3 /1 */ |
|
8603 |
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); |
|
8604 |
ins_pipe(ialu_reg_reg); |
|
8605 |
%} |
|
8606 |
// end of ROR expand |
|
8607 |
||
8608 |
// Rotate Right by one |
|
8609 |
instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) |
|
8610 |
%{ |
|
8611 |
match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); |
|
8612 |
||
8613 |
expand %{ |
|
8614 |
rorL_rReg_imm1(dst, cr); |
|
8615 |
%} |
|
8616 |
%} |
|
8617 |
||
8618 |
// Rotate Right by 8-bit immediate |
|
8619 |
instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) |
|
8620 |
%{ |
|
8621 |
predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); |
|
8622 |
match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); |
|
8623 |
||
8624 |
expand %{ |
|
8625 |
rorL_rReg_imm8(dst, rshift, cr); |
|
8626 |
%} |
|
8627 |
%} |
|
8628 |
||
8629 |
// Rotate Right by variable |
|
8630 |
instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) |
|
8631 |
%{ |
|
8632 |
match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); |
|
8633 |
||
8634 |
expand %{ |
|
8635 |
rorL_rReg_CL(dst, shift, cr); |
|
8636 |
%} |
|
8637 |
%} |
|
8638 |
||
8639 |
// Rotate Right by variable |
|
8640 |
instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) |
|
8641 |
%{ |
|
8642 |
match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); |
|
8643 |
||
8644 |
expand %{ |
|
8645 |
rorL_rReg_CL(dst, shift, cr); |
|
8646 |
%} |
|
8647 |
%} |
|
8648 |
||
8649 |
// Logical Instructions |
|
8650 |
||
8651 |
// Integer Logical Instructions |
|
8652 |
||
8653 |
// And Instructions |
|
8654 |
// And Register with Register |
|
8655 |
instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
8656 |
%{ |
|
8657 |
match(Set dst (AndI dst src)); |
|
8658 |
effect(KILL cr); |
|
8659 |
||
8660 |
format %{ "andl $dst, $src\t# int" %} |
|
8661 |
opcode(0x23); |
|
8662 |
ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); |
|
8663 |
ins_pipe(ialu_reg_reg); |
|
8664 |
%} |
|
8665 |
||
8666 |
// And Register with Immediate 255 |
|
8667 |
instruct andI_rReg_imm255(rRegI dst, immI_255 src) |
|
8668 |
%{ |
|
8669 |
match(Set dst (AndI dst src)); |
|
8670 |
||
8671 |
format %{ "movzbl $dst, $dst\t# int & 0xFF" %} |
|
8672 |
opcode(0x0F, 0xB6); |
|
8673 |
ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
|
8674 |
ins_pipe(ialu_reg); |
|
8675 |
%} |
|
8676 |
||
8677 |
// And Register with Immediate 255 and promote to long |
|
8678 |
instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) |
|
8679 |
%{ |
|
8680 |
match(Set dst (ConvI2L (AndI src mask))); |
|
8681 |
||
8682 |
format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} |
|
8683 |
opcode(0x0F, 0xB6); |
|
8684 |
ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
8685 |
ins_pipe(ialu_reg); |
|
8686 |
%} |
|
8687 |
||
8688 |
// And Register with Immediate 65535 |
|
8689 |
instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) |
|
8690 |
%{ |
|
8691 |
match(Set dst (AndI dst src)); |
|
8692 |
||
8693 |
format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} |
|
8694 |
opcode(0x0F, 0xB7); |
|
8695 |
ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
|
8696 |
ins_pipe(ialu_reg); |
|
8697 |
%} |
|
8698 |
||
8699 |
// And Register with Immediate 65535 and promote to long |
|
8700 |
instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) |
|
8701 |
%{ |
|
8702 |
match(Set dst (ConvI2L (AndI src mask))); |
|
8703 |
||
8704 |
format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} |
|
8705 |
opcode(0x0F, 0xB7); |
|
8706 |
ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
8707 |
ins_pipe(ialu_reg); |
|
8708 |
%} |
|
8709 |
||
8710 |
// And Register with Immediate |
|
8711 |
instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) |
|
8712 |
%{ |
|
8713 |
match(Set dst (AndI dst src)); |
|
8714 |
effect(KILL cr); |
|
8715 |
||
8716 |
format %{ "andl $dst, $src\t# int" %} |
|
8717 |
opcode(0x81, 0x04); /* Opcode 81 /4 */ |
|
8718 |
ins_encode(OpcSErm(dst, src), Con8or32(src)); |
|
8719 |
ins_pipe(ialu_reg); |
|
8720 |
%} |
|
8721 |
||
8722 |
// And Register with Memory |
|
8723 |
instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) |
|
8724 |
%{ |
|
8725 |
match(Set dst (AndI dst (LoadI src))); |
|
8726 |
effect(KILL cr); |
|
8727 |
||
8728 |
ins_cost(125); |
|
8729 |
format %{ "andl $dst, $src\t# int" %} |
|
8730 |
opcode(0x23); |
|
8731 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
8732 |
ins_pipe(ialu_reg_mem); |
|
8733 |
%} |
|
8734 |
||
8735 |
// And Memory with Register |
|
8736 |
instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) |
|
8737 |
%{ |
|
8738 |
match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
|
8739 |
effect(KILL cr); |
|
8740 |
||
8741 |
ins_cost(150); |
|
8742 |
format %{ "andl $dst, $src\t# int" %} |
|
8743 |
opcode(0x21); /* Opcode 21 /r */ |
|
8744 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
8745 |
ins_pipe(ialu_mem_reg); |
|
8746 |
%} |
|
8747 |
||
8748 |
// And Memory with Immediate |
|
8749 |
instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) |
|
8750 |
%{ |
|
8751 |
match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
|
8752 |
effect(KILL cr); |
|
8753 |
||
8754 |
ins_cost(125); |
|
8755 |
format %{ "andl $dst, $src\t# int" %} |
|
8756 |
opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
|
8757 |
ins_encode(REX_mem(dst), OpcSE(src), |
|
8758 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
8759 |
ins_pipe(ialu_mem_imm); |
|
8760 |
%} |
|
8761 |
||
8762 |
// Or Instructions |
|
8763 |
// Or Register with Register |
|
8764 |
instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
8765 |
%{ |
|
8766 |
match(Set dst (OrI dst src)); |
|
8767 |
effect(KILL cr); |
|
8768 |
||
8769 |
format %{ "orl $dst, $src\t# int" %} |
|
8770 |
opcode(0x0B); |
|
8771 |
ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); |
|
8772 |
ins_pipe(ialu_reg_reg); |
|
8773 |
%} |
|
8774 |
||
8775 |
// Or Register with Immediate |
|
8776 |
instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) |
|
8777 |
%{ |
|
8778 |
match(Set dst (OrI dst src)); |
|
8779 |
effect(KILL cr); |
|
8780 |
||
8781 |
format %{ "orl $dst, $src\t# int" %} |
|
8782 |
opcode(0x81, 0x01); /* Opcode 81 /1 id */ |
|
8783 |
ins_encode(OpcSErm(dst, src), Con8or32(src)); |
|
8784 |
ins_pipe(ialu_reg); |
|
8785 |
%} |
|
8786 |
||
8787 |
// Or Register with Memory |
|
8788 |
instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) |
|
8789 |
%{ |
|
8790 |
match(Set dst (OrI dst (LoadI src))); |
|
8791 |
effect(KILL cr); |
|
8792 |
||
8793 |
ins_cost(125); |
|
8794 |
format %{ "orl $dst, $src\t# int" %} |
|
8795 |
opcode(0x0B); |
|
8796 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
8797 |
ins_pipe(ialu_reg_mem); |
|
8798 |
%} |
|
8799 |
||
8800 |
// Or Memory with Register |
|
8801 |
instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) |
|
8802 |
%{ |
|
8803 |
match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
|
8804 |
effect(KILL cr); |
|
8805 |
||
8806 |
ins_cost(150); |
|
8807 |
format %{ "orl $dst, $src\t# int" %} |
|
8808 |
opcode(0x09); /* Opcode 09 /r */ |
|
8809 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
8810 |
ins_pipe(ialu_mem_reg); |
|
8811 |
%} |
|
8812 |
||
8813 |
// Or Memory with Immediate |
|
8814 |
instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) |
|
8815 |
%{ |
|
8816 |
match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
|
8817 |
effect(KILL cr); |
|
8818 |
||
8819 |
ins_cost(125); |
|
8820 |
format %{ "orl $dst, $src\t# int" %} |
|
8821 |
opcode(0x81, 0x1); /* Opcode 81 /1 id */ |
|
8822 |
ins_encode(REX_mem(dst), OpcSE(src), |
|
8823 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
8824 |
ins_pipe(ialu_mem_imm); |
|
8825 |
%} |
|
8826 |
||
8827 |
// Xor Instructions |
|
8828 |
// Xor Register with Register |
|
8829 |
instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
|
8830 |
%{ |
|
8831 |
match(Set dst (XorI dst src)); |
|
8832 |
effect(KILL cr); |
|
8833 |
||
8834 |
format %{ "xorl $dst, $src\t# int" %} |
|
8835 |
opcode(0x33); |
|
8836 |
ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); |
|
8837 |
ins_pipe(ialu_reg_reg); |
|
8838 |
%} |
|
8839 |
||
1435 | 8840 |
// Xor Register with Immediate -1 |
8841 |
instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
8842 |
match(Set dst (XorI dst imm)); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
8843 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
8844 |
format %{ "not $dst" %} |
1435 | 8845 |
ins_encode %{ |
8846 |
__ notl($dst$$Register); |
|
8847 |
%} |
|
8848 |
ins_pipe(ialu_reg); |
|
8849 |
%} |
|
8850 |
||
1 | 8851 |
// Xor Register with Immediate |
8852 |
instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) |
|
8853 |
%{ |
|
8854 |
match(Set dst (XorI dst src)); |
|
8855 |
effect(KILL cr); |
|
8856 |
||
8857 |
format %{ "xorl $dst, $src\t# int" %} |
|
8858 |
opcode(0x81, 0x06); /* Opcode 81 /6 id */ |
|
8859 |
ins_encode(OpcSErm(dst, src), Con8or32(src)); |
|
8860 |
ins_pipe(ialu_reg); |
|
8861 |
%} |
|
8862 |
||
8863 |
// Xor Register with Memory |
|
8864 |
instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) |
|
8865 |
%{ |
|
8866 |
match(Set dst (XorI dst (LoadI src))); |
|
8867 |
effect(KILL cr); |
|
8868 |
||
8869 |
ins_cost(125); |
|
8870 |
format %{ "xorl $dst, $src\t# int" %} |
|
8871 |
opcode(0x33); |
|
8872 |
ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); |
|
8873 |
ins_pipe(ialu_reg_mem); |
|
8874 |
%} |
|
8875 |
||
8876 |
// Xor Memory with Register |
|
8877 |
instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) |
|
8878 |
%{ |
|
8879 |
match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
|
8880 |
effect(KILL cr); |
|
8881 |
||
8882 |
ins_cost(150); |
|
8883 |
format %{ "xorl $dst, $src\t# int" %} |
|
8884 |
opcode(0x31); /* Opcode 31 /r */ |
|
8885 |
ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); |
|
8886 |
ins_pipe(ialu_mem_reg); |
|
8887 |
%} |
|
8888 |
||
8889 |
// Xor Memory with Immediate |
|
8890 |
instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) |
|
8891 |
%{ |
|
8892 |
match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
|
8893 |
effect(KILL cr); |
|
8894 |
||
8895 |
ins_cost(125); |
|
8896 |
format %{ "xorl $dst, $src\t# int" %} |
|
8897 |
opcode(0x81, 0x6); /* Opcode 81 /6 id */ |
|
8898 |
ins_encode(REX_mem(dst), OpcSE(src), |
|
8899 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
8900 |
ins_pipe(ialu_mem_imm); |
|
8901 |
%} |
|
8902 |
||
8903 |
||
8904 |
// Long Logical Instructions |
|
8905 |
||
8906 |
// And Instructions |
|
8907 |
// And Register with Register |
|
8908 |
instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
8909 |
%{ |
|
8910 |
match(Set dst (AndL dst src)); |
|
8911 |
effect(KILL cr); |
|
8912 |
||
8913 |
format %{ "andq $dst, $src\t# long" %} |
|
8914 |
opcode(0x23); |
|
8915 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
8916 |
ins_pipe(ialu_reg_reg); |
|
8917 |
%} |
|
8918 |
||
8919 |
// And Register with Immediate 255 |
|
8920 |
instruct andL_rReg_imm255(rRegL dst, immL_255 src) |
|
8921 |
%{ |
|
8922 |
match(Set dst (AndL dst src)); |
|
8923 |
||
2033
5bce9ca56d29
6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents:
2022
diff
changeset
|
8924 |
format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
1 | 8925 |
opcode(0x0F, 0xB6); |
8926 |
ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
|
8927 |
ins_pipe(ialu_reg); |
|
8928 |
%} |
|
8929 |
||
8930 |
// And Register with Immediate 65535 |
|
2033
5bce9ca56d29
6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents:
2022
diff
changeset
|
8931 |
instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
1 | 8932 |
%{ |
8933 |
match(Set dst (AndL dst src)); |
|
8934 |
||
8935 |
format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} |
|
8936 |
opcode(0x0F, 0xB7); |
|
8937 |
ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); |
|
8938 |
ins_pipe(ialu_reg); |
|
8939 |
%} |
|
8940 |
||
8941 |
// And Register with Immediate |
|
8942 |
instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) |
|
8943 |
%{ |
|
8944 |
match(Set dst (AndL dst src)); |
|
8945 |
effect(KILL cr); |
|
8946 |
||
8947 |
format %{ "andq $dst, $src\t# long" %} |
|
8948 |
opcode(0x81, 0x04); /* Opcode 81 /4 */ |
|
8949 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
8950 |
ins_pipe(ialu_reg); |
|
8951 |
%} |
|
8952 |
||
8953 |
// And Register with Memory |
|
8954 |
instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) |
|
8955 |
%{ |
|
8956 |
match(Set dst (AndL dst (LoadL src))); |
|
8957 |
effect(KILL cr); |
|
8958 |
||
8959 |
ins_cost(125); |
|
8960 |
format %{ "andq $dst, $src\t# long" %} |
|
8961 |
opcode(0x23); |
|
8962 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
8963 |
ins_pipe(ialu_reg_mem); |
|
8964 |
%} |
|
8965 |
||
8966 |
// And Memory with Register |
|
8967 |
instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) |
|
8968 |
%{ |
|
8969 |
match(Set dst (StoreL dst (AndL (LoadL dst) src))); |
|
8970 |
effect(KILL cr); |
|
8971 |
||
8972 |
ins_cost(150); |
|
8973 |
format %{ "andq $dst, $src\t# long" %} |
|
8974 |
opcode(0x21); /* Opcode 21 /r */ |
|
8975 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
8976 |
ins_pipe(ialu_mem_reg); |
|
8977 |
%} |
|
8978 |
||
8979 |
// And Memory with Immediate |
|
8980 |
instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) |
|
8981 |
%{ |
|
8982 |
match(Set dst (StoreL dst (AndL (LoadL dst) src))); |
|
8983 |
effect(KILL cr); |
|
8984 |
||
8985 |
ins_cost(125); |
|
8986 |
format %{ "andq $dst, $src\t# long" %} |
|
8987 |
opcode(0x81, 0x4); /* Opcode 81 /4 id */ |
|
8988 |
ins_encode(REX_mem_wide(dst), OpcSE(src), |
|
8989 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
8990 |
ins_pipe(ialu_mem_imm); |
|
8991 |
%} |
|
8992 |
||
8993 |
// Or Instructions |
|
8994 |
// Or Register with Register |
|
8995 |
instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
8996 |
%{ |
|
8997 |
match(Set dst (OrL dst src)); |
|
8998 |
effect(KILL cr); |
|
8999 |
||
9000 |
format %{ "orq $dst, $src\t# long" %} |
|
9001 |
opcode(0x0B); |
|
9002 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
9003 |
ins_pipe(ialu_reg_reg); |
|
9004 |
%} |
|
9005 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9006 |
// Use any_RegP to match R15 (TLS register) without spilling. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9007 |
instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9008 |
match(Set dst (OrL dst (CastP2X src))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9009 |
effect(KILL cr); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9010 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9011 |
format %{ "orq $dst, $src\t# long" %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9012 |
opcode(0x0B); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9013 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9014 |
ins_pipe(ialu_reg_reg); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9015 |
%} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9016 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
9017 |
|
1 | 9018 |
// Or Register with Immediate |
9019 |
instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) |
|
9020 |
%{ |
|
9021 |
match(Set dst (OrL dst src)); |
|
9022 |
effect(KILL cr); |
|
9023 |
||
9024 |
format %{ "orq $dst, $src\t# long" %} |
|
9025 |
opcode(0x81, 0x01); /* Opcode 81 /1 id */ |
|
9026 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
9027 |
ins_pipe(ialu_reg); |
|
9028 |
%} |
|
9029 |
||
9030 |
// Or Register with Memory |
|
9031 |
instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) |
|
9032 |
%{ |
|
9033 |
match(Set dst (OrL dst (LoadL src))); |
|
9034 |
effect(KILL cr); |
|
9035 |
||
9036 |
ins_cost(125); |
|
9037 |
format %{ "orq $dst, $src\t# long" %} |
|
9038 |
opcode(0x0B); |
|
9039 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
9040 |
ins_pipe(ialu_reg_mem); |
|
9041 |
%} |
|
9042 |
||
9043 |
// Or Memory with Register |
|
9044 |
instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) |
|
9045 |
%{ |
|
9046 |
match(Set dst (StoreL dst (OrL (LoadL dst) src))); |
|
9047 |
effect(KILL cr); |
|
9048 |
||
9049 |
ins_cost(150); |
|
9050 |
format %{ "orq $dst, $src\t# long" %} |
|
9051 |
opcode(0x09); /* Opcode 09 /r */ |
|
9052 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
9053 |
ins_pipe(ialu_mem_reg); |
|
9054 |
%} |
|
9055 |
||
9056 |
// Or Memory with Immediate |
|
9057 |
instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) |
|
9058 |
%{ |
|
9059 |
match(Set dst (StoreL dst (OrL (LoadL dst) src))); |
|
9060 |
effect(KILL cr); |
|
9061 |
||
9062 |
ins_cost(125); |
|
9063 |
format %{ "orq $dst, $src\t# long" %} |
|
9064 |
opcode(0x81, 0x1); /* Opcode 81 /1 id */ |
|
9065 |
ins_encode(REX_mem_wide(dst), OpcSE(src), |
|
9066 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
9067 |
ins_pipe(ialu_mem_imm); |
|
9068 |
%} |
|
9069 |
||
9070 |
// Xor Instructions |
|
9071 |
// Xor Register with Register |
|
9072 |
instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
|
9073 |
%{ |
|
9074 |
match(Set dst (XorL dst src)); |
|
9075 |
effect(KILL cr); |
|
9076 |
||
9077 |
format %{ "xorq $dst, $src\t# long" %} |
|
9078 |
opcode(0x33); |
|
9079 |
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
9080 |
ins_pipe(ialu_reg_reg); |
|
9081 |
%} |
|
9082 |
||
1435 | 9083 |
// Xor Register with Immediate -1 |
9084 |
instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
9085 |
match(Set dst (XorL dst imm)); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
9086 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
9087 |
format %{ "notq $dst" %} |
1435 | 9088 |
ins_encode %{ |
9089 |
__ notq($dst$$Register); |
|
9090 |
%} |
|
9091 |
ins_pipe(ialu_reg); |
|
9092 |
%} |
|
9093 |
||
1 | 9094 |
// Xor Register with Immediate |
9095 |
instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) |
|
9096 |
%{ |
|
9097 |
match(Set dst (XorL dst src)); |
|
9098 |
effect(KILL cr); |
|
9099 |
||
9100 |
format %{ "xorq $dst, $src\t# long" %} |
|
9101 |
opcode(0x81, 0x06); /* Opcode 81 /6 id */ |
|
9102 |
ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); |
|
9103 |
ins_pipe(ialu_reg); |
|
9104 |
%} |
|
9105 |
||
9106 |
// Xor Register with Memory |
|
9107 |
instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) |
|
9108 |
%{ |
|
9109 |
match(Set dst (XorL dst (LoadL src))); |
|
9110 |
effect(KILL cr); |
|
9111 |
||
9112 |
ins_cost(125); |
|
9113 |
format %{ "xorq $dst, $src\t# long" %} |
|
9114 |
opcode(0x33); |
|
9115 |
ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); |
|
9116 |
ins_pipe(ialu_reg_mem); |
|
9117 |
%} |
|
9118 |
||
9119 |
// Xor Memory with Register |
|
9120 |
instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) |
|
9121 |
%{ |
|
9122 |
match(Set dst (StoreL dst (XorL (LoadL dst) src))); |
|
9123 |
effect(KILL cr); |
|
9124 |
||
9125 |
ins_cost(150); |
|
9126 |
format %{ "xorq $dst, $src\t# long" %} |
|
9127 |
opcode(0x31); /* Opcode 31 /r */ |
|
9128 |
ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); |
|
9129 |
ins_pipe(ialu_mem_reg); |
|
9130 |
%} |
|
9131 |
||
9132 |
// Xor Memory with Immediate |
|
9133 |
instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) |
|
9134 |
%{ |
|
9135 |
match(Set dst (StoreL dst (XorL (LoadL dst) src))); |
|
9136 |
effect(KILL cr); |
|
9137 |
||
9138 |
ins_cost(125); |
|
9139 |
format %{ "xorq $dst, $src\t# long" %} |
|
9140 |
opcode(0x81, 0x6); /* Opcode 81 /6 id */ |
|
9141 |
ins_encode(REX_mem_wide(dst), OpcSE(src), |
|
9142 |
RM_opc_mem(secondary, dst), Con8or32(src)); |
|
9143 |
ins_pipe(ialu_mem_imm); |
|
9144 |
%} |
|
9145 |
||
9146 |
// Convert Int to Boolean |
|
9147 |
instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) |
|
9148 |
%{ |
|
9149 |
match(Set dst (Conv2B src)); |
|
9150 |
effect(KILL cr); |
|
9151 |
||
9152 |
format %{ "testl $src, $src\t# ci2b\n\t" |
|
9153 |
"setnz $dst\n\t" |
|
9154 |
"movzbl $dst, $dst" %} |
|
9155 |
ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl |
|
9156 |
setNZ_reg(dst), |
|
9157 |
REX_reg_breg(dst, dst), // movzbl |
|
9158 |
Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); |
|
9159 |
ins_pipe(pipe_slow); // XXX |
|
9160 |
%} |
|
9161 |
||
9162 |
// Convert Pointer to Boolean |
|
9163 |
instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) |
|
9164 |
%{ |
|
9165 |
match(Set dst (Conv2B src)); |
|
9166 |
effect(KILL cr); |
|
9167 |
||
9168 |
format %{ "testq $src, $src\t# cp2b\n\t" |
|
9169 |
"setnz $dst\n\t" |
|
9170 |
"movzbl $dst, $dst" %} |
|
9171 |
ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq |
|
9172 |
setNZ_reg(dst), |
|
9173 |
REX_reg_breg(dst, dst), // movzbl |
|
9174 |
Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); |
|
9175 |
ins_pipe(pipe_slow); // XXX |
|
9176 |
%} |
|
9177 |
||
9178 |
instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) |
|
9179 |
%{ |
|
9180 |
match(Set dst (CmpLTMask p q)); |
|
9181 |
effect(KILL cr); |
|
9182 |
||
9183 |
ins_cost(400); // XXX |
|
9184 |
format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
|
9185 |
"setlt $dst\n\t" |
|
9186 |
"movzbl $dst, $dst\n\t" |
|
9187 |
"negl $dst" %} |
|
9188 |
ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl |
|
9189 |
setLT_reg(dst), |
|
9190 |
REX_reg_breg(dst, dst), // movzbl |
|
9191 |
Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), |
|
9192 |
neg_reg(dst)); |
|
9193 |
ins_pipe(pipe_slow); |
|
9194 |
%} |
|
9195 |
||
9196 |
instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) |
|
9197 |
%{ |
|
9198 |
match(Set dst (CmpLTMask dst zero)); |
|
9199 |
effect(KILL cr); |
|
9200 |
||
9201 |
ins_cost(100); // XXX |
|
9202 |
format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
|
9203 |
opcode(0xC1, 0x7); /* C1 /7 ib */ |
|
9204 |
ins_encode(reg_opc_imm(dst, 0x1F)); |
|
9205 |
ins_pipe(ialu_reg); |
|
9206 |
%} |
|
9207 |
||
9208 |
||
9961
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9209 |
instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr) |
1 | 9210 |
%{ |
9211 |
match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
|
9212 |
effect(TEMP tmp, KILL cr); |
|
9213 |
||
9214 |
ins_cost(400); // XXX |
|
9215 |
format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" |
|
9216 |
"sbbl $tmp, $tmp\n\t" |
|
9217 |
"andl $tmp, $y\n\t" |
|
9218 |
"addl $p, $tmp" %} |
|
9961
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9219 |
ins_encode %{ |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9220 |
Register Rp = $p$$Register; |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9221 |
Register Rq = $q$$Register; |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9222 |
Register Ry = $y$$Register; |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9223 |
Register Rt = $tmp$$Register; |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9224 |
__ subl(Rp, Rq); |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9225 |
__ sbbl(Rt, Rt); |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9226 |
__ andl(Rt, Ry); |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9227 |
__ addl(Rp, Rt); |
5d84243241ac
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
8871
diff
changeset
|
9228 |
%} |
1 | 9229 |
ins_pipe(pipe_cmplt); |
9230 |
%} |
|
9231 |
||
9232 |
//---------- FP Instructions------------------------------------------------ |
|
9233 |
||
9234 |
instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) |
|
9235 |
%{ |
|
9236 |
match(Set cr (CmpF src1 src2)); |
|
9237 |
||
9238 |
ins_cost(145); |
|
9239 |
format %{ "ucomiss $src1, $src2\n\t" |
|
9240 |
"jnp,s exit\n\t" |
|
9241 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9242 |
"andq [rsp], #0xffffff2b\n\t" |
|
9243 |
"popfq\n" |
|
11427 | 9244 |
"exit:" %} |
9245 |
ins_encode %{ |
|
9246 |
__ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
9247 |
emit_cmpfp_fixup(_masm); |
|
9248 |
%} |
|
1 | 9249 |
ins_pipe(pipe_slow); |
9250 |
%} |
|
9251 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9252 |
instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9253 |
match(Set cr (CmpF src1 src2)); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9254 |
|
11427 | 9255 |
ins_cost(100); |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9256 |
format %{ "ucomiss $src1, $src2" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9257 |
ins_encode %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9258 |
__ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9259 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9260 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9261 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9262 |
|
1 | 9263 |
instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
9264 |
%{ |
|
9265 |
match(Set cr (CmpF src1 (LoadF src2))); |
|
9266 |
||
9267 |
ins_cost(145); |
|
9268 |
format %{ "ucomiss $src1, $src2\n\t" |
|
9269 |
"jnp,s exit\n\t" |
|
9270 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9271 |
"andq [rsp], #0xffffff2b\n\t" |
|
9272 |
"popfq\n" |
|
11427 | 9273 |
"exit:" %} |
9274 |
ins_encode %{ |
|
9275 |
__ ucomiss($src1$$XMMRegister, $src2$$Address); |
|
9276 |
emit_cmpfp_fixup(_masm); |
|
9277 |
%} |
|
1 | 9278 |
ins_pipe(pipe_slow); |
9279 |
%} |
|
9280 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9281 |
instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9282 |
match(Set cr (CmpF src1 (LoadF src2))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9283 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9284 |
ins_cost(100); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9285 |
format %{ "ucomiss $src1, $src2" %} |
11427 | 9286 |
ins_encode %{ |
9287 |
__ ucomiss($src1$$XMMRegister, $src2$$Address); |
|
9288 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9289 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9290 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9291 |
|
7433 | 9292 |
instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
9293 |
match(Set cr (CmpF src con)); |
|
1 | 9294 |
|
9295 |
ins_cost(145); |
|
7433 | 9296 |
format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
1 | 9297 |
"jnp,s exit\n\t" |
9298 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9299 |
"andq [rsp], #0xffffff2b\n\t" |
|
9300 |
"popfq\n" |
|
11427 | 9301 |
"exit:" %} |
7433 | 9302 |
ins_encode %{ |
9303 |
__ ucomiss($src$$XMMRegister, $constantaddress($con)); |
|
10006 | 9304 |
emit_cmpfp_fixup(_masm); |
7433 | 9305 |
%} |
9306 |
ins_pipe(pipe_slow); |
|
9307 |
%} |
|
9308 |
||
9309 |
instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ |
|
9310 |
match(Set cr (CmpF src con)); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9311 |
ins_cost(100); |
7433 | 9312 |
format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
9313 |
ins_encode %{ |
|
9314 |
__ ucomiss($src$$XMMRegister, $constantaddress($con)); |
|
9315 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9316 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9317 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9318 |
|
1 | 9319 |
instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
9320 |
%{ |
|
9321 |
match(Set cr (CmpD src1 src2)); |
|
9322 |
||
9323 |
ins_cost(145); |
|
9324 |
format %{ "ucomisd $src1, $src2\n\t" |
|
9325 |
"jnp,s exit\n\t" |
|
9326 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9327 |
"andq [rsp], #0xffffff2b\n\t" |
|
9328 |
"popfq\n" |
|
11427 | 9329 |
"exit:" %} |
9330 |
ins_encode %{ |
|
9331 |
__ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
9332 |
emit_cmpfp_fixup(_masm); |
|
9333 |
%} |
|
1 | 9334 |
ins_pipe(pipe_slow); |
9335 |
%} |
|
9336 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9337 |
instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9338 |
match(Set cr (CmpD src1 src2)); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9339 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9340 |
ins_cost(100); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9341 |
format %{ "ucomisd $src1, $src2 test" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9342 |
ins_encode %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9343 |
__ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9344 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9345 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9346 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9347 |
|
1 | 9348 |
instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
9349 |
%{ |
|
9350 |
match(Set cr (CmpD src1 (LoadD src2))); |
|
9351 |
||
9352 |
ins_cost(145); |
|
9353 |
format %{ "ucomisd $src1, $src2\n\t" |
|
9354 |
"jnp,s exit\n\t" |
|
9355 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9356 |
"andq [rsp], #0xffffff2b\n\t" |
|
9357 |
"popfq\n" |
|
11427 | 9358 |
"exit:" %} |
9359 |
ins_encode %{ |
|
9360 |
__ ucomisd($src1$$XMMRegister, $src2$$Address); |
|
9361 |
emit_cmpfp_fixup(_masm); |
|
9362 |
%} |
|
1 | 9363 |
ins_pipe(pipe_slow); |
9364 |
%} |
|
9365 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9366 |
instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9367 |
match(Set cr (CmpD src1 (LoadD src2))); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9368 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9369 |
ins_cost(100); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9370 |
format %{ "ucomisd $src1, $src2" %} |
11427 | 9371 |
ins_encode %{ |
9372 |
__ ucomisd($src1$$XMMRegister, $src2$$Address); |
|
9373 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9374 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9375 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9376 |
|
7433 | 9377 |
instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
9378 |
match(Set cr (CmpD src con)); |
|
1 | 9379 |
|
9380 |
ins_cost(145); |
|
7433 | 9381 |
format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
1 | 9382 |
"jnp,s exit\n\t" |
9383 |
"pushfq\t# saw NaN, set CF\n\t" |
|
9384 |
"andq [rsp], #0xffffff2b\n\t" |
|
9385 |
"popfq\n" |
|
11427 | 9386 |
"exit:" %} |
7433 | 9387 |
ins_encode %{ |
9388 |
__ ucomisd($src$$XMMRegister, $constantaddress($con)); |
|
10006 | 9389 |
emit_cmpfp_fixup(_masm); |
7433 | 9390 |
%} |
9391 |
ins_pipe(pipe_slow); |
|
9392 |
%} |
|
9393 |
||
9394 |
instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ |
|
9395 |
match(Set cr (CmpD src con)); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9396 |
ins_cost(100); |
7433 | 9397 |
format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
9398 |
ins_encode %{ |
|
9399 |
__ ucomisd($src$$XMMRegister, $constantaddress($con)); |
|
9400 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9401 |
ins_pipe(pipe_slow); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9402 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
9403 |
|
1 | 9404 |
// Compare into -1,0,1 |
9405 |
instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) |
|
9406 |
%{ |
|
9407 |
match(Set dst (CmpF3 src1 src2)); |
|
9408 |
effect(KILL cr); |
|
9409 |
||
9410 |
ins_cost(275); |
|
9411 |
format %{ "ucomiss $src1, $src2\n\t" |
|
9412 |
"movl $dst, #-1\n\t" |
|
9413 |
"jp,s done\n\t" |
|
9414 |
"jb,s done\n\t" |
|
9415 |
"setne $dst\n\t" |
|
9416 |
"movzbl $dst, $dst\n" |
|
9417 |
"done:" %} |
|
11427 | 9418 |
ins_encode %{ |
9419 |
__ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
9420 |
emit_cmpfp3(_masm, $dst$$Register); |
|
9421 |
%} |
|
1 | 9422 |
ins_pipe(pipe_slow); |
9423 |
%} |
|
9424 |
||
9425 |
// Compare into -1,0,1 |
|
9426 |
instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) |
|
9427 |
%{ |
|
9428 |
match(Set dst (CmpF3 src1 (LoadF src2))); |
|
9429 |
effect(KILL cr); |
|
9430 |
||
9431 |
ins_cost(275); |
|
9432 |
format %{ "ucomiss $src1, $src2\n\t" |
|
9433 |
"movl $dst, #-1\n\t" |
|
9434 |
"jp,s done\n\t" |
|
9435 |
"jb,s done\n\t" |
|
9436 |
"setne $dst\n\t" |
|
9437 |
"movzbl $dst, $dst\n" |
|
9438 |
"done:" %} |
|
11427 | 9439 |
ins_encode %{ |
9440 |
__ ucomiss($src1$$XMMRegister, $src2$$Address); |
|
9441 |
emit_cmpfp3(_masm, $dst$$Register); |
|
9442 |
%} |
|
1 | 9443 |
ins_pipe(pipe_slow); |
9444 |
%} |
|
9445 |
||
9446 |
// Compare into -1,0,1 |
|
7433 | 9447 |
instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
9448 |
match(Set dst (CmpF3 src con)); |
|
1 | 9449 |
effect(KILL cr); |
9450 |
||
9451 |
ins_cost(275); |
|
7433 | 9452 |
format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
1 | 9453 |
"movl $dst, #-1\n\t" |
9454 |
"jp,s done\n\t" |
|
9455 |
"jb,s done\n\t" |
|
9456 |
"setne $dst\n\t" |
|
9457 |
"movzbl $dst, $dst\n" |
|
9458 |
"done:" %} |
|
7433 | 9459 |
ins_encode %{ |
9460 |
__ ucomiss($src$$XMMRegister, $constantaddress($con)); |
|
11427 | 9461 |
emit_cmpfp3(_masm, $dst$$Register); |
7433 | 9462 |
%} |
1 | 9463 |
ins_pipe(pipe_slow); |
9464 |
%} |
|
9465 |
||
9466 |
// Compare into -1,0,1 |
|
9467 |
instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) |
|
9468 |
%{ |
|
9469 |
match(Set dst (CmpD3 src1 src2)); |
|
9470 |
effect(KILL cr); |
|
9471 |
||
9472 |
ins_cost(275); |
|
9473 |
format %{ "ucomisd $src1, $src2\n\t" |
|
9474 |
"movl $dst, #-1\n\t" |
|
9475 |
"jp,s done\n\t" |
|
9476 |
"jb,s done\n\t" |
|
9477 |
"setne $dst\n\t" |
|
9478 |
"movzbl $dst, $dst\n" |
|
9479 |
"done:" %} |
|
11427 | 9480 |
ins_encode %{ |
9481 |
__ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
9482 |
emit_cmpfp3(_masm, $dst$$Register); |
|
9483 |
%} |
|
1 | 9484 |
ins_pipe(pipe_slow); |
9485 |
%} |
|
9486 |
||
9487 |
// Compare into -1,0,1 |
|
9488 |
instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) |
|
9489 |
%{ |
|
9490 |
match(Set dst (CmpD3 src1 (LoadD src2))); |
|
9491 |
effect(KILL cr); |
|
9492 |
||
9493 |
ins_cost(275); |
|
9494 |
format %{ "ucomisd $src1, $src2\n\t" |
|
9495 |
"movl $dst, #-1\n\t" |
|
9496 |
"jp,s done\n\t" |
|
9497 |
"jb,s done\n\t" |
|
9498 |
"setne $dst\n\t" |
|
9499 |
"movzbl $dst, $dst\n" |
|
9500 |
"done:" %} |
|
11427 | 9501 |
ins_encode %{ |
9502 |
__ ucomisd($src1$$XMMRegister, $src2$$Address); |
|
9503 |
emit_cmpfp3(_masm, $dst$$Register); |
|
9504 |
%} |
|
1 | 9505 |
ins_pipe(pipe_slow); |
9506 |
%} |
|
9507 |
||
9508 |
// Compare into -1,0,1 |
|
7433 | 9509 |
instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
9510 |
match(Set dst (CmpD3 src con)); |
|
1 | 9511 |
effect(KILL cr); |
9512 |
||
9513 |
ins_cost(275); |
|
7433 | 9514 |
format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
1 | 9515 |
"movl $dst, #-1\n\t" |
9516 |
"jp,s done\n\t" |
|
9517 |
"jb,s done\n\t" |
|
9518 |
"setne $dst\n\t" |
|
9519 |
"movzbl $dst, $dst\n" |
|
9520 |
"done:" %} |
|
7433 | 9521 |
ins_encode %{ |
9522 |
__ ucomisd($src$$XMMRegister, $constantaddress($con)); |
|
11427 | 9523 |
emit_cmpfp3(_masm, $dst$$Register); |
7433 | 9524 |
%} |
1 | 9525 |
ins_pipe(pipe_slow); |
9526 |
%} |
|
9527 |
||
9528 |
// -----------Trig and Trancendental Instructions------------------------------ |
|
9529 |
instruct cosD_reg(regD dst) %{ |
|
9530 |
match(Set dst (CosD dst)); |
|
9531 |
||
9532 |
format %{ "dcos $dst\n\t" %} |
|
9533 |
opcode(0xD9, 0xFF); |
|
9534 |
ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); |
|
9535 |
ins_pipe( pipe_slow ); |
|
9536 |
%} |
|
9537 |
||
9538 |
instruct sinD_reg(regD dst) %{ |
|
9539 |
match(Set dst (SinD dst)); |
|
9540 |
||
9541 |
format %{ "dsin $dst\n\t" %} |
|
9542 |
opcode(0xD9, 0xFE); |
|
9543 |
ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); |
|
9544 |
ins_pipe( pipe_slow ); |
|
9545 |
%} |
|
9546 |
||
9547 |
instruct tanD_reg(regD dst) %{ |
|
9548 |
match(Set dst (TanD dst)); |
|
9549 |
||
9550 |
format %{ "dtan $dst\n\t" %} |
|
9551 |
ins_encode( Push_SrcXD(dst), |
|
9552 |
Opcode(0xD9), Opcode(0xF2), //fptan |
|
9553 |
Opcode(0xDD), Opcode(0xD8), //fstp st |
|
9554 |
Push_ResultXD(dst) ); |
|
9555 |
ins_pipe( pipe_slow ); |
|
9556 |
%} |
|
9557 |
||
9558 |
instruct log10D_reg(regD dst) %{ |
|
9559 |
// The source and result Double operands in XMM registers |
|
9560 |
match(Set dst (Log10D dst)); |
|
9561 |
// fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number |
|
9562 |
// fyl2x ; compute log_10(2) * log_2(x) |
|
9563 |
format %{ "fldlg2\t\t\t#Log10\n\t" |
|
9564 |
"fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" |
|
9565 |
%} |
|
9566 |
ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 |
|
9567 |
Push_SrcXD(dst), |
|
9568 |
Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
9569 |
Push_ResultXD(dst)); |
|
9570 |
||
9571 |
ins_pipe( pipe_slow ); |
|
9572 |
%} |
|
9573 |
||
9574 |
instruct logD_reg(regD dst) %{ |
|
9575 |
// The source and result Double operands in XMM registers |
|
9576 |
match(Set dst (LogD dst)); |
|
9577 |
// fldln2 ; push log_e(2) on the FPU stack; full 80-bit number |
|
9578 |
// fyl2x ; compute log_e(2) * log_2(x) |
|
9579 |
format %{ "fldln2\t\t\t#Log_e\n\t" |
|
9580 |
"fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" |
|
9581 |
%} |
|
9582 |
ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 |
|
9583 |
Push_SrcXD(dst), |
|
9584 |
Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
9585 |
Push_ResultXD(dst)); |
|
9586 |
ins_pipe( pipe_slow ); |
|
9587 |
%} |
|
9588 |
||
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9589 |
instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9590 |
match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9591 |
effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9592 |
format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9593 |
ins_encode %{ |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9594 |
__ subptr(rsp, 8); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9595 |
__ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9596 |
__ fld_d(Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9597 |
__ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9598 |
__ fld_d(Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9599 |
__ fast_pow(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9600 |
__ fstp_d(Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9601 |
__ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9602 |
__ addptr(rsp, 8); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9603 |
%} |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9604 |
ins_pipe( pipe_slow ); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9605 |
%} |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9606 |
|
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9607 |
instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9608 |
match(Set dst (ExpD src)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9609 |
effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9610 |
format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9611 |
ins_encode %{ |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9612 |
__ subptr(rsp, 8); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9613 |
__ movdbl(Address(rsp, 0), $src$$XMMRegister); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9614 |
__ fld_d(Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9615 |
__ fast_exp(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9616 |
__ fstp_d(Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9617 |
__ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9618 |
__ addptr(rsp, 8); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9619 |
%} |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9620 |
ins_pipe( pipe_slow ); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
12268
diff
changeset
|
9621 |
%} |
1 | 9622 |
|
9623 |
//----------Arithmetic Conversion Instructions--------------------------------- |
|
9624 |
||
9625 |
instruct roundFloat_nop(regF dst) |
|
9626 |
%{ |
|
9627 |
match(Set dst (RoundFloat dst)); |
|
9628 |
||
9629 |
ins_cost(0); |
|
9630 |
ins_encode(); |
|
9631 |
ins_pipe(empty); |
|
9632 |
%} |
|
9633 |
||
9634 |
instruct roundDouble_nop(regD dst) |
|
9635 |
%{ |
|
9636 |
match(Set dst (RoundDouble dst)); |
|
9637 |
||
9638 |
ins_cost(0); |
|
9639 |
ins_encode(); |
|
9640 |
ins_pipe(empty); |
|
9641 |
%} |
|
9642 |
||
9643 |
instruct convF2D_reg_reg(regD dst, regF src) |
|
9644 |
%{ |
|
9645 |
match(Set dst (ConvF2D src)); |
|
9646 |
||
9647 |
format %{ "cvtss2sd $dst, $src" %} |
|
11427 | 9648 |
ins_encode %{ |
9649 |
__ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); |
|
9650 |
%} |
|
1 | 9651 |
ins_pipe(pipe_slow); // XXX |
9652 |
%} |
|
9653 |
||
9654 |
instruct convF2D_reg_mem(regD dst, memory src) |
|
9655 |
%{ |
|
9656 |
match(Set dst (ConvF2D (LoadF src))); |
|
9657 |
||
9658 |
format %{ "cvtss2sd $dst, $src" %} |
|
11427 | 9659 |
ins_encode %{ |
9660 |
__ cvtss2sd ($dst$$XMMRegister, $src$$Address); |
|
9661 |
%} |
|
1 | 9662 |
ins_pipe(pipe_slow); // XXX |
9663 |
%} |
|
9664 |
||
9665 |
instruct convD2F_reg_reg(regF dst, regD src) |
|
9666 |
%{ |
|
9667 |
match(Set dst (ConvD2F src)); |
|
9668 |
||
9669 |
format %{ "cvtsd2ss $dst, $src" %} |
|
11427 | 9670 |
ins_encode %{ |
9671 |
__ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); |
|
9672 |
%} |
|
1 | 9673 |
ins_pipe(pipe_slow); // XXX |
9674 |
%} |
|
9675 |
||
9676 |
instruct convD2F_reg_mem(regF dst, memory src) |
|
9677 |
%{ |
|
9678 |
match(Set dst (ConvD2F (LoadD src))); |
|
9679 |
||
9680 |
format %{ "cvtsd2ss $dst, $src" %} |
|
11427 | 9681 |
ins_encode %{ |
9682 |
__ cvtsd2ss ($dst$$XMMRegister, $src$$Address); |
|
9683 |
%} |
|
1 | 9684 |
ins_pipe(pipe_slow); // XXX |
9685 |
%} |
|
9686 |
||
9687 |
// XXX do mem variants |
|
9688 |
instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) |
|
9689 |
%{ |
|
9690 |
match(Set dst (ConvF2I src)); |
|
9691 |
effect(KILL cr); |
|
9692 |
||
9693 |
format %{ "cvttss2sil $dst, $src\t# f2i\n\t" |
|
9694 |
"cmpl $dst, #0x80000000\n\t" |
|
9695 |
"jne,s done\n\t" |
|
9696 |
"subq rsp, #8\n\t" |
|
9697 |
"movss [rsp], $src\n\t" |
|
9698 |
"call f2i_fixup\n\t" |
|
9699 |
"popq $dst\n" |
|
9700 |
"done: "%} |
|
11427 | 9701 |
ins_encode %{ |
9702 |
Label done; |
|
9703 |
__ cvttss2sil($dst$$Register, $src$$XMMRegister); |
|
9704 |
__ cmpl($dst$$Register, 0x80000000); |
|
9705 |
__ jccb(Assembler::notEqual, done); |
|
9706 |
__ subptr(rsp, 8); |
|
9707 |
__ movflt(Address(rsp, 0), $src$$XMMRegister); |
|
9708 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); |
|
9709 |
__ pop($dst$$Register); |
|
9710 |
__ bind(done); |
|
9711 |
%} |
|
1 | 9712 |
ins_pipe(pipe_slow); |
9713 |
%} |
|
9714 |
||
9715 |
instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) |
|
9716 |
%{ |
|
9717 |
match(Set dst (ConvF2L src)); |
|
9718 |
effect(KILL cr); |
|
9719 |
||
9720 |
format %{ "cvttss2siq $dst, $src\t# f2l\n\t" |
|
9721 |
"cmpq $dst, [0x8000000000000000]\n\t" |
|
9722 |
"jne,s done\n\t" |
|
9723 |
"subq rsp, #8\n\t" |
|
9724 |
"movss [rsp], $src\n\t" |
|
9725 |
"call f2l_fixup\n\t" |
|
9726 |
"popq $dst\n" |
|
9727 |
"done: "%} |
|
11427 | 9728 |
ins_encode %{ |
9729 |
Label done; |
|
9730 |
__ cvttss2siq($dst$$Register, $src$$XMMRegister); |
|
9731 |
__ cmp64($dst$$Register, |
|
9732 |
ExternalAddress((address) StubRoutines::x86::double_sign_flip())); |
|
9733 |
__ jccb(Assembler::notEqual, done); |
|
9734 |
__ subptr(rsp, 8); |
|
9735 |
__ movflt(Address(rsp, 0), $src$$XMMRegister); |
|
9736 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); |
|
9737 |
__ pop($dst$$Register); |
|
9738 |
__ bind(done); |
|
9739 |
%} |
|
1 | 9740 |
ins_pipe(pipe_slow); |
9741 |
%} |
|
9742 |
||
9743 |
instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) |
|
9744 |
%{ |
|
9745 |
match(Set dst (ConvD2I src)); |
|
9746 |
effect(KILL cr); |
|
9747 |
||
9748 |
format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" |
|
9749 |
"cmpl $dst, #0x80000000\n\t" |
|
9750 |
"jne,s done\n\t" |
|
9751 |
"subq rsp, #8\n\t" |
|
9752 |
"movsd [rsp], $src\n\t" |
|
9753 |
"call d2i_fixup\n\t" |
|
9754 |
"popq $dst\n" |
|
9755 |
"done: "%} |
|
11427 | 9756 |
ins_encode %{ |
9757 |
Label done; |
|
9758 |
__ cvttsd2sil($dst$$Register, $src$$XMMRegister); |
|
9759 |
__ cmpl($dst$$Register, 0x80000000); |
|
9760 |
__ jccb(Assembler::notEqual, done); |
|
9761 |
__ subptr(rsp, 8); |
|
9762 |
__ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
9763 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); |
|
9764 |
__ pop($dst$$Register); |
|
9765 |
__ bind(done); |
|
9766 |
%} |
|
1 | 9767 |
ins_pipe(pipe_slow); |
9768 |
%} |
|
9769 |
||
9770 |
instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) |
|
9771 |
%{ |
|
9772 |
match(Set dst (ConvD2L src)); |
|
9773 |
effect(KILL cr); |
|
9774 |
||
9775 |
format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" |
|
9776 |
"cmpq $dst, [0x8000000000000000]\n\t" |
|
9777 |
"jne,s done\n\t" |
|
9778 |
"subq rsp, #8\n\t" |
|
9779 |
"movsd [rsp], $src\n\t" |
|
9780 |
"call d2l_fixup\n\t" |
|
9781 |
"popq $dst\n" |
|
9782 |
"done: "%} |
|
11427 | 9783 |
ins_encode %{ |
9784 |
Label done; |
|
9785 |
__ cvttsd2siq($dst$$Register, $src$$XMMRegister); |
|
9786 |
__ cmp64($dst$$Register, |
|
9787 |
ExternalAddress((address) StubRoutines::x86::double_sign_flip())); |
|
9788 |
__ jccb(Assembler::notEqual, done); |
|
9789 |
__ subptr(rsp, 8); |
|
9790 |
__ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
9791 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); |
|
9792 |
__ pop($dst$$Register); |
|
9793 |
__ bind(done); |
|
9794 |
%} |
|
1 | 9795 |
ins_pipe(pipe_slow); |
9796 |
%} |
|
9797 |
||
9798 |
instruct convI2F_reg_reg(regF dst, rRegI src) |
|
9799 |
%{ |
|
244 | 9800 |
predicate(!UseXmmI2F); |
1 | 9801 |
match(Set dst (ConvI2F src)); |
9802 |
||
9803 |
format %{ "cvtsi2ssl $dst, $src\t# i2f" %} |
|
11427 | 9804 |
ins_encode %{ |
9805 |
__ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); |
|
9806 |
%} |
|
1 | 9807 |
ins_pipe(pipe_slow); // XXX |
9808 |
%} |
|
9809 |
||
9810 |
instruct convI2F_reg_mem(regF dst, memory src) |
|
9811 |
%{ |
|
9812 |
match(Set dst (ConvI2F (LoadI src))); |
|
9813 |
||
9814 |
format %{ "cvtsi2ssl $dst, $src\t# i2f" %} |
|
11427 | 9815 |
ins_encode %{ |
9816 |
__ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); |
|
9817 |
%} |
|
1 | 9818 |
ins_pipe(pipe_slow); // XXX |
9819 |
%} |
|
9820 |
||
9821 |
instruct convI2D_reg_reg(regD dst, rRegI src) |
|
9822 |
%{ |
|
244 | 9823 |
predicate(!UseXmmI2D); |
1 | 9824 |
match(Set dst (ConvI2D src)); |
9825 |
||
9826 |
format %{ "cvtsi2sdl $dst, $src\t# i2d" %} |
|
11427 | 9827 |
ins_encode %{ |
9828 |
__ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); |
|
9829 |
%} |
|
1 | 9830 |
ins_pipe(pipe_slow); // XXX |
9831 |
%} |
|
9832 |
||
9833 |
instruct convI2D_reg_mem(regD dst, memory src) |
|
9834 |
%{ |
|
9835 |
match(Set dst (ConvI2D (LoadI src))); |
|
9836 |
||
9837 |
format %{ "cvtsi2sdl $dst, $src\t# i2d" %} |
|
11427 | 9838 |
ins_encode %{ |
9839 |
__ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); |
|
9840 |
%} |
|
1 | 9841 |
ins_pipe(pipe_slow); // XXX |
9842 |
%} |
|
9843 |
||
244 | 9844 |
instruct convXI2F_reg(regF dst, rRegI src) |
9845 |
%{ |
|
9846 |
predicate(UseXmmI2F); |
|
9847 |
match(Set dst (ConvI2F src)); |
|
9848 |
||
9849 |
format %{ "movdl $dst, $src\n\t" |
|
9850 |
"cvtdq2psl $dst, $dst\t# i2f" %} |
|
9851 |
ins_encode %{ |
|
9852 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
9853 |
__ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
|
9854 |
%} |
|
9855 |
ins_pipe(pipe_slow); // XXX |
|
9856 |
%} |
|
9857 |
||
9858 |
instruct convXI2D_reg(regD dst, rRegI src) |
|
9859 |
%{ |
|
9860 |
predicate(UseXmmI2D); |
|
9861 |
match(Set dst (ConvI2D src)); |
|
9862 |
||
9863 |
format %{ "movdl $dst, $src\n\t" |
|
9864 |
"cvtdq2pdl $dst, $dst\t# i2d" %} |
|
9865 |
ins_encode %{ |
|
9866 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
9867 |
__ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
|
9868 |
%} |
|
9869 |
ins_pipe(pipe_slow); // XXX |
|
9870 |
%} |
|
9871 |
||
1 | 9872 |
instruct convL2F_reg_reg(regF dst, rRegL src) |
9873 |
%{ |
|
9874 |
match(Set dst (ConvL2F src)); |
|
9875 |
||
9876 |
format %{ "cvtsi2ssq $dst, $src\t# l2f" %} |
|
11427 | 9877 |
ins_encode %{ |
9878 |
__ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); |
|
9879 |
%} |
|
1 | 9880 |
ins_pipe(pipe_slow); // XXX |
9881 |
%} |
|
9882 |
||
9883 |
instruct convL2F_reg_mem(regF dst, memory src) |
|
9884 |
%{ |
|
9885 |
match(Set dst (ConvL2F (LoadL src))); |
|
9886 |
||
9887 |
format %{ "cvtsi2ssq $dst, $src\t# l2f" %} |
|
11427 | 9888 |
ins_encode %{ |
9889 |
__ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); |
|
9890 |
%} |
|
1 | 9891 |
ins_pipe(pipe_slow); // XXX |
9892 |
%} |
|
9893 |
||
9894 |
instruct convL2D_reg_reg(regD dst, rRegL src) |
|
9895 |
%{ |
|
9896 |
match(Set dst (ConvL2D src)); |
|
9897 |
||
9898 |
format %{ "cvtsi2sdq $dst, $src\t# l2d" %} |
|
11427 | 9899 |
ins_encode %{ |
9900 |
__ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); |
|
9901 |
%} |
|
1 | 9902 |
ins_pipe(pipe_slow); // XXX |
9903 |
%} |
|
9904 |
||
9905 |
instruct convL2D_reg_mem(regD dst, memory src) |
|
9906 |
%{ |
|
9907 |
match(Set dst (ConvL2D (LoadL src))); |
|
9908 |
||
9909 |
format %{ "cvtsi2sdq $dst, $src\t# l2d" %} |
|
11427 | 9910 |
ins_encode %{ |
9911 |
__ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); |
|
9912 |
%} |
|
1 | 9913 |
ins_pipe(pipe_slow); // XXX |
9914 |
%} |
|
9915 |
||
9916 |
instruct convI2L_reg_reg(rRegL dst, rRegI src) |
|
9917 |
%{ |
|
9918 |
match(Set dst (ConvI2L src)); |
|
9919 |
||
9920 |
ins_cost(125); |
|
9921 |
format %{ "movslq $dst, $src\t# i2l" %} |
|
3177 | 9922 |
ins_encode %{ |
9923 |
__ movslq($dst$$Register, $src$$Register); |
|
9924 |
%} |
|
1 | 9925 |
ins_pipe(ialu_reg_reg); |
9926 |
%} |
|
9927 |
||
9928 |
// instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) |
|
9929 |
// %{ |
|
9930 |
// match(Set dst (ConvI2L src)); |
|
9931 |
// // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && |
|
9932 |
// // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); |
|
9933 |
// predicate(((const TypeNode*) n)->type()->is_long()->_hi == |
|
9934 |
// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && |
|
9935 |
// ((const TypeNode*) n)->type()->is_long()->_lo == |
|
9936 |
// (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); |
|
9937 |
||
9938 |
// format %{ "movl $dst, $src\t# unsigned i2l" %} |
|
9939 |
// ins_encode(enc_copy(dst, src)); |
|
9940 |
// // opcode(0x63); // needs REX.W |
|
9941 |
// // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); |
|
9942 |
// ins_pipe(ialu_reg_reg); |
|
9943 |
// %} |
|
9944 |
||
9945 |
// Zero-extend convert int to long |
|
9946 |
instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) |
|
9947 |
%{ |
|
9948 |
match(Set dst (AndL (ConvI2L src) mask)); |
|
9949 |
||
9950 |
format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} |
|
11427 | 9951 |
ins_encode %{ |
9952 |
if ($dst$$reg != $src$$reg) { |
|
9953 |
__ movl($dst$$Register, $src$$Register); |
|
9954 |
} |
|
9955 |
%} |
|
1 | 9956 |
ins_pipe(ialu_reg_reg); |
9957 |
%} |
|
9958 |
||
9959 |
// Zero-extend convert int to long |
|
9960 |
instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) |
|
9961 |
%{ |
|
9962 |
match(Set dst (AndL (ConvI2L (LoadI src)) mask)); |
|
9963 |
||
9964 |
format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} |
|
11427 | 9965 |
ins_encode %{ |
9966 |
__ movl($dst$$Register, $src$$Address); |
|
9967 |
%} |
|
1 | 9968 |
ins_pipe(ialu_reg_mem); |
9969 |
%} |
|
9970 |
||
9971 |
instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) |
|
9972 |
%{ |
|
9973 |
match(Set dst (AndL src mask)); |
|
9974 |
||
9975 |
format %{ "movl $dst, $src\t# zero-extend long" %} |
|
11427 | 9976 |
ins_encode %{ |
9977 |
__ movl($dst$$Register, $src$$Register); |
|
9978 |
%} |
|
1 | 9979 |
ins_pipe(ialu_reg_reg); |
9980 |
%} |
|
9981 |
||
9982 |
instruct convL2I_reg_reg(rRegI dst, rRegL src) |
|
9983 |
%{ |
|
9984 |
match(Set dst (ConvL2I src)); |
|
9985 |
||
9986 |
format %{ "movl $dst, $src\t# l2i" %} |
|
11427 | 9987 |
ins_encode %{ |
9988 |
__ movl($dst$$Register, $src$$Register); |
|
9989 |
%} |
|
1 | 9990 |
ins_pipe(ialu_reg_reg); |
9991 |
%} |
|
9992 |
||
9993 |
||
9994 |
instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
|
9995 |
match(Set dst (MoveF2I src)); |
|
9996 |
effect(DEF dst, USE src); |
|
9997 |
||
9998 |
ins_cost(125); |
|
9999 |
format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} |
|
11427 | 10000 |
ins_encode %{ |
10001 |
__ movl($dst$$Register, Address(rsp, $src$$disp)); |
|
10002 |
%} |
|
1 | 10003 |
ins_pipe(ialu_reg_mem); |
10004 |
%} |
|
10005 |
||
10006 |
instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ |
|
10007 |
match(Set dst (MoveI2F src)); |
|
10008 |
effect(DEF dst, USE src); |
|
10009 |
||
10010 |
ins_cost(125); |
|
10011 |
format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} |
|
11427 | 10012 |
ins_encode %{ |
10013 |
__ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); |
|
10014 |
%} |
|
1 | 10015 |
ins_pipe(pipe_slow); |
10016 |
%} |
|
10017 |
||
10018 |
instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ |
|
10019 |
match(Set dst (MoveD2L src)); |
|
10020 |
effect(DEF dst, USE src); |
|
10021 |
||
10022 |
ins_cost(125); |
|
10023 |
format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} |
|
11427 | 10024 |
ins_encode %{ |
10025 |
__ movq($dst$$Register, Address(rsp, $src$$disp)); |
|
10026 |
%} |
|
1 | 10027 |
ins_pipe(ialu_reg_mem); |
10028 |
%} |
|
10029 |
||
10030 |
instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ |
|
10031 |
predicate(!UseXmmLoadAndClearUpper); |
|
10032 |
match(Set dst (MoveL2D src)); |
|
10033 |
effect(DEF dst, USE src); |
|
10034 |
||
10035 |
ins_cost(125); |
|
10036 |
format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} |
|
11427 | 10037 |
ins_encode %{ |
10038 |
__ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); |
|
10039 |
%} |
|
1 | 10040 |
ins_pipe(pipe_slow); |
10041 |
%} |
|
10042 |
||
10043 |
instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ |
|
10044 |
predicate(UseXmmLoadAndClearUpper); |
|
10045 |
match(Set dst (MoveL2D src)); |
|
10046 |
effect(DEF dst, USE src); |
|
10047 |
||
10048 |
ins_cost(125); |
|
10049 |
format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} |
|
11427 | 10050 |
ins_encode %{ |
10051 |
__ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); |
|
10052 |
%} |
|
1 | 10053 |
ins_pipe(pipe_slow); |
10054 |
%} |
|
10055 |
||
10056 |
||
10057 |
instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ |
|
10058 |
match(Set dst (MoveF2I src)); |
|
10059 |
effect(DEF dst, USE src); |
|
10060 |
||
10061 |
ins_cost(95); // XXX |
|
10062 |
format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} |
|
11427 | 10063 |
ins_encode %{ |
10064 |
__ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); |
|
10065 |
%} |
|
1 | 10066 |
ins_pipe(pipe_slow); |
10067 |
%} |
|
10068 |
||
10069 |
instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
|
10070 |
match(Set dst (MoveI2F src)); |
|
10071 |
effect(DEF dst, USE src); |
|
10072 |
||
10073 |
ins_cost(100); |
|
10074 |
format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} |
|
11427 | 10075 |
ins_encode %{ |
10076 |
__ movl(Address(rsp, $dst$$disp), $src$$Register); |
|
10077 |
%} |
|
1 | 10078 |
ins_pipe( ialu_mem_reg ); |
10079 |
%} |
|
10080 |
||
10081 |
instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ |
|
10082 |
match(Set dst (MoveD2L src)); |
|
10083 |
effect(DEF dst, USE src); |
|
10084 |
||
10085 |
ins_cost(95); // XXX |
|
10086 |
format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} |
|
11427 | 10087 |
ins_encode %{ |
10088 |
__ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
|
10089 |
%} |
|
1 | 10090 |
ins_pipe(pipe_slow); |
10091 |
%} |
|
10092 |
||
10093 |
instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ |
|
10094 |
match(Set dst (MoveL2D src)); |
|
10095 |
effect(DEF dst, USE src); |
|
10096 |
||
10097 |
ins_cost(100); |
|
10098 |
format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} |
|
11427 | 10099 |
ins_encode %{ |
10100 |
__ movq(Address(rsp, $dst$$disp), $src$$Register); |
|
10101 |
%} |
|
1 | 10102 |
ins_pipe(ialu_mem_reg); |
10103 |
%} |
|
10104 |
||
10105 |
instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ |
|
10106 |
match(Set dst (MoveF2I src)); |
|
10107 |
effect(DEF dst, USE src); |
|
10108 |
ins_cost(85); |
|
10109 |
format %{ "movd $dst,$src\t# MoveF2I" %} |
|
11427 | 10110 |
ins_encode %{ |
10111 |
__ movdl($dst$$Register, $src$$XMMRegister); |
|
10112 |
%} |
|
1 | 10113 |
ins_pipe( pipe_slow ); |
10114 |
%} |
|
10115 |
||
10116 |
instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ |
|
10117 |
match(Set dst (MoveD2L src)); |
|
10118 |
effect(DEF dst, USE src); |
|
10119 |
ins_cost(85); |
|
10120 |
format %{ "movd $dst,$src\t# MoveD2L" %} |
|
11427 | 10121 |
ins_encode %{ |
10122 |
__ movdq($dst$$Register, $src$$XMMRegister); |
|
10123 |
%} |
|
1 | 10124 |
ins_pipe( pipe_slow ); |
10125 |
%} |
|
10126 |
||
10127 |
instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ |
|
10128 |
match(Set dst (MoveI2F src)); |
|
10129 |
effect(DEF dst, USE src); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
10130 |
ins_cost(100); |
1 | 10131 |
format %{ "movd $dst,$src\t# MoveI2F" %} |
11427 | 10132 |
ins_encode %{ |
10133 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
10134 |
%} |
|
1 | 10135 |
ins_pipe( pipe_slow ); |
10136 |
%} |
|
10137 |
||
10138 |
instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ |
|
10139 |
match(Set dst (MoveL2D src)); |
|
10140 |
effect(DEF dst, USE src); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13104
diff
changeset
|
10141 |
ins_cost(100); |
1 | 10142 |
format %{ "movd $dst,$src\t# MoveL2D" %} |
11427 | 10143 |
ins_encode %{ |
10144 |
__ movdq($dst$$XMMRegister, $src$$Register); |
|
10145 |
%} |
|
1 | 10146 |
ins_pipe( pipe_slow ); |
10147 |
%} |
|
10148 |
||
10149 |
||
10150 |
// ======================================================================= |
|
10151 |
// fast clearing of an array |
|
10152 |
instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
10153 |
rFlagsReg cr) |
|
10154 |
%{ |
|
10155 |
match(Set dummy (ClearArray cnt base)); |
|
10156 |
effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
10157 |
||
10158 |
format %{ "xorl rax, rax\t# ClearArray:\n\t" |
|
10159 |
"rep stosq\t# Store rax to *rdi++ while rcx--" %} |
|
10160 |
ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax |
|
10161 |
Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos |
|
10162 |
ins_pipe(pipe_slow); |
|
10163 |
%} |
|
10164 |
||
8332 | 10165 |
instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
10166 |
rax_RegI result, regD tmp1, rFlagsReg cr) |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10167 |
%{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10168 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
8332 | 10169 |
effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
10170 |
||
10171 |
format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10172 |
ins_encode %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10173 |
__ string_compare($str1$$Register, $str2$$Register, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10174 |
$cnt1$$Register, $cnt2$$Register, $result$$Register, |
8332 | 10175 |
$tmp1$$XMMRegister); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10176 |
%} |
2348 | 10177 |
ins_pipe( pipe_slow ); |
10178 |
%} |
|
10179 |
||
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10180 |
// fast search of substring with known size. |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10181 |
instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10182 |
rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10183 |
%{ |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10184 |
predicate(UseSSE42Intrinsics); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10185 |
match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10186 |
effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10187 |
|
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10188 |
format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10189 |
ins_encode %{ |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10190 |
int icnt2 = (int)$int_cnt2$$constant; |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10191 |
if (icnt2 >= 8) { |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10192 |
// IndexOf for constant substrings with size >= 8 elements |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10193 |
// which don't need to be loaded through stack. |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10194 |
__ string_indexofC8($str1$$Register, $str2$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10195 |
$cnt1$$Register, $cnt2$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10196 |
icnt2, $result$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10197 |
$vec$$XMMRegister, $tmp$$Register); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10198 |
} else { |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10199 |
// Small strings are loaded through stack if they cross page boundary. |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10200 |
__ string_indexof($str1$$Register, $str2$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10201 |
$cnt1$$Register, $cnt2$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10202 |
icnt2, $result$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10203 |
$vec$$XMMRegister, $tmp$$Register); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10204 |
} |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10205 |
%} |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10206 |
ins_pipe( pipe_slow ); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10207 |
%} |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10208 |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10209 |
instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10210 |
rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
2348 | 10211 |
%{ |
10212 |
predicate(UseSSE42Intrinsics); |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10213 |
match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10214 |
effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10215 |
|
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10216 |
format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10217 |
ins_encode %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10218 |
__ string_indexof($str1$$Register, $str2$$Register, |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10219 |
$cnt1$$Register, $cnt2$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10220 |
(-1), $result$$Register, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
10221 |
$vec$$XMMRegister, $tmp$$Register); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10222 |
%} |
2348 | 10223 |
ins_pipe( pipe_slow ); |
10224 |
%} |
|
10225 |
||
10226 |
// fast string equals |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10227 |
instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10228 |
regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10229 |
%{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10230 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10231 |
effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10232 |
|
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10233 |
format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10234 |
ins_encode %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10235 |
__ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10236 |
$cnt$$Register, $result$$Register, $tmp3$$Register, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10237 |
$tmp1$$XMMRegister, $tmp2$$XMMRegister); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10238 |
%} |
1 | 10239 |
ins_pipe( pipe_slow ); |
10240 |
%} |
|
10241 |
||
595
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10242 |
// fast array equals |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10243 |
instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10244 |
regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
2348 | 10245 |
%{ |
595
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10246 |
match(Set result (AryEq ary1 ary2)); |
2348 | 10247 |
effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
595
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10248 |
//ins_cost(300); |
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10249 |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10250 |
format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10251 |
ins_encode %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10252 |
__ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10253 |
$tmp3$$Register, $result$$Register, $tmp4$$Register, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10254 |
$tmp1$$XMMRegister, $tmp2$$XMMRegister); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3177
diff
changeset
|
10255 |
%} |
595
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10256 |
ins_pipe( pipe_slow ); |
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10257 |
%} |
a2be4c89de81
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
594
diff
changeset
|
10258 |
|
1 | 10259 |
//----------Control Flow Instructions------------------------------------------ |
10260 |
// Signed compare Instructions |
|
10261 |
||
10262 |
// XXX more variants!! |
|
10263 |
instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) |
|
10264 |
%{ |
|
10265 |
match(Set cr (CmpI op1 op2)); |
|
10266 |
effect(DEF cr, USE op1, USE op2); |
|
10267 |
||
10268 |
format %{ "cmpl $op1, $op2" %} |
|
10269 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10270 |
ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); |
|
10271 |
ins_pipe(ialu_cr_reg_reg); |
|
10272 |
%} |
|
10273 |
||
10274 |
instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) |
|
10275 |
%{ |
|
10276 |
match(Set cr (CmpI op1 op2)); |
|
10277 |
||
10278 |
format %{ "cmpl $op1, $op2" %} |
|
10279 |
opcode(0x81, 0x07); /* Opcode 81 /7 */ |
|
10280 |
ins_encode(OpcSErm(op1, op2), Con8or32(op2)); |
|
10281 |
ins_pipe(ialu_cr_reg_imm); |
|
10282 |
%} |
|
10283 |
||
10284 |
instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) |
|
10285 |
%{ |
|
10286 |
match(Set cr (CmpI op1 (LoadI op2))); |
|
10287 |
||
10288 |
ins_cost(500); // XXX |
|
10289 |
format %{ "cmpl $op1, $op2" %} |
|
10290 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10291 |
ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); |
|
10292 |
ins_pipe(ialu_cr_reg_mem); |
|
10293 |
%} |
|
10294 |
||
10295 |
instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) |
|
10296 |
%{ |
|
10297 |
match(Set cr (CmpI src zero)); |
|
10298 |
||
10299 |
format %{ "testl $src, $src" %} |
|
10300 |
opcode(0x85); |
|
10301 |
ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); |
|
10302 |
ins_pipe(ialu_cr_reg_imm); |
|
10303 |
%} |
|
10304 |
||
10305 |
instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) |
|
10306 |
%{ |
|
10307 |
match(Set cr (CmpI (AndI src con) zero)); |
|
10308 |
||
10309 |
format %{ "testl $src, $con" %} |
|
10310 |
opcode(0xF7, 0x00); |
|
10311 |
ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); |
|
10312 |
ins_pipe(ialu_cr_reg_imm); |
|
10313 |
%} |
|
10314 |
||
10315 |
instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) |
|
10316 |
%{ |
|
10317 |
match(Set cr (CmpI (AndI src (LoadI mem)) zero)); |
|
10318 |
||
10319 |
format %{ "testl $src, $mem" %} |
|
10320 |
opcode(0x85); |
|
10321 |
ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); |
|
10322 |
ins_pipe(ialu_cr_reg_mem); |
|
10323 |
%} |
|
10324 |
||
10325 |
// Unsigned compare Instructions; really, same as signed except they |
|
10326 |
// produce an rFlagsRegU instead of rFlagsReg. |
|
10327 |
instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) |
|
10328 |
%{ |
|
10329 |
match(Set cr (CmpU op1 op2)); |
|
10330 |
||
10331 |
format %{ "cmpl $op1, $op2\t# unsigned" %} |
|
10332 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10333 |
ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); |
|
10334 |
ins_pipe(ialu_cr_reg_reg); |
|
10335 |
%} |
|
10336 |
||
10337 |
instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) |
|
10338 |
%{ |
|
10339 |
match(Set cr (CmpU op1 op2)); |
|
10340 |
||
10341 |
format %{ "cmpl $op1, $op2\t# unsigned" %} |
|
10342 |
opcode(0x81,0x07); /* Opcode 81 /7 */ |
|
10343 |
ins_encode(OpcSErm(op1, op2), Con8or32(op2)); |
|
10344 |
ins_pipe(ialu_cr_reg_imm); |
|
10345 |
%} |
|
10346 |
||
10347 |
instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) |
|
10348 |
%{ |
|
10349 |
match(Set cr (CmpU op1 (LoadI op2))); |
|
10350 |
||
10351 |
ins_cost(500); // XXX |
|
10352 |
format %{ "cmpl $op1, $op2\t# unsigned" %} |
|
10353 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10354 |
ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); |
|
10355 |
ins_pipe(ialu_cr_reg_mem); |
|
10356 |
%} |
|
10357 |
||
10358 |
// // // Cisc-spilled version of cmpU_rReg |
|
10359 |
// //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) |
|
10360 |
// //%{ |
|
10361 |
// // match(Set cr (CmpU (LoadI op1) op2)); |
|
10362 |
// // |
|
10363 |
// // format %{ "CMPu $op1,$op2" %} |
|
10364 |
// // ins_cost(500); |
|
10365 |
// // opcode(0x39); /* Opcode 39 /r */ |
|
10366 |
// // ins_encode( OpcP, reg_mem( op1, op2) ); |
|
10367 |
// //%} |
|
10368 |
||
10369 |
instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) |
|
10370 |
%{ |
|
10371 |
match(Set cr (CmpU src zero)); |
|
10372 |
||
10373 |
format %{ "testl $src, $src\t# unsigned" %} |
|
10374 |
opcode(0x85); |
|
10375 |
ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); |
|
10376 |
ins_pipe(ialu_cr_reg_imm); |
|
10377 |
%} |
|
10378 |
||
10379 |
instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) |
|
10380 |
%{ |
|
10381 |
match(Set cr (CmpP op1 op2)); |
|
10382 |
||
10383 |
format %{ "cmpq $op1, $op2\t# ptr" %} |
|
10384 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10385 |
ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); |
|
10386 |
ins_pipe(ialu_cr_reg_reg); |
|
10387 |
%} |
|
10388 |
||
10389 |
instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) |
|
10390 |
%{ |
|
10391 |
match(Set cr (CmpP op1 (LoadP op2))); |
|
10392 |
||
10393 |
ins_cost(500); // XXX |
|
10394 |
format %{ "cmpq $op1, $op2\t# ptr" %} |
|
10395 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10396 |
ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
|
10397 |
ins_pipe(ialu_cr_reg_mem); |
|
10398 |
%} |
|
10399 |
||
10400 |
// // // Cisc-spilled version of cmpP_rReg |
|
10401 |
// //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) |
|
10402 |
// //%{ |
|
10403 |
// // match(Set cr (CmpP (LoadP op1) op2)); |
|
10404 |
// // |
|
10405 |
// // format %{ "CMPu $op1,$op2" %} |
|
10406 |
// // ins_cost(500); |
|
10407 |
// // opcode(0x39); /* Opcode 39 /r */ |
|
10408 |
// // ins_encode( OpcP, reg_mem( op1, op2) ); |
|
10409 |
// //%} |
|
10410 |
||
10411 |
// XXX this is generalized by compP_rReg_mem??? |
|
10412 |
// Compare raw pointer (used in out-of-heap check). |
|
10413 |
// Only works because non-oop pointers must be raw pointers |
|
10414 |
// and raw pointers have no anti-dependencies. |
|
10415 |
instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) |
|
10416 |
%{ |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
10417 |
predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
1 | 10418 |
match(Set cr (CmpP op1 (LoadP op2))); |
10419 |
||
10420 |
format %{ "cmpq $op1, $op2\t# raw ptr" %} |
|
10421 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10422 |
ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
|
10423 |
ins_pipe(ialu_cr_reg_mem); |
|
10424 |
%} |
|
10425 |
||
10426 |
// This will generate a signed flags result. This should be OK since |
|
10427 |
// any compare to a zero should be eq/neq. |
|
10428 |
instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) |
|
10429 |
%{ |
|
10430 |
match(Set cr (CmpP src zero)); |
|
10431 |
||
10432 |
format %{ "testq $src, $src\t# ptr" %} |
|
10433 |
opcode(0x85); |
|
10434 |
ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); |
|
10435 |
ins_pipe(ialu_cr_reg_imm); |
|
10436 |
%} |
|
10437 |
||
10438 |
// This will generate a signed flags result. This should be OK since |
|
10439 |
// any compare to a zero should be eq/neq. |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10440 |
instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10441 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10442 |
predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
1 | 10443 |
match(Set cr (CmpP (LoadP op) zero)); |
10444 |
||
10445 |
ins_cost(500); // XXX |
|
10446 |
format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
|
10447 |
opcode(0xF7); /* Opcode F7 /0 */ |
|
10448 |
ins_encode(REX_mem_wide(op), |
|
10449 |
OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); |
|
10450 |
ins_pipe(ialu_cr_reg_imm); |
|
10451 |
%} |
|
10452 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10453 |
instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10454 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10455 |
predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10456 |
match(Set cr (CmpP (LoadP mem) zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10457 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10458 |
format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10459 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10460 |
__ cmpq(r12, $mem$$Address); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10461 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10462 |
ins_pipe(ialu_cr_reg_mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10463 |
%} |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10464 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10465 |
instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10466 |
%{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10467 |
match(Set cr (CmpN op1 op2)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10468 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10469 |
format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10470 |
ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10471 |
ins_pipe(ialu_cr_reg_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10472 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10473 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10474 |
instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10475 |
%{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10476 |
match(Set cr (CmpN src (LoadN mem))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10477 |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10478 |
format %{ "cmpl $src, $mem\t# compressed ptr" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10479 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10480 |
__ cmpl($src$$Register, $mem$$Address); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10481 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10482 |
ins_pipe(ialu_cr_reg_mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10483 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10484 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10485 |
instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10486 |
match(Set cr (CmpN op1 op2)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10487 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10488 |
format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10489 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10490 |
__ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10491 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10492 |
ins_pipe(ialu_cr_reg_imm); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10493 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10494 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10495 |
instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10496 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10497 |
match(Set cr (CmpN src (LoadN mem))); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10498 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10499 |
format %{ "cmpl $mem, $src\t# compressed ptr" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10500 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10501 |
__ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10502 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10503 |
ins_pipe(ialu_cr_reg_mem); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10504 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10505 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10506 |
instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10507 |
match(Set cr (CmpN src zero)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10508 |
|
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10509 |
format %{ "testl $src, $src\t# compressed ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10510 |
ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10511 |
ins_pipe(ialu_cr_reg_imm); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10512 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
244
diff
changeset
|
10513 |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10514 |
instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10515 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10516 |
predicate(Universe::narrow_oop_base() != NULL); |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10517 |
match(Set cr (CmpN (LoadN mem) zero)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10518 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10519 |
ins_cost(500); // XXX |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10520 |
format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10521 |
ins_encode %{ |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10522 |
__ cmpl($mem$$Address, (int)0xFFFFFFFF); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10523 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10524 |
ins_pipe(ialu_cr_reg_mem); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10525 |
%} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10526 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10527 |
instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10528 |
%{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10529 |
predicate(Universe::narrow_oop_base() == NULL); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10530 |
match(Set cr (CmpN (LoadN mem) zero)); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10531 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10532 |
format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10533 |
ins_encode %{ |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
10534 |
__ cmpl(r12, $mem$$Address); |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10535 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10536 |
ins_pipe(ialu_cr_reg_mem); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10537 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
10538 |
|
1 | 10539 |
// Yanked all unsigned pointer compare operations. |
10540 |
// Pointer compares are done with CmpP which is already unsigned. |
|
10541 |
||
10542 |
instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) |
|
10543 |
%{ |
|
10544 |
match(Set cr (CmpL op1 op2)); |
|
10545 |
||
10546 |
format %{ "cmpq $op1, $op2" %} |
|
10547 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10548 |
ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); |
|
10549 |
ins_pipe(ialu_cr_reg_reg); |
|
10550 |
%} |
|
10551 |
||
10552 |
instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) |
|
10553 |
%{ |
|
10554 |
match(Set cr (CmpL op1 op2)); |
|
10555 |
||
10556 |
format %{ "cmpq $op1, $op2" %} |
|
10557 |
opcode(0x81, 0x07); /* Opcode 81 /7 */ |
|
10558 |
ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); |
|
10559 |
ins_pipe(ialu_cr_reg_imm); |
|
10560 |
%} |
|
10561 |
||
10562 |
instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) |
|
10563 |
%{ |
|
10564 |
match(Set cr (CmpL op1 (LoadL op2))); |
|
10565 |
||
10566 |
format %{ "cmpq $op1, $op2" %} |
|
10567 |
opcode(0x3B); /* Opcode 3B /r */ |
|
10568 |
ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
|
10569 |
ins_pipe(ialu_cr_reg_mem); |
|
10570 |
%} |
|
10571 |
||
10572 |
instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) |
|
10573 |
%{ |
|
10574 |
match(Set cr (CmpL src zero)); |
|
10575 |
||
10576 |
format %{ "testq $src, $src" %} |
|
10577 |
opcode(0x85); |
|
10578 |
ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); |
|
10579 |
ins_pipe(ialu_cr_reg_imm); |
|
10580 |
%} |
|
10581 |
||
10582 |
instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) |
|
10583 |
%{ |
|
10584 |
match(Set cr (CmpL (AndL src con) zero)); |
|
10585 |
||
10586 |
format %{ "testq $src, $con\t# long" %} |
|
10587 |
opcode(0xF7, 0x00); |
|
10588 |
ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); |
|
10589 |
ins_pipe(ialu_cr_reg_imm); |
|
10590 |
%} |
|
10591 |
||
10592 |
instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) |
|
10593 |
%{ |
|
10594 |
match(Set cr (CmpL (AndL src (LoadL mem)) zero)); |
|
10595 |
||
10596 |
format %{ "testq $src, $mem" %} |
|
10597 |
opcode(0x85); |
|
10598 |
ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); |
|
10599 |
ins_pipe(ialu_cr_reg_mem); |
|
10600 |
%} |
|
10601 |
||
10602 |
// Manifest a CmpL result in an integer register. Very painful. |
|
10603 |
// This is the test to avoid. |
|
10604 |
instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) |
|
10605 |
%{ |
|
10606 |
match(Set dst (CmpL3 src1 src2)); |
|
10607 |
effect(KILL flags); |
|
10608 |
||
10609 |
ins_cost(275); // XXX |
|
10610 |
format %{ "cmpq $src1, $src2\t# CmpL3\n\t" |
|
10611 |
"movl $dst, -1\n\t" |
|
10612 |
"jl,s done\n\t" |
|
10613 |
"setne $dst\n\t" |
|
10614 |
"movzbl $dst, $dst\n\t" |
|
10615 |
"done:" %} |
|
10616 |
ins_encode(cmpl3_flag(src1, src2, dst)); |
|
10617 |
ins_pipe(pipe_slow); |
|
10618 |
%} |
|
10619 |
||
10620 |
//----------Max and Min-------------------------------------------------------- |
|
10621 |
// Min Instructions |
|
10622 |
||
10623 |
instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) |
|
10624 |
%{ |
|
10625 |
effect(USE_DEF dst, USE src, USE cr); |
|
10626 |
||
10627 |
format %{ "cmovlgt $dst, $src\t# min" %} |
|
10628 |
opcode(0x0F, 0x4F); |
|
10629 |
ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
10630 |
ins_pipe(pipe_cmov_reg); |
|
10631 |
%} |
|
10632 |
||
10633 |
||
10634 |
instruct minI_rReg(rRegI dst, rRegI src) |
|
10635 |
%{ |
|
10636 |
match(Set dst (MinI dst src)); |
|
10637 |
||
10638 |
ins_cost(200); |
|
10639 |
expand %{ |
|
10640 |
rFlagsReg cr; |
|
10641 |
compI_rReg(cr, dst, src); |
|
10642 |
cmovI_reg_g(dst, src, cr); |
|
10643 |
%} |
|
10644 |
%} |
|
10645 |
||
10646 |
instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) |
|
10647 |
%{ |
|
10648 |
effect(USE_DEF dst, USE src, USE cr); |
|
10649 |
||
10650 |
format %{ "cmovllt $dst, $src\t# max" %} |
|
10651 |
opcode(0x0F, 0x4C); |
|
10652 |
ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); |
|
10653 |
ins_pipe(pipe_cmov_reg); |
|
10654 |
%} |
|
10655 |
||
10656 |
||
10657 |
instruct maxI_rReg(rRegI dst, rRegI src) |
|
10658 |
%{ |
|
10659 |
match(Set dst (MaxI dst src)); |
|
10660 |
||
10661 |
ins_cost(200); |
|
10662 |
expand %{ |
|
10663 |
rFlagsReg cr; |
|
10664 |
compI_rReg(cr, dst, src); |
|
10665 |
cmovI_reg_l(dst, src, cr); |
|
10666 |
%} |
|
10667 |
%} |
|
10668 |
||
10669 |
// ============================================================================ |
|
10670 |
// Branch Instructions |
|
10671 |
||
10672 |
// Jump Direct - Label defines a relative address from JMP+1 |
|
10673 |
instruct jmpDir(label labl) |
|
10674 |
%{ |
|
10675 |
match(Goto); |
|
10676 |
effect(USE labl); |
|
10677 |
||
10678 |
ins_cost(300); |
|
10679 |
format %{ "jmp $labl" %} |
|
10680 |
size(5); |
|
10264 | 10681 |
ins_encode %{ |
10682 |
Label* L = $labl$$label; |
|
10683 |
__ jmp(*L, false); // Always long jump |
|
10684 |
%} |
|
1 | 10685 |
ins_pipe(pipe_jmp); |
10686 |
%} |
|
10687 |
||
10688 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
10689 |
instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) |
|
10690 |
%{ |
|
10691 |
match(If cop cr); |
|
10692 |
effect(USE labl); |
|
10693 |
||
10694 |
ins_cost(300); |
|
10695 |
format %{ "j$cop $labl" %} |
|
10696 |
size(6); |
|
10264 | 10697 |
ins_encode %{ |
10698 |
Label* L = $labl$$label; |
|
10699 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10700 |
%} |
|
1 | 10701 |
ins_pipe(pipe_jcc); |
10702 |
%} |
|
10703 |
||
10704 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
10705 |
instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) |
|
10706 |
%{ |
|
10707 |
match(CountedLoopEnd cop cr); |
|
10708 |
effect(USE labl); |
|
10709 |
||
10710 |
ins_cost(300); |
|
10711 |
format %{ "j$cop $labl\t# loop end" %} |
|
10712 |
size(6); |
|
10264 | 10713 |
ins_encode %{ |
10714 |
Label* L = $labl$$label; |
|
10715 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10716 |
%} |
|
1 | 10717 |
ins_pipe(pipe_jcc); |
10718 |
%} |
|
10719 |
||
10720 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10721 |
instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
1 | 10722 |
match(CountedLoopEnd cop cmp); |
10723 |
effect(USE labl); |
|
10724 |
||
10725 |
ins_cost(300); |
|
10726 |
format %{ "j$cop,u $labl\t# loop end" %} |
|
10727 |
size(6); |
|
10264 | 10728 |
ins_encode %{ |
10729 |
Label* L = $labl$$label; |
|
10730 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10731 |
%} |
|
1 | 10732 |
ins_pipe(pipe_jcc); |
10733 |
%} |
|
10734 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10735 |
instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10736 |
match(CountedLoopEnd cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10737 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10738 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10739 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10740 |
format %{ "j$cop,u $labl\t# loop end" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10741 |
size(6); |
10264 | 10742 |
ins_encode %{ |
10743 |
Label* L = $labl$$label; |
|
10744 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10745 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10746 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10747 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10748 |
|
1 | 10749 |
// Jump Direct Conditional - using unsigned comparison |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10750 |
instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
1 | 10751 |
match(If cop cmp); |
10752 |
effect(USE labl); |
|
10753 |
||
10754 |
ins_cost(300); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10755 |
format %{ "j$cop,u $labl" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10756 |
size(6); |
10264 | 10757 |
ins_encode %{ |
10758 |
Label* L = $labl$$label; |
|
10759 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10760 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10761 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10762 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10763 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10764 |
instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10765 |
match(If cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10766 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10767 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10768 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10769 |
format %{ "j$cop,u $labl" %} |
1 | 10770 |
size(6); |
10264 | 10771 |
ins_encode %{ |
10772 |
Label* L = $labl$$label; |
|
10773 |
__ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump |
|
10774 |
%} |
|
1 | 10775 |
ins_pipe(pipe_jcc); |
10776 |
%} |
|
10777 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10778 |
instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10779 |
match(If cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10780 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10781 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10782 |
ins_cost(200); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10783 |
format %{ $$template |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10784 |
if ($cop$$cmpcode == Assembler::notEqual) { |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10785 |
$$emit$$"jp,u $labl\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10786 |
$$emit$$"j$cop,u $labl" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10787 |
} else { |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10788 |
$$emit$$"jp,u done\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10789 |
$$emit$$"j$cop,u $labl\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10790 |
$$emit$$"done:" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10791 |
} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10792 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10793 |
ins_encode %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10794 |
Label* l = $labl$$label; |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10795 |
if ($cop$$cmpcode == Assembler::notEqual) { |
10264 | 10796 |
__ jcc(Assembler::parity, *l, false); |
10797 |
__ jcc(Assembler::notEqual, *l, false); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10798 |
} else if ($cop$$cmpcode == Assembler::equal) { |
10264 | 10799 |
Label done; |
10800 |
__ jccb(Assembler::parity, done); |
|
10801 |
__ jcc(Assembler::equal, *l, false); |
|
10802 |
__ bind(done); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10803 |
} else { |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10804 |
ShouldNotReachHere(); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10805 |
} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10806 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10807 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10808 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10809 |
|
1 | 10810 |
// ============================================================================ |
10811 |
// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary |
|
10812 |
// superklass array for an instance of the superklass. Set a hidden |
|
10813 |
// internal cache on a hit (cache is checked with exposed code in |
|
10814 |
// gen_subtype_check()). Return NZ for a miss or zero for a hit. The |
|
10815 |
// encoding ALSO sets flags. |
|
10816 |
||
10817 |
instruct partialSubtypeCheck(rdi_RegP result, |
|
10818 |
rsi_RegP sub, rax_RegP super, rcx_RegI rcx, |
|
10819 |
rFlagsReg cr) |
|
10820 |
%{ |
|
10821 |
match(Set result (PartialSubtypeCheck sub super)); |
|
10822 |
effect(KILL rcx, KILL cr); |
|
10823 |
||
10824 |
ins_cost(1100); // slightly larger than the next version |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11429
diff
changeset
|
10825 |
format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
10826 |
"movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
10827 |
"addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
1 | 10828 |
"repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
10829 |
"jne,s miss\t\t# Missed: rdi not-zero\n\t" |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11429
diff
changeset
|
10830 |
"movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
1 | 10831 |
"xorq $result, $result\t\t Hit: rdi zero\n\t" |
10832 |
"miss:\t" %} |
|
10833 |
||
10834 |
opcode(0x1); // Force a XOR of RDI |
|
10835 |
ins_encode(enc_PartialSubtypeCheck()); |
|
10836 |
ins_pipe(pipe_slow); |
|
10837 |
%} |
|
10838 |
||
10839 |
instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, |
|
10840 |
rsi_RegP sub, rax_RegP super, rcx_RegI rcx, |
|
10841 |
immP0 zero, |
|
10842 |
rdi_RegP result) |
|
10843 |
%{ |
|
10844 |
match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); |
|
10845 |
effect(KILL rcx, KILL result); |
|
10846 |
||
10847 |
ins_cost(1000); |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11429
diff
changeset
|
10848 |
format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
10849 |
"movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
10850 |
"addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
1 | 10851 |
"repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
10852 |
"jne,s miss\t\t# Missed: flags nz\n\t" |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11429
diff
changeset
|
10853 |
"movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
1 | 10854 |
"miss:\t" %} |
10855 |
||
10856 |
opcode(0x0); // No need to XOR RDI |
|
10857 |
ins_encode(enc_PartialSubtypeCheck()); |
|
10858 |
ins_pipe(pipe_slow); |
|
10859 |
%} |
|
10860 |
||
10861 |
// ============================================================================ |
|
10862 |
// Branch Instructions -- short offset versions |
|
10863 |
// |
|
10864 |
// These instructions are used to replace jumps of a long offset (the default |
|
10865 |
// match) with jumps of a shorter offset. These instructions are all tagged |
|
10866 |
// with the ins_short_branch attribute, which causes the ADLC to suppress the |
|
10867 |
// match rules in general matching. Instead, the ADLC generates a conversion |
|
10868 |
// method in the MachNode which can be used to do in-place replacement of the |
|
10869 |
// long variant with the shorter variant. The compiler will determine if a |
|
10870 |
// branch can be taken by the is_short_branch_offset() predicate in the machine |
|
10871 |
// specific code section of the file. |
|
10872 |
||
10873 |
// Jump Direct - Label defines a relative address from JMP+1 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10874 |
instruct jmpDir_short(label labl) %{ |
1 | 10875 |
match(Goto); |
10876 |
effect(USE labl); |
|
10877 |
||
10878 |
ins_cost(300); |
|
10879 |
format %{ "jmp,s $labl" %} |
|
10880 |
size(2); |
|
10264 | 10881 |
ins_encode %{ |
10882 |
Label* L = $labl$$label; |
|
10883 |
__ jmpb(*L); |
|
10884 |
%} |
|
1 | 10885 |
ins_pipe(pipe_jmp); |
10886 |
ins_short_branch(1); |
|
10887 |
%} |
|
10888 |
||
10889 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10890 |
instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
1 | 10891 |
match(If cop cr); |
10892 |
effect(USE labl); |
|
10893 |
||
10894 |
ins_cost(300); |
|
10895 |
format %{ "j$cop,s $labl" %} |
|
10896 |
size(2); |
|
10264 | 10897 |
ins_encode %{ |
10898 |
Label* L = $labl$$label; |
|
10899 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10900 |
%} |
|
1 | 10901 |
ins_pipe(pipe_jcc); |
10902 |
ins_short_branch(1); |
|
10903 |
%} |
|
10904 |
||
10905 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10906 |
instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
1 | 10907 |
match(CountedLoopEnd cop cr); |
10908 |
effect(USE labl); |
|
10909 |
||
10910 |
ins_cost(300); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10911 |
format %{ "j$cop,s $labl\t# loop end" %} |
1 | 10912 |
size(2); |
10264 | 10913 |
ins_encode %{ |
10914 |
Label* L = $labl$$label; |
|
10915 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10916 |
%} |
|
1 | 10917 |
ins_pipe(pipe_jcc); |
10918 |
ins_short_branch(1); |
|
10919 |
%} |
|
10920 |
||
10921 |
// Jump Direct Conditional - Label defines a relative address from Jcc+1 |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10922 |
instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10923 |
match(CountedLoopEnd cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10924 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10925 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10926 |
ins_cost(300); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10927 |
format %{ "j$cop,us $labl\t# loop end" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10928 |
size(2); |
10264 | 10929 |
ins_encode %{ |
10930 |
Label* L = $labl$$label; |
|
10931 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10932 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10933 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10934 |
ins_short_branch(1); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10935 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10936 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10937 |
instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
1 | 10938 |
match(CountedLoopEnd cop cmp); |
10939 |
effect(USE labl); |
|
10940 |
||
10941 |
ins_cost(300); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10942 |
format %{ "j$cop,us $labl\t# loop end" %} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10943 |
size(2); |
10264 | 10944 |
ins_encode %{ |
10945 |
Label* L = $labl$$label; |
|
10946 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10947 |
%} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10948 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10949 |
ins_short_branch(1); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10950 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10951 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10952 |
// Jump Direct Conditional - using unsigned comparison |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10953 |
instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10954 |
match(If cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10955 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10956 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10957 |
ins_cost(300); |
1 | 10958 |
format %{ "j$cop,us $labl" %} |
10959 |
size(2); |
|
10264 | 10960 |
ins_encode %{ |
10961 |
Label* L = $labl$$label; |
|
10962 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10963 |
%} |
|
1 | 10964 |
ins_pipe(pipe_jcc); |
10965 |
ins_short_branch(1); |
|
10966 |
%} |
|
10967 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10968 |
instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
1 | 10969 |
match(If cop cmp); |
10970 |
effect(USE labl); |
|
10971 |
||
10972 |
ins_cost(300); |
|
10973 |
format %{ "j$cop,us $labl" %} |
|
10974 |
size(2); |
|
10264 | 10975 |
ins_encode %{ |
10976 |
Label* L = $labl$$label; |
|
10977 |
__ jccb((Assembler::Condition)($cop$$cmpcode), *L); |
|
10978 |
%} |
|
1 | 10979 |
ins_pipe(pipe_jcc); |
10980 |
ins_short_branch(1); |
|
10981 |
%} |
|
10982 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10983 |
instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10984 |
match(If cop cmp); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10985 |
effect(USE labl); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10986 |
|
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10987 |
ins_cost(300); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10988 |
format %{ $$template |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10989 |
if ($cop$$cmpcode == Assembler::notEqual) { |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10990 |
$$emit$$"jp,u,s $labl\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10991 |
$$emit$$"j$cop,u,s $labl" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10992 |
} else { |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10993 |
$$emit$$"jp,u,s done\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10994 |
$$emit$$"j$cop,u,s $labl\n\t" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10995 |
$$emit$$"done:" |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10996 |
} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10997 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10998 |
size(4); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
10999 |
ins_encode %{ |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11000 |
Label* l = $labl$$label; |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11001 |
if ($cop$$cmpcode == Assembler::notEqual) { |
10264 | 11002 |
__ jccb(Assembler::parity, *l); |
11003 |
__ jccb(Assembler::notEqual, *l); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11004 |
} else if ($cop$$cmpcode == Assembler::equal) { |
10264 | 11005 |
Label done; |
11006 |
__ jccb(Assembler::parity, done); |
|
11007 |
__ jccb(Assembler::equal, *l); |
|
11008 |
__ bind(done); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11009 |
} else { |
10264 | 11010 |
ShouldNotReachHere(); |
11011 |
} |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11012 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11013 |
ins_pipe(pipe_jcc); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11014 |
ins_short_branch(1); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11015 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
1435
diff
changeset
|
11016 |
|
1 | 11017 |
// ============================================================================ |
11018 |
// inlined locking and unlocking |
|
11019 |
||
11020 |
instruct cmpFastLock(rFlagsReg cr, |
|
11445 | 11021 |
rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) |
1 | 11022 |
%{ |
11023 |
match(Set cr (FastLock object box)); |
|
11445 | 11024 |
effect(TEMP tmp, TEMP scr, USE_KILL box); |
1 | 11025 |
|
11026 |
ins_cost(300); |
|
11445 | 11027 |
format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
1 | 11028 |
ins_encode(Fast_Lock(object, box, tmp, scr)); |
11029 |
ins_pipe(pipe_slow); |
|
11030 |
%} |
|
11031 |
||
11032 |
instruct cmpFastUnlock(rFlagsReg cr, |
|
11033 |
rRegP object, rax_RegP box, rRegP tmp) |
|
11034 |
%{ |
|
11035 |
match(Set cr (FastUnlock object box)); |
|
11445 | 11036 |
effect(TEMP tmp, USE_KILL box); |
1 | 11037 |
|
11038 |
ins_cost(300); |
|
11445 | 11039 |
format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
1 | 11040 |
ins_encode(Fast_Unlock(object, box, tmp)); |
11041 |
ins_pipe(pipe_slow); |
|
11042 |
%} |
|
11043 |
||
11044 |
||
11045 |
// ============================================================================ |
|
11046 |
// Safepoint Instructions |
|
11047 |
instruct safePoint_poll(rFlagsReg cr) |
|
11048 |
%{ |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11049 |
predicate(!Assembler::is_polling_page_far()); |
1 | 11050 |
match(SafePoint); |
11051 |
effect(KILL cr); |
|
11052 |
||
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11053 |
format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
1 | 11054 |
"# Safepoint: poll for GC" %} |
11055 |
ins_cost(125); |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11056 |
ins_encode %{ |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11057 |
AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11058 |
__ testl(rax, addr); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11059 |
%} |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11060 |
ins_pipe(ialu_reg_mem); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11061 |
%} |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11062 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11063 |
instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11064 |
%{ |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11065 |
predicate(Assembler::is_polling_page_far()); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11066 |
match(SafePoint poll); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11067 |
effect(KILL cr, USE poll); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11068 |
|
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11069 |
format %{ "testl rax, [$poll]\t" |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11070 |
"# Safepoint: poll for GC" %} |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11071 |
ins_cost(125); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11072 |
ins_encode %{ |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11073 |
__ relocate(relocInfo::poll_type); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11074 |
__ testl(rax, Address($poll$$Register, 0)); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8868
diff
changeset
|
11075 |
%} |
1 | 11076 |
ins_pipe(ialu_reg_mem); |
11077 |
%} |
|
11078 |
||
11079 |
// ============================================================================ |
|
11080 |
// Procedure Call/Return Instructions |
|
11081 |
// Call Java Static Instruction |
|
11082 |
// Note: If this code changes, the corresponding ret_addr_offset() and |
|
11083 |
// compute_padding() functions will have to be adjusted. |
|
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11084 |
instruct CallStaticJavaDirect(method meth) %{ |
1 | 11085 |
match(CallStaticJava); |
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11086 |
predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
1 | 11087 |
effect(USE meth); |
11088 |
||
11089 |
ins_cost(300); |
|
11090 |
format %{ "call,static " %} |
|
11091 |
opcode(0xE8); /* E8 cd */ |
|
11092 |
ins_encode(Java_Static_Call(meth), call_epilog); |
|
11093 |
ins_pipe(pipe_slow); |
|
11094 |
ins_alignment(4); |
|
11095 |
%} |
|
11096 |
||
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11097 |
// Call Java Static Instruction (method handle version) |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11098 |
// Note: If this code changes, the corresponding ret_addr_offset() and |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11099 |
// compute_padding() functions will have to be adjusted. |
5690 | 11100 |
instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11101 |
match(CallStaticJava); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11102 |
predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11103 |
effect(USE meth); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11104 |
// RBP is saved by all callees (for interpreter stack correction). |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11105 |
// We use it here for a similar purpose, in {preserve,restore}_SP. |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11106 |
|
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11107 |
ins_cost(300); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11108 |
format %{ "call,static/MethodHandle " %} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11109 |
opcode(0xE8); /* E8 cd */ |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11110 |
ins_encode(preserve_SP, |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11111 |
Java_Static_Call(meth), |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11112 |
restore_SP, |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11113 |
call_epilog); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11114 |
ins_pipe(pipe_slow); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11115 |
ins_alignment(4); |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11116 |
%} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
3908
diff
changeset
|
11117 |
|
1 | 11118 |
// Call Java Dynamic Instruction |
11119 |
// Note: If this code changes, the corresponding ret_addr_offset() and |
|
11120 |
// compute_padding() functions will have to be adjusted. |
|
11121 |
instruct CallDynamicJavaDirect(method meth) |
|
11122 |
%{ |
|
11123 |
match(CallDynamicJava); |
|
11124 |
effect(USE meth); |
|
11125 |
||
11126 |
ins_cost(300); |
|
11127 |
format %{ "movq rax, #Universe::non_oop_word()\n\t" |
|
11128 |
"call,dynamic " %} |
|
11129 |
ins_encode(Java_Dynamic_Call(meth), call_epilog); |
|
11130 |
ins_pipe(pipe_slow); |
|
11131 |
ins_alignment(4); |
|
11132 |
%} |
|
11133 |
||
11134 |
// Call Runtime Instruction |
|
11135 |
instruct CallRuntimeDirect(method meth) |
|
11136 |
%{ |
|
11137 |
match(CallRuntime); |
|
11138 |
effect(USE meth); |
|
11139 |
||
11140 |
ins_cost(300); |
|
11141 |
format %{ "call,runtime " %} |
|
11142 |
opcode(0xE8); /* E8 cd */ |
|
11143 |
ins_encode(Java_To_Runtime(meth)); |
|
11144 |
ins_pipe(pipe_slow); |
|
11145 |
%} |
|
11146 |
||
11147 |
// Call runtime without safepoint |
|
11148 |
instruct CallLeafDirect(method meth) |
|
11149 |
%{ |
|
11150 |
match(CallLeaf); |
|
11151 |
effect(USE meth); |
|
11152 |
||
11153 |
ins_cost(300); |
|
11154 |
format %{ "call_leaf,runtime " %} |
|
11155 |
opcode(0xE8); /* E8 cd */ |
|
11156 |
ins_encode(Java_To_Runtime(meth)); |
|
11157 |
ins_pipe(pipe_slow); |
|
11158 |
%} |
|
11159 |
||
11160 |
// Call runtime without safepoint |
|
11161 |
instruct CallLeafNoFPDirect(method meth) |
|
11162 |
%{ |
|
11163 |
match(CallLeafNoFP); |
|
11164 |
effect(USE meth); |
|
11165 |
||
11166 |
ins_cost(300); |
|
11167 |
format %{ "call_leaf_nofp,runtime " %} |
|
11168 |
opcode(0xE8); /* E8 cd */ |
|
11169 |
ins_encode(Java_To_Runtime(meth)); |
|
11170 |
ins_pipe(pipe_slow); |
|
11171 |
%} |
|
11172 |
||
11173 |
// Return Instruction |
|
11174 |
// Remove the return address & jump to it. |
|
11175 |
// Notice: We always emit a nop after a ret to make sure there is room |
|
11176 |
// for safepoint patching |
|
11177 |
instruct Ret() |
|
11178 |
%{ |
|
11179 |
match(Return); |
|
11180 |
||
11181 |
format %{ "ret" %} |
|
11182 |
opcode(0xC3); |
|
11183 |
ins_encode(OpcP); |
|
11184 |
ins_pipe(pipe_jmp); |
|
11185 |
%} |
|
11186 |
||
11187 |
// Tail Call; Jump from runtime stub to Java code. |
|
11188 |
// Also known as an 'interprocedural jump'. |
|
11189 |
// Target of jump will eventually return to caller. |
|
11190 |
// TailJump below removes the return address. |
|
11191 |
instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) |
|
11192 |
%{ |
|
11193 |
match(TailCall jump_target method_oop); |
|
11194 |
||
11195 |
ins_cost(300); |
|
11196 |
format %{ "jmp $jump_target\t# rbx holds method oop" %} |
|
11197 |
opcode(0xFF, 0x4); /* Opcode FF /4 */ |
|
11198 |
ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); |
|
11199 |
ins_pipe(pipe_jmp); |
|
11200 |
%} |
|
11201 |
||
11202 |
// Tail Jump; remove the return address; jump to target. |
|
11203 |
// TailCall above leaves the return address around. |
|
11204 |
instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) |
|
11205 |
%{ |
|
11206 |
match(TailJump jump_target ex_oop); |
|
11207 |
||
11208 |
ins_cost(300); |
|
11209 |
format %{ "popq rdx\t# pop return address\n\t" |
|
11210 |
"jmp $jump_target" %} |
|
11211 |
opcode(0xFF, 0x4); /* Opcode FF /4 */ |
|
11212 |
ins_encode(Opcode(0x5a), // popq rdx |
|
11213 |
REX_reg(jump_target), OpcP, reg_opc(jump_target)); |
|
11214 |
ins_pipe(pipe_jmp); |
|
11215 |
%} |
|
11216 |
||
11217 |
// Create exception oop: created by stack-crawling runtime code. |
|
11218 |
// Created exception is now available to this handler, and is setup |
|
11219 |
// just prior to jumping to this handler. No code emitted. |
|
11220 |
instruct CreateException(rax_RegP ex_oop) |
|
11221 |
%{ |
|
11222 |
match(Set ex_oop (CreateEx)); |
|
11223 |
||
11224 |
size(0); |
|
11225 |
// use the following format syntax |
|
11226 |
format %{ "# exception oop is in rax; no code emitted" %} |
|
11227 |
ins_encode(); |
|
11228 |
ins_pipe(empty); |
|
11229 |
%} |
|
11230 |
||
11231 |
// Rethrow exception: |
|
11232 |
// The exception oop will come in the first argument position. |
|
11233 |
// Then JUMP (not call) to the rethrow stub code. |
|
11234 |
instruct RethrowException() |
|
11235 |
%{ |
|
11236 |
match(Rethrow); |
|
11237 |
||
11238 |
// use the following format syntax |
|
11239 |
format %{ "jmp rethrow_stub" %} |
|
11240 |
ins_encode(enc_rethrow); |
|
11241 |
ins_pipe(pipe_jmp); |
|
11242 |
%} |
|
11243 |
||
11244 |
||
11794 | 11245 |
// ============================================================================ |
11246 |
// This name is KNOWN by the ADLC and cannot be changed. |
|
11247 |
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type |
|
11248 |
// for this guy. |
|
11249 |
instruct tlsLoadP(r15_RegP dst) %{ |
|
11250 |
match(Set dst (ThreadLocal)); |
|
11251 |
effect(DEF dst); |
|
11252 |
||
11253 |
size(0); |
|
11254 |
format %{ "# TLS is in R15" %} |
|
11255 |
ins_encode( /*empty encoding*/ ); |
|
11256 |
ins_pipe(ialu_reg_reg); |
|
11257 |
%} |
|
11258 |
||
11259 |
||
1 | 11260 |
//----------PEEPHOLE RULES----------------------------------------------------- |
11261 |
// These must follow all instruction definitions as they use the names |
|
11262 |
// defined in the instructions definitions. |
|
11263 |
// |
|
2131 | 11264 |
// peepmatch ( root_instr_name [preceding_instruction]* ); |
1 | 11265 |
// |
11266 |
// peepconstraint %{ |
|
11267 |
// (instruction_number.operand_name relational_op instruction_number.operand_name |
|
11268 |
// [, ...] ); |
|
11269 |
// // instruction numbers are zero-based using left to right order in peepmatch |
|
11270 |
// |
|
11271 |
// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); |
|
11272 |
// // provide an instruction_number.operand_name for each operand that appears |
|
11273 |
// // in the replacement instruction's match rule |
|
11274 |
// |
|
11275 |
// ---------VM FLAGS--------------------------------------------------------- |
|
11276 |
// |
|
11277 |
// All peephole optimizations can be turned off using -XX:-OptoPeephole |
|
11278 |
// |
|
11279 |
// Each peephole rule is given an identifying number starting with zero and |
|
11280 |
// increasing by one in the order seen by the parser. An individual peephole |
|
11281 |
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# |
|
11282 |
// on the command-line. |
|
11283 |
// |
|
11284 |
// ---------CURRENT LIMITATIONS---------------------------------------------- |
|
11285 |
// |
|
11286 |
// Only match adjacent instructions in same basic block |
|
11287 |
// Only equality constraints |
|
11288 |
// Only constraints between operands, not (0.dest_reg == RAX_enc) |
|
11289 |
// Only one replacement instruction |
|
11290 |
// |
|
11291 |
// ---------EXAMPLE---------------------------------------------------------- |
|
11292 |
// |
|
11293 |
// // pertinent parts of existing instructions in architecture description |
|
11294 |
// instruct movI(rRegI dst, rRegI src) |
|
11295 |
// %{ |
|
11296 |
// match(Set dst (CopyI src)); |
|
11297 |
// %} |
|
11298 |
// |
|
11299 |
// instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) |
|
11300 |
// %{ |
|
11301 |
// match(Set dst (AddI dst src)); |
|
11302 |
// effect(KILL cr); |
|
11303 |
// %} |
|
11304 |
// |
|
11305 |
// // Change (inc mov) to lea |
|
11306 |
// peephole %{ |
|
11307 |
// // increment preceeded by register-register move |
|
11308 |
// peepmatch ( incI_rReg movI ); |
|
11309 |
// // require that the destination register of the increment |
|
11310 |
// // match the destination register of the move |
|
11311 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11312 |
// // construct a replacement instruction that sets |
|
11313 |
// // the destination to ( move's source register + one ) |
|
11314 |
// peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); |
|
11315 |
// %} |
|
11316 |
// |
|
11317 |
||
11318 |
// Implementation no longer uses movX instructions since |
|
11319 |
// machine-independent system no longer uses CopyX nodes. |
|
11320 |
// |
|
11321 |
// peephole |
|
11322 |
// %{ |
|
11323 |
// peepmatch (incI_rReg movI); |
|
11324 |
// peepconstraint (0.dst == 1.dst); |
|
11325 |
// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); |
|
11326 |
// %} |
|
11327 |
||
11328 |
// peephole |
|
11329 |
// %{ |
|
11330 |
// peepmatch (decI_rReg movI); |
|
11331 |
// peepconstraint (0.dst == 1.dst); |
|
11332 |
// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); |
|
11333 |
// %} |
|
11334 |
||
11335 |
// peephole |
|
11336 |
// %{ |
|
11337 |
// peepmatch (addI_rReg_imm movI); |
|
11338 |
// peepconstraint (0.dst == 1.dst); |
|
11339 |
// peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); |
|
11340 |
// %} |
|
11341 |
||
11342 |
// peephole |
|
11343 |
// %{ |
|
11344 |
// peepmatch (incL_rReg movL); |
|
11345 |
// peepconstraint (0.dst == 1.dst); |
|
11346 |
// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); |
|
11347 |
// %} |
|
11348 |
||
11349 |
// peephole |
|
11350 |
// %{ |
|
11351 |
// peepmatch (decL_rReg movL); |
|
11352 |
// peepconstraint (0.dst == 1.dst); |
|
11353 |
// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); |
|
11354 |
// %} |
|
11355 |
||
11356 |
// peephole |
|
11357 |
// %{ |
|
11358 |
// peepmatch (addL_rReg_imm movL); |
|
11359 |
// peepconstraint (0.dst == 1.dst); |
|
11360 |
// peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); |
|
11361 |
// %} |
|
11362 |
||
11363 |
// peephole |
|
11364 |
// %{ |
|
11365 |
// peepmatch (addP_rReg_imm movP); |
|
11366 |
// peepconstraint (0.dst == 1.dst); |
|
11367 |
// peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); |
|
11368 |
// %} |
|
11369 |
||
11370 |
// // Change load of spilled value to only a spill |
|
11371 |
// instruct storeI(memory mem, rRegI src) |
|
11372 |
// %{ |
|
11373 |
// match(Set mem (StoreI mem src)); |
|
11374 |
// %} |
|
11375 |
// |
|
11376 |
// instruct loadI(rRegI dst, memory mem) |
|
11377 |
// %{ |
|
11378 |
// match(Set dst (LoadI mem)); |
|
11379 |
// %} |
|
11380 |
// |
|
11381 |
||
11382 |
peephole |
|
11383 |
%{ |
|
11384 |
peepmatch (loadI storeI); |
|
11385 |
peepconstraint (1.src == 0.dst, 1.mem == 0.mem); |
|
11386 |
peepreplace (storeI(1.mem 1.mem 1.src)); |
|
11387 |
%} |
|
11388 |
||
11389 |
peephole |
|
11390 |
%{ |
|
11391 |
peepmatch (loadL storeL); |
|
11392 |
peepconstraint (1.src == 0.dst, 1.mem == 0.mem); |
|
11393 |
peepreplace (storeL(1.mem 1.mem 1.src)); |
|
11394 |
%} |
|
11395 |
||
11396 |
//----------SMARTSPILL RULES--------------------------------------------------- |
|
11397 |
// These must follow all instruction definitions as they use the names |
|
11398 |
// defined in the instructions definitions. |