8144448: Avoid placing CTI immediately following or preceding RDPC instruction
Summary: Best practice for new SPARC CPUs
Reviewed-by: kvn
Contributed-by: phedlin@oracle.com
--- a/hotspot/src/cpu/sparc/vm/assembler_sparc.cpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/assembler_sparc.cpp Tue Jun 27 15:46:16 2017 +0200
@@ -26,6 +26,36 @@
#include "asm/assembler.hpp"
#include "asm/assembler.inline.hpp"
+#include "assembler_sparc.hpp"
+
int AbstractAssembler::code_fill_byte() {
return 0x00; // illegal instruction 0x00000000
}
+
+#ifdef VALIDATE_PIPELINE
+/* Walk over the current code section and verify that there are no obvious
+ * pipeline hazards exposed in the code generated.
+ */
+void Assembler::validate_no_pipeline_hazards() {
+ const CodeSection* csect = code_section();
+
+ address addr0 = csect->start();
+ address addrN = csect->end();
+ uint32_t prev = 0;
+
+ assert((addrN - addr0) % BytesPerInstWord == 0, "must be");
+
+ for (address pc = addr0; pc != addrN; pc += BytesPerInstWord) {
+ uint32_t insn = *reinterpret_cast<uint32_t*>(pc);
+
+ // 1. General case: No CTI immediately after other CTI
+ assert(!(is_cti(prev) && is_cti(insn)), "CTI-CTI not allowed.");
+
+ // 2. Special case: No CTI immediately after/before RDPC
+ assert(!(is_cti(prev) && is_rdpc(insn)), "CTI-RDPC not allowed.");
+ assert(!(is_rdpc(prev) && is_cti(insn)), "RDPC-CTI not allowed.");
+
+ prev = insn;
+ }
+}
+#endif
--- a/hotspot/src/cpu/sparc/vm/assembler_sparc.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/assembler_sparc.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -28,10 +28,10 @@
#include "asm/register.hpp"
// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
-// level; i.e., what you write
-// is what you get. The Assembler is generating code into a CodeBuffer.
+// level; i.e., what you write is what you get. The Assembler is generating code
+// into a CodeBuffer.
-class Assembler : public AbstractAssembler {
+class Assembler : public AbstractAssembler {
friend class AbstractAssembler;
friend class AddressLiteral;
@@ -244,18 +244,18 @@
};
enum op5s {
- aes_eround01_op5 = 0x00,
- aes_eround23_op5 = 0x01,
- aes_dround01_op5 = 0x02,
- aes_dround23_op5 = 0x03,
- aes_eround01_l_op5 = 0x04,
- aes_eround23_l_op5 = 0x05,
- aes_dround01_l_op5 = 0x06,
- aes_dround23_l_op5 = 0x07,
- aes_kexpand1_op5 = 0x08
+ aes_eround01_op5 = 0x00,
+ aes_eround23_op5 = 0x01,
+ aes_dround01_op5 = 0x02,
+ aes_dround23_op5 = 0x03,
+ aes_eround01_l_op5 = 0x04,
+ aes_eround23_l_op5 = 0x05,
+ aes_dround01_l_op5 = 0x06,
+ aes_dround23_l_op5 = 0x07,
+ aes_kexpand1_op5 = 0x08
};
- enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
+ enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
enum Condition {
// for FBfcc & FBPfcc instruction
@@ -278,59 +278,38 @@
f_unorderedOrLessOrEqual = 14,
f_ordered = 15,
- // V8 coproc, pp 123 v8 manual
-
- cp_always = 8,
- cp_never = 0,
- cp_3 = 7,
- cp_2 = 6,
- cp_2or3 = 5,
- cp_1 = 4,
- cp_1or3 = 3,
- cp_1or2 = 2,
- cp_1or2or3 = 1,
- cp_0 = 9,
- cp_0or3 = 10,
- cp_0or2 = 11,
- cp_0or2or3 = 12,
- cp_0or1 = 13,
- cp_0or1or3 = 14,
- cp_0or1or2 = 15,
-
-
// for integers
- never = 0,
- equal = 1,
- zero = 1,
- lessEqual = 2,
- less = 3,
- lessEqualUnsigned = 4,
- lessUnsigned = 5,
- carrySet = 5,
- negative = 6,
- overflowSet = 7,
- always = 8,
- notEqual = 9,
- notZero = 9,
- greater = 10,
- greaterEqual = 11,
- greaterUnsigned = 12,
- greaterEqualUnsigned = 13,
- carryClear = 13,
- positive = 14,
- overflowClear = 15
+ never = 0,
+ equal = 1,
+ zero = 1,
+ lessEqual = 2,
+ less = 3,
+ lessEqualUnsigned = 4,
+ lessUnsigned = 5,
+ carrySet = 5,
+ negative = 6,
+ overflowSet = 7,
+ always = 8,
+ notEqual = 9,
+ notZero = 9,
+ greater = 10,
+ greaterEqual = 11,
+ greaterUnsigned = 12,
+ greaterEqualUnsigned = 13,
+ carryClear = 13,
+ positive = 14,
+ overflowClear = 15
};
enum CC {
- icc = 0, xcc = 2,
// ptr_cc is the correct condition code for a pointer or intptr_t:
- ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
- fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
+ icc = 0, xcc = 2, ptr_cc = xcc,
+ fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
};
enum PrefetchFcn {
- severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
+ severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
};
public:
@@ -354,7 +333,7 @@
return is_simm(d, nbits + 2);
}
- address target_distance(Label& L) {
+ address target_distance(Label &L) {
// Assembler::target(L) should be called only when
// a branch instruction is emitted since non-bound
// labels record current pc() as a branch address.
@@ -364,7 +343,7 @@
}
// test if label is in simm16 range in words (wdisp16).
- bool is_in_wdisp16_range(Label& L) {
+ bool is_in_wdisp16_range(Label &L) {
return is_in_wdisp_range(target_distance(L), pc(), 16);
}
// test if the distance between two addresses fits in simm30 range in words
@@ -392,41 +371,39 @@
// and be sign-extended. Check the range.
static void assert_signed_range(intptr_t x, int nbits) {
- assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
+ assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
"value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
}
static void assert_signed_word_disp_range(intptr_t x, int nbits) {
- assert( (x & 3) == 0, "not word aligned");
+ assert((x & 3) == 0, "not word aligned");
assert_signed_range(x, nbits + 2);
}
static void assert_unsigned_const(int x, int nbits) {
- assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
+ assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
}
- // fields: note bits numbered from LSB = 0,
- // fields known by inclusive bit range
+ // fields: note bits numbered from LSB = 0, fields known by inclusive bit range
static int fmask(juint hi_bit, juint lo_bit) {
- assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
- return (1 << ( hi_bit-lo_bit + 1 )) - 1;
+ assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
+ return (1 << (hi_bit-lo_bit + 1)) - 1;
}
// inverse of u_field
static int inv_u_field(int x, int hi_bit, int lo_bit) {
juint r = juint(x) >> lo_bit;
- r &= fmask( hi_bit, lo_bit);
+ r &= fmask(hi_bit, lo_bit);
return int(r);
}
-
// signed version: extract from field and sign-extend
static int inv_s_field(int x, int hi_bit, int lo_bit) {
int sign_shift = 31 - hi_bit;
- return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
+ return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
}
// given a field that ranges from hi_bit to lo_bit (inclusive,
@@ -435,72 +412,102 @@
#ifdef ASSERT
static int u_field(int x, int hi_bit, int lo_bit) {
- assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
+ assert((x & ~fmask(hi_bit, lo_bit)) == 0,
"value out of range");
int r = x << lo_bit;
- assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
+ assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
return r;
}
#else
// make sure this is inlined as it will reduce code size significantly
- #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
+ #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
#endif
- static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
- static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
- static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
- static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
+ static int inv_op(int x) { return inv_u_field(x, 31, 30); }
+ static int inv_op2(int x) { return inv_u_field(x, 24, 22); }
+ static int inv_op3(int x) { return inv_u_field(x, 24, 19); }
+ static int inv_cond(int x) { return inv_u_field(x, 28, 25); }
- static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
+ static bool inv_immed(int x) { return (x & Assembler::immed(true)) != 0; }
- static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
- static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
- static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
+ static Register inv_rd(int x) { return as_Register(inv_u_field(x, 29, 25)); }
+ static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); }
+ static Register inv_rs2(int x) { return as_Register(inv_u_field(x, 4, 0)); }
- static int op( int x) { return u_field(x, 31, 30); }
- static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
- static int fcn( int x) { return u_field(x, 29, 25); }
- static int op3( int x) { return u_field(x, 24, 19); }
- static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
- static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
- static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
- static int cond( int x) { return u_field(x, 28, 25); }
- static int cond_mov( int x) { return u_field(x, 17, 14); }
- static int rcond( RCondition x) { return u_field(x, 12, 10); }
- static int op2( int x) { return u_field(x, 24, 22); }
- static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
- static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
- static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
- static int imm_asi( int x) { return u_field(x, 12, 5); }
- static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
- static int opf_low6( int w) { return u_field(w, 10, 5); }
- static int opf_low5( int w) { return u_field(w, 9, 5); }
- static int op5( int x) { return u_field(x, 8, 5); }
- static int trapcc( CC cc) { return u_field(cc, 12, 11); }
- static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
- static int opf( int x) { return u_field(x, 13, 5); }
+ static int op(int x) { return u_field(x, 31, 30); }
+ static int rd(Register r) { return u_field(r->encoding(), 29, 25); }
+ static int fcn(int x) { return u_field(x, 29, 25); }
+ static int op3(int x) { return u_field(x, 24, 19); }
+ static int rs1(Register r) { return u_field(r->encoding(), 18, 14); }
+ static int rs2(Register r) { return u_field(r->encoding(), 4, 0); }
+ static int annul(bool a) { return u_field(a ? 1 : 0, 29, 29); }
+ static int cond(int x) { return u_field(x, 28, 25); }
+ static int cond_mov(int x) { return u_field(x, 17, 14); }
+ static int rcond(RCondition x) { return u_field(x, 12, 10); }
+ static int op2(int x) { return u_field(x, 24, 22); }
+ static int predict(bool p) { return u_field(p ? 1 : 0, 19, 19); }
+ static int branchcc(CC fcca) { return u_field(fcca, 21, 20); }
+ static int cmpcc(CC fcca) { return u_field(fcca, 26, 25); }
+ static int imm_asi(int x) { return u_field(x, 12, 5); }
+ static int immed(bool i) { return u_field(i ? 1 : 0, 13, 13); }
+ static int opf_low6(int w) { return u_field(w, 10, 5); }
+ static int opf_low5(int w) { return u_field(w, 9, 5); }
+ static int op5(int x) { return u_field(x, 8, 5); }
+ static int trapcc(CC cc) { return u_field(cc, 12, 11); }
+ static int sx(int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
+ static int opf(int x) { return u_field(x, 13, 5); }
- static bool is_cbcond( int x ) {
+ static bool is_cbcond(int x) {
return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
}
- static bool is_cxb( int x ) {
+ static bool is_cxb(int x) {
assert(is_cbcond(x), "wrong instruction");
- return (x & (1<<21)) != 0;
+ return (x & (1 << 21)) != 0;
+ }
+ static bool is_branch(int x) {
+ if (inv_op(x) != Assembler::branch_op) return false;
+
+ bool is_bpr = inv_op2(x) == Assembler::bpr_op2;
+ bool is_bp = inv_op2(x) == Assembler::bp_op2;
+ bool is_br = inv_op2(x) == Assembler::br_op2;
+ bool is_fp = inv_op2(x) == Assembler::fb_op2;
+ bool is_fbp = inv_op2(x) == Assembler::fbp_op2;
+
+ return is_bpr || is_bp || is_br || is_fp || is_fbp;
}
- static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
- static int inv_cond_cbcond(int x) {
- assert(is_cbcond(x), "wrong instruction");
- return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
+ static bool is_call(int x) {
+ return inv_op(x) == Assembler::call_op;
+ }
+ static bool is_jump(int x) {
+ if (inv_op(x) != Assembler::arith_op) return false;
+
+ bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3;
+ bool is_rett = inv_op3(x) == Assembler::rett_op3;
+
+ return is_jmpl || is_rett;
+ }
+ static bool is_rdpc(int x) {
+ return (inv_op(x) == Assembler::arith_op && inv_op3(x) == Assembler::rdreg_op3 &&
+ inv_u_field(x, 18, 14) == 5);
+ }
+ static bool is_cti(int x) {
+ return is_branch(x) || is_call(x) || is_jump(x); // Ignoring done/retry
}
- static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
- static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
+ static int cond_cbcond(int x) { return u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); }
+ static int inv_cond_cbcond(int x) {
+ assert(is_cbcond(x), "wrong instruction");
+ return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3);
+ }
- static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
- static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
- static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
- static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
+ static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
+ static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
+
+ static int fd(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
+ static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
+ static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
+ static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
// some float instructions use this encoding on the op3 field
static int alt_op3(int op, FloatRegisterImpl::Width w) {
@@ -514,23 +521,22 @@
return op3(r);
}
-
// compute inverse of simm
static int inv_simm(int x, int nbits) {
return (int)(x << (32 - nbits)) >> (32 - nbits);
}
- static int inv_simm13( int x ) { return inv_simm(x, 13); }
+ static int inv_simm13(int x) { return inv_simm(x, 13); }
// signed immediate, in low bits, nbits long
static int simm(int x, int nbits) {
assert_signed_range(x, nbits);
- return x & (( 1 << nbits ) - 1);
+ return x & ((1 << nbits) - 1);
}
// compute inverse of wdisp16
static intptr_t inv_wdisp16(int x, intptr_t pos) {
- int lo = x & (( 1 << 14 ) - 1);
+ int lo = x & ((1 << 14) - 1);
int hi = (x >> 20) & 3;
if (hi >= 2) hi |= ~1;
return (((hi << 14) | lo) << 2) + pos;
@@ -540,9 +546,8 @@
static int wdisp16(intptr_t x, intptr_t off) {
intptr_t xx = x - off;
assert_signed_word_disp_range(xx, 16);
- int r = (xx >> 2) & ((1 << 14) - 1)
- | ( ( (xx>>(2+14)) & 3 ) << 20 );
- assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
+ int r = (xx >> 2) & ((1 << 14) - 1) | (((xx >> (2+14)) & 3) << 20);
+ assert(inv_wdisp16(r, off) == x, "inverse is not inverse");
return r;
}
@@ -560,254 +565,289 @@
assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
intptr_t xx = x - off;
assert_signed_word_disp_range(xx, 10);
- int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
- | ( ( (xx >> (2+8)) & 3 ) << 19 );
+ int r = (((xx >> 2) & ((1 << 8) - 1)) << 5) | (((xx >> (2+8)) & 3) << 19);
// Have to fake cbcond instruction to pass assert in inv_wdisp10()
- assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
+ assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
return r;
}
// word displacement in low-order nbits bits
- static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
- int pre_sign_extend = x & (( 1 << nbits ) - 1);
- int r = pre_sign_extend >= ( 1 << (nbits-1) )
- ? pre_sign_extend | ~(( 1 << nbits ) - 1)
- : pre_sign_extend;
+ static intptr_t inv_wdisp(int x, intptr_t pos, int nbits) {
+ int pre_sign_extend = x & ((1 << nbits) - 1);
+ int r = (pre_sign_extend >= (1 << (nbits - 1)) ?
+ pre_sign_extend | ~((1 << nbits) - 1) : pre_sign_extend);
return (r << 2) + pos;
}
- static int wdisp( intptr_t x, intptr_t off, int nbits ) {
+ static int wdisp(intptr_t x, intptr_t off, int nbits) {
intptr_t xx = x - off;
assert_signed_word_disp_range(xx, nbits);
- int r = (xx >> 2) & (( 1 << nbits ) - 1);
- assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
+ int r = (xx >> 2) & ((1 << nbits) - 1);
+ assert(inv_wdisp(r, off, nbits) == x, "inverse not inverse");
return r;
}
// Extract the top 32 bits in a 64 bit word
- static int32_t hi32( int64_t x ) {
- int32_t r = int32_t( (uint64_t)x >> 32 );
+ static int32_t hi32(int64_t x) {
+ int32_t r = int32_t((uint64_t)x >> 32);
return r;
}
// given a sethi instruction, extract the constant, left-justified
- static int inv_hi22( int x ) {
+ static int inv_hi22(int x) {
return x << 10;
}
// create an imm22 field, given a 32-bit left-justified constant
- static int hi22( int x ) {
- int r = int( juint(x) >> 10 );
- assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
+ static int hi22(int x) {
+ int r = int(juint(x) >> 10);
+ assert((r & ~((1 << 22) - 1)) == 0, "just checkin'");
return r;
}
// create a low10 __value__ (not a field) for a given a 32-bit constant
- static int low10( int x ) {
+ static int low10(int x) {
return x & ((1 << 10) - 1);
}
// create a low12 __value__ (not a field) for a given a 32-bit constant
- static int low12( int x ) {
+ static int low12(int x) {
return x & ((1 << 12) - 1);
}
// AES crypto instructions supported only on certain processors
- static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
+ static void aes_only() { assert(VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
// SHA crypto instructions supported only on certain processors
- static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
- static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
- static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
+ static void sha1_only() { assert(VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
+ static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
+ static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
// CRC32C instruction supported only on certain processors
- static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
+ static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
// instruction only in VIS1
- static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
+ static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
// instruction only in VIS2
- static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
+ static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
// instruction only in VIS3
- static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
+ static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
// instruction deprecated in v9
- static void v9_dep() { } // do nothing for now
+ static void v9_dep() { } // do nothing for now
protected:
- // Simple delay-slot scheme:
- // In order to check the programmer, the assembler keeps track of delay slots.
- // It forbids CTIs in delay slots (conservative, but should be OK).
- // Also, when putting an instruction into a delay slot, you must say
- // asm->delayed()->add(...), in order to check that you don't omit
- // delay-slot instructions.
- // To implement this, we use a simple FSA
+#ifdef ASSERT
+#define VALIDATE_PIPELINE
+#endif
-#ifdef ASSERT
- #define CHECK_DELAY
-#endif
-#ifdef CHECK_DELAY
- enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
+#ifdef VALIDATE_PIPELINE
+ // A simple delay-slot scheme:
+ // In order to check the programmer, the assembler keeps track of delay-slots.
+ // It forbids CTIs in delay-slots (conservative, but should be OK). Also, when
+ // emitting an instruction into a delay-slot, you must do so using delayed(),
+ // e.g. asm->delayed()->add(...), in order to check that you do not omit the
+ // delay-slot instruction. To implement this, we use a simple FSA.
+ enum { NoDelay, AtDelay, FillDelay } _delay_state;
+
+ // A simple hazard scheme:
+ // In order to avoid pipeline stalls, due to single cycle pipeline hazards, we
+ // adopt a simplistic state tracking mechanism that will enforce an additional
+ // 'nop' instruction to be inserted prior to emitting an instruction that can
+ // expose a given hazard (currently, PC-related hazards only).
+ enum { NoHazard, PcHazard } _hazard_state;
#endif
public:
- // Tells assembler next instruction must NOT be in delay slot.
- // Use at start of multinstruction macros.
+ // Tell the assembler that the next instruction must NOT be in delay-slot.
+ // Use at start of multi-instruction macros.
void assert_not_delayed() {
- // This is a separate overloading to avoid creation of string constants
- // in non-asserted code--with some compilers this pollutes the object code.
-#ifdef CHECK_DELAY
- assert_not_delayed("next instruction should not be a delay slot");
-#endif
- }
- void assert_not_delayed(const char* msg) {
-#ifdef CHECK_DELAY
- assert(delay_state == no_delay, msg);
+ // This is a separate entry to avoid the creation of string constants in
+ // non-asserted code, with some compilers this pollutes the object code.
+#ifdef VALIDATE_PIPELINE
+ assert_no_delay("Next instruction should not be in a delay-slot.");
#endif
}
protected:
- // Insert a nop if the previous is cbcond
- inline void insert_nop_after_cbcond();
+ void assert_no_delay(const char* msg) {
+#ifdef VALIDATE_PIPELINE
+ assert(_delay_state == NoDelay, msg);
+#endif
+ }
- // Delay slot helpers
- // cti is called when emitting control-transfer instruction,
- // BEFORE doing the emitting.
- // Only effective when assertion-checking is enabled.
- void cti() {
- // A cbcond instruction immediately followed by a CTI
- // instruction introduces pipeline stalls, we need to avoid that.
- no_cbcond_before();
-#ifdef CHECK_DELAY
- assert_not_delayed("cti should not be in delay slot");
+ void assert_no_hazard() {
+#ifdef VALIDATE_PIPELINE
+ assert(_hazard_state == NoHazard, "Unsolicited pipeline hazard.");
#endif
}
- // called when emitting cti with a delay slot, AFTER emitting
- void has_delay_slot() {
-#ifdef CHECK_DELAY
- assert_not_delayed("just checking");
- delay_state = at_delay_slot;
+ private:
+ inline int32_t prev_insn() {
+ assert(offset() > 0, "Interface violation.");
+ int32_t* addr = (int32_t*)pc() - 1;
+ return *addr;
+ }
+
+#ifdef VALIDATE_PIPELINE
+ void validate_no_pipeline_hazards();
+#endif
+
+ protected:
+ // Avoid possible pipeline stall by inserting an additional 'nop' instruction,
+ // if the previous instruction is a 'cbcond' or a 'rdpc'.
+ inline void avoid_pipeline_stall();
+
+ // A call to cti() is made before emitting a control-transfer instruction (CTI)
+ // in order to assert a CTI is not emitted right after a 'cbcond', nor in the
+ // delay-slot of another CTI. Only effective when assertions are enabled.
+ void cti() {
+ // A 'cbcond' or 'rdpc' instruction immediately followed by a CTI introduces
+ // a pipeline stall, which we make sure to prohibit.
+ assert_no_cbcond_before();
+ assert_no_rdpc_before();
+#ifdef VALIDATE_PIPELINE
+ assert_no_hazard();
+ assert_no_delay("CTI in delay-slot.");
#endif
}
- // cbcond instruction should not be generated one after an other
- bool cbcond_before() {
- if (offset() == 0) return false; // it is first instruction
- int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
- return is_cbcond(x);
+ // Called when emitting CTI with a delay-slot, AFTER emitting.
+ inline void induce_delay_slot() {
+#ifdef VALIDATE_PIPELINE
+ assert_no_delay("Already in delay-slot.");
+ _delay_state = AtDelay;
+#endif
+ }
+
+ inline void induce_pc_hazard() {
+#ifdef VALIDATE_PIPELINE
+ assert_no_hazard();
+ _hazard_state = PcHazard;
+#endif
}
- void no_cbcond_before() {
- assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
+ bool is_cbcond_before() { return offset() > 0 ? is_cbcond(prev_insn()) : false; }
+
+ bool is_rdpc_before() { return offset() > 0 ? is_rdpc(prev_insn()) : false; }
+
+ void assert_no_cbcond_before() {
+ assert(offset() == 0 || !is_cbcond_before(), "CBCOND should not be followed by CTI.");
}
-public:
- bool use_cbcond(Label& L) {
- if (!UseCBCond || cbcond_before()) return false;
+ void assert_no_rdpc_before() {
+ assert(offset() == 0 || !is_rdpc_before(), "RDPC should not be followed by CTI.");
+ }
+
+ public:
+
+ bool use_cbcond(Label &L) {
+ if (!UseCBCond || is_cbcond_before()) return false;
intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
- assert( (x & 3) == 0, "not word aligned");
+ assert((x & 3) == 0, "not word aligned");
return is_simm12(x);
}
// Tells assembler you know that next instruction is delayed
Assembler* delayed() {
-#ifdef CHECK_DELAY
- assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
- delay_state = filling_delay_slot;
+#ifdef VALIDATE_PIPELINE
+ assert(_delay_state == AtDelay, "Delayed instruction not in delay-slot.");
+ _delay_state = FillDelay;
#endif
return this;
}
void flush() {
-#ifdef CHECK_DELAY
- assert ( delay_state == no_delay, "ending code with a delay slot");
+#ifdef VALIDATE_PIPELINE
+ assert(_delay_state == NoDelay, "Ending code with a delay-slot.");
+ validate_no_pipeline_hazards();
#endif
AbstractAssembler::flush();
}
inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
- inline void emit_data(int x);
- inline void emit_data(int, RelocationHolder const&);
+ inline void emit_data(int);
+ inline void emit_data(int, RelocationHolder const &rspec);
inline void emit_data(int, relocInfo::relocType rtype);
- // helper for above fcns
+ // helper for above functions
inline void check_delay();
public:
// instructions, refer to page numbers in the SPARC Architecture Manual, V9
- // pp 135 (addc was addx in v8)
+ // pp 135
- inline void add(Register s1, Register s2, Register d );
- inline void add(Register s1, int simm13a, Register d );
+ inline void add(Register s1, Register s2, Register d);
+ inline void add(Register s1, int simm13a, Register d);
- inline void addcc( Register s1, Register s2, Register d );
- inline void addcc( Register s1, int simm13a, Register d );
- inline void addc( Register s1, Register s2, Register d );
- inline void addc( Register s1, int simm13a, Register d );
- inline void addccc( Register s1, Register s2, Register d );
- inline void addccc( Register s1, int simm13a, Register d );
+ inline void addcc(Register s1, Register s2, Register d);
+ inline void addcc(Register s1, int simm13a, Register d);
+ inline void addc(Register s1, Register s2, Register d);
+ inline void addc(Register s1, int simm13a, Register d);
+ inline void addccc(Register s1, Register s2, Register d);
+ inline void addccc(Register s1, int simm13a, Register d);
// 4-operand AES instructions
- inline void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
- inline void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d );
+ inline void aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
+ inline void aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d);
// 3-operand AES instructions
- inline void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d );
- inline void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d);
+ inline void aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d);
// pp 136
inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
- inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
+ inline void bpr(RCondition c, bool a, Predict p, Register s1, Label &L);
// compare and branch
- inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
- inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
+ inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label &L);
+ inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label &L);
protected: // use MacroAssembler::br instead
// pp 138
- inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
- inline void fb( Condition c, bool a, Label& L );
+ inline void fb(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
+ inline void fb(Condition c, bool a, Label &L);
// pp 141
- inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
- inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
+ inline void fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
+ inline void fbp(Condition c, bool a, CC cc, Predict p, Label &L);
// pp 144
- inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
- inline void br( Condition c, bool a, Label& L );
+ inline void br(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
+ inline void br(Condition c, bool a, Label &L);
// pp 146
- inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
- inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
+ inline void bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
+ inline void bp(Condition c, bool a, CC cc, Predict p, Label &L);
// pp 149
- inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
- inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
+ inline void call(address d, relocInfo::relocType rt = relocInfo::runtime_call_type);
+ inline void call(Label &L, relocInfo::relocType rt = relocInfo::runtime_call_type);
- inline void call( address d, RelocationHolder const& rspec );
+ inline void call(address d, RelocationHolder const &rspec);
public:
@@ -818,19 +858,19 @@
// at address s1 is swapped with the data in d. If the values are not equal,
// the the contents of memory at s1 is loaded into d, without the swap.
- inline void casa( Register s1, Register s2, Register d, int ia = -1 );
- inline void casxa( Register s1, Register s2, Register d, int ia = -1 );
+ inline void casa(Register s1, Register s2, Register d, int ia = -1);
+ inline void casxa(Register s1, Register s2, Register d, int ia = -1);
// pp 152
- inline void udiv( Register s1, Register s2, Register d );
- inline void udiv( Register s1, int simm13a, Register d );
- inline void sdiv( Register s1, Register s2, Register d );
- inline void sdiv( Register s1, int simm13a, Register d );
- inline void udivcc( Register s1, Register s2, Register d );
- inline void udivcc( Register s1, int simm13a, Register d );
- inline void sdivcc( Register s1, Register s2, Register d );
- inline void sdivcc( Register s1, int simm13a, Register d );
+ inline void udiv(Register s1, Register s2, Register d);
+ inline void udiv(Register s1, int simm13a, Register d);
+ inline void sdiv(Register s1, Register s2, Register d);
+ inline void sdiv(Register s1, int simm13a, Register d);
+ inline void udivcc(Register s1, Register s2, Register d);
+ inline void udivcc(Register s1, int simm13a, Register d);
+ inline void sdivcc(Register s1, Register s2, Register d);
+ inline void sdivcc(Register s1, int simm13a, Register d);
// pp 155
@@ -839,54 +879,54 @@
// pp 156
- inline void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
- inline void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
+ inline void fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
// pp 157
- inline void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
- inline void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
+ inline void fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
+ inline void fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
// pp 159
- inline void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
- inline void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
+ inline void ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
// pp 160
- inline void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d );
+ inline void ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d);
// pp 161
- inline void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
- inline void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
+ inline void fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
// pp 162
- inline void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
- inline void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
- inline void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
// pp 163
- inline void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
- inline void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d );
- inline void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
+ inline void fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d);
+ inline void fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
// FXORs/FXORd instructions
- inline void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
// pp 164
- inline void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
+ inline void fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
// pp 165
- inline void flush( Register s1, Register s2 );
- inline void flush( Register s1, int simm13a);
+ inline void flush(Register s1, Register s2);
+ inline void flush(Register s1, int simm13a);
// pp 167
@@ -894,139 +934,140 @@
// pp 168
- void illtrap( int const22a);
- // v8 unimp == illtrap(0)
+ void illtrap(int const22a);
// pp 169
- void impdep1( int id1, int const19a );
- void impdep2( int id1, int const19a );
+ void impdep1(int id1, int const19a);
+ void impdep2(int id1, int const19a);
// pp 170
- void jmpl( Register s1, Register s2, Register d );
- void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
+ void jmpl(Register s1, Register s2, Register d);
+ void jmpl(Register s1, int simm13a, Register d,
+ RelocationHolder const &rspec = RelocationHolder());
// 171
inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
- inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
+ inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d,
+ RelocationHolder const &rspec = RelocationHolder());
- inline void ldfsr( Register s1, Register s2 );
- inline void ldfsr( Register s1, int simm13a);
- inline void ldxfsr( Register s1, Register s2 );
- inline void ldxfsr( Register s1, int simm13a);
+ inline void ldfsr(Register s1, Register s2);
+ inline void ldfsr(Register s1, int simm13a);
+ inline void ldxfsr(Register s1, Register s2);
+ inline void ldxfsr(Register s1, int simm13a);
// 173
- inline void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d );
- inline void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
+ inline void ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d);
+ inline void ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d);
- // pp 175, lduw is ld on v8
+ // pp 175
- inline void ldsb( Register s1, Register s2, Register d );
- inline void ldsb( Register s1, int simm13a, Register d);
- inline void ldsh( Register s1, Register s2, Register d );
- inline void ldsh( Register s1, int simm13a, Register d);
- inline void ldsw( Register s1, Register s2, Register d );
- inline void ldsw( Register s1, int simm13a, Register d);
- inline void ldub( Register s1, Register s2, Register d );
- inline void ldub( Register s1, int simm13a, Register d);
- inline void lduh( Register s1, Register s2, Register d );
- inline void lduh( Register s1, int simm13a, Register d);
- inline void lduw( Register s1, Register s2, Register d );
- inline void lduw( Register s1, int simm13a, Register d);
- inline void ldx( Register s1, Register s2, Register d );
- inline void ldx( Register s1, int simm13a, Register d);
- inline void ldd( Register s1, Register s2, Register d );
- inline void ldd( Register s1, int simm13a, Register d);
+ inline void ldsb(Register s1, Register s2, Register d);
+ inline void ldsb(Register s1, int simm13a, Register d);
+ inline void ldsh(Register s1, Register s2, Register d);
+ inline void ldsh(Register s1, int simm13a, Register d);
+ inline void ldsw(Register s1, Register s2, Register d);
+ inline void ldsw(Register s1, int simm13a, Register d);
+ inline void ldub(Register s1, Register s2, Register d);
+ inline void ldub(Register s1, int simm13a, Register d);
+ inline void lduh(Register s1, Register s2, Register d);
+ inline void lduh(Register s1, int simm13a, Register d);
+ inline void lduw(Register s1, Register s2, Register d);
+ inline void lduw(Register s1, int simm13a, Register d);
+ inline void ldx(Register s1, Register s2, Register d);
+ inline void ldx(Register s1, int simm13a, Register d);
+ inline void ldd(Register s1, Register s2, Register d);
+ inline void ldd(Register s1, int simm13a, Register d);
// pp 177
- inline void ldsba( Register s1, Register s2, int ia, Register d );
- inline void ldsba( Register s1, int simm13a, Register d );
- inline void ldsha( Register s1, Register s2, int ia, Register d );
- inline void ldsha( Register s1, int simm13a, Register d );
- inline void ldswa( Register s1, Register s2, int ia, Register d );
- inline void ldswa( Register s1, int simm13a, Register d );
- inline void lduba( Register s1, Register s2, int ia, Register d );
- inline void lduba( Register s1, int simm13a, Register d );
- inline void lduha( Register s1, Register s2, int ia, Register d );
- inline void lduha( Register s1, int simm13a, Register d );
- inline void lduwa( Register s1, Register s2, int ia, Register d );
- inline void lduwa( Register s1, int simm13a, Register d );
- inline void ldxa( Register s1, Register s2, int ia, Register d );
- inline void ldxa( Register s1, int simm13a, Register d );
+ inline void ldsba(Register s1, Register s2, int ia, Register d);
+ inline void ldsba(Register s1, int simm13a, Register d);
+ inline void ldsha(Register s1, Register s2, int ia, Register d);
+ inline void ldsha(Register s1, int simm13a, Register d);
+ inline void ldswa(Register s1, Register s2, int ia, Register d);
+ inline void ldswa(Register s1, int simm13a, Register d);
+ inline void lduba(Register s1, Register s2, int ia, Register d);
+ inline void lduba(Register s1, int simm13a, Register d);
+ inline void lduha(Register s1, Register s2, int ia, Register d);
+ inline void lduha(Register s1, int simm13a, Register d);
+ inline void lduwa(Register s1, Register s2, int ia, Register d);
+ inline void lduwa(Register s1, int simm13a, Register d);
+ inline void ldxa(Register s1, Register s2, int ia, Register d);
+ inline void ldxa(Register s1, int simm13a, Register d);
// pp 181
- inline void and3( Register s1, Register s2, Register d );
- inline void and3( Register s1, int simm13a, Register d );
- inline void andcc( Register s1, Register s2, Register d );
- inline void andcc( Register s1, int simm13a, Register d );
- inline void andn( Register s1, Register s2, Register d );
- inline void andn( Register s1, int simm13a, Register d );
- inline void andncc( Register s1, Register s2, Register d );
- inline void andncc( Register s1, int simm13a, Register d );
- inline void or3( Register s1, Register s2, Register d );
- inline void or3( Register s1, int simm13a, Register d );
- inline void orcc( Register s1, Register s2, Register d );
- inline void orcc( Register s1, int simm13a, Register d );
- inline void orn( Register s1, Register s2, Register d );
- inline void orn( Register s1, int simm13a, Register d );
- inline void orncc( Register s1, Register s2, Register d );
- inline void orncc( Register s1, int simm13a, Register d );
- inline void xor3( Register s1, Register s2, Register d );
- inline void xor3( Register s1, int simm13a, Register d );
- inline void xorcc( Register s1, Register s2, Register d );
- inline void xorcc( Register s1, int simm13a, Register d );
- inline void xnor( Register s1, Register s2, Register d );
- inline void xnor( Register s1, int simm13a, Register d );
- inline void xnorcc( Register s1, Register s2, Register d );
- inline void xnorcc( Register s1, int simm13a, Register d );
+ inline void and3(Register s1, Register s2, Register d);
+ inline void and3(Register s1, int simm13a, Register d);
+ inline void andcc(Register s1, Register s2, Register d);
+ inline void andcc(Register s1, int simm13a, Register d);
+ inline void andn(Register s1, Register s2, Register d);
+ inline void andn(Register s1, int simm13a, Register d);
+ inline void andncc(Register s1, Register s2, Register d);
+ inline void andncc(Register s1, int simm13a, Register d);
+ inline void or3(Register s1, Register s2, Register d);
+ inline void or3(Register s1, int simm13a, Register d);
+ inline void orcc(Register s1, Register s2, Register d);
+ inline void orcc(Register s1, int simm13a, Register d);
+ inline void orn(Register s1, Register s2, Register d);
+ inline void orn(Register s1, int simm13a, Register d);
+ inline void orncc(Register s1, Register s2, Register d);
+ inline void orncc(Register s1, int simm13a, Register d);
+ inline void xor3(Register s1, Register s2, Register d);
+ inline void xor3(Register s1, int simm13a, Register d);
+ inline void xorcc(Register s1, Register s2, Register d);
+ inline void xorcc(Register s1, int simm13a, Register d);
+ inline void xnor(Register s1, Register s2, Register d);
+ inline void xnor(Register s1, int simm13a, Register d);
+ inline void xnorcc(Register s1, Register s2, Register d);
+ inline void xnorcc(Register s1, int simm13a, Register d);
// pp 183
- inline void membar( Membar_mask_bits const7a );
+ inline void membar(Membar_mask_bits const7a);
// pp 185
- inline void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d );
+ inline void fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d);
// pp 189
- inline void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d );
+ inline void fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d);
// pp 191
- inline void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d );
- inline void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d );
+ inline void movcc(Condition c, bool floatCC, CC cca, Register s2, Register d);
+ inline void movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d);
// pp 195
- inline void movr( RCondition c, Register s1, Register s2, Register d );
- inline void movr( RCondition c, Register s1, int simm10a, Register d );
+ inline void movr(RCondition c, Register s1, Register s2, Register d);
+ inline void movr(RCondition c, Register s1, int simm10a, Register d);
// pp 196
- inline void mulx( Register s1, Register s2, Register d );
- inline void mulx( Register s1, int simm13a, Register d );
- inline void sdivx( Register s1, Register s2, Register d );
- inline void sdivx( Register s1, int simm13a, Register d );
- inline void udivx( Register s1, Register s2, Register d );
- inline void udivx( Register s1, int simm13a, Register d );
+ inline void mulx(Register s1, Register s2, Register d);
+ inline void mulx(Register s1, int simm13a, Register d);
+ inline void sdivx(Register s1, Register s2, Register d);
+ inline void sdivx(Register s1, int simm13a, Register d);
+ inline void udivx(Register s1, Register s2, Register d);
+ inline void udivx(Register s1, int simm13a, Register d);
// pp 197
- inline void umul( Register s1, Register s2, Register d );
- inline void umul( Register s1, int simm13a, Register d );
- inline void smul( Register s1, Register s2, Register d );
- inline void smul( Register s1, int simm13a, Register d );
- inline void umulcc( Register s1, Register s2, Register d );
- inline void umulcc( Register s1, int simm13a, Register d );
- inline void smulcc( Register s1, Register s2, Register d );
- inline void smulcc( Register s1, int simm13a, Register d );
+ inline void umul(Register s1, Register s2, Register d);
+ inline void umul(Register s1, int simm13a, Register d);
+ inline void smul(Register s1, Register s2, Register d);
+ inline void smul(Register s1, int simm13a, Register d);
+ inline void umulcc(Register s1, Register s2, Register d);
+ inline void umulcc(Register s1, int simm13a, Register d);
+ inline void smulcc(Register s1, Register s2, Register d);
+ inline void smulcc(Register s1, int simm13a, Register d);
// pp 201
@@ -1036,40 +1077,40 @@
// pp 202
- inline void popc( Register s, Register d);
- inline void popc( int simm13a, Register d);
+ inline void popc(Register s, Register d);
+ inline void popc(int simm13a, Register d);
// pp 203
- inline void prefetch( Register s1, Register s2, PrefetchFcn f);
- inline void prefetch( Register s1, int simm13a, PrefetchFcn f);
+ inline void prefetch(Register s1, Register s2, PrefetchFcn f);
+ inline void prefetch(Register s1, int simm13a, PrefetchFcn f);
- inline void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f );
- inline void prefetcha( Register s1, int simm13a, PrefetchFcn f );
+ inline void prefetcha(Register s1, Register s2, int ia, PrefetchFcn f);
+ inline void prefetcha(Register s1, int simm13a, PrefetchFcn f);
// pp 208
// not implementing read privileged register
- inline void rdy( Register d);
- inline void rdccr( Register d);
- inline void rdasi( Register d);
- inline void rdtick( Register d);
- inline void rdpc( Register d);
- inline void rdfprs( Register d);
+ inline void rdy(Register d);
+ inline void rdccr(Register d);
+ inline void rdasi(Register d);
+ inline void rdtick(Register d);
+ inline void rdpc(Register d);
+ inline void rdfprs(Register d);
// pp 213
- inline void rett( Register s1, Register s2);
- inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
+ inline void rett(Register s1, Register s2);
+ inline void rett(Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
// pp 214
- inline void save( Register s1, Register s2, Register d );
- inline void save( Register s1, int simm13a, Register d );
+ inline void save(Register s1, Register s2, Register d);
+ inline void save(Register s1, int simm13a, Register d);
- inline void restore( Register s1 = G0, Register s2 = G0, Register d = G0 );
- inline void restore( Register s1, int simm13a, Register d );
+ inline void restore(Register s1 = G0, Register s2 = G0, Register d = G0);
+ inline void restore(Register s1, int simm13a, Register d);
// pp 216
@@ -1078,26 +1119,27 @@
// pp 217
- inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
+ inline void sethi(int imm22a, Register d, RelocationHolder const &rspec = RelocationHolder());
+
// pp 218
- inline void sll( Register s1, Register s2, Register d );
- inline void sll( Register s1, int imm5a, Register d );
- inline void srl( Register s1, Register s2, Register d );
- inline void srl( Register s1, int imm5a, Register d );
- inline void sra( Register s1, Register s2, Register d );
- inline void sra( Register s1, int imm5a, Register d );
+ inline void sll(Register s1, Register s2, Register d);
+ inline void sll(Register s1, int imm5a, Register d);
+ inline void srl(Register s1, Register s2, Register d);
+ inline void srl(Register s1, int imm5a, Register d);
+ inline void sra(Register s1, Register s2, Register d);
+ inline void sra(Register s1, int imm5a, Register d);
- inline void sllx( Register s1, Register s2, Register d );
- inline void sllx( Register s1, int imm6a, Register d );
- inline void srlx( Register s1, Register s2, Register d );
- inline void srlx( Register s1, int imm6a, Register d );
- inline void srax( Register s1, Register s2, Register d );
- inline void srax( Register s1, int imm6a, Register d );
+ inline void sllx(Register s1, Register s2, Register d);
+ inline void sllx(Register s1, int imm6a, Register d);
+ inline void srlx(Register s1, Register s2, Register d);
+ inline void srlx(Register s1, int imm6a, Register d);
+ inline void srax(Register s1, Register s2, Register d);
+ inline void srax(Register s1, int imm6a, Register d);
// pp 220
- inline void sir( int simm13a );
+ inline void sir(int simm13a);
// pp 221
@@ -1105,125 +1147,125 @@
// pp 222
- inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
- inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
+ inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
+ inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
- inline void stfsr( Register s1, Register s2 );
- inline void stfsr( Register s1, int simm13a);
- inline void stxfsr( Register s1, Register s2 );
- inline void stxfsr( Register s1, int simm13a);
+ inline void stfsr(Register s1, Register s2);
+ inline void stfsr(Register s1, int simm13a);
+ inline void stxfsr(Register s1, Register s2);
+ inline void stxfsr(Register s1, int simm13a);
- // pp 224
+ // pp 224
- inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia );
- inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a );
+ inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia);
+ inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
- // p 226
+ // pp 226
- inline void stb( Register d, Register s1, Register s2 );
- inline void stb( Register d, Register s1, int simm13a);
- inline void sth( Register d, Register s1, Register s2 );
- inline void sth( Register d, Register s1, int simm13a);
- inline void stw( Register d, Register s1, Register s2 );
- inline void stw( Register d, Register s1, int simm13a);
- inline void stx( Register d, Register s1, Register s2 );
- inline void stx( Register d, Register s1, int simm13a);
- inline void std( Register d, Register s1, Register s2 );
- inline void std( Register d, Register s1, int simm13a);
+ inline void stb(Register d, Register s1, Register s2);
+ inline void stb(Register d, Register s1, int simm13a);
+ inline void sth(Register d, Register s1, Register s2);
+ inline void sth(Register d, Register s1, int simm13a);
+ inline void stw(Register d, Register s1, Register s2);
+ inline void stw(Register d, Register s1, int simm13a);
+ inline void stx(Register d, Register s1, Register s2);
+ inline void stx(Register d, Register s1, int simm13a);
+ inline void std(Register d, Register s1, Register s2);
+ inline void std(Register d, Register s1, int simm13a);
// pp 177
- inline void stba( Register d, Register s1, Register s2, int ia );
- inline void stba( Register d, Register s1, int simm13a );
- inline void stha( Register d, Register s1, Register s2, int ia );
- inline void stha( Register d, Register s1, int simm13a );
- inline void stwa( Register d, Register s1, Register s2, int ia );
- inline void stwa( Register d, Register s1, int simm13a );
- inline void stxa( Register d, Register s1, Register s2, int ia );
- inline void stxa( Register d, Register s1, int simm13a );
- inline void stda( Register d, Register s1, Register s2, int ia );
- inline void stda( Register d, Register s1, int simm13a );
+ inline void stba(Register d, Register s1, Register s2, int ia);
+ inline void stba(Register d, Register s1, int simm13a);
+ inline void stha(Register d, Register s1, Register s2, int ia);
+ inline void stha(Register d, Register s1, int simm13a);
+ inline void stwa(Register d, Register s1, Register s2, int ia);
+ inline void stwa(Register d, Register s1, int simm13a);
+ inline void stxa(Register d, Register s1, Register s2, int ia);
+ inline void stxa(Register d, Register s1, int simm13a);
+ inline void stda(Register d, Register s1, Register s2, int ia);
+ inline void stda(Register d, Register s1, int simm13a);
// pp 230
- inline void sub( Register s1, Register s2, Register d );
- inline void sub( Register s1, int simm13a, Register d );
+ inline void sub(Register s1, Register s2, Register d);
+ inline void sub(Register s1, int simm13a, Register d);
- inline void subcc( Register s1, Register s2, Register d );
- inline void subcc( Register s1, int simm13a, Register d );
- inline void subc( Register s1, Register s2, Register d );
- inline void subc( Register s1, int simm13a, Register d );
- inline void subccc( Register s1, Register s2, Register d );
- inline void subccc( Register s1, int simm13a, Register d );
+ inline void subcc(Register s1, Register s2, Register d);
+ inline void subcc(Register s1, int simm13a, Register d);
+ inline void subc(Register s1, Register s2, Register d);
+ inline void subc(Register s1, int simm13a, Register d);
+ inline void subccc(Register s1, Register s2, Register d);
+ inline void subccc(Register s1, int simm13a, Register d);
// pp 231
- inline void swap( Register s1, Register s2, Register d );
- inline void swap( Register s1, int simm13a, Register d);
+ inline void swap(Register s1, Register s2, Register d);
+ inline void swap(Register s1, int simm13a, Register d);
// pp 232
- inline void swapa( Register s1, Register s2, int ia, Register d );
- inline void swapa( Register s1, int simm13a, Register d );
+ inline void swapa(Register s1, Register s2, int ia, Register d);
+ inline void swapa(Register s1, int simm13a, Register d);
// pp 234, note op in book is wrong, see pp 268
- inline void taddcc( Register s1, Register s2, Register d );
- inline void taddcc( Register s1, int simm13a, Register d );
+ inline void taddcc(Register s1, Register s2, Register d);
+ inline void taddcc(Register s1, int simm13a, Register d);
// pp 235
- inline void tsubcc( Register s1, Register s2, Register d );
- inline void tsubcc( Register s1, int simm13a, Register d );
+ inline void tsubcc(Register s1, Register s2, Register d);
+ inline void tsubcc(Register s1, int simm13a, Register d);
// pp 237
- inline void trap( Condition c, CC cc, Register s1, Register s2 );
- inline void trap( Condition c, CC cc, Register s1, int trapa );
+ inline void trap(Condition c, CC cc, Register s1, Register s2);
+ inline void trap(Condition c, CC cc, Register s1, int trapa);
// simple uncond. trap
- inline void trap( int trapa );
+ inline void trap(int trapa);
// pp 239 omit write priv register for now
- inline void wry( Register d);
+ inline void wry(Register d);
inline void wrccr(Register s);
inline void wrccr(Register s, int simm13a);
inline void wrasi(Register d);
// wrasi(d, imm) stores (d xor imm) to asi
inline void wrasi(Register d, int simm13a);
- inline void wrfprs( Register d);
+ inline void wrfprs(Register d);
- // VIS1 instructions
+ // VIS1 instructions
- inline void alignaddr( Register s1, Register s2, Register d );
+ inline void alignaddr(Register s1, Register s2, Register d);
- inline void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d);
- inline void fzero( FloatRegisterImpl::Width w, FloatRegister d );
+ inline void fzero(FloatRegisterImpl::Width w, FloatRegister d);
- inline void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d );
+ inline void fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d);
- inline void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d );
+ inline void fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d);
- inline void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d);
- inline void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 );
+ inline void stpartialf(Register s1, Register s2, FloatRegister d, int ia = -1);
- // VIS2 instructions
+ // VIS2 instructions
- inline void edge8n( Register s1, Register s2, Register d );
+ inline void edge8n(Register s1, Register s2, Register d);
- inline void bmask( Register s1, Register s2, Register d );
- inline void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void bmask(Register s1, Register s2, Register d);
+ inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d);
// VIS3 instructions
- inline void movstosw( FloatRegister s, Register d );
- inline void movstouw( FloatRegister s, Register d );
- inline void movdtox( FloatRegister s, Register d );
+ inline void movstosw(FloatRegister s, Register d);
+ inline void movstouw(FloatRegister s, Register d);
+ inline void movdtox(FloatRegister s, Register d);
- inline void movwtos( Register s, FloatRegister d );
- inline void movxtod( Register s, FloatRegister d );
+ inline void movwtos(Register s, FloatRegister d);
+ inline void movxtod(Register s, FloatRegister d);
inline void xmulx(Register s1, Register s2, Register d);
inline void xmulxhi(Register s1, Register s2, Register d);
@@ -1236,12 +1278,13 @@
// CRC32C instruction
- inline void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d );
+ inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
// Creation
Assembler(CodeBuffer* code) : AbstractAssembler(code) {
-#ifdef CHECK_DELAY
- delay_state = no_delay;
+#ifdef VALIDATE_PIPELINE
+ _delay_state = NoDelay;
+ _hazard_state = NoHazard;
#endif
}
};
--- a/hotspot/src/cpu/sparc/vm/assembler_sparc.inline.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/assembler_sparc.inline.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -28,21 +28,42 @@
#include "asm/assembler.hpp"
-inline void Assembler::insert_nop_after_cbcond() {
- if (UseCBCond && cbcond_before()) {
+inline void Assembler::avoid_pipeline_stall() {
+#ifdef VALIDATE_PIPELINE
+ if (_hazard_state == PcHazard) {
+ assert(is_cbcond_before() || is_rdpc_before(), "PC-hazard not preceeded by CBCOND or RDPC.");
+ assert_no_delay("Must not have PC-hazard state in delay-slot.");
nop();
+ _hazard_state = NoHazard;
+ }
+#endif
+
+ bool post_cond = is_cbcond_before();
+ bool post_rdpc = is_rdpc_before();
+
+ if (post_cond || post_rdpc) {
+ nop();
+#ifdef VALIDATE_PIPELINE
+ if (_hazard_state != PcHazard) {
+ assert(post_cond, "CBCOND before when no hazard @0x%p\n", pc());
+ assert(post_rdpc, "RDPC before when no hazard @0x%p\n", pc());
+ }
+#endif
}
}
inline void Assembler::check_delay() {
-# ifdef CHECK_DELAY
- guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
- delay_state = no_delay;
-# endif
+#ifdef VALIDATE_PIPELINE
+ guarantee(_delay_state != AtDelay, "Use delayed() when filling delay-slot");
+ _delay_state = NoDelay;
+#endif
}
inline void Assembler::emit_int32(int x) {
check_delay();
+#ifdef VALIDATE_PIPELINE
+ _hazard_state = NoHazard;
+#endif
AbstractAssembler::emit_int32(x);
}
@@ -55,394 +76,1019 @@
emit_int32(x);
}
-inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
+inline void Assembler::emit_data(int x, RelocationHolder const &rspec) {
relocate(rspec);
emit_int32(x);
}
-inline void Assembler::add(Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::add(Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::add(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::add(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::addcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::addcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::addc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::addc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::addccc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::addccc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
-
+inline void Assembler::aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D));
+}
// 3-operand AES instructions
-inline void Assembler::aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
-inline void Assembler::aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
+inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D));
+}
+inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ aes_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D));
+}
-inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { insert_nop_after_cbcond(); cti(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
-inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { insert_nop_after_cbcond(); bpr( c, a, p, s1, target(L)); }
-
-inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); insert_nop_after_cbcond(); cti(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
-inline void Assembler::fb( Condition c, bool a, Label& L ) { insert_nop_after_cbcond(); fb(c, a, target(L)); }
+inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);
+ induce_delay_slot();
+}
+inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) {
+ // Note[+]: All assembly emit routines using the 'target()' branch back-patch
+ // resolver must call 'avoid_pipeline_stall()' prior to calling 'target()'
+ // (we must do so even though the call will be made, as here, in the above
+ // implementation of 'bpr()', invoked below). The reason is the assumption
+ // made in 'target()', where using the current PC as the address for back-
+ // patching prevents any additional code to be emitted _after_ the address
+ // has been set (implicitly) in order to refer to the correct instruction.
+ avoid_pipeline_stall();
+ bpr(c, a, p, s1, target(L));
+}
-inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { insert_nop_after_cbcond(); cti(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
-inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { insert_nop_after_cbcond(); fbp(c, a, cc, p, target(L)); }
+inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) {
+ v9_dep();
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);
+ induce_delay_slot();
+}
+inline void Assembler::fb(Condition c, bool a, Label &L) {
+ avoid_pipeline_stall();
+ fb(c, a, target(L));
+}
+
+inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);
+ induce_delay_slot();
+}
+inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) {
+ avoid_pipeline_stall();
+ fbp(c, a, cc, p, target(L));
+}
-inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); insert_nop_after_cbcond(); cti(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
-inline void Assembler::br( Condition c, bool a, Label& L ) { insert_nop_after_cbcond(); br(c, a, target(L)); }
+inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) {
+ v9_dep();
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);
+ induce_delay_slot();
+}
+inline void Assembler::br(Condition c, bool a, Label &L) {
+ avoid_pipeline_stall();
+ br(c, a, target(L));
+}
-inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { insert_nop_after_cbcond(); cti(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
-inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { insert_nop_after_cbcond(); bp(c, a, cc, p, target(L)); }
+inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);
+ induce_delay_slot();
+}
+inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) {
+ avoid_pipeline_stall();
+ bp(c, a, cc, p, target(L));
+}
// compare and branch
-inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label& L) { cti(); no_cbcond_before(); emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); }
-inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label& L) { cti(); no_cbcond_before(); emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); }
-
-inline void Assembler::call( address d, relocInfo::relocType rt ) { insert_nop_after_cbcond(); cti(); emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
-inline void Assembler::call( Label& L, relocInfo::relocType rt ) { insert_nop_after_cbcond(); call( target(L), rt); }
-
-inline void Assembler::call( address d, RelocationHolder const& rspec ) { insert_nop_after_cbcond(); cti(); emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); has_delay_slot(); assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
+inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2));
+ induce_pc_hazard();
+}
+inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5));
+ induce_pc_hazard();
+}
-inline void Assembler::casa( Register s1, Register s2, Register d, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
-inline void Assembler::casxa( Register s1, Register s2, Register d, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
+inline void Assembler::call(address d, relocInfo::relocType rt) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);
+ induce_delay_slot();
+ assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec");
+}
+inline void Assembler::call(Label &L, relocInfo::relocType rt) {
+ avoid_pipeline_stall();
+ call(target(L), rt);
+}
-inline void Assembler::udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
-inline void Assembler::udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
-inline void Assembler::sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
-inline void Assembler::udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
-inline void Assembler::sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::call(address d, RelocationHolder const &rspec) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec);
+ induce_delay_slot();
+ assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec");
+}
+
+inline void Assembler::casa(Register s1, Register s2, Register d, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));
+}
+inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2));
+}
-inline void Assembler::done() { cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
-inline void Assembler::retry() { cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
-
-inline void Assembler::fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
-inline void Assembler::fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
-
-inline void Assembler::fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
-inline void Assembler::fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
-
-inline void Assembler::ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
-inline void Assembler::ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
+inline void Assembler::udiv(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::udiv(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::sdiv(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::sdiv(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::udivcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::udivcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::sdivcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::sdivcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
+inline void Assembler::done() {
+ cti();
+ emit_int32(op(arith_op) | fcn(0) | op3(done_op3));
+}
+inline void Assembler::retry() {
+ cti();
+ emit_int32(op(arith_op) | fcn(1) | op3(retry_op3));
+}
-inline void Assembler::fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
-inline void Assembler::fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
+inline void Assembler::fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w));
+}
+inline void Assembler::fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w));
+}
-inline void Assembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
-inline void Assembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
-inline void Assembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
-inline void Assembler::fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
-inline void Assembler::fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
-inline void Assembler::fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
+inline void Assembler::fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) {
+ emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w));
+}
+inline void Assembler::fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) {
+ emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w));
+}
+
+inline void Assembler::ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w));
+}
+inline void Assembler::ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w));
+}
+
+inline void Assembler::ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw));
+}
+
+inline void Assembler::fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D));
+}
+inline void Assembler::fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S));
+}
-inline void Assembler::fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
-
-inline void Assembler::fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
+inline void Assembler::fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w));
+}
+inline void Assembler::fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w));
+}
+inline void Assembler::fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w));
+}
+inline void Assembler::fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w));
+}
+inline void Assembler::fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw));
+}
+inline void Assembler::fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w));
+}
-inline void Assembler::flush( Register s1, Register s2) { emit_int32( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
-inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w));
+}
-inline void Assembler::flushw() { emit_int32( op(arith_op) | op3(flushw_op3) ); }
+inline void Assembler::fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w));
+}
-inline void Assembler::illtrap( int const22a) { emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
+inline void Assembler::flush(Register s1, Register s2) {
+ emit_int32(op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::flush(Register s1, int simm13a) {
+ emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::impdep1( int id1, int const19a ) { emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
-inline void Assembler::impdep2( int id1, int const19a ) { emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
+inline void Assembler::flushw() {
+ emit_int32(op(arith_op) | op3(flushw_op3));
+}
+
+inline void Assembler::illtrap(int const22a) {
+ emit_int32(op(branch_op) | u_field(const22a, 21, 0));
+}
-inline void Assembler::jmpl( Register s1, Register s2, Register d ) { insert_nop_after_cbcond(); cti(); emit_int32( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
-inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { insert_nop_after_cbcond(); cti(); emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
+inline void Assembler::impdep1(int id1, int const19a) {
+ emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0));
+}
+inline void Assembler::impdep2(int id1, int const19a) {
+ emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0));
+}
-inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
+inline void Assembler::jmpl(Register s1, Register s2, Register d) {
+ avoid_pipeline_stall();
+ cti();
+ emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));
+ induce_delay_slot();
+}
+inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) {
+ avoid_pipeline_stall();
+ cti();
+ emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);
+ induce_delay_slot();
+}
-inline void Assembler::ldxfsr( Register s1, Register s2) { emit_int32( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldxfsr( Register s1, int simm13a) { emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) {
+ emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);
+}
+
+inline void Assembler::ldxfsr(Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldxfsr(Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::ldsb(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldsb(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::ldsh(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldsh(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldsw(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldsw(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldub(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldub(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::lduh(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::lduh(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::lduw(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::lduw(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ldx( Register s1, Register s2, Register d) { emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldx( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::ldx(Register s1, Register s2, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldx(Register s1, int simm13a, Register d) {
+ emit_data(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldd(Register s1, Register s2, Register d) {
+ v9_dep();
+ assert(d->is_even(), "not even");
+ emit_int32(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::ldd(Register s1, int simm13a, Register d) {
+ v9_dep();
+ assert(d->is_even(), "not even");
+ emit_data(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::ldswa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::ldswa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::ldxa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::ldxa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::ldsba(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::ldsba(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldsha(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::ldsha(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldswa(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::ldswa(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::lduba(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::lduba(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::lduha(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::lduha(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::lduwa(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::lduwa(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::ldxa(Register s1, Register s2, int ia, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::ldxa(Register s1, int simm13a, Register d) {
+ emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::and3(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::and3(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::andcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::andcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::andn(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::andn(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::andncc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::andncc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::or3(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::or3(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::orcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::orcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::orn(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::orn(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::orncc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::orncc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::xor3(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::xor3(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::xorcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::xorcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::xnor(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::xnor(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::xnorcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::xnorcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::membar( Membar_mask_bits const7a ) { emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
+inline void Assembler::membar(Membar_mask_bits const7a) {
+ emit_int32(op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field(int(const7a), 6, 0));
+}
-inline void Assembler::fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
-
-inline void Assembler::fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
+inline void Assembler::fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w));
+}
-inline void Assembler::movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
-inline void Assembler::movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
+inline void Assembler::fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d) {
+ emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w));
+}
-inline void Assembler::movr( RCondition c, Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
-inline void Assembler::movr( RCondition c, Register s1, int simm10a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
+inline void Assembler::movcc(Condition c, bool floatCC, CC cca, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2));
+}
+inline void Assembler::movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11));
+}
+
+inline void Assembler::movr(RCondition c, Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2));
+}
+inline void Assembler::movr(RCondition c, Register s1, int simm10a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10));
+}
-inline void Assembler::mulx( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::mulx( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::sdivx( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::sdivx( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::udivx( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::udivx( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::mulx(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::mulx(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::sdivx(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::sdivx(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::udivx(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::udivx(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-
-inline void Assembler::nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
+inline void Assembler::umul(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::umul(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::smul(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::smul(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::umulcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::umulcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::smulcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::smulcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::sw_count() { emit_int32( op(branch_op) | op2(sethi_op2) | 0x3f0 ); }
+inline void Assembler::nop() {
+ emit_int32(op(branch_op) | op2(sethi_op2));
+}
-inline void Assembler::popc( Register s, Register d) { emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
-inline void Assembler::popc( int simm13a, Register d) { emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::sw_count() {
+ emit_int32(op(branch_op) | op2(sethi_op2) | 0x3f0);
+}
-inline void Assembler::prefetch( Register s1, Register s2, PrefetchFcn f) { emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::prefetch( Register s1, int simm13a, PrefetchFcn f) { emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::popc(Register s, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | rs2(s));
+}
+inline void Assembler::popc(int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::prefetcha( Register s1, int simm13a, PrefetchFcn f ) { emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) {
+ emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) {
+ emit_data(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+
+inline void Assembler::prefetcha(Register s1, Register s2, int ia, PrefetchFcn f) {
+ emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) {
+ emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
-inline void Assembler::rdccr( Register d) { emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
-inline void Assembler::rdasi( Register d) { emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
-inline void Assembler::rdtick( Register d) { emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
-inline void Assembler::rdpc( Register d) { emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
-inline void Assembler::rdfprs( Register d) { emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
+inline void Assembler::rdy(Register d) {
+ v9_dep();
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14));
+}
+inline void Assembler::rdccr(Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14));
+}
+inline void Assembler::rdasi(Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14));
+}
+inline void Assembler::rdtick(Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14));
+}
+inline void Assembler::rdpc(Register d) {
+ avoid_pipeline_stall();
+ cti();
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14));
+ induce_pc_hazard();
+}
+inline void Assembler::rdfprs(Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14));
+}
-inline void Assembler::rett( Register s1, Register s2 ) { cti(); emit_int32( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
-inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { cti(); emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
+inline void Assembler::rett(Register s1, Register s2) {
+ cti();
+ emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2));
+ induce_delay_slot();
+}
+inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) {
+ cti();
+ emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt);
+ induce_delay_slot();
+}
-inline void Assembler::save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::save( Register s1, int simm13a, Register d ) {
+inline void Assembler::save(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::save(Register s1, int simm13a, Register d) {
// make sure frame is at least large enough for the register save area
assert(-simm13a >= 16 * wordSize, "frame too small");
- emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
+ emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
}
-inline void Assembler::restore( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::restore(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::restore(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 216
-inline void Assembler::saved() { emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
-inline void Assembler::restored() { emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
+inline void Assembler::saved() {
+ emit_int32(op(arith_op) | fcn(0) | op3(saved_op3));
+}
+inline void Assembler::restored() {
+ emit_int32(op(arith_op) | fcn(1) | op3(saved_op3));
+}
-inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
+inline void Assembler::sethi(int imm22a, Register d, RelocationHolder const &rspec) {
+ emit_data(op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec);
+}
-inline void Assembler::sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
-inline void Assembler::sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
-inline void Assembler::srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
-inline void Assembler::srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
-inline void Assembler::sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
-inline void Assembler::sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
+inline void Assembler::sll(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2));
+}
+inline void Assembler::sll(Register s1, int imm5a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0));
+}
+inline void Assembler::srl(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2));
+}
+inline void Assembler::srl(Register s1, int imm5a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0));
+}
+inline void Assembler::sra(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2));
+}
+inline void Assembler::sra(Register s1, int imm5a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0));
+}
-inline void Assembler::sllx( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
-inline void Assembler::sllx( Register s1, int imm6a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
-inline void Assembler::srlx( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
-inline void Assembler::srlx( Register s1, int imm6a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
-inline void Assembler::srax( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
-inline void Assembler::srax( Register s1, int imm6a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
-
-inline void Assembler::sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::sllx(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2));
+}
+inline void Assembler::sllx(Register s1, int imm6a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0));
+}
+inline void Assembler::srlx(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2));
+}
+inline void Assembler::srlx(Register s1, int imm6a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0));
+}
+inline void Assembler::srax(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2));
+}
+inline void Assembler::srax(Register s1, int imm6a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0));
+}
- // pp 221
+inline void Assembler::sir(int simm13a) {
+ emit_int32(op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13));
+}
+
+// pp 221
-inline void Assembler::stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
+inline void Assembler::stbar() {
+ emit_int32(op(arith_op) | op3(membar_op3) | u_field(15, 18, 14));
+}
- // pp 222
+// pp 222
-inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) {
+ emit_data(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::stxfsr( Register s1, Register s2) { emit_int32( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::stxfsr( Register s1, int simm13a) { emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::stxfsr(Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::stxfsr(Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
- // p 226
+// p 226
-inline void Assembler::stb( Register d, Register s1, Register s2) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::sth( Register d, Register s1, Register s2) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::stw( Register d, Register s1, Register s2) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::stb(Register d, Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::stb(Register d, Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::sth(Register d, Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::sth(Register d, Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::stw(Register d, Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::stw(Register d, Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::stx( Register d, Register s1, Register s2) { emit_int32( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::stx( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_int32( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::stx(Register d, Register s1, Register s2) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::stx(Register d, Register s1, int simm13a) {
+ emit_data(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::std(Register d, Register s1, Register s2) {
+ v9_dep();
+ assert(d->is_even(), "not even");
+ emit_int32(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::std(Register d, Register s1, int simm13a) {
+ v9_dep();
+ assert(d->is_even(), "not even");
+ emit_data(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::stxa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stxa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::stba(Register d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stba(Register d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::stha(Register d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stha(Register d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::stwa(Register d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stwa(Register d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::stxa(Register d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stxa(Register d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::stda(Register d, Register s1, Register s2, int ia) {
+ emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::stda(Register d, Register s1, int simm13a) {
+ emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 230
-inline void Assembler::sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::sub(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::sub(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
-inline void Assembler::subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::subcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::subcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::subc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::subc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::subccc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::subccc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 231
-inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
+inline void Assembler::swap(Register s1, Register s2, Register d) {
+ v9_dep();
+ emit_int32(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::swap(Register s1, int simm13a, Register d) {
+ v9_dep();
+ emit_data(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
-inline void Assembler::swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
-inline void Assembler::swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::swapa(Register s1, Register s2, int ia, Register d) {
+ v9_dep();
+ emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+inline void Assembler::swapa(Register s1, int simm13a, Register d) {
+ v9_dep();
+ emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 234, note op in book is wrong, see pp 268
-inline void Assembler::taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::taddcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::taddcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 235
-inline void Assembler::tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
-inline void Assembler::tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+inline void Assembler::tsubcc(Register s1, Register s2, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | rs2(s2));
+}
+inline void Assembler::tsubcc(Register s1, int simm13a, Register d) {
+ emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13));
+}
// pp 237
-inline void Assembler::trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
-inline void Assembler::trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
+inline void Assembler::trap(Condition c, CC cc, Register s1, Register s2) {
+ emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2));
+}
+inline void Assembler::trap(Condition c, CC cc, Register s1, int trapa) {
+ emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0));
+}
// simple uncond. trap
-inline void Assembler::trap( int trapa ) { trap( always, icc, G0, trapa ); }
+inline void Assembler::trap(int trapa) {
+ trap(always, icc, G0, trapa);
+}
-inline void Assembler::wry(Register d) { v9_dep(); emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
-inline void Assembler::wrccr(Register s) { emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
-inline void Assembler::wrccr(Register s, int simm13a) { emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::wrasi(Register d) { emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
+inline void Assembler::wry(Register d) {
+ v9_dep();
+ emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25));
+}
+inline void Assembler::wrccr(Register s) {
+ emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25));
+}
+inline void Assembler::wrccr(Register s, int simm13a) {
+ emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::wrasi(Register d) {
+ emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25));
+}
// wrasi(d, imm) stores (d xor imm) to asi
-inline void Assembler::wrasi(Register d, int simm13a) { emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
-inline void Assembler::wrfprs(Register d) { emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
+inline void Assembler::wrasi(Register d, int simm13a) {
+ emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13));
+}
+inline void Assembler::wrfprs(Register d) {
+ emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25));
+}
-inline void Assembler::alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
-
-inline void Assembler::faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
+inline void Assembler::alignaddr(Register s1, Register s2, Register d) {
+ vis1_only();
+ emit_int32(op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2));
+}
-inline void Assembler::fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); }
+inline void Assembler::faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D));
+}
-inline void Assembler::fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
+inline void Assembler::fzero(FloatRegisterImpl::Width w, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w));
+}
-inline void Assembler::fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); }
+inline void Assembler::fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w));
+}
-inline void Assembler::fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); }
+inline void Assembler::fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w));
+}
-inline void Assembler::stpartialf( Register s1, Register s2, FloatRegister d, int ia ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
+inline void Assembler::fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ vis1_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S));
+}
-// VIS2 instructions
+inline void Assembler::stpartialf(Register s1, Register s2, FloatRegister d, int ia) {
+ vis1_only();
+ emit_int32(op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2));
+}
+
+// VIS2 instructions
-inline void Assembler::edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
+inline void Assembler::edge8n(Register s1, Register s2, Register d) {
+ vis2_only();
+ emit_int32(op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2));
+}
-inline void Assembler::bmask( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); }
-inline void Assembler::bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis2_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); }
+inline void Assembler::bmask(Register s1, Register s2, Register d) {
+ vis2_only();
+ emit_int32(op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2));
+}
+inline void Assembler::bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ vis2_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D));
+}
// VIS3 instructions
-inline void Assembler::movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
-inline void Assembler::movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
-inline void Assembler::movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
+inline void Assembler::movstosw(FloatRegister s, Register d) {
+ vis3_only();
+ emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S));
+}
+inline void Assembler::movstouw(FloatRegister s, Register d) {
+ vis3_only();
+ emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S));
+}
+inline void Assembler::movdtox(FloatRegister s, Register d) {
+ vis3_only();
+ emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D));
+}
-inline void Assembler::movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
-inline void Assembler::movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
+inline void Assembler::movwtos(Register s, FloatRegister d) {
+ vis3_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s));
+}
+inline void Assembler::movxtod(Register s, FloatRegister d) {
+ vis3_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s));
+}
-inline void Assembler::xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
-inline void Assembler::xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
+inline void Assembler::xmulx(Register s1, Register s2, Register d) {
+ vis3_only();
+ emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2));
+}
+inline void Assembler::xmulxhi(Register s1, Register s2, Register d) {
+ vis3_only();
+ emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2));
+}
// Crypto SHA instructions
-inline void Assembler::sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
-inline void Assembler::sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
-inline void Assembler::sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
+inline void Assembler::sha1() {
+ sha1_only();
+ emit_int32(op(arith_op) | op3(sha_op3) | opf(sha1_opf));
+}
+inline void Assembler::sha256() {
+ sha256_only();
+ emit_int32(op(arith_op) | op3(sha_op3) | opf(sha256_opf));
+}
+inline void Assembler::sha512() {
+ sha512_only();
+ emit_int32(op(arith_op) | op3(sha_op3) | opf(sha512_opf));
+}
// CRC32C instruction
-inline void Assembler::crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d ) { crc32c_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); }
+inline void Assembler::crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d) {
+ crc32c_only();
+ emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D));
+}
#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
--- a/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.cpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.cpp Tue Jun 27 15:46:16 2017 +0200
@@ -651,9 +651,9 @@
void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
address save_pc;
int shiftcnt;
-# ifdef CHECK_DELAY
- assert_not_delayed((char*) "cannot put two instructions in delay slot");
-# endif
+#ifdef VALIDATE_PIPELINE
+ assert_no_delay("Cannot put two instructions in delay-slot.");
+#endif
v9_dep();
save_pc = pc();
@@ -752,7 +752,7 @@
return;
}
}
- assert_not_delayed((char*) "cannot put two instructions in delay slot");
+ assert_no_delay("Cannot put two instructions in delay-slot.");
internal_sethi(addrlit, d, ForceRelocatable);
if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
add(d, addrlit.low10(), d, addrlit.rspec());
--- a/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -662,9 +662,6 @@
inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
- // get PC the best way
- inline int get_pc( Register d );
-
// Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
inline void cmp( Register s1, Register s2 );
inline void cmp( Register s1, int simm13a );
@@ -1396,7 +1393,7 @@
void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
- // CRC32 code for java.util.zip.CRC32::updateBytes0() instrinsic.
+ // CRC32 code for java.util.zip.CRC32::updateBytes0() intrinsic.
void kernel_crc32(Register crc, Register buf, Register len, Register table);
// Fold 128-bit data chunk
void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
@@ -1404,7 +1401,7 @@
// Fold 8-bit data
void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
void fold_8bit_crc32(Register crc, Register table, Register tmp);
- // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer instrinsic.
+ // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer intrinsic.
void kernel_crc32c(Register crc, Register buf, Register len, Register table);
};
--- a/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -185,7 +185,8 @@
}
inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
- insert_nop_after_cbcond();
+ // See note[+] on 'avoid_pipeline_stalls()', in "assembler_sparc.inline.hpp".
+ avoid_pipeline_stall();
br(c, a, p, target(L));
}
@@ -197,7 +198,7 @@
}
inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
- insert_nop_after_cbcond();
+ avoid_pipeline_stall();
brx(c, a, p, target(L));
}
@@ -219,7 +220,7 @@
}
inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
- insert_nop_after_cbcond();
+ avoid_pipeline_stall();
fb(c, a, p, target(L));
}
@@ -268,13 +269,12 @@
}
}
-inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
- insert_nop_after_cbcond();
- MacroAssembler::call( target(L), rt);
+inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
+ avoid_pipeline_stall();
+ MacroAssembler::call(target(L), rt);
}
-
inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
@@ -304,13 +304,6 @@
}
}
-// clobbers o7 on V8!!
-// returns delta from gotten pc to addr after
-inline int MacroAssembler::get_pc( Register d ) {
- int x = offset();
- rdpc(d);
- return offset() - x;
-}
inline void MacroAssembler::cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
inline void MacroAssembler::cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
--- a/hotspot/src/cpu/sparc/vm/methodHandles_sparc.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/methodHandles_sparc.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
// Adapters
enum /* platform_dependent_constants */ {
- adapter_code_size = NOT_LP64(23000 DEBUG_ONLY(+ 40000)) LP64_ONLY(35000 DEBUG_ONLY(+ 50000))
+ adapter_code_size = 35000 DEBUG_ONLY(+ 50000)
};
// Additional helper methods for MethodHandles code generation:
--- a/hotspot/src/cpu/sparc/vm/nativeInst_sparc.hpp Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/nativeInst_sparc.hpp Tue Jun 27 15:46:16 2017 +0200
@@ -67,11 +67,8 @@
bool is_illegal();
bool is_zombie() {
int x = long_at(0);
- return is_op3(x,
- Assembler::ldsw_op3,
- Assembler::ldst_op)
- && Assembler::inv_rs1(x) == G0
- && Assembler::inv_rd(x) == O7;
+ return (is_op3(x, Assembler::ldsw_op3, Assembler::ldst_op) &&
+ inv_rs1(x) == G0 && inv_rd(x) == O7);
}
bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss
bool is_return() {
@@ -129,29 +126,11 @@
bool is_load_store_with_small_offset(Register reg);
public:
-#ifdef ASSERT
- static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
-#else
- // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
- static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); }
-#endif
static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
static int illegal_instruction(); // the output of __ breakpoint_trap()
static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
- static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
- return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
- }
-
- static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
- return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
- }
-
- static int sethi_instruction(Register rd, int imm22a) {
- return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
- }
-
- protected:
+protected:
address addr_at(int offset) const { return address(this) + offset; }
int long_at(int offset) const { return *(int*)addr_at(offset); }
void set_long_at(int offset, int i); /* deals with I-cache */
--- a/hotspot/src/cpu/sparc/vm/sparc.ad Tue Jun 27 15:36:45 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad Tue Jun 27 15:46:16 2017 +0200
@@ -1072,7 +1072,13 @@
__ rdpc(r);
- if (disp != 0) {
+ if (disp == 0) {
+ // Emitting an additional 'nop' instruction in order not to cause a code
+ // size adjustment in the code following the table setup (if the instruction
+ // immediately following after this section is a CTI).
+ __ nop();
+ }
+ else {
assert(r != O7, "need temporary");
__ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
}
@@ -8624,7 +8630,7 @@
predicate(UseCBCond);
effect(USE labl);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "BA $labl\t! short branch" %}
ins_encode %{
@@ -8965,7 +8971,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
ins_encode %{
@@ -8983,7 +8989,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
ins_encode %{
@@ -9001,7 +9007,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
ins_encode %{
@@ -9019,7 +9025,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
ins_encode %{
@@ -9037,7 +9043,7 @@
predicate(UseCBCond);
effect(USE labl, KILL xcc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
ins_encode %{
@@ -9055,7 +9061,7 @@
predicate(UseCBCond);
effect(USE labl, KILL xcc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
ins_encode %{
@@ -9074,7 +9080,7 @@
predicate(UseCBCond);
effect(USE labl, KILL pcc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
ins_encode %{
@@ -9092,7 +9098,7 @@
predicate(UseCBCond);
effect(USE labl, KILL pcc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
ins_encode %{
@@ -9110,7 +9116,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
ins_encode %{
@@ -9128,7 +9134,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
ins_encode %{
@@ -9147,7 +9153,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
ins_encode %{
@@ -9165,7 +9171,7 @@
predicate(UseCBCond);
effect(USE labl, KILL icc);
- size(4);
+ size(4); // Assuming no NOP inserted.
ins_cost(BRANCH_COST);
format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
ins_encode %{