author | glaubitz |
Mon, 09 Sep 2019 15:14:16 +0200 | |
changeset 58050 | 9fba708740d6 |
parent 53244 | 9807daeb47c4 |
child 58932 | 8623f75be895 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_SPARC_NATIVEINST_SPARC_HPP |
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#define CPU_SPARC_NATIVEINST_SPARC_HPP |
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#include "asm/macroAssembler.hpp" |
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#include "runtime/icache.hpp" |
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#include "runtime/os.hpp" |
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// We have interface for the following instructions: |
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// - NativeInstruction |
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// - - NativeCall |
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// - - NativeFarCall |
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// - - NativeMovConstReg |
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// - - NativeMovConstRegPatching |
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// - - NativeMovRegMem |
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// - - NativeJump |
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// - - NativeGeneralJump |
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// - - NativeIllegalInstruction |
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// The base class for different kinds of native instruction abstractions. |
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// Provides the primitive operations to manipulate code relative to this. |
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class NativeInstruction { |
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friend class Relocation; |
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public: |
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enum Sparc_specific_constants { |
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nop_instruction_size = 4 |
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}; |
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||
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bool is_nop() { return long_at(0) == nop_instruction(); } |
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bool is_call() { return is_op(long_at(0), Assembler::call_op); } |
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bool is_call_reg() { return is_op(long_at(0), Assembler::arith_op); } |
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bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2) |
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&& inv_rd(long_at(0)) != G0); } |
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bool sets_cc() { |
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// conservative (returns true for some instructions that do not set the |
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// the condition code, such as, "save". |
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// Does not return true for the deprecated tagged instructions, such as, TADDcc |
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int x = long_at(0); |
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return (is_op(x, Assembler::arith_op) && |
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(inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3); |
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} |
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bool is_illegal(); |
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bool is_zombie() { |
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int x = long_at(0); |
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return (is_op3(x, Assembler::ldsw_op3, Assembler::ldst_op) && |
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inv_rs1(x) == G0 && inv_rd(x) == O7); |
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} |
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bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss |
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bool is_return() { |
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// is it the output of MacroAssembler::ret or MacroAssembler::retl? |
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int x = long_at(0); |
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const int pc_return_offset = 8; // see frame_sparc.hpp |
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return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op) |
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&& (inv_rs1(x) == I7 || inv_rs1(x) == O7) |
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&& inv_immed(x) && inv_simm(x, 13) == pc_return_offset |
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&& inv_rd(x) == G0; |
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} |
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bool is_int_jump() { |
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// is it the output of MacroAssembler::b? |
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int x = long_at(0); |
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return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2); |
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} |
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bool is_float_jump() { |
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// is it the output of MacroAssembler::fb? |
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int x = long_at(0); |
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return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2); |
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} |
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bool is_jump() { |
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return is_int_jump() || is_float_jump(); |
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} |
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bool is_cond_jump() { |
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int x = long_at(0); |
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return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) || |
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(is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always); |
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} |
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bool is_stack_bang() { |
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int x = long_at(0); |
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return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) && |
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(inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch); |
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} |
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bool is_prefetch() { |
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int x = long_at(0); |
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return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op); |
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} |
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bool is_membar() { |
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int x = long_at(0); |
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return is_op3(x, Assembler::membar_op3, Assembler::arith_op) && |
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(inv_rd(x) == G0) && (inv_rs1(x) == O7); |
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} |
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bool is_safepoint_poll() { |
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int x = long_at(0); |
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return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) && |
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(inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0); |
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} |
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bool is_zero_test(Register ®); |
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bool is_load_store_with_small_offset(Register reg); |
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public: |
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static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); } |
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static int illegal_instruction(); // the output of __ breakpoint_trap() |
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static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); } |
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protected: |
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address addr_at(int offset) const { return address(this) + offset; } |
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int long_at(int offset) const { return *(int*)addr_at(offset); } |
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void set_long_at(int offset, int i); /* deals with I-cache */ |
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void set_jlong_at(int offset, jlong i); /* deals with I-cache */ |
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void set_addr_at(int offset, address x); /* deals with I-cache */ |
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address instruction_address() const { return addr_at(0); } |
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address next_instruction_address() const { return addr_at(BytesPerInstWord); } |
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static bool is_op( int x, Assembler::ops opval) { |
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return Assembler::inv_op(x) == opval; |
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} |
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static bool is_op2(int x, Assembler::op2s op2val) { |
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return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val; |
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} |
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static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) { |
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return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val; |
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} |
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// utilities to help subclasses decode: |
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static Register inv_rd( int x ) { return Assembler::inv_rd( x); } |
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static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); } |
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static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); } |
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static bool inv_immed( int x ) { return Assembler::inv_immed(x); } |
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static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; } |
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static int inv_cond( int x ) { return Assembler::inv_cond(x); } |
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static int inv_op( int x ) { return Assembler::inv_op( x); } |
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static int inv_op2( int x ) { return Assembler::inv_op2(x); } |
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static int inv_op3( int x ) { return Assembler::inv_op3(x); } |
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static int inv_simm( int x, int nbits ) { return Assembler::inv_simm(x, nbits); } |
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static intptr_t inv_wdisp( int x, int nbits ) { return Assembler::inv_wdisp( x, 0, nbits); } |
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static intptr_t inv_wdisp16( int x ) { return Assembler::inv_wdisp16(x, 0); } |
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static int branch_destination_offset(int x) { return MacroAssembler::branch_destination(x, 0); } |
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static int patch_branch_destination_offset(int dest_offset, int x) { |
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return MacroAssembler::patched_branch(dest_offset, x, 0); |
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} |
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// utility for checking if x is either of 2 small constants |
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static bool is_either(int x, int k1, int k2) { |
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// return x == k1 || x == k2; |
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return (1 << x) & (1 << k1 | 1 << k2); |
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} |
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// utility for checking overflow of signed instruction fields |
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static bool fits_in_simm(int x, int nbits) { |
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// cf. Assembler::assert_signed_range() |
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// return -(1 << nbits-1) <= x && x < ( 1 << nbits-1), |
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return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits); |
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} |
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// set a signed immediate field |
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static int set_simm(int insn, int imm, int nbits) { |
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return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits); |
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} |
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// set a wdisp field (disp should be the difference of two addresses) |
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static int set_wdisp(int insn, intptr_t disp, int nbits) { |
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return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits); |
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} |
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static int set_wdisp16(int insn, intptr_t disp) { |
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return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0); |
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} |
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// get a simm13 field from an arithmetic or memory instruction |
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static int get_simm13(int insn) { |
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assert(is_either(Assembler::inv_op(insn), |
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Assembler::arith_op, Assembler::ldst_op) && |
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(insn & Assembler::immed(true)), "must have a simm13 field"); |
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return Assembler::inv_simm(insn, 13); |
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} |
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// set the simm13 field of an arithmetic or memory instruction |
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static bool set_simm13(int insn, int imm) { |
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get_simm13(insn); // tickle the assertion check |
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return set_simm(insn, imm, 13); |
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} |
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// combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st |
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static intptr_t data64( address pc, int arith_insn ) { |
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assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi"); |
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intptr_t hi = (intptr_t)gethi( (unsigned int *)pc ); |
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intptr_t lo = (intptr_t)get_simm13(arith_insn); |
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assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits"); |
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return hi | lo; |
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} |
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// Regenerate the instruction sequence that performs the 64 bit |
|
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// sethi. This only does the sethi. The disp field (bottom 10 bits) |
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// must be handled separately. |
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static void set_data64_sethi(address instaddr, intptr_t x); |
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static void verify_data64_sethi(address instaddr, intptr_t x); |
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// combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st) |
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static int data32(int sethi_insn, int arith_insn) { |
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assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); |
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int hi = Assembler::inv_hi22(sethi_insn); |
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int lo = get_simm13(arith_insn); |
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assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits"); |
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return hi | lo; |
236 |
} |
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238 |
static int set_data32_sethi(int sethi_insn, int imm) { |
|
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// note that Assembler::hi22 clips the low 10 bits for us |
|
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assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); |
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return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm); |
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242 |
} |
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243 |
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static int set_data32_simm13(int arith_insn, int imm) { |
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get_simm13(arith_insn); // tickle the assertion check |
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int imm10 = Assembler::low10(imm); |
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return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13); |
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248 |
} |
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249 |
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250 |
static int low10(int imm) { |
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251 |
return Assembler::low10(imm); |
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252 |
} |
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253 |
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// Perform the inverse of the LP64 Macroassembler::sethi |
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// routine. Extracts the 54 bits of address from the instruction |
|
256 |
// stream. This routine must agree with the sethi routine in |
|
257 |
// assembler_inline_sparc.hpp |
|
258 |
static address gethi( unsigned int *pc ) { |
|
259 |
int i = 0; |
|
260 |
uintptr_t adr; |
|
261 |
// We first start out with the real sethi instruction |
|
262 |
assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi"); |
|
263 |
adr = (unsigned int)Assembler::inv_hi22( *(pc++) ); |
|
264 |
i++; |
|
265 |
while ( i < 7 ) { |
|
266 |
// We're done if we hit a nop |
|
267 |
if ( (int)*pc == nop_instruction() ) break; |
|
268 |
assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" ); |
|
269 |
switch ( Assembler::inv_op3(*pc) ) { |
|
270 |
case Assembler::xor_op3: |
|
271 |
adr ^= (intptr_t)get_simm13( *pc ); |
|
272 |
return ( (address)adr ); |
|
273 |
break; |
|
274 |
case Assembler::sll_op3: |
|
275 |
adr <<= ( *pc & 0x3f ); |
|
276 |
break; |
|
277 |
case Assembler::or_op3: |
|
278 |
adr |= (intptr_t)get_simm13( *pc ); |
|
279 |
break; |
|
280 |
default: |
|
281 |
assert ( 0, "in gethi - Should not reach here" ); |
|
282 |
break; |
|
283 |
} |
|
284 |
pc++; |
|
285 |
i++; |
|
286 |
} |
|
287 |
return ( (address)adr ); |
|
288 |
} |
|
289 |
||
290 |
public: |
|
291 |
void verify(); |
|
292 |
void print(); |
|
293 |
||
294 |
// unit test stuff |
|
295 |
static void test() {} // override for testing |
|
296 |
||
297 |
inline friend NativeInstruction* nativeInstruction_at(address address); |
|
298 |
}; |
|
299 |
||
300 |
inline NativeInstruction* nativeInstruction_at(address address) { |
|
301 |
NativeInstruction* inst = (NativeInstruction*)address; |
|
302 |
#ifdef ASSERT |
|
303 |
inst->verify(); |
|
304 |
#endif |
|
305 |
return inst; |
|
306 |
} |
|
307 |
||
308 |
||
309 |
||
310 |
//----------------------------------------------------------------------------- |
|
311 |
||
312 |
// The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions. |
|
313 |
// (used to manipulate inline caches, primitive & dll calls, etc.) |
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class NativeCall; |
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|
1 | 316 |
inline NativeCall* nativeCall_at(address instr); |
317 |
inline NativeCall* nativeCall_overwriting_at(address instr, |
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address destination = NULL); |
1 | 319 |
inline NativeCall* nativeCall_before(address return_address); |
320 |
class NativeCall: public NativeInstruction { |
|
321 |
public: |
|
322 |
enum Sparc_specific_constants { |
|
323 |
instruction_size = 8, |
|
324 |
return_address_offset = 8, |
|
325 |
call_displacement_width = 30, |
|
326 |
displacement_offset = 0, |
|
327 |
instruction_offset = 0 |
|
328 |
}; |
|
329 |
address instruction_address() const { return addr_at(0); } |
|
330 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
331 |
address return_address() const { return addr_at(return_address_offset); } |
|
332 |
||
333 |
address destination() const { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); } |
|
334 |
address displacement_address() const { return addr_at(displacement_offset); } |
|
335 |
void set_destination(address dest) { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); } |
|
336 |
void set_destination_mt_safe(address dest); |
|
337 |
||
338 |
void verify_alignment() {} // do nothing on sparc |
|
339 |
void verify(); |
|
340 |
void print(); |
|
341 |
||
342 |
// unit test stuff |
|
343 |
static void test(); |
|
344 |
||
345 |
// Creation |
|
346 |
friend inline NativeCall* nativeCall_at(address instr); |
|
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347 |
friend NativeCall* nativeCall_overwriting_at(address instr, address destination) { |
1 | 348 |
// insert a "blank" call: |
349 |
NativeCall* call = (NativeCall*)instr; |
|
350 |
call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr)); |
|
351 |
call->set_long_at(1 * BytesPerInstWord, nop_instruction()); |
|
352 |
assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size"); |
|
353 |
// check its structure now: |
|
354 |
assert(nativeCall_at(instr)->destination() == destination, "correct call destination"); |
|
355 |
return call; |
|
356 |
} |
|
357 |
||
358 |
friend inline NativeCall* nativeCall_before(address return_address) { |
|
359 |
NativeCall* call = (NativeCall*)(return_address - return_address_offset); |
|
360 |
#ifdef ASSERT |
|
361 |
call->verify(); |
|
362 |
#endif |
|
363 |
return call; |
|
364 |
} |
|
365 |
||
366 |
static bool is_call_at(address instr) { |
|
367 |
return nativeInstruction_at(instr)->is_call(); |
|
368 |
} |
|
369 |
||
370 |
static bool is_call_before(address instr) { |
|
371 |
return nativeInstruction_at(instr - return_address_offset)->is_call(); |
|
372 |
} |
|
373 |
||
374 |
static bool is_call_to(address instr, address target) { |
|
375 |
return nativeInstruction_at(instr)->is_call() && |
|
376 |
nativeCall_at(instr)->destination() == target; |
|
377 |
} |
|
378 |
||
379 |
// MT-safe patching of a call instruction. |
|
380 |
static void insert(address code_pos, address entry) { |
|
381 |
(void)nativeCall_overwriting_at(code_pos, entry); |
|
382 |
} |
|
383 |
||
384 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
385 |
}; |
|
386 |
inline NativeCall* nativeCall_at(address instr) { |
|
387 |
NativeCall* call = (NativeCall*)instr; |
|
388 |
#ifdef ASSERT |
|
389 |
call->verify(); |
|
390 |
#endif |
|
391 |
return call; |
|
392 |
} |
|
393 |
||
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|
394 |
class NativeCallReg: public NativeInstruction { |
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|
395 |
public: |
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|
396 |
enum Sparc_specific_constants { |
c59f1676d27e
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|
397 |
instruction_size = 8, |
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changeset
|
398 |
return_address_offset = 8, |
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parents:
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diff
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|
399 |
instruction_offset = 0 |
c59f1676d27e
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diff
changeset
|
400 |
}; |
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|
401 |
|
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|
402 |
address next_instruction_address() const { |
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|
403 |
return addr_at(instruction_size); |
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|
404 |
} |
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|
405 |
}; |
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|
406 |
|
1 | 407 |
// The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere |
408 |
// instructions in the sparcv9 vm. Used to call native methods which may be loaded |
|
409 |
// anywhere in the address space, possibly out of reach of a call instruction. |
|
410 |
||
411 |
// The format of this extended-range call is: |
|
412 |
// jumpl_to addr, lreg |
|
413 |
// == sethi %hi54(addr), O7 ; jumpl O7, %lo10(addr), O7 ; <delay> |
|
414 |
// That is, it is essentially the same as a NativeJump. |
|
415 |
class NativeFarCall; |
|
58050
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diff
changeset
|
416 |
inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL); |
1 | 417 |
inline NativeFarCall* nativeFarCall_at(address instr); |
418 |
class NativeFarCall: public NativeInstruction { |
|
419 |
public: |
|
420 |
enum Sparc_specific_constants { |
|
421 |
// instruction_size includes the delay slot instruction. |
|
422 |
instruction_size = 9 * BytesPerInstWord, |
|
423 |
return_address_offset = 9 * BytesPerInstWord, |
|
424 |
jmpl_offset = 7 * BytesPerInstWord, |
|
425 |
displacement_offset = 0, |
|
426 |
instruction_offset = 0 |
|
427 |
}; |
|
428 |
address instruction_address() const { return addr_at(0); } |
|
429 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
430 |
address return_address() const { return addr_at(return_address_offset); } |
|
431 |
||
432 |
address destination() const { |
|
433 |
return (address) data64(addr_at(0), long_at(jmpl_offset)); |
|
434 |
} |
|
435 |
address displacement_address() const { return addr_at(displacement_offset); } |
|
436 |
void set_destination(address dest); |
|
437 |
||
438 |
bool destination_is_compiled_verified_entry_point(); |
|
439 |
||
440 |
void verify(); |
|
441 |
void print(); |
|
442 |
||
443 |
// unit test stuff |
|
444 |
static void test(); |
|
445 |
||
446 |
// Creation |
|
447 |
friend inline NativeFarCall* nativeFarCall_at(address instr) { |
|
448 |
NativeFarCall* call = (NativeFarCall*)instr; |
|
449 |
#ifdef ASSERT |
|
450 |
call->verify(); |
|
451 |
#endif |
|
452 |
return call; |
|
453 |
} |
|
454 |
||
58050
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parents:
53244
diff
changeset
|
455 |
friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination) { |
1 | 456 |
Unimplemented(); |
457 |
NativeFarCall* call = (NativeFarCall*)instr; |
|
458 |
return call; |
|
459 |
} |
|
460 |
||
461 |
friend NativeFarCall* nativeFarCall_before(address return_address) { |
|
462 |
NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset); |
|
463 |
#ifdef ASSERT |
|
464 |
call->verify(); |
|
465 |
#endif |
|
466 |
return call; |
|
467 |
} |
|
468 |
||
469 |
static bool is_call_at(address instr); |
|
470 |
||
471 |
// MT-safe patching of a call instruction. |
|
472 |
static void insert(address code_pos, address entry) { |
|
473 |
(void)nativeFarCall_overwriting_at(code_pos, entry); |
|
474 |
} |
|
475 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
476 |
}; |
|
477 |
||
478 |
||
33632 | 479 |
// An interface for accessing/manipulating 32 bit native set_metadata imm, reg instructions |
480 |
// (used to manipulate inlined data references, etc.) |
|
481 |
// set_metadata imm, reg |
|
482 |
// == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg |
|
483 |
class NativeMovConstReg32; |
|
484 |
inline NativeMovConstReg32* nativeMovConstReg32_at(address address); |
|
485 |
class NativeMovConstReg32: public NativeInstruction { |
|
486 |
public: |
|
487 |
enum Sparc_specific_constants { |
|
488 |
sethi_offset = 0, |
|
489 |
add_offset = 4, |
|
490 |
instruction_size = 8 |
|
491 |
}; |
|
492 |
||
493 |
address instruction_address() const { return addr_at(0); } |
|
494 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
495 |
||
496 |
// (The [set_]data accessor respects oop_type relocs also.) |
|
497 |
intptr_t data() const; |
|
498 |
void set_data(intptr_t x); |
|
499 |
||
500 |
// report the destination register |
|
501 |
Register destination() { return inv_rd(long_at(sethi_offset)); } |
|
502 |
||
503 |
void verify(); |
|
504 |
void print(); |
|
505 |
||
506 |
// unit test stuff |
|
507 |
static void test(); |
|
508 |
||
509 |
// Creation |
|
510 |
friend inline NativeMovConstReg32* nativeMovConstReg32_at(address address) { |
|
511 |
NativeMovConstReg32* test = (NativeMovConstReg32*)address; |
|
512 |
#ifdef ASSERT |
|
513 |
test->verify(); |
|
514 |
#endif |
|
515 |
return test; |
|
516 |
} |
|
517 |
}; |
|
518 |
||
13728
882756847a04
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parents:
8921
diff
changeset
|
519 |
// An interface for accessing/manipulating native set_metadata imm, reg instructions. |
1 | 520 |
// (used to manipulate inlined data references, etc.) |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
8921
diff
changeset
|
521 |
// set_metadata imm, reg |
1 | 522 |
// == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg |
523 |
class NativeMovConstReg; |
|
524 |
inline NativeMovConstReg* nativeMovConstReg_at(address address); |
|
525 |
class NativeMovConstReg: public NativeInstruction { |
|
526 |
public: |
|
527 |
enum Sparc_specific_constants { |
|
528 |
sethi_offset = 0, |
|
529 |
add_offset = 7 * BytesPerInstWord, |
|
530 |
instruction_size = 8 * BytesPerInstWord |
|
531 |
}; |
|
532 |
||
533 |
address instruction_address() const { return addr_at(0); } |
|
534 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
535 |
||
536 |
// (The [set_]data accessor respects oop_type relocs also.) |
|
537 |
intptr_t data() const; |
|
538 |
void set_data(intptr_t x); |
|
539 |
||
540 |
// report the destination register |
|
541 |
Register destination() { return inv_rd(long_at(sethi_offset)); } |
|
542 |
||
543 |
void verify(); |
|
544 |
void print(); |
|
545 |
||
546 |
// unit test stuff |
|
547 |
static void test(); |
|
548 |
||
549 |
// Creation |
|
550 |
friend inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
|
551 |
NativeMovConstReg* test = (NativeMovConstReg*)address; |
|
552 |
#ifdef ASSERT |
|
553 |
test->verify(); |
|
554 |
#endif |
|
555 |
return test; |
|
556 |
} |
|
557 |
||
558 |
||
559 |
friend NativeMovConstReg* nativeMovConstReg_before(address address) { |
|
560 |
NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size); |
|
561 |
#ifdef ASSERT |
|
562 |
test->verify(); |
|
563 |
#endif |
|
564 |
return test; |
|
565 |
} |
|
566 |
||
567 |
}; |
|
568 |
||
569 |
||
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
8921
diff
changeset
|
570 |
// An interface for accessing/manipulating native set_metadata imm, reg instructions. |
1 | 571 |
// (used to manipulate inlined data references, etc.) |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
8921
diff
changeset
|
572 |
// set_metadata imm, reg |
1 | 573 |
// == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg |
574 |
// |
|
575 |
// Note that it is identical to NativeMovConstReg with the exception of a nop between the |
|
576 |
// sethi and the add. The nop is required to be in the delay slot of the call instruction |
|
577 |
// which overwrites the sethi during patching. |
|
578 |
class NativeMovConstRegPatching; |
|
579 |
inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction { |
|
580 |
public: |
|
581 |
enum Sparc_specific_constants { |
|
582 |
sethi_offset = 0, |
|
583 |
nop_offset = 7 * BytesPerInstWord, |
|
584 |
add_offset = nop_offset + BytesPerInstWord, |
|
585 |
instruction_size = add_offset + BytesPerInstWord |
|
586 |
}; |
|
587 |
||
588 |
address instruction_address() const { return addr_at(0); } |
|
589 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
590 |
||
591 |
// (The [set_]data accessor respects oop_type relocs also.) |
|
592 |
int data() const; |
|
593 |
void set_data(int x); |
|
594 |
||
595 |
// report the destination register |
|
596 |
Register destination() { return inv_rd(long_at(sethi_offset)); } |
|
597 |
||
598 |
void verify(); |
|
599 |
void print(); |
|
600 |
||
601 |
// unit test stuff |
|
602 |
static void test(); |
|
603 |
||
604 |
// Creation |
|
605 |
friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
|
606 |
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address; |
|
607 |
#ifdef ASSERT |
|
608 |
test->verify(); |
|
609 |
#endif |
|
610 |
return test; |
|
611 |
} |
|
612 |
||
613 |
||
614 |
friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) { |
|
615 |
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size); |
|
616 |
#ifdef ASSERT |
|
617 |
test->verify(); |
|
618 |
#endif |
|
619 |
return test; |
|
620 |
} |
|
621 |
||
622 |
}; |
|
623 |
||
624 |
||
625 |
// An interface for accessing/manipulating native memory ops |
|
626 |
// ld* [reg + offset], reg |
|
627 |
// st* reg, [reg + offset] |
|
628 |
// sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2 |
|
629 |
// sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg] |
|
630 |
// Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x} |
|
631 |
// |
|
632 |
class NativeMovRegMem; |
|
633 |
inline NativeMovRegMem* nativeMovRegMem_at (address address); |
|
634 |
class NativeMovRegMem: public NativeInstruction { |
|
635 |
public: |
|
636 |
enum Sparc_specific_constants { |
|
637 |
op3_mask_ld = 1 << Assembler::lduw_op3 | |
|
638 |
1 << Assembler::ldub_op3 | |
|
639 |
1 << Assembler::lduh_op3 | |
|
640 |
1 << Assembler::ldd_op3 | |
|
641 |
1 << Assembler::ldsw_op3 | |
|
642 |
1 << Assembler::ldsb_op3 | |
|
643 |
1 << Assembler::ldsh_op3 | |
|
644 |
1 << Assembler::ldx_op3, |
|
645 |
op3_mask_st = 1 << Assembler::stw_op3 | |
|
646 |
1 << Assembler::stb_op3 | |
|
647 |
1 << Assembler::sth_op3 | |
|
648 |
1 << Assembler::std_op3 | |
|
649 |
1 << Assembler::stx_op3, |
|
650 |
op3_ldst_int_limit = Assembler::ldf_op3, |
|
651 |
op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) | |
|
652 |
1 << (Assembler::lddf_op3 - op3_ldst_int_limit), |
|
653 |
op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) | |
|
654 |
1 << (Assembler::stdf_op3 - op3_ldst_int_limit), |
|
655 |
||
656 |
offset_width = 13, |
|
657 |
sethi_offset = 0, |
|
658 |
add_offset = 7 * BytesPerInstWord, |
|
659 |
ldst_offset = add_offset + BytesPerInstWord |
|
660 |
}; |
|
661 |
bool is_immediate() const { |
|
662 |
// check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset] |
|
663 |
int i0 = long_at(0); |
|
664 |
return (is_op(i0, Assembler::ldst_op)); |
|
665 |
} |
|
666 |
||
667 |
address instruction_address() const { return addr_at(0); } |
|
668 |
address next_instruction_address() const { |
|
669 |
return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord)); |
|
670 |
} |
|
671 |
intptr_t offset() const { |
|
672 |
return is_immediate()? inv_simm(long_at(0), offset_width) : |
|
673 |
nativeMovConstReg_at(addr_at(0))->data(); |
|
674 |
} |
|
675 |
void set_offset(intptr_t x) { |
|
676 |
if (is_immediate()) { |
|
677 |
guarantee(fits_in_simm(x, offset_width), "data block offset overflow"); |
|
678 |
set_long_at(0, set_simm(long_at(0), x, offset_width)); |
|
679 |
} else |
|
680 |
nativeMovConstReg_at(addr_at(0))->set_data(x); |
|
681 |
} |
|
682 |
||
683 |
void add_offset_in_bytes(intptr_t radd_offset) { |
|
684 |
set_offset (offset() + radd_offset); |
|
685 |
} |
|
686 |
||
687 |
void copy_instruction_to(address new_instruction_address); |
|
688 |
||
689 |
void verify(); |
|
690 |
void print (); |
|
691 |
||
692 |
// unit test stuff |
|
693 |
static void test(); |
|
694 |
||
695 |
private: |
|
696 |
friend inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
|
697 |
NativeMovRegMem* test = (NativeMovRegMem*)address; |
|
698 |
#ifdef ASSERT |
|
699 |
test->verify(); |
|
700 |
#endif |
|
701 |
return test; |
|
702 |
} |
|
703 |
}; |
|
704 |
||
705 |
||
706 |
// An interface for accessing/manipulating native jumps |
|
707 |
// jump_to addr |
|
708 |
// == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay> |
|
709 |
// jumpl_to addr, lreg |
|
710 |
// == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), lreg ; <delay> |
|
711 |
class NativeJump; |
|
712 |
inline NativeJump* nativeJump_at(address address); |
|
713 |
class NativeJump: public NativeInstruction { |
|
714 |
private: |
|
715 |
void guarantee_displacement(int disp, int width) { |
|
716 |
guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow"); |
|
717 |
} |
|
718 |
||
719 |
public: |
|
720 |
enum Sparc_specific_constants { |
|
721 |
sethi_offset = 0, |
|
722 |
jmpl_offset = 7 * BytesPerInstWord, |
|
723 |
instruction_size = 9 * BytesPerInstWord // includes delay slot |
|
724 |
}; |
|
725 |
||
726 |
address instruction_address() const { return addr_at(0); } |
|
727 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
728 |
||
729 |
address jump_destination() const { |
|
730 |
return (address) data64(instruction_address(), long_at(jmpl_offset)); |
|
731 |
} |
|
732 |
void set_jump_destination(address dest) { |
|
733 |
set_data64_sethi( instruction_address(), (intptr_t)dest); |
|
734 |
set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest)); |
|
735 |
} |
|
736 |
||
737 |
// Creation |
|
738 |
friend inline NativeJump* nativeJump_at(address address) { |
|
739 |
NativeJump* jump = (NativeJump*)address; |
|
740 |
#ifdef ASSERT |
|
741 |
jump->verify(); |
|
742 |
#endif |
|
743 |
return jump; |
|
744 |
} |
|
745 |
||
746 |
void verify(); |
|
747 |
void print(); |
|
748 |
||
749 |
// Unit testing stuff |
|
750 |
static void test(); |
|
751 |
||
752 |
// Insertion of native jump instruction |
|
753 |
static void insert(address code_pos, address entry); |
|
754 |
// MT-safe insertion of native jump at verified method entry |
|
755 |
static void check_verified_entry_alignment(address entry, address verified_entry) { |
|
756 |
// nothing to do for sparc. |
|
757 |
} |
|
758 |
static void patch_verified_entry(address entry, address verified_entry, address dest); |
|
759 |
}; |
|
760 |
||
761 |
||
762 |
||
763 |
// Despite the name, handles only simple branches. |
|
764 |
class NativeGeneralJump; |
|
765 |
inline NativeGeneralJump* nativeGeneralJump_at(address address); |
|
766 |
class NativeGeneralJump: public NativeInstruction { |
|
767 |
public: |
|
768 |
enum Sparc_specific_constants { |
|
769 |
instruction_size = 8 |
|
770 |
}; |
|
771 |
||
772 |
address instruction_address() const { return addr_at(0); } |
|
773 |
address jump_destination() const { return addr_at(0) + branch_destination_offset(long_at(0)); } |
|
774 |
void set_jump_destination(address dest) { |
|
775 |
int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0)); |
|
776 |
set_long_at(0, patched_instr); |
|
777 |
} |
|
778 |
NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));} |
|
779 |
void fill_delay_slot(int instr) { set_long_at(4, instr);} |
|
780 |
Assembler::Condition condition() { |
|
781 |
int x = long_at(0); |
|
782 |
return (Assembler::Condition) Assembler::inv_cond(x); |
|
783 |
} |
|
784 |
||
785 |
// Creation |
|
786 |
friend inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
|
787 |
NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
|
788 |
#ifdef ASSERT |
|
789 |
jump->verify(); |
|
790 |
#endif |
|
791 |
return jump; |
|
792 |
} |
|
793 |
||
794 |
// Insertion of native general jump instruction |
|
795 |
static void insert_unconditional(address code_pos, address entry); |
|
796 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
797 |
||
798 |
void verify(); |
|
799 |
}; |
|
800 |
||
801 |
||
802 |
class NativeIllegalInstruction: public NativeInstruction { |
|
803 |
public: |
|
804 |
enum Sparc_specific_constants { |
|
805 |
instruction_size = 4 |
|
806 |
}; |
|
807 |
||
808 |
// Insert illegal opcode as specific address |
|
809 |
static void insert(address code_pos); |
|
810 |
}; |
|
7397 | 811 |
|
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
53149
diff
changeset
|
812 |
#endif // CPU_SPARC_NATIVEINST_SPARC_HPP |