/*

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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

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 *

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

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#ifndef CPU_SPARC_ASSEMBLER_SPARC_HPP

#define CPU_SPARC_ASSEMBLER_SPARC_HPP

#include "asm/register.hpp"

// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction

// level; i.e., what you write is what you get. The Assembler is generating code

// into a CodeBuffer.

class Assembler : public AbstractAssembler {

  friend class AbstractAssembler;

  friend class AddressLiteral;

  // code patchers need various routines like inv_wdisp()

  friend class NativeInstruction;

  friend class NativeGeneralJump;

  friend class Relocation;

  friend class Label;

 public:

  // op carries format info; see page 62 & 267

  enum ops {

    call_op   = 1, // fmt 1

    branch_op = 0, // also sethi (fmt2)

    arith_op  = 2, // fmt 3, arith & misc

    ldst_op   = 3  // fmt 3, load/store

  };

  enum op2s {

    bpr_op2   = 3,

    fb_op2    = 6,

    fbp_op2   = 5,

    br_op2    = 2,

    bp_op2    = 1,

    sethi_op2 = 4

  };

  enum op3s {

    // selected op3s

    add_op3      = 0x00,

    and_op3      = 0x01,

    or_op3       = 0x02,

    xor_op3      = 0x03,

    sub_op3      = 0x04,

    andn_op3     = 0x05,

    orn_op3      = 0x06,

    xnor_op3     = 0x07,

    addc_op3     = 0x08,

    mulx_op3     = 0x09,

    umul_op3     = 0x0a,

    smul_op3     = 0x0b,

    subc_op3     = 0x0c,

    udivx_op3    = 0x0d,

    udiv_op3     = 0x0e,

    sdiv_op3     = 0x0f,

    addcc_op3    = 0x10,

    andcc_op3    = 0x11,

    orcc_op3     = 0x12,

    xorcc_op3    = 0x13,

    subcc_op3    = 0x14,

    andncc_op3   = 0x15,

    orncc_op3    = 0x16,

    xnorcc_op3   = 0x17,

    addccc_op3   = 0x18,

    aes4_op3     = 0x19,

    umulcc_op3   = 0x1a,

    smulcc_op3   = 0x1b,

    subccc_op3   = 0x1c,

    udivcc_op3   = 0x1e,

    sdivcc_op3   = 0x1f,

    taddcc_op3   = 0x20,

    tsubcc_op3   = 0x21,

    taddcctv_op3 = 0x22,

    tsubcctv_op3 = 0x23,

    mulscc_op3   = 0x24,

    sll_op3      = 0x25,

    sllx_op3     = 0x25,

    srl_op3      = 0x26,

    srlx_op3     = 0x26,

    sra_op3      = 0x27,

    srax_op3     = 0x27,

    rdreg_op3    = 0x28,

    membar_op3   = 0x28,

    flushw_op3   = 0x2b,

    movcc_op3    = 0x2c,

    sdivx_op3    = 0x2d,

    popc_op3     = 0x2e,

    movr_op3     = 0x2f,

    sir_op3      = 0x30,

    wrreg_op3    = 0x30,

    saved_op3    = 0x31,

    fpop1_op3    = 0x34,

    fpop2_op3    = 0x35,

    impdep1_op3  = 0x36,

    addx_op3     = 0x36,

    aes3_op3     = 0x36,

    sha_op3      = 0x36,

    bmask_op3    = 0x36,

    bshuffle_op3   = 0x36,

    alignaddr_op3  = 0x36,

    faligndata_op3 = 0x36,

    flog3_op3    = 0x36,

    edge_op3     = 0x36,

    fzero_op3    = 0x36,

    fsrc_op3     = 0x36,

    fnot_op3     = 0x36,

    mpmul_op3    = 0x36,

    umulx_op3    = 0x36,

    xmulx_op3    = 0x36,

    crc32c_op3   = 0x36,

    impdep2_op3  = 0x37,

    stpartialf_op3 = 0x37,

    jmpl_op3     = 0x38,

    rett_op3     = 0x39,

    trap_op3     = 0x3a,

    flush_op3    = 0x3b,

    save_op3     = 0x3c,

    restore_op3  = 0x3d,

    done_op3     = 0x3e,

    retry_op3    = 0x3e,

    lduw_op3     = 0x00,

    ldub_op3     = 0x01,

    lduh_op3     = 0x02,

    ldd_op3      = 0x03,

    stw_op3      = 0x04,

    stb_op3      = 0x05,

    sth_op3      = 0x06,

    std_op3      = 0x07,

    ldsw_op3     = 0x08,

    ldsb_op3     = 0x09,

    ldsh_op3     = 0x0a,

    ldx_op3      = 0x0b,

    stx_op3      = 0x0e,

    swap_op3     = 0x0f,

    stwa_op3     = 0x14,

    stxa_op3     = 0x1e,

    ldf_op3      = 0x20,

    ldfsr_op3    = 0x21,

    ldqf_op3     = 0x22,

    lddf_op3     = 0x23,

    stf_op3      = 0x24,

    stfsr_op3    = 0x25,

    stqf_op3     = 0x26,

    stdf_op3     = 0x27,

    prefetch_op3 = 0x2d,

    casa_op3     = 0x3c,

    casxa_op3    = 0x3e,

    mftoi_op3    = 0x36,

    alt_bit_op3  = 0x10,

     cc_bit_op3  = 0x10

  };

  enum opfs {

    // selected opfs

    edge8n_opf         = 0x01,

    fmovs_opf          = 0x01,

    fmovd_opf          = 0x02,

    fnegs_opf          = 0x05,

    fnegd_opf          = 0x06,

    addxc_opf          = 0x11,

    addxccc_opf        = 0x13,

    umulxhi_opf        = 0x16,

    alignaddr_opf      = 0x18,

    bmask_opf          = 0x19,

    fadds_opf          = 0x41,

    faddd_opf          = 0x42,

    fsubs_opf          = 0x45,

    fsubd_opf          = 0x46,

    faligndata_opf     = 0x48,

    fmuls_opf          = 0x49,

    fmuld_opf          = 0x4a,

    bshuffle_opf       = 0x4c,

    fdivs_opf          = 0x4d,

    fdivd_opf          = 0x4e,

    fcmps_opf          = 0x51,

    fcmpd_opf          = 0x52,

    fstox_opf          = 0x81,

    fdtox_opf          = 0x82,

    fxtos_opf          = 0x84,

    fxtod_opf          = 0x88,

    fitos_opf          = 0xc4,

    fdtos_opf          = 0xc6,

    fitod_opf          = 0xc8,

    fstod_opf          = 0xc9,

    fstoi_opf          = 0xd1,

    fdtoi_opf          = 0xd2,

    mdtox_opf          = 0x110,

    mstouw_opf         = 0x111,

    mstosw_opf         = 0x113,

    xmulx_opf          = 0x115,

    xmulxhi_opf        = 0x116,

    mxtod_opf          = 0x118,

    mwtos_opf          = 0x119,

    aes_kexpand0_opf   = 0x130,

    aes_kexpand2_opf   = 0x131,

    sha1_opf           = 0x141,

    sha256_opf         = 0x142,

    sha512_opf         = 0x143,

    crc32c_opf         = 0x147,

    mpmul_opf          = 0x148

  };

  enum op5s {

    aes_eround01_op5   = 0x00,

    aes_eround23_op5   = 0x01,

    aes_dround01_op5   = 0x02,

    aes_dround23_op5   = 0x03,

    aes_eround01_l_op5 = 0x04,

    aes_eround23_l_op5 = 0x05,

    aes_dround01_l_op5 = 0x06,

    aes_dround23_l_op5 = 0x07,

    aes_kexpand1_op5   = 0x08

  };

  enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };

  enum Condition {

     // for FBfcc & FBPfcc instruction

    f_never                     = 0,

    f_notEqual                  = 1,

    f_notZero                   = 1,

    f_lessOrGreater             = 2,

    f_unorderedOrLess           = 3,

    f_less                      = 4,

    f_unorderedOrGreater        = 5,

    f_greater                   = 6,

    f_unordered                 = 7,

    f_always                    = 8,

    f_equal                     = 9,

    f_zero                      = 9,

    f_unorderedOrEqual          = 10,

    f_greaterOrEqual            = 11,

    f_unorderedOrGreaterOrEqual = 12,

    f_lessOrEqual               = 13,

    f_unorderedOrLessOrEqual    = 14,

    f_ordered                   = 15,

    // for integers

    never                = 0,

    equal                = 1,

    zero                 = 1,

    lessEqual            = 2,

    less                 = 3,

    lessEqualUnsigned    = 4,

    lessUnsigned         = 5,

    carrySet             = 5,

    negative             = 6,

    overflowSet          = 7,

    always               = 8,

    notEqual             = 9,

    notZero              = 9,

    greater              = 10,

    greaterEqual         = 11,

    greaterUnsigned      = 12,

    greaterEqualUnsigned = 13,

    carryClear           = 13,

    positive             = 14,

    overflowClear        = 15

  };

  enum CC {

    // ptr_cc is the correct condition code for a pointer or intptr_t:

    icc  = 0, xcc  = 2, ptr_cc = xcc,

    fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3

  };

  enum PrefetchFcn {

    severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4

  };

 public:

  // Helper functions for groups of instructions

  enum Predict { pt = 1, pn = 0 }; // pt = predict taken

  enum Membar_mask_bits { // page 184, v9

    StoreStore = 1 << 3,

    LoadStore  = 1 << 2,

    StoreLoad  = 1 << 1,

    LoadLoad   = 1 << 0,

    Sync       = 1 << 6,

    MemIssue   = 1 << 5,

    Lookaside  = 1 << 4

  };

  //---<  calculate length of instruction  >---

  // With SPARC being a RISC architecture, this always is BytesPerInstWord

  // instruction must start at passed address

  static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }

  //---<  longest instructions  >---

  static unsigned int instr_maxlen() { return BytesPerInstWord; }

  static bool is_in_wdisp_range(address a, address b, int nbits) {

    intptr_t d = intptr_t(b) - intptr_t(a);

    return is_simm(d, nbits + 2);

  }

  address target_distance(Label &L) {

    // Assembler::target(L) should be called only when

    // a branch instruction is emitted since non-bound

    // labels record current pc() as a branch address.

    if (L.is_bound()) return target(L);

    // Return current address for non-bound labels.

    return pc();

  }

  // test if label is in simm16 range in words (wdisp16).

  bool is_in_wdisp16_range(Label &L) {

    return is_in_wdisp_range(target_distance(L), pc(), 16);

  }

  // test if the distance between two addresses fits in simm30 range in words

  static bool is_in_wdisp30_range(address a, address b) {

    return is_in_wdisp_range(a, b, 30);

  }

  enum ASIs { // page 72, v9

    ASI_PRIMARY            = 0x80,

    ASI_PRIMARY_NOFAULT    = 0x82,

    ASI_PRIMARY_LITTLE     = 0x88,

    // 8x8-bit partial store

    ASI_PST8_PRIMARY       = 0xC0,

    // Block initializing store

    ASI_ST_BLKINIT_PRIMARY = 0xE2,

    // Most-Recently-Used (MRU) BIS variant

    ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2

    // add more from book as needed

  };

 protected:

  // helpers

  // x is supposed to fit in a field "nbits" wide

  // and be sign-extended. Check the range.

  static void assert_signed_range(intptr_t x, int nbits) {

    assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),

           "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);

  }

  static void assert_signed_word_disp_range(intptr_t x, int nbits) {

    assert((x & 3) == 0, "not word aligned");

    assert_signed_range(x, nbits + 2);

  }

  static void assert_unsigned_range(int x, int nbits) {

    assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");

  }

  // fields: note bits numbered from LSB = 0, fields known by inclusive bit range

  static int fmask(juint hi_bit, juint lo_bit) {

    assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");

    return (1 << (hi_bit-lo_bit + 1)) - 1;

  }

  // inverse of u_field

  static int inv_u_field(int x, int hi_bit, int lo_bit) {

    juint r = juint(x) >> lo_bit;

    r &= fmask(hi_bit, lo_bit);

    return int(r);

  }

  // signed version: extract from field and sign-extend

  static int inv_s_field(int x, int hi_bit, int lo_bit) {

    int sign_shift = 31 - hi_bit;

    return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit);

  }

  // given a field that ranges from hi_bit to lo_bit (inclusive,

  // LSB = 0), and an unsigned value for the field,

  // shift it into the field

#ifdef ASSERT

  static int u_field(int x, int hi_bit, int lo_bit) {

    assert((x & ~fmask(hi_bit, lo_bit)) == 0,

            "value out of range");

    int r = x << lo_bit;

    assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");

    return r;

  }

#else

  // make sure this is inlined as it will reduce code size significantly

  #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))

#endif

  static int inv_op(int x)   { return inv_u_field(x, 31, 30); }

  static int inv_op2(int x)  { return inv_u_field(x, 24, 22); }

  static int inv_op3(int x)  { return inv_u_field(x, 24, 19); }

  static int inv_cond(int x) { return inv_u_field(x, 28, 25); }

  static bool inv_immed(int x)   { return (x & Assembler::immed(true)) != 0; }

  static Register inv_rd(int x)  { return as_Register(inv_u_field(x, 29, 25)); }

  static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); }

  static Register inv_rs2(int x) { return as_Register(inv_u_field(x,  4,  0)); }

  static int op(int x)           { return u_field(x,             31, 30); }

  static int rd(Register r)      { return u_field(r->encoding(), 29, 25); }

  static int fcn(int x)          { return u_field(x,             29, 25); }

  static int op3(int x)          { return u_field(x,             24, 19); }

  static int rs1(Register r)     { return u_field(r->encoding(), 18, 14); }

  static int rs2(Register r)     { return u_field(r->encoding(),  4,  0); }

  static int annul(bool a)       { return u_field(a ? 1 : 0,     29, 29); }

  static int cond(int x)         { return u_field(x,             28, 25); }

  static int cond_mov(int x)     { return u_field(x,             17, 14); }

  static int rcond(RCondition x) { return u_field(x,             12, 10); }

  static int op2(int x)          { return u_field(x,             24, 22); }

  static int predict(bool p)     { return u_field(p ? 1 : 0,     19, 19); }

  static int branchcc(CC fcca)   { return u_field(fcca,          21, 20); }

  static int cmpcc(CC fcca)      { return u_field(fcca,          26, 25); }

  static int imm_asi(int x)      { return u_field(x,             12,  5); }

  static int immed(bool i)       { return u_field(i ? 1 : 0,     13, 13); }

  static int opf_low6(int w)     { return u_field(w,             10,  5); }

  static int opf_low5(int w)     { return u_field(w,              9,  5); }

  static int op5(int x)          { return u_field(x,              8,  5); }

  static int trapcc(CC cc)       { return u_field(cc,            12, 11); }

  static int sx(int i)           { return u_field(i,             12, 12); } // shift x=1 means 64-bit

  static int opf(int x)          { return u_field(x,             13,  5); }

  static bool is_cbcond(int x) {

    return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&

            inv_op(x) == branch_op && inv_op2(x) == bpr_op2);

  }

  static bool is_cxb(int x) {

    assert(is_cbcond(x), "wrong instruction");

    return (x & (1 << 21)) != 0;

  }

  static bool is_branch(int x) {

    if (inv_op(x) != Assembler::branch_op) return false;

    bool is_bpr = inv_op2(x) == Assembler::bpr_op2;

    bool is_bp  = inv_op2(x) == Assembler::bp_op2;

    bool is_br  = inv_op2(x) == Assembler::br_op2;

    bool is_fp  = inv_op2(x) == Assembler::fb_op2;

    bool is_fbp = inv_op2(x) == Assembler::fbp_op2;

    return is_bpr || is_bp || is_br || is_fp || is_fbp;

  }

  static bool is_call(int x) {

    return inv_op(x) == Assembler::call_op;

  }

  static bool is_jump(int x) {

    if (inv_op(x) != Assembler::arith_op) return false;

    bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3;

    bool is_rett = inv_op3(x) == Assembler::rett_op3;

    return is_jmpl || is_rett;

  }

  static bool is_rdpc(int x) {