hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp
author never
Wed, 27 Aug 2008 00:21:55 -0700
changeset 1066 717c3345024f
parent 670 ddf3e9583f2f
child 2571 d602ad6538bd
permissions -rw-r--r--
5108146: Merge i486 and amd64 cpu directories 6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
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/*
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 * Copyright 1998-2008 Sun Microsystems, Inc.  All Rights Reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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 * CA 95054 USA or visit www.sun.com if you need additional information or
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 * have any questions.
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 *
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 */
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# include "incls/_precompiled.incl"
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# include "incls/_relocInfo_sparc.cpp.incl"
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void Relocation::pd_set_data_value(address x, intptr_t o) {
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  NativeInstruction* ip = nativeInstruction_at(addr());
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  jint inst = ip->long_at(0);
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  assert(inst != NativeInstruction::illegal_instruction(), "no breakpoint");
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  switch (Assembler::inv_op(inst)) {
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  case Assembler::ldst_op:
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    #ifdef ASSERT
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      switch (Assembler::inv_op3(inst)) {
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        case Assembler::lduw_op3:
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        case Assembler::ldub_op3:
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        case Assembler::lduh_op3:
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        case Assembler::ldd_op3:
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        case Assembler::ldsw_op3:
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        case Assembler::ldsb_op3:
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        case Assembler::ldsh_op3:
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        case Assembler::ldx_op3:
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        case Assembler::ldf_op3:
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        case Assembler::lddf_op3:
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        case Assembler::stw_op3:
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        case Assembler::stb_op3:
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        case Assembler::sth_op3:
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        case Assembler::std_op3:
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        case Assembler::stx_op3:
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        case Assembler::stf_op3:
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        case Assembler::stdf_op3:
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        case Assembler::casa_op3:
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        case Assembler::casxa_op3:
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          break;
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        default:
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          ShouldNotReachHere();
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      }
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      goto do_non_sethi;
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    #endif
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  case Assembler::arith_op:
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    #ifdef ASSERT
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      switch (Assembler::inv_op3(inst)) {
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        case Assembler::or_op3:
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        case Assembler::add_op3:
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        case Assembler::jmpl_op3:
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          break;
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        default:
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          ShouldNotReachHere();
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      }
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    do_non_sethi:;
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    #endif
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    {
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    guarantee(Assembler::inv_immed(inst), "must have a simm13 field");
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    int simm13 = Assembler::low10((intptr_t)x) + o;
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    guarantee(Assembler::is_simm13(simm13), "offset can't overflow simm13");
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    inst &= ~Assembler::simm(    -1, 13);
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    inst |=  Assembler::simm(simm13, 13);
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    ip->set_long_at(0, inst);
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    }
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    break;
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  case Assembler::branch_op:
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    {
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#ifdef _LP64
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    jint inst2;
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    guarantee(Assembler::inv_op2(inst)==Assembler::sethi_op2, "must be sethi");
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    if (format() != 0) {
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      assert(type() == relocInfo::oop_type, "only narrow oops case");
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      jint np = oopDesc::encode_heap_oop((oop)x);
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      inst &= ~Assembler::hi22(-1);
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      inst |=  Assembler::hi22((intptr_t)np);
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      ip->set_long_at(0, inst);
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      inst2 = ip->long_at( NativeInstruction::nop_instruction_size );
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      guarantee(Assembler::inv_op(inst2)==Assembler::arith_op, "arith op");
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      ip->set_long_at(NativeInstruction::nop_instruction_size, ip->set_data32_simm13( inst2, (intptr_t)np));
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      break;
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    }
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    ip->set_data64_sethi( ip->addr_at(0), (intptr_t)x );
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#ifdef COMPILER2
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    // [RGV] Someone must have missed putting in a reloc entry for the
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    // add in compiler2.
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    inst2 = ip->long_at( NativeMovConstReg::add_offset );
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    guarantee(Assembler::inv_op(inst2)==Assembler::arith_op, "arith op");
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    ip->set_long_at(NativeMovConstReg::add_offset,ip->set_data32_simm13( inst2, (intptr_t)x+o));
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#endif
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#else
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    guarantee(Assembler::inv_op2(inst)==Assembler::sethi_op2, "must be sethi");
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    inst &= ~Assembler::hi22(     -1);
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    inst |=  Assembler::hi22((intptr_t)x);
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    // (ignore offset; it doesn't play into the sethi)
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    ip->set_long_at(0, inst);
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#endif
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    }
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    break;
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  default:
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    guarantee(false, "instruction must perform arithmetic or memory access");
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  }
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}
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address Relocation::pd_call_destination(address orig_addr) {
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  intptr_t adj = 0;
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  if (orig_addr != NULL) {
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    // We just moved this call instruction from orig_addr to addr().
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    // This means its target will appear to have grown by addr() - orig_addr.
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    adj = -( addr() - orig_addr );
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  }
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  if (NativeCall::is_call_at(addr())) {
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    NativeCall* call = nativeCall_at(addr());
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    return call->destination() + adj;
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  }
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  if (NativeFarCall::is_call_at(addr())) {
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    NativeFarCall* call = nativeFarCall_at(addr());
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    return call->destination() + adj;
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  }
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  // Special case:  Patchable branch local to the code cache.
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  // This will break badly if the code cache grows larger than a few Mb.
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  NativeGeneralJump* br = nativeGeneralJump_at(addr());
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  return br->jump_destination() + adj;
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}
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void Relocation::pd_set_call_destination(address x) {
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  if (NativeCall::is_call_at(addr())) {
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    NativeCall* call = nativeCall_at(addr());
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    call->set_destination(x);
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    return;
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  }
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  if (NativeFarCall::is_call_at(addr())) {
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    NativeFarCall* call = nativeFarCall_at(addr());
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    call->set_destination(x);
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    return;
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  }
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  // Special case:  Patchable branch local to the code cache.
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  // This will break badly if the code cache grows larger than a few Mb.
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  NativeGeneralJump* br = nativeGeneralJump_at(addr());
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  br->set_jump_destination(x);
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}
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address* Relocation::pd_address_in_code() {
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  // SPARC never embeds addresses in code, at present.
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  //assert(type() == relocInfo::oop_type, "only oops are inlined at present");
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  return (address*)addr();
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}
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address Relocation::pd_get_address_from_code() {
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  // SPARC never embeds addresses in code, at present.
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  //assert(type() == relocInfo::oop_type, "only oops are inlined at present");
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  return *(address*)addr();
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}
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int Relocation::pd_breakpoint_size() {
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  // minimum breakpoint size, in short words
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  return NativeIllegalInstruction::instruction_size / sizeof(short);
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}
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void Relocation::pd_swap_in_breakpoint(address x, short* instrs, int instrlen) {
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  Untested("pd_swap_in_breakpoint");
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  // %%% probably do not need a general instrlen; just use the trap size
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  if (instrs != NULL) {
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    assert(instrlen * sizeof(short) == NativeIllegalInstruction::instruction_size, "enough instrlen in reloc. data");
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    for (int i = 0; i < instrlen; i++) {
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      instrs[i] = ((short*)x)[i];
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    }
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  }
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  NativeIllegalInstruction::insert(x);
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}
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void Relocation::pd_swap_out_breakpoint(address x, short* instrs, int instrlen) {
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  Untested("pd_swap_out_breakpoint");
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  assert(instrlen * sizeof(short) == sizeof(int), "enough buf");
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  union { int l; short s[1]; } u;
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  for (int i = 0; i < instrlen; i++) {
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    u.s[i] = instrs[i];
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  }
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  NativeInstruction* ni = nativeInstruction_at(x);
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  ni->set_long_at(0, u.l);
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}
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void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
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}
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void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
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}