author | duke |
Wed, 05 Jul 2017 19:47:10 +0200 | |
changeset 25031 | 28dd0c7beb3c |
parent 24669 | 14439491d407 |
child 28954 | 7dda6c26cc98 |
child 29180 | 50369728b00e |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "c1/c1_InstructionPrinter.hpp" |
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#include "c1/c1_LIR.hpp" |
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#include "c1/c1_LIRAssembler.hpp" |
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#include "c1/c1_ValueStack.hpp" |
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#include "ci/ciInstance.hpp" |
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#include "runtime/sharedRuntime.hpp" |
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Register LIR_OprDesc::as_register() const { |
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return FrameMap::cpu_rnr2reg(cpu_regnr()); |
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} |
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||
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Register LIR_OprDesc::as_register_lo() const { |
|
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return FrameMap::cpu_rnr2reg(cpu_regnrLo()); |
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} |
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||
41 |
Register LIR_OprDesc::as_register_hi() const { |
|
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return FrameMap::cpu_rnr2reg(cpu_regnrHi()); |
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} |
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||
1066 | 45 |
#if defined(X86) |
1 | 46 |
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XMMRegister LIR_OprDesc::as_xmm_float_reg() const { |
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return FrameMap::nr2xmmreg(xmm_regnr()); |
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} |
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||
51 |
XMMRegister LIR_OprDesc::as_xmm_double_reg() const { |
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assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); |
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return FrameMap::nr2xmmreg(xmm_regnrLo()); |
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} |
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||
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#endif // X86 |
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#if defined(SPARC) || defined(PPC) |
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FloatRegister LIR_OprDesc::as_float_reg() const { |
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return FrameMap::nr2floatreg(fpu_regnr()); |
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} |
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||
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FloatRegister LIR_OprDesc::as_double_reg() const { |
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return FrameMap::nr2floatreg(fpu_regnrHi()); |
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} |
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||
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#endif |
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||
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#ifdef ARM |
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FloatRegister LIR_OprDesc::as_float_reg() const { |
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return as_FloatRegister(fpu_regnr()); |
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} |
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FloatRegister LIR_OprDesc::as_double_reg() const { |
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return as_FloatRegister(fpu_regnrLo()); |
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} |
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#endif |
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LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
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||
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LIR_Opr LIR_OprFact::value_type(ValueType* type) { |
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ValueTag tag = type->tag(); |
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switch (tag) { |
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case metaDataTag : { |
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ClassConstant* c = type->as_ClassConstant(); |
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if (c != NULL && !c->value()->is_loaded()) { |
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return LIR_OprFact::metadataConst(NULL); |
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} else if (c != NULL) { |
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return LIR_OprFact::metadataConst(c->value()->constant_encoding()); |
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} else { |
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MethodConstant* m = type->as_MethodConstant(); |
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assert (m != NULL, "not a class or a method?"); |
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return LIR_OprFact::metadataConst(m->value()->constant_encoding()); |
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} |
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} |
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case objectTag : { |
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return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); |
102 |
} |
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case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
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case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
105 |
case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); |
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case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); |
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107 |
case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); |
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default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
1 | 109 |
} |
110 |
} |
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111 |
||
112 |
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113 |
LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { |
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114 |
switch (type->tag()) { |
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case objectTag: return LIR_OprFact::oopConst(NULL); |
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case addressTag:return LIR_OprFact::addressConst(0); |
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case intTag: return LIR_OprFact::intConst(0); |
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case floatTag: return LIR_OprFact::floatConst(0.0); |
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case longTag: return LIR_OprFact::longConst(0); |
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case doubleTag: return LIR_OprFact::doubleConst(0.0); |
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default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
1 | 122 |
} |
123 |
return illegalOpr; |
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} |
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||
126 |
||
127 |
||
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//--------------------------------------------------- |
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130 |
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LIR_Address::Scale LIR_Address::scale(BasicType type) { |
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int elem_size = type2aelembytes(type); |
1 | 133 |
switch (elem_size) { |
134 |
case 1: return LIR_Address::times_1; |
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case 2: return LIR_Address::times_2; |
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case 4: return LIR_Address::times_4; |
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case 8: return LIR_Address::times_8; |
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} |
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ShouldNotReachHere(); |
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return LIR_Address::times_1; |
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} |
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143 |
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#ifndef PRODUCT |
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void LIR_Address::verify() const { |
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#if defined(SPARC) || defined(PPC) |
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assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
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assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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#endif |
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#ifdef ARM |
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assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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// Note: offsets higher than 4096 must not be rejected here. They can |
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// be handled by the back-end or will be rejected if not. |
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#endif |
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#ifdef _LP64 |
156 |
assert(base()->is_cpu_register(), "wrong base operand"); |
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assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); |
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assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
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"wrong type for addresses"); |
160 |
#else |
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161 |
assert(base()->is_single_cpu(), "wrong base operand"); |
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assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); |
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assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
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"wrong type for addresses"); |
165 |
#endif |
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166 |
} |
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167 |
#endif |
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168 |
||
169 |
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170 |
//--------------------------------------------------- |
|
171 |
||
172 |
char LIR_OprDesc::type_char(BasicType t) { |
|
173 |
switch (t) { |
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174 |
case T_ARRAY: |
|
175 |
t = T_OBJECT; |
|
176 |
case T_BOOLEAN: |
|
177 |
case T_CHAR: |
|
178 |
case T_FLOAT: |
|
179 |
case T_DOUBLE: |
|
180 |
case T_BYTE: |
|
181 |
case T_SHORT: |
|
182 |
case T_INT: |
|
183 |
case T_LONG: |
|
184 |
case T_OBJECT: |
|
185 |
case T_ADDRESS: |
|
186 |
case T_VOID: |
|
187 |
return ::type2char(t); |
|
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case T_METADATA: |
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189 |
return 'M'; |
1 | 190 |
case T_ILLEGAL: |
191 |
return '?'; |
|
192 |
||
193 |
default: |
|
194 |
ShouldNotReachHere(); |
|
1066 | 195 |
return '?'; |
1 | 196 |
} |
197 |
} |
|
198 |
||
199 |
#ifndef PRODUCT |
|
200 |
void LIR_OprDesc::validate_type() const { |
|
201 |
||
202 |
#ifdef ASSERT |
|
203 |
if (!is_pointer() && !is_illegal()) { |
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OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 |
1 | 205 |
switch (as_BasicType(type_field())) { |
206 |
case T_LONG: |
|
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assert((kindfield == cpu_register || kindfield == stack_value) && |
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size_field() == double_size, "must match"); |
1 | 209 |
break; |
210 |
case T_FLOAT: |
|
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// FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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assert((kindfield == fpu_register || kindfield == stack_value |
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ARM_ONLY(|| kindfield == cpu_register) |
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PPC_ONLY(|| kindfield == cpu_register) ) && |
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size_field() == single_size, "must match"); |
1 | 216 |
break; |
217 |
case T_DOUBLE: |
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// FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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assert((kindfield == fpu_register || kindfield == stack_value |
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ARM_ONLY(|| kindfield == cpu_register) |
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PPC_ONLY(|| kindfield == cpu_register) ) && |
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222 |
size_field() == double_size, "must match"); |
1 | 223 |
break; |
224 |
case T_BOOLEAN: |
|
225 |
case T_CHAR: |
|
226 |
case T_BYTE: |
|
227 |
case T_SHORT: |
|
228 |
case T_INT: |
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case T_ADDRESS: |
1 | 230 |
case T_OBJECT: |
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case T_METADATA: |
1 | 232 |
case T_ARRAY: |
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assert((kindfield == cpu_register || kindfield == stack_value) && |
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size_field() == single_size, "must match"); |
1 | 235 |
break; |
236 |
||
237 |
case T_ILLEGAL: |
|
238 |
// XXX TKR also means unknown right now |
|
239 |
// assert(is_illegal(), "must match"); |
|
240 |
break; |
|
241 |
||
242 |
default: |
|
243 |
ShouldNotReachHere(); |
|
244 |
} |
|
245 |
} |
|
246 |
#endif |
|
247 |
||
248 |
} |
|
249 |
#endif // PRODUCT |
|
250 |
||
251 |
||
252 |
bool LIR_OprDesc::is_oop() const { |
|
253 |
if (is_pointer()) { |
|
254 |
return pointer()->is_oop_pointer(); |
|
255 |
} else { |
|
256 |
OprType t= type_field(); |
|
257 |
assert(t != unknown_type, "not set"); |
|
258 |
return t == object_type; |
|
259 |
} |
|
260 |
} |
|
261 |
||
262 |
||
263 |
||
264 |
void LIR_Op2::verify() const { |
|
265 |
#ifdef ASSERT |
|
266 |
switch (code()) { |
|
267 |
case lir_cmove: |
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case lir_xchg: |
1 | 269 |
break; |
270 |
||
271 |
default: |
|
272 |
assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), |
|
273 |
"can't produce oops from arith"); |
|
274 |
} |
|
275 |
||
276 |
if (TwoOperandLIRForm) { |
|
277 |
switch (code()) { |
|
278 |
case lir_add: |
|
279 |
case lir_sub: |
|
280 |
case lir_mul: |
|
281 |
case lir_mul_strictfp: |
|
282 |
case lir_div: |
|
283 |
case lir_div_strictfp: |
|
284 |
case lir_rem: |
|
285 |
case lir_logic_and: |
|
286 |
case lir_logic_or: |
|
287 |
case lir_logic_xor: |
|
288 |
case lir_shl: |
|
289 |
case lir_shr: |
|
290 |
assert(in_opr1() == result_opr(), "opr1 and result must match"); |
|
291 |
assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); |
|
292 |
break; |
|
293 |
||
294 |
// special handling for lir_ushr because of write barriers |
|
295 |
case lir_ushr: |
|
296 |
assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); |
|
297 |
assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); |
|
298 |
break; |
|
299 |
||
300 |
} |
|
301 |
} |
|
302 |
#endif |
|
303 |
} |
|
304 |
||
305 |
||
306 |
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) |
|
307 |
: LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
|
308 |
, _cond(cond) |
|
309 |
, _type(type) |
|
310 |
, _label(block->label()) |
|
311 |
, _block(block) |
|
312 |
, _ublock(NULL) |
|
313 |
, _stub(NULL) { |
|
314 |
} |
|
315 |
||
316 |
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : |
|
317 |
LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
|
318 |
, _cond(cond) |
|
319 |
, _type(type) |
|
320 |
, _label(stub->entry()) |
|
321 |
, _block(NULL) |
|
322 |
, _ublock(NULL) |
|
323 |
, _stub(stub) { |
|
324 |
} |
|
325 |
||
326 |
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) |
|
327 |
: LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) |
|
328 |
, _cond(cond) |
|
329 |
, _type(type) |
|
330 |
, _label(block->label()) |
|
331 |
, _block(block) |
|
332 |
, _ublock(ublock) |
|
333 |
, _stub(NULL) |
|
334 |
{ |
|
335 |
} |
|
336 |
||
337 |
void LIR_OpBranch::change_block(BlockBegin* b) { |
|
338 |
assert(_block != NULL, "must have old block"); |
|
339 |
assert(_block->label() == label(), "must be equal"); |
|
340 |
||
341 |
_block = b; |
|
342 |
_label = b->label(); |
|
343 |
} |
|
344 |
||
345 |
void LIR_OpBranch::change_ublock(BlockBegin* b) { |
|
346 |
assert(_ublock != NULL, "must have old block"); |
|
347 |
_ublock = b; |
|
348 |
} |
|
349 |
||
350 |
void LIR_OpBranch::negate_cond() { |
|
351 |
switch (_cond) { |
|
352 |
case lir_cond_equal: _cond = lir_cond_notEqual; break; |
|
353 |
case lir_cond_notEqual: _cond = lir_cond_equal; break; |
|
354 |
case lir_cond_less: _cond = lir_cond_greaterEqual; break; |
|
355 |
case lir_cond_lessEqual: _cond = lir_cond_greater; break; |
|
356 |
case lir_cond_greaterEqual: _cond = lir_cond_less; break; |
|
357 |
case lir_cond_greater: _cond = lir_cond_lessEqual; break; |
|
358 |
default: ShouldNotReachHere(); |
|
359 |
} |
|
360 |
} |
|
361 |
||
362 |
||
363 |
LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, |
|
364 |
LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
|
365 |
bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, |
|
6453 | 366 |
CodeStub* stub) |
367 |
||
1 | 368 |
: LIR_Op(code, result, NULL) |
369 |
, _object(object) |
|
370 |
, _array(LIR_OprFact::illegalOpr) |
|
371 |
, _klass(klass) |
|
372 |
, _tmp1(tmp1) |
|
373 |
, _tmp2(tmp2) |
|
374 |
, _tmp3(tmp3) |
|
375 |
, _fast_check(fast_check) |
|
376 |
, _stub(stub) |
|
377 |
, _info_for_patch(info_for_patch) |
|
378 |
, _info_for_exception(info_for_exception) |
|
6453 | 379 |
, _profiled_method(NULL) |
380 |
, _profiled_bci(-1) |
|
381 |
, _should_profile(false) |
|
382 |
{ |
|
1 | 383 |
if (code == lir_checkcast) { |
384 |
assert(info_for_exception != NULL, "checkcast throws exceptions"); |
|
385 |
} else if (code == lir_instanceof) { |
|
386 |
assert(info_for_exception == NULL, "instanceof throws no exceptions"); |
|
387 |
} else { |
|
388 |
ShouldNotReachHere(); |
|
389 |
} |
|
390 |
} |
|
391 |
||
392 |
||
393 |
||
6453 | 394 |
LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) |
1 | 395 |
: LIR_Op(code, LIR_OprFact::illegalOpr, NULL) |
396 |
, _object(object) |
|
397 |
, _array(array) |
|
398 |
, _klass(NULL) |
|
399 |
, _tmp1(tmp1) |
|
400 |
, _tmp2(tmp2) |
|
401 |
, _tmp3(tmp3) |
|
402 |
, _fast_check(false) |
|
403 |
, _stub(NULL) |
|
404 |
, _info_for_patch(NULL) |
|
405 |
, _info_for_exception(info_for_exception) |
|
6453 | 406 |
, _profiled_method(NULL) |
407 |
, _profiled_bci(-1) |
|
408 |
, _should_profile(false) |
|
409 |
{ |
|
1 | 410 |
if (code == lir_store_check) { |
8067
f5f4eac4c48f
7008809: should report the class in ArrayStoreExceptions from compiled code
never
parents:
7427
diff
changeset
|
411 |
_stub = new ArrayStoreExceptionStub(object, info_for_exception); |
1 | 412 |
assert(info_for_exception != NULL, "store_check throws exceptions"); |
413 |
} else { |
|
414 |
ShouldNotReachHere(); |
|
415 |
} |
|
416 |
} |
|
417 |
||
418 |
||
419 |
LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, |
|
420 |
LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) |
|
421 |
: LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) |
|
422 |
, _tmp(tmp) |
|
423 |
, _src(src) |
|
424 |
, _src_pos(src_pos) |
|
425 |
, _dst(dst) |
|
426 |
, _dst_pos(dst_pos) |
|
427 |
, _flags(flags) |
|
428 |
, _expected_type(expected_type) |
|
429 |
, _length(length) { |
|
430 |
_stub = new ArrayCopyStub(this); |
|
431 |
} |
|
432 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
433 |
LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
434 |
: LIR_Op(lir_updatecrc32, res, NULL) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
435 |
, _crc(crc) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
436 |
, _val(val) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
437 |
} |
1 | 438 |
|
439 |
//-------------------verify-------------------------- |
|
440 |
||
441 |
void LIR_Op1::verify() const { |
|
442 |
switch(code()) { |
|
443 |
case lir_move: |
|
444 |
assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); |
|
445 |
break; |
|
446 |
case lir_null_check: |
|
447 |
assert(in_opr()->is_register(), "must be"); |
|
448 |
break; |
|
449 |
case lir_return: |
|
450 |
assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); |
|
451 |
break; |
|
452 |
} |
|
453 |
} |
|
454 |
||
455 |
void LIR_OpRTCall::verify() const { |
|
456 |
assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); |
|
457 |
} |
|
458 |
||
459 |
//-------------------visits-------------------------- |
|
460 |
||
461 |
// complete rework of LIR instruction visitor. |
|
462 |
// The virtual calls for each instruction type is replaced by a big |
|
463 |
// switch that adds the operands for each instruction |
|
464 |
||
465 |
void LIR_OpVisitState::visit(LIR_Op* op) { |
|
466 |
// copy information from the LIR_Op |
|
467 |
reset(); |
|
468 |
set_op(op); |
|
469 |
||
470 |
switch (op->code()) { |
|
471 |
||
472 |
// LIR_Op0 |
|
473 |
case lir_word_align: // result and info always invalid |
|
474 |
case lir_backwardbranch_target: // result and info always invalid |
|
475 |
case lir_build_frame: // result and info always invalid |
|
476 |
case lir_fpop_raw: // result and info always invalid |
|
477 |
case lir_24bit_FPU: // result and info always invalid |
|
478 |
case lir_reset_FPU: // result and info always invalid |
|
479 |
case lir_breakpoint: // result and info always invalid |
|
480 |
case lir_membar: // result and info always invalid |
|
481 |
case lir_membar_acquire: // result and info always invalid |
|
482 |
case lir_membar_release: // result and info always invalid |
|
11886
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
483 |
case lir_membar_loadload: // result and info always invalid |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
484 |
case lir_membar_storestore: // result and info always invalid |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
485 |
case lir_membar_loadstore: // result and info always invalid |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
486 |
case lir_membar_storeload: // result and info always invalid |
1 | 487 |
{ |
488 |
assert(op->as_Op0() != NULL, "must be"); |
|
489 |
assert(op->_info == NULL, "info not used by this instruction"); |
|
490 |
assert(op->_result->is_illegal(), "not used"); |
|
491 |
break; |
|
492 |
} |
|
493 |
||
494 |
case lir_nop: // may have info, result always invalid |
|
495 |
case lir_std_entry: // may have result, info always invalid |
|
496 |
case lir_osr_entry: // may have result, info always invalid |
|
497 |
case lir_get_thread: // may have result, info always invalid |
|
498 |
{ |
|
499 |
assert(op->as_Op0() != NULL, "must be"); |
|
500 |
if (op->_info != NULL) do_info(op->_info); |
|
501 |
if (op->_result->is_valid()) do_output(op->_result); |
|
502 |
break; |
|
503 |
} |
|
504 |
||
505 |
||
506 |
// LIR_OpLabel |
|
507 |
case lir_label: // result and info always invalid |
|
508 |
{ |
|
509 |
assert(op->as_OpLabel() != NULL, "must be"); |
|
510 |
assert(op->_info == NULL, "info not used by this instruction"); |
|
511 |
assert(op->_result->is_illegal(), "not used"); |
|
512 |
break; |
|
513 |
} |
|
514 |
||
515 |
||
516 |
// LIR_Op1 |
|
517 |
case lir_fxch: // input always valid, result and info always invalid |
|
518 |
case lir_fld: // input always valid, result and info always invalid |
|
519 |
case lir_ffree: // input always valid, result and info always invalid |
|
520 |
case lir_push: // input always valid, result and info always invalid |
|
521 |
case lir_pop: // input always valid, result and info always invalid |
|
522 |
case lir_return: // input always valid, result and info always invalid |
|
523 |
case lir_leal: // input and result always valid, info always invalid |
|
524 |
case lir_neg: // input and result always valid, info always invalid |
|
525 |
case lir_monaddr: // input and result always valid, info always invalid |
|
526 |
case lir_null_check: // input and info always valid, result always invalid |
|
527 |
case lir_move: // input and result always valid, may have info |
|
6453 | 528 |
case lir_pack64: // input and result always valid |
529 |
case lir_unpack64: // input and result always valid |
|
1 | 530 |
case lir_prefetchr: // input always valid, result and info always invalid |
531 |
case lir_prefetchw: // input always valid, result and info always invalid |
|
532 |
{ |
|
533 |
assert(op->as_Op1() != NULL, "must be"); |
|
534 |
LIR_Op1* op1 = (LIR_Op1*)op; |
|
535 |
||
536 |
if (op1->_info) do_info(op1->_info); |
|
537 |
if (op1->_opr->is_valid()) do_input(op1->_opr); |
|
538 |
if (op1->_result->is_valid()) do_output(op1->_result); |
|
539 |
||
540 |
break; |
|
541 |
} |
|
542 |
||
543 |
case lir_safepoint: |
|
544 |
{ |
|
545 |
assert(op->as_Op1() != NULL, "must be"); |
|
546 |
LIR_Op1* op1 = (LIR_Op1*)op; |
|
547 |
||
548 |
assert(op1->_info != NULL, ""); do_info(op1->_info); |
|
549 |
if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register |
|
550 |
assert(op1->_result->is_illegal(), "safepoint does not produce value"); |
|
551 |
||
552 |
break; |
|
553 |
} |
|
554 |
||
555 |
// LIR_OpConvert; |
|
556 |
case lir_convert: // input and result always valid, info always invalid |
|
557 |
{ |
|
558 |
assert(op->as_OpConvert() != NULL, "must be"); |
|
559 |
LIR_OpConvert* opConvert = (LIR_OpConvert*)op; |
|
560 |
||
561 |
assert(opConvert->_info == NULL, "must be"); |
|
562 |
if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); |
|
563 |
if (opConvert->_result->is_valid()) do_output(opConvert->_result); |
|
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
564 |
#ifdef PPC |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
565 |
if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
566 |
if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
567 |
#endif |
1 | 568 |
do_stub(opConvert->_stub); |
569 |
||
570 |
break; |
|
571 |
} |
|
572 |
||
573 |
// LIR_OpBranch; |
|
574 |
case lir_branch: // may have info, input and result register always invalid |
|
575 |
case lir_cond_float_branch: // may have info, input and result register always invalid |
|
576 |
{ |
|
577 |
assert(op->as_OpBranch() != NULL, "must be"); |
|
578 |
LIR_OpBranch* opBranch = (LIR_OpBranch*)op; |
|
579 |
||
580 |
if (opBranch->_info != NULL) do_info(opBranch->_info); |
|
581 |
assert(opBranch->_result->is_illegal(), "not used"); |
|
582 |
if (opBranch->_stub != NULL) opBranch->stub()->visit(this); |
|
583 |
||
584 |
break; |
|
585 |
} |
|
586 |
||
587 |
||
588 |
// LIR_OpAllocObj |
|
589 |
case lir_alloc_object: |
|
590 |
{ |
|
591 |
assert(op->as_OpAllocObj() != NULL, "must be"); |
|
592 |
LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; |
|
593 |
||
594 |
if (opAllocObj->_info) do_info(opAllocObj->_info); |
|
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
595 |
if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
596 |
do_temp(opAllocObj->_opr); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
597 |
} |
1 | 598 |
if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
599 |
if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); |
|
600 |
if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); |
|
601 |
if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); |
|
602 |
if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); |
|
603 |
do_stub(opAllocObj->_stub); |
|
604 |
break; |
|
605 |
} |
|
606 |
||
607 |
||
608 |
// LIR_OpRoundFP; |
|
609 |
case lir_roundfp: { |
|
610 |
assert(op->as_OpRoundFP() != NULL, "must be"); |
|
611 |
LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; |
|
612 |
||
613 |
assert(op->_info == NULL, "info not used by this instruction"); |
|
614 |
assert(opRoundFP->_tmp->is_illegal(), "not used"); |
|
615 |
do_input(opRoundFP->_opr); |
|
616 |
do_output(opRoundFP->_result); |
|
617 |
||
618 |
break; |
|
619 |
} |
|
620 |
||
621 |
||
622 |
// LIR_Op2 |
|
623 |
case lir_cmp: |
|
624 |
case lir_cmp_l2i: |
|
625 |
case lir_ucmp_fd2i: |
|
626 |
case lir_cmp_fd2i: |
|
627 |
case lir_add: |
|
628 |
case lir_sub: |
|
629 |
case lir_mul: |
|
630 |
case lir_div: |
|
631 |
case lir_rem: |
|
632 |
case lir_sqrt: |
|
633 |
case lir_abs: |
|
634 |
case lir_logic_and: |
|
635 |
case lir_logic_or: |
|
636 |
case lir_logic_xor: |
|
637 |
case lir_shl: |
|
638 |
case lir_shr: |
|
639 |
case lir_ushr: |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
640 |
case lir_xadd: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
641 |
case lir_xchg: |
16611 | 642 |
case lir_assert: |
1 | 643 |
{ |
644 |
assert(op->as_Op2() != NULL, "must be"); |
|
645 |
LIR_Op2* op2 = (LIR_Op2*)op; |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
646 |
assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
647 |
op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
1 | 648 |
|
649 |
if (op2->_info) do_info(op2->_info); |
|
650 |
if (op2->_opr1->is_valid()) do_input(op2->_opr1); |
|
651 |
if (op2->_opr2->is_valid()) do_input(op2->_opr2); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
652 |
if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
1 | 653 |
if (op2->_result->is_valid()) do_output(op2->_result); |
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
654 |
if (op->code() == lir_xchg || op->code() == lir_xadd) { |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
655 |
// on ARM and PPC, return value is loaded first so could |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
656 |
// destroy inputs. On other platforms that implement those |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
657 |
// (x86, sparc), the extra constrainsts are harmless. |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
658 |
if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
659 |
if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
660 |
} |
1 | 661 |
|
662 |
break; |
|
663 |
} |
|
664 |
||
665 |
// special handling for cmove: right input operand must not be equal |
|
666 |
// to the result operand, otherwise the backend fails |
|
667 |
case lir_cmove: |
|
668 |
{ |
|
669 |
assert(op->as_Op2() != NULL, "must be"); |
|
670 |
LIR_Op2* op2 = (LIR_Op2*)op; |
|
671 |
||
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
672 |
assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
673 |
op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
1 | 674 |
assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); |
675 |
||
676 |
do_input(op2->_opr1); |
|
677 |
do_input(op2->_opr2); |
|
678 |
do_temp(op2->_opr2); |
|
679 |
do_output(op2->_result); |
|
680 |
||
681 |
break; |
|
682 |
} |
|
683 |
||
684 |
// vspecial handling for strict operations: register input operands |
|
685 |
// as temp to guarantee that they do not overlap with other |
|
686 |
// registers |
|
687 |
case lir_mul_strictfp: |
|
688 |
case lir_div_strictfp: |
|
689 |
{ |
|
690 |
assert(op->as_Op2() != NULL, "must be"); |
|
691 |
LIR_Op2* op2 = (LIR_Op2*)op; |
|
692 |
||
693 |
assert(op2->_info == NULL, "not used"); |
|
694 |
assert(op2->_opr1->is_valid(), "used"); |
|
695 |
assert(op2->_opr2->is_valid(), "used"); |
|
696 |
assert(op2->_result->is_valid(), "used"); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
697 |
assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
698 |
op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
1 | 699 |
|
700 |
do_input(op2->_opr1); do_temp(op2->_opr1); |
|
701 |
do_input(op2->_opr2); do_temp(op2->_opr2); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
702 |
if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
1 | 703 |
do_output(op2->_result); |
704 |
||
705 |
break; |
|
706 |
} |
|
707 |
||
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
708 |
case lir_throw: { |
1 | 709 |
assert(op->as_Op2() != NULL, "must be"); |
710 |
LIR_Op2* op2 = (LIR_Op2*)op; |
|
711 |
||
712 |
if (op2->_info) do_info(op2->_info); |
|
713 |
if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
|
714 |
if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter |
|
715 |
assert(op2->_result->is_illegal(), "no result"); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
716 |
assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
717 |
op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
1 | 718 |
|
719 |
break; |
|
720 |
} |
|
721 |
||
5334
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
722 |
case lir_unwind: { |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
723 |
assert(op->as_Op1() != NULL, "must be"); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
724 |
LIR_Op1* op1 = (LIR_Op1*)op; |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
725 |
|
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
726 |
assert(op1->_info == NULL, "no info"); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
727 |
assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
728 |
assert(op1->_result->is_illegal(), "no result"); |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
729 |
|
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
730 |
break; |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
731 |
} |
b2d040a8d375
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
5052
diff
changeset
|
732 |
|
1 | 733 |
|
734 |
case lir_tan: |
|
735 |
case lir_sin: |
|
3800
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
736 |
case lir_cos: |
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
737 |
case lir_log: |
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
738 |
case lir_log10: |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
739 |
case lir_exp: { |
1 | 740 |
assert(op->as_Op2() != NULL, "must be"); |
741 |
LIR_Op2* op2 = (LIR_Op2*)op; |
|
742 |
||
3800
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
743 |
// On x86 tan/sin/cos need two temporary fpu stack slots and |
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
744 |
// log/log10 need one so handle opr2 and tmp as temp inputs. |
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
745 |
// Register input operand as temp to guarantee that it doesn't |
3195b4844b5a
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
1066
diff
changeset
|
746 |
// overlap with the input. |
1 | 747 |
assert(op2->_info == NULL, "not used"); |
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
748 |
assert(op2->_tmp5->is_illegal(), "not used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
749 |
assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
750 |
assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
751 |
assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); |
1 | 752 |
assert(op2->_opr1->is_valid(), "used"); |
753 |
do_input(op2->_opr1); do_temp(op2->_opr1); |
|
754 |
||
755 |
if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
756 |
if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
757 |
if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
758 |
if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
759 |
if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); |
1 | 760 |
if (op2->_result->is_valid()) do_output(op2->_result); |
761 |
||
762 |
break; |
|
763 |
} |
|
764 |
||
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
765 |
case lir_pow: { |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
766 |
assert(op->as_Op2() != NULL, "must be"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
767 |
LIR_Op2* op2 = (LIR_Op2*)op; |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
768 |
|
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
769 |
// On x86 pow needs two temporary fpu stack slots: tmp1 and |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
770 |
// tmp2. Register input operands as temps to guarantee that it |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
771 |
// doesn't overlap with the temporary slots. |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
772 |
assert(op2->_info == NULL, "not used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
773 |
assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
774 |
assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
775 |
&& op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
776 |
assert(op2->_result->is_valid(), "used"); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
777 |
|
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
778 |
do_input(op2->_opr1); do_temp(op2->_opr1); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
779 |
do_input(op2->_opr2); do_temp(op2->_opr2); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
780 |
do_temp(op2->_tmp1); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
781 |
do_temp(op2->_tmp2); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
782 |
do_temp(op2->_tmp3); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
783 |
do_temp(op2->_tmp4); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
784 |
do_temp(op2->_tmp5); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
785 |
do_output(op2->_result); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
786 |
|
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
787 |
break; |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
788 |
} |
1 | 789 |
|
790 |
// LIR_Op3 |
|
791 |
case lir_idiv: |
|
792 |
case lir_irem: { |
|
793 |
assert(op->as_Op3() != NULL, "must be"); |
|
794 |
LIR_Op3* op3= (LIR_Op3*)op; |
|
795 |
||
796 |
if (op3->_info) do_info(op3->_info); |
|
797 |
if (op3->_opr1->is_valid()) do_input(op3->_opr1); |
|
798 |
||
799 |
// second operand is input and temp, so ensure that second operand |
|
800 |
// and third operand get not the same register |
|
801 |
if (op3->_opr2->is_valid()) do_input(op3->_opr2); |
|
802 |
if (op3->_opr2->is_valid()) do_temp(op3->_opr2); |
|
803 |
if (op3->_opr3->is_valid()) do_temp(op3->_opr3); |
|
804 |
||
805 |
if (op3->_result->is_valid()) do_output(op3->_result); |
|
806 |
||
807 |
break; |
|
808 |
} |
|
809 |
||
810 |
||
811 |
// LIR_OpJavaCall |
|
812 |
case lir_static_call: |
|
813 |
case lir_optvirtual_call: |
|
814 |
case lir_icvirtual_call: |
|
5046 | 815 |
case lir_virtual_call: |
816 |
case lir_dynamic_call: { |
|
817 |
LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); |
|
818 |
assert(opJavaCall != NULL, "must be"); |
|
1 | 819 |
|
820 |
if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); |
|
821 |
||
822 |
// only visit register parameters |
|
823 |
int n = opJavaCall->_arguments->length(); |
|
15760
cbb77ea2a3a3
8005722: Assert in c1_LIR.hpp incorrect wrt to number of register operands
bpittore
parents:
15228
diff
changeset
|
824 |
for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { |
1 | 825 |
if (!opJavaCall->_arguments->at(i)->is_pointer()) { |
826 |
do_input(*opJavaCall->_arguments->adr_at(i)); |
|
827 |
} |
|
828 |
} |
|
829 |
||
830 |
if (opJavaCall->_info) do_info(opJavaCall->_info); |
|
5687 | 831 |
if (opJavaCall->is_method_handle_invoke()) { |
832 |
opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); |
|
833 |
do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); |
|
834 |
} |
|
1 | 835 |
do_call(); |
836 |
if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); |
|
837 |
||
838 |
break; |
|
839 |
} |
|
840 |
||
841 |
||
842 |
// LIR_OpRTCall |
|
843 |
case lir_rtcall: { |
|
844 |
assert(op->as_OpRTCall() != NULL, "must be"); |
|
845 |
LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; |
|
846 |
||
847 |
// only visit register parameters |
|
848 |
int n = opRTCall->_arguments->length(); |
|
849 |
for (int i = 0; i < n; i++) { |
|
850 |
if (!opRTCall->_arguments->at(i)->is_pointer()) { |
|
851 |
do_input(*opRTCall->_arguments->adr_at(i)); |
|
852 |
} |
|
853 |
} |
|
854 |
if (opRTCall->_info) do_info(opRTCall->_info); |
|
855 |
if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); |
|
856 |
do_call(); |
|
857 |
if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); |
|
858 |
||
859 |
break; |
|
860 |
} |
|
861 |
||
862 |
||
863 |
// LIR_OpArrayCopy |
|
864 |
case lir_arraycopy: { |
|
865 |
assert(op->as_OpArrayCopy() != NULL, "must be"); |
|
866 |
LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; |
|
867 |
||
868 |
assert(opArrayCopy->_result->is_illegal(), "unused"); |
|
869 |
assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); |
|
870 |
assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); |
|
871 |
assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); |
|
872 |
assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); |
|
873 |
assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); |
|
874 |
assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); |
|
875 |
if (opArrayCopy->_info) do_info(opArrayCopy->_info); |
|
876 |
||
877 |
// the implementation of arraycopy always has a call into the runtime |
|
878 |
do_call(); |
|
879 |
||
880 |
break; |
|
881 |
} |
|
882 |
||
883 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
884 |
// LIR_OpUpdateCRC32 |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
885 |
case lir_updatecrc32: { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
886 |
assert(op->as_OpUpdateCRC32() != NULL, "must be"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
887 |
LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
888 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
889 |
assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
890 |
assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
891 |
assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
892 |
assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
893 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
894 |
break; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
895 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
896 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
897 |
|
1 | 898 |
// LIR_OpLock |
899 |
case lir_lock: |
|
900 |
case lir_unlock: { |
|
901 |
assert(op->as_OpLock() != NULL, "must be"); |
|
902 |
LIR_OpLock* opLock = (LIR_OpLock*)op; |
|
903 |
||
904 |
if (opLock->_info) do_info(opLock->_info); |
|
905 |
||
906 |
// TODO: check if these operands really have to be temp |
|
907 |
// (or if input is sufficient). This may have influence on the oop map! |
|
908 |
assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); |
|
909 |
assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); |
|
910 |
assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); |
|
911 |
||
912 |
if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); |
|
913 |
assert(opLock->_result->is_illegal(), "unused"); |
|
914 |
||
915 |
do_stub(opLock->_stub); |
|
916 |
||
917 |
break; |
|
918 |
} |
|
919 |
||
920 |
||
921 |
// LIR_OpDelay |
|
922 |
case lir_delay_slot: { |
|
923 |
assert(op->as_OpDelay() != NULL, "must be"); |
|
924 |
LIR_OpDelay* opDelay = (LIR_OpDelay*)op; |
|
925 |
||
926 |
visit(opDelay->delay_op()); |
|
927 |
break; |
|
928 |
} |
|
929 |
||
930 |
// LIR_OpTypeCheck |
|
931 |
case lir_instanceof: |
|
932 |
case lir_checkcast: |
|
933 |
case lir_store_check: { |
|
934 |
assert(op->as_OpTypeCheck() != NULL, "must be"); |
|
935 |
LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; |
|
936 |
||
937 |
if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); |
|
938 |
if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); |
|
939 |
if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); |
|
11433
2a2e375199de
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
10562
diff
changeset
|
940 |
if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { |
2a2e375199de
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
10562
diff
changeset
|
941 |
do_temp(opTypeCheck->_object); |
2a2e375199de
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
10562
diff
changeset
|
942 |
} |
1 | 943 |
if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); |
944 |
if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); |
|
945 |
if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); |
|
946 |
if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); |
|
947 |
if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); |
|
948 |
do_stub(opTypeCheck->_stub); |
|
949 |
break; |
|
950 |
} |
|
951 |
||
952 |
// LIR_OpCompareAndSwap |
|
953 |
case lir_cas_long: |
|
954 |
case lir_cas_obj: |
|
955 |
case lir_cas_int: { |
|
956 |
assert(op->as_OpCompareAndSwap() != NULL, "must be"); |
|
957 |
LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; |
|
958 |
||
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
959 |
assert(opCompareAndSwap->_addr->is_valid(), "used"); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
960 |
assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
961 |
assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
1 | 962 |
if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
963 |
do_input(opCompareAndSwap->_addr); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
964 |
do_temp(opCompareAndSwap->_addr); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
965 |
do_input(opCompareAndSwap->_cmp_value); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
966 |
do_temp(opCompareAndSwap->_cmp_value); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
967 |
do_input(opCompareAndSwap->_new_value); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
968 |
do_temp(opCompareAndSwap->_new_value); |
1 | 969 |
if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
970 |
if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); |
|
971 |
if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); |
|
972 |
||
973 |
break; |
|
974 |
} |
|
975 |
||
976 |
||
977 |
// LIR_OpAllocArray; |
|
978 |
case lir_alloc_array: { |
|
979 |
assert(op->as_OpAllocArray() != NULL, "must be"); |
|
980 |
LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; |
|
981 |
||
982 |
if (opAllocArray->_info) do_info(opAllocArray->_info); |
|
983 |
if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); |
|
984 |
if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); |
|
985 |
if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); |
|
986 |
if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); |
|
987 |
if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); |
|
988 |
if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); |
|
989 |
if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); |
|
990 |
do_stub(opAllocArray->_stub); |
|
991 |
break; |
|
992 |
} |
|
993 |
||
994 |
// LIR_OpProfileCall: |
|
995 |
case lir_profile_call: { |
|
996 |
assert(op->as_OpProfileCall() != NULL, "must be"); |
|
997 |
LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; |
|
998 |
||
999 |
if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); |
|
1000 |
assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); |
|
1001 |
assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); |
|
1002 |
break; |
|
1003 |
} |
|
20702
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1004 |
|
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1005 |
// LIR_OpProfileType: |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1006 |
case lir_profile_type: { |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1007 |
assert(op->as_OpProfileType() != NULL, "must be"); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1008 |
LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1009 |
|
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1010 |
do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1011 |
do_input(opProfileType->_obj); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1012 |
do_temp(opProfileType->_tmp); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1013 |
break; |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1014 |
} |
1 | 1015 |
default: |
1016 |
ShouldNotReachHere(); |
|
1017 |
} |
|
1018 |
} |
|
1019 |
||
1020 |
||
1021 |
void LIR_OpVisitState::do_stub(CodeStub* stub) { |
|
1022 |
if (stub != NULL) { |
|
1023 |
stub->visit(this); |
|
1024 |
} |
|
1025 |
} |
|
1026 |
||
1027 |
XHandlers* LIR_OpVisitState::all_xhandler() { |
|
1028 |
XHandlers* result = NULL; |
|
1029 |
||
1030 |
int i; |
|
1031 |
for (i = 0; i < info_count(); i++) { |
|
1032 |
if (info_at(i)->exception_handlers() != NULL) { |
|
1033 |
result = info_at(i)->exception_handlers(); |
|
1034 |
break; |
|
1035 |
} |
|
1036 |
} |
|
1037 |
||
1038 |
#ifdef ASSERT |
|
1039 |
for (i = 0; i < info_count(); i++) { |
|
1040 |
assert(info_at(i)->exception_handlers() == NULL || |
|
1041 |
info_at(i)->exception_handlers() == result, |
|
1042 |
"only one xhandler list allowed per LIR-operation"); |
|
1043 |
} |
|
1044 |
#endif |
|
1045 |
||
1046 |
if (result != NULL) { |
|
1047 |
return result; |
|
1048 |
} else { |
|
1049 |
return new XHandlers(); |
|
1050 |
} |
|
1051 |
||
1052 |
return result; |
|
1053 |
} |
|
1054 |
||
1055 |
||
1056 |
#ifdef ASSERT |
|
1057 |
bool LIR_OpVisitState::no_operands(LIR_Op* op) { |
|
1058 |
visit(op); |
|
1059 |
||
1060 |
return opr_count(inputMode) == 0 && |
|
1061 |
opr_count(outputMode) == 0 && |
|
1062 |
opr_count(tempMode) == 0 && |
|
1063 |
info_count() == 0 && |
|
1064 |
!has_call() && |
|
1065 |
!has_slow_case(); |
|
1066 |
} |
|
1067 |
#endif |
|
1068 |
||
1069 |
//--------------------------------------------------- |
|
1070 |
||
1071 |
||
1072 |
void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { |
|
1073 |
masm->emit_call(this); |
|
1074 |
} |
|
1075 |
||
1076 |
void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { |
|
1077 |
masm->emit_rtcall(this); |
|
1078 |
} |
|
1079 |
||
1080 |
void LIR_OpLabel::emit_code(LIR_Assembler* masm) { |
|
1081 |
masm->emit_opLabel(this); |
|
1082 |
} |
|
1083 |
||
1084 |
void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { |
|
1085 |
masm->emit_arraycopy(this); |
|
24669 | 1086 |
masm->append_code_stub(stub()); |
1 | 1087 |
} |
1088 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1089 |
void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1090 |
masm->emit_updatecrc32(this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1091 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1092 |
|
1 | 1093 |
void LIR_Op0::emit_code(LIR_Assembler* masm) { |
1094 |
masm->emit_op0(this); |
|
1095 |
} |
|
1096 |
||
1097 |
void LIR_Op1::emit_code(LIR_Assembler* masm) { |
|
1098 |
masm->emit_op1(this); |
|
1099 |
} |
|
1100 |
||
1101 |
void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { |
|
1102 |
masm->emit_alloc_obj(this); |
|
24669 | 1103 |
masm->append_code_stub(stub()); |
1 | 1104 |
} |
1105 |
||
1106 |
void LIR_OpBranch::emit_code(LIR_Assembler* masm) { |
|
1107 |
masm->emit_opBranch(this); |
|
1108 |
if (stub()) { |
|
24669 | 1109 |
masm->append_code_stub(stub()); |
1 | 1110 |
} |
1111 |
} |
|
1112 |
||
1113 |
void LIR_OpConvert::emit_code(LIR_Assembler* masm) { |
|
1114 |
masm->emit_opConvert(this); |
|
1115 |
if (stub() != NULL) { |
|
24669 | 1116 |
masm->append_code_stub(stub()); |
1 | 1117 |
} |
1118 |
} |
|
1119 |
||
1120 |
void LIR_Op2::emit_code(LIR_Assembler* masm) { |
|
1121 |
masm->emit_op2(this); |
|
1122 |
} |
|
1123 |
||
1124 |
void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { |
|
1125 |
masm->emit_alloc_array(this); |
|
24669 | 1126 |
masm->append_code_stub(stub()); |
1 | 1127 |
} |
1128 |
||
1129 |
void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { |
|
6461
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1130 |
masm->emit_opTypeCheck(this); |
1 | 1131 |
if (stub()) { |
24669 | 1132 |
masm->append_code_stub(stub()); |
1 | 1133 |
} |
1134 |
} |
|
1135 |
||
1136 |
void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { |
|
1137 |
masm->emit_compare_and_swap(this); |
|
1138 |
} |
|
1139 |
||
1140 |
void LIR_Op3::emit_code(LIR_Assembler* masm) { |
|
1141 |
masm->emit_op3(this); |
|
1142 |
} |
|
1143 |
||
1144 |
void LIR_OpLock::emit_code(LIR_Assembler* masm) { |
|
1145 |
masm->emit_lock(this); |
|
1146 |
if (stub()) { |
|
24669 | 1147 |
masm->append_code_stub(stub()); |
1 | 1148 |
} |
1149 |
} |
|
1150 |
||
16611 | 1151 |
#ifdef ASSERT |
1152 |
void LIR_OpAssert::emit_code(LIR_Assembler* masm) { |
|
1153 |
masm->emit_assert(this); |
|
1154 |
} |
|
1155 |
#endif |
|
1 | 1156 |
|
1157 |
void LIR_OpDelay::emit_code(LIR_Assembler* masm) { |
|
1158 |
masm->emit_delay(this); |
|
1159 |
} |
|
1160 |
||
1161 |
void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { |
|
1162 |
masm->emit_profile_call(this); |
|
1163 |
} |
|
1164 |
||
20702
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1165 |
void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1166 |
masm->emit_profile_type(this); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1167 |
} |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1168 |
|
1 | 1169 |
// LIR_List |
1170 |
LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) |
|
1171 |
: _operations(8) |
|
1172 |
, _compilation(compilation) |
|
1173 |
#ifndef PRODUCT |
|
1174 |
, _block(block) |
|
1175 |
#endif |
|
1176 |
#ifdef ASSERT |
|
1177 |
, _file(NULL) |
|
1178 |
, _line(0) |
|
1179 |
#endif |
|
1180 |
{ } |
|
1181 |
||
1182 |
||
1183 |
#ifdef ASSERT |
|
1184 |
void LIR_List::set_file_and_line(const char * file, int line) { |
|
1185 |
const char * f = strrchr(file, '/'); |
|
1186 |
if (f == NULL) f = strrchr(file, '\\'); |
|
1187 |
if (f == NULL) { |
|
1188 |
f = file; |
|
1189 |
} else { |
|
1190 |
f++; |
|
1191 |
} |
|
1192 |
_file = f; |
|
1193 |
_line = line; |
|
1194 |
} |
|
1195 |
#endif |
|
1196 |
||
1197 |
||
1198 |
void LIR_List::append(LIR_InsertionBuffer* buffer) { |
|
1199 |
assert(this == buffer->lir_list(), "wrong lir list"); |
|
1200 |
const int n = _operations.length(); |
|
1201 |
||
1202 |
if (buffer->number_of_ops() > 0) { |
|
1203 |
// increase size of instructions list |
|
1204 |
_operations.at_grow(n + buffer->number_of_ops() - 1, NULL); |
|
1205 |
// insert ops from buffer into instructions list |
|
1206 |
int op_index = buffer->number_of_ops() - 1; |
|
1207 |
int ip_index = buffer->number_of_insertion_points() - 1; |
|
1208 |
int from_index = n - 1; |
|
1209 |
int to_index = _operations.length() - 1; |
|
1210 |
for (; ip_index >= 0; ip_index --) { |
|
1211 |
int index = buffer->index_at(ip_index); |
|
1212 |
// make room after insertion point |
|
1213 |
while (index < from_index) { |
|
1214 |
_operations.at_put(to_index --, _operations.at(from_index --)); |
|
1215 |
} |
|
1216 |
// insert ops from buffer |
|
1217 |
for (int i = buffer->count_at(ip_index); i > 0; i --) { |
|
1218 |
_operations.at_put(to_index --, buffer->op_at(op_index --)); |
|
1219 |
} |
|
1220 |
} |
|
1221 |
} |
|
1222 |
||
1223 |
buffer->finish(); |
|
1224 |
} |
|
1225 |
||
1226 |
||
1227 |
void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1228 |
assert(reg->type() == T_OBJECT, "bad reg"); |
1 | 1229 |
append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); |
1230 |
} |
|
1231 |
||
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
12739
diff
changeset
|
1232 |
void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { |
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1233 |
assert(reg->type() == T_METADATA, "bad reg"); |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
12739
diff
changeset
|
1234 |
append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
12739
diff
changeset
|
1235 |
} |
1 | 1236 |
|
1237 |
void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1238 |
append(new LIR_Op1( |
|
1239 |
lir_move, |
|
1240 |
LIR_OprFact::address(addr), |
|
1241 |
src, |
|
1242 |
addr->type(), |
|
1243 |
patch_code, |
|
1244 |
info)); |
|
1245 |
} |
|
1246 |
||
1247 |
||
1248 |
void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1249 |
append(new LIR_Op1( |
|
1250 |
lir_move, |
|
1251 |
LIR_OprFact::address(address), |
|
1252 |
dst, |
|
1253 |
address->type(), |
|
1254 |
patch_code, |
|
1255 |
info, lir_move_volatile)); |
|
1256 |
} |
|
1257 |
||
1258 |
void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1259 |
append(new LIR_Op1( |
|
1260 |
lir_move, |
|
1261 |
LIR_OprFact::address(new LIR_Address(base, offset, type)), |
|
1262 |
dst, |
|
1263 |
type, |
|
1264 |
patch_code, |
|
1265 |
info, lir_move_volatile)); |
|
1266 |
} |
|
1267 |
||
1268 |
||
1269 |
void LIR_List::prefetch(LIR_Address* addr, bool is_store) { |
|
1270 |
append(new LIR_Op1( |
|
1271 |
is_store ? lir_prefetchw : lir_prefetchr, |
|
1272 |
LIR_OprFact::address(addr))); |
|
1273 |
} |
|
1274 |
||
1275 |
||
1276 |
void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1277 |
append(new LIR_Op1( |
|
1278 |
lir_move, |
|
1279 |
LIR_OprFact::intConst(v), |
|
1280 |
LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), |
|
1281 |
type, |
|
1282 |
patch_code, |
|
1283 |
info)); |
|
1284 |
} |
|
1285 |
||
1286 |
||
1287 |
void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1288 |
append(new LIR_Op1( |
|
1289 |
lir_move, |
|
1290 |
LIR_OprFact::oopConst(o), |
|
1291 |
LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), |
|
1292 |
type, |
|
1293 |
patch_code, |
|
1294 |
info)); |
|
1295 |
} |
|
1296 |
||
1297 |
||
1298 |
void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1299 |
append(new LIR_Op1( |
|
1300 |
lir_move, |
|
1301 |
src, |
|
1302 |
LIR_OprFact::address(addr), |
|
1303 |
addr->type(), |
|
1304 |
patch_code, |
|
1305 |
info)); |
|
1306 |
} |
|
1307 |
||
1308 |
||
1309 |
void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1310 |
append(new LIR_Op1( |
|
1311 |
lir_move, |
|
1312 |
src, |
|
1313 |
LIR_OprFact::address(addr), |
|
1314 |
addr->type(), |
|
1315 |
patch_code, |
|
1316 |
info, |
|
1317 |
lir_move_volatile)); |
|
1318 |
} |
|
1319 |
||
1320 |
void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { |
|
1321 |
append(new LIR_Op1( |
|
1322 |
lir_move, |
|
1323 |
src, |
|
1324 |
LIR_OprFact::address(new LIR_Address(base, offset, type)), |
|
1325 |
type, |
|
1326 |
patch_code, |
|
1327 |
info, lir_move_volatile)); |
|
1328 |
} |
|
1329 |
||
1330 |
||
1331 |
void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
|
1332 |
append(new LIR_Op3( |
|
1333 |
lir_idiv, |
|
1334 |
left, |
|
1335 |
right, |
|
1336 |
tmp, |
|
1337 |
res, |
|
1338 |
info)); |
|
1339 |
} |
|
1340 |
||
1341 |
||
1342 |
void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
|
1343 |
append(new LIR_Op3( |
|
1344 |
lir_idiv, |
|
1345 |
left, |
|
1346 |
LIR_OprFact::intConst(right), |
|
1347 |
tmp, |
|
1348 |
res, |
|
1349 |
info)); |
|
1350 |
} |
|
1351 |
||
1352 |
||
1353 |
void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
|
1354 |
append(new LIR_Op3( |
|
1355 |
lir_irem, |
|
1356 |
left, |
|
1357 |
right, |
|
1358 |
tmp, |
|
1359 |
res, |
|
1360 |
info)); |
|
1361 |
} |
|
1362 |
||
1363 |
||
1364 |
void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { |
|
1365 |
append(new LIR_Op3( |
|
1366 |
lir_irem, |
|
1367 |
left, |
|
1368 |
LIR_OprFact::intConst(right), |
|
1369 |
tmp, |
|
1370 |
res, |
|
1371 |
info)); |
|
1372 |
} |
|
1373 |
||
1374 |
||
1375 |
void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { |
|
1376 |
append(new LIR_Op2( |
|
1377 |
lir_cmp, |
|
1378 |
condition, |
|
1379 |
LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), |
|
1380 |
LIR_OprFact::intConst(c), |
|
1381 |
info)); |
|
1382 |
} |
|
1383 |
||
1384 |
||
1385 |
void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { |
|
1386 |
append(new LIR_Op2( |
|
1387 |
lir_cmp, |
|
1388 |
condition, |
|
1389 |
reg, |
|
1390 |
LIR_OprFact::address(addr), |
|
1391 |
info)); |
|
1392 |
} |
|
1393 |
||
1394 |
void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, |
|
1395 |
int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { |
|
1396 |
append(new LIR_OpAllocObj( |
|
1397 |
klass, |
|
1398 |
dst, |
|
1399 |
t1, |
|
1400 |
t2, |
|
1401 |
t3, |
|
1402 |
t4, |
|
1403 |
header_size, |
|
1404 |
object_size, |
|
1405 |
init_check, |
|
1406 |
stub)); |
|
1407 |
} |
|
1408 |
||
1409 |
void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { |
|
1410 |
append(new LIR_OpAllocArray( |
|
1411 |
klass, |
|
1412 |
len, |
|
1413 |
dst, |
|
1414 |
t1, |
|
1415 |
t2, |
|
1416 |
t3, |
|
1417 |
t4, |
|
1418 |
type, |
|
1419 |
stub)); |
|
1420 |
} |
|
1421 |
||
1422 |
void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
|
1423 |
append(new LIR_Op2( |
|
1424 |
lir_shl, |
|
1425 |
value, |
|
1426 |
count, |
|
1427 |
dst, |
|
1428 |
tmp)); |
|
1429 |
} |
|
1430 |
||
1431 |
void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
|
1432 |
append(new LIR_Op2( |
|
1433 |
lir_shr, |
|
1434 |
value, |
|
1435 |
count, |
|
1436 |
dst, |
|
1437 |
tmp)); |
|
1438 |
} |
|
1439 |
||
1440 |
||
1441 |
void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { |
|
1442 |
append(new LIR_Op2( |
|
1443 |
lir_ushr, |
|
1444 |
value, |
|
1445 |
count, |
|
1446 |
dst, |
|
1447 |
tmp)); |
|
1448 |
} |
|
1449 |
||
1450 |
void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { |
|
1451 |
append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, |
|
1452 |
left, |
|
1453 |
right, |
|
1454 |
dst)); |
|
1455 |
} |
|
1456 |
||
1457 |
void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { |
|
1458 |
append(new LIR_OpLock( |
|
1459 |
lir_lock, |
|
1460 |
hdr, |
|
1461 |
obj, |
|
1462 |
lock, |
|
1463 |
scratch, |
|
1464 |
stub, |
|
1465 |
info)); |
|
1466 |
} |
|
1467 |
||
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1468 |
void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
1 | 1469 |
append(new LIR_OpLock( |
1470 |
lir_unlock, |
|
1471 |
hdr, |
|
1472 |
obj, |
|
1473 |
lock, |
|
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1474 |
scratch, |
1 | 1475 |
stub, |
1476 |
NULL)); |
|
1477 |
} |
|
1478 |
||
1479 |
||
1480 |
void check_LIR() { |
|
1481 |
// cannot do the proper checking as PRODUCT and other modes return different results |
|
1482 |
// guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); |
|
1483 |
} |
|
1484 |
||
1485 |
||
1486 |
||
1487 |
void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, |
|
1488 |
LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, |
|
1489 |
CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, |
|
1490 |
ciMethod* profiled_method, int profiled_bci) { |
|
6453 | 1491 |
LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, |
1492 |
tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); |
|
1493 |
if (profiled_method != NULL) { |
|
1494 |
c->set_profiled_method(profiled_method); |
|
1495 |
c->set_profiled_bci(profiled_bci); |
|
1496 |
c->set_should_profile(true); |
|
1497 |
} |
|
1498 |
append(c); |
|
1 | 1499 |
} |
1500 |
||
6461
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1501 |
void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1502 |
LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1503 |
if (profiled_method != NULL) { |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1504 |
c->set_profiled_method(profiled_method); |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1505 |
c->set_profiled_bci(profiled_bci); |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1506 |
c->set_should_profile(true); |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1507 |
} |
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1508 |
append(c); |
1 | 1509 |
} |
1510 |
||
1511 |
||
10562 | 1512 |
void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
1513 |
CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { |
|
1514 |
LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); |
|
1515 |
if (profiled_method != NULL) { |
|
1516 |
c->set_profiled_method(profiled_method); |
|
1517 |
c->set_profiled_bci(profiled_bci); |
|
1518 |
c->set_should_profile(true); |
|
1519 |
} |
|
1520 |
append(c); |
|
1 | 1521 |
} |
1522 |
||
1523 |
||
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1524 |
void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1525 |
LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1526 |
append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
1 | 1527 |
} |
1528 |
||
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1529 |
void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1530 |
LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1531 |
append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
1 | 1532 |
} |
1533 |
||
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1534 |
void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1535 |
LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1536 |
append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
1 | 1537 |
} |
1538 |
||
1539 |
||
1540 |
#ifdef PRODUCT |
|
1541 |
||
1542 |
void print_LIR(BlockList* blocks) { |
|
1543 |
} |
|
1544 |
||
1545 |
#else |
|
1546 |
// LIR_OprDesc |
|
1547 |
void LIR_OprDesc::print() const { |
|
1548 |
print(tty); |
|
1549 |
} |
|
1550 |
||
1551 |
void LIR_OprDesc::print(outputStream* out) const { |
|
1552 |
if (is_illegal()) { |
|
1553 |
return; |
|
1554 |
} |
|
1555 |
||
1556 |
out->print("["); |
|
1557 |
if (is_pointer()) { |
|
1558 |
pointer()->print_value_on(out); |
|
1559 |
} else if (is_single_stack()) { |
|
1560 |
out->print("stack:%d", single_stack_ix()); |
|
1561 |
} else if (is_double_stack()) { |
|
1562 |
out->print("dbl_stack:%d",double_stack_ix()); |
|
1563 |
} else if (is_virtual()) { |
|
1564 |
out->print("R%d", vreg_number()); |
|
1565 |
} else if (is_single_cpu()) { |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1566 |
out->print("%s", as_register()->name()); |
1 | 1567 |
} else if (is_double_cpu()) { |
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1568 |
out->print("%s", as_register_hi()->name()); |
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1569 |
out->print("%s", as_register_lo()->name()); |
1066 | 1570 |
#if defined(X86) |
1 | 1571 |
} else if (is_single_xmm()) { |
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1572 |
out->print("%s", as_xmm_float_reg()->name()); |
1 | 1573 |
} else if (is_double_xmm()) { |
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1574 |
out->print("%s", as_xmm_double_reg()->name()); |
1 | 1575 |
} else if (is_single_fpu()) { |
1576 |
out->print("fpu%d", fpu_regnr()); |
|
1577 |
} else if (is_double_fpu()) { |
|
1578 |
out->print("fpu%d", fpu_regnrLo()); |
|
6176
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1579 |
#elif defined(ARM) |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1580 |
} else if (is_single_fpu()) { |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1581 |
out->print("s%d", fpu_regnr()); |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1582 |
} else if (is_double_fpu()) { |
4d9030fe341f
6953477: Increase portability and flexibility of building Hotspot
bobv
parents:
5702
diff
changeset
|
1583 |
out->print("d%d", fpu_regnrLo() >> 1); |
1 | 1584 |
#else |
1585 |
} else if (is_single_fpu()) { |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1586 |
out->print("%s", as_float_reg()->name()); |
1 | 1587 |
} else if (is_double_fpu()) { |
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1588 |
out->print("%s", as_double_reg()->name()); |
1 | 1589 |
#endif |
1590 |
||
1591 |
} else if (is_illegal()) { |
|
1592 |
out->print("-"); |
|
1593 |
} else { |
|
1594 |
out->print("Unknown Operand"); |
|
1595 |
} |
|
1596 |
if (!is_illegal()) { |
|
1597 |
out->print("|%c", type_char()); |
|
1598 |
} |
|
1599 |
if (is_register() && is_last_use()) { |
|
1600 |
out->print("(last_use)"); |
|
1601 |
} |
|
1602 |
out->print("]"); |
|
1603 |
} |
|
1604 |
||
1605 |
||
1606 |
// LIR_Address |
|
1607 |
void LIR_Const::print_value_on(outputStream* out) const { |
|
1608 |
switch (type()) { |
|
5048
c31b6243f37e
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
5046
diff
changeset
|
1609 |
case T_ADDRESS:out->print("address:%d",as_jint()); break; |
1 | 1610 |
case T_INT: out->print("int:%d", as_jint()); break; |
15228
e92acc84ade3
7102489: RFE: cleanup jlong typedef on __APPLE__and _LLP64 systems.
hseigel
parents:
13886
diff
changeset
|
1611 |
case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; |
1 | 1612 |
case T_FLOAT: out->print("flt:%f", as_jfloat()); break; |
1613 |
case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1614 |
case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; |
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1615 |
case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; |
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1616 |
default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; |
1 | 1617 |
} |
1618 |
} |
|
1619 |
||
1620 |
// LIR_Address |
|
1621 |
void LIR_Address::print_value_on(outputStream* out) const { |
|
1622 |
out->print("Base:"); _base->print(out); |
|
1623 |
if (!_index->is_illegal()) { |
|
1624 |
out->print(" Index:"); _index->print(out); |
|
1625 |
switch (scale()) { |
|
1626 |
case times_1: break; |
|
1627 |
case times_2: out->print(" * 2"); break; |
|
1628 |
case times_4: out->print(" * 4"); break; |
|
1629 |
case times_8: out->print(" * 8"); break; |
|
1630 |
} |
|
1631 |
} |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1632 |
out->print(" Disp: " INTX_FORMAT, _disp); |
1 | 1633 |
} |
1634 |
||
1635 |
// debug output of block header without InstructionPrinter |
|
1636 |
// (because phi functions are not necessary for LIR) |
|
1637 |
static void print_block(BlockBegin* x) { |
|
1638 |
// print block id |
|
1639 |
BlockEnd* end = x->end(); |
|
1640 |
tty->print("B%d ", x->block_id()); |
|
1641 |
||
1642 |
// print flags |
|
1643 |
if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); |
|
1644 |
if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); |
|
1645 |
if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); |
|
1646 |
if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); |
|
1647 |
if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); |
|
1648 |
if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); |
|
1649 |
if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); |
|
1650 |
||
1651 |
// print block bci range |
|
6745 | 1652 |
tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); |
1 | 1653 |
|
1654 |
// print predecessors and successors |
|
1655 |
if (x->number_of_preds() > 0) { |
|
1656 |
tty->print("preds: "); |
|
1657 |
for (int i = 0; i < x->number_of_preds(); i ++) { |
|
1658 |
tty->print("B%d ", x->pred_at(i)->block_id()); |
|
1659 |
} |
|
1660 |
} |
|
1661 |
||
1662 |
if (x->number_of_sux() > 0) { |
|
1663 |
tty->print("sux: "); |
|
1664 |
for (int i = 0; i < x->number_of_sux(); i ++) { |
|
1665 |
tty->print("B%d ", x->sux_at(i)->block_id()); |
|
1666 |
} |
|
1667 |
} |
|
1668 |
||
1669 |
// print exception handlers |
|
1670 |
if (x->number_of_exception_handlers() > 0) { |
|
1671 |
tty->print("xhandler: "); |
|
1672 |
for (int i = 0; i < x->number_of_exception_handlers(); i++) { |
|
1673 |
tty->print("B%d ", x->exception_handler_at(i)->block_id()); |
|
1674 |
} |
|
1675 |
} |
|
1676 |
||
1677 |
tty->cr(); |
|
1678 |
} |
|
1679 |
||
1680 |
void print_LIR(BlockList* blocks) { |
|
1681 |
tty->print_cr("LIR:"); |
|
1682 |
int i; |
|
1683 |
for (i = 0; i < blocks->length(); i++) { |
|
1684 |
BlockBegin* bb = blocks->at(i); |
|
1685 |
print_block(bb); |
|
1686 |
tty->print("__id_Instruction___________________________________________"); tty->cr(); |
|
1687 |
bb->lir()->print_instructions(); |
|
1688 |
} |
|
1689 |
} |
|
1690 |
||
1691 |
void LIR_List::print_instructions() { |
|
1692 |
for (int i = 0; i < _operations.length(); i++) { |
|
1693 |
_operations.at(i)->print(); tty->cr(); |
|
1694 |
} |
|
1695 |
tty->cr(); |
|
1696 |
} |
|
1697 |
||
1698 |
// LIR_Ops printing routines |
|
1699 |
// LIR_Op |
|
1700 |
void LIR_Op::print_on(outputStream* out) const { |
|
1701 |
if (id() != -1 || PrintCFGToFile) { |
|
1702 |
out->print("%4d ", id()); |
|
1703 |
} else { |
|
1704 |
out->print(" "); |
|
1705 |
} |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
21102
diff
changeset
|
1706 |
out->print("%s ", name()); |
1 | 1707 |
print_instr(out); |
6745 | 1708 |
if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); |
1 | 1709 |
#ifdef ASSERT |
1710 |
if (Verbose && _file != NULL) { |
|
1711 |
out->print(" (%s:%d)", _file, _line); |
|
1712 |
} |
|
1713 |
#endif |
|
1714 |
} |
|
1715 |
||
1716 |
const char * LIR_Op::name() const { |
|
1717 |
const char* s = NULL; |
|
1718 |
switch(code()) { |
|
1719 |
// LIR_Op0 |
|
1720 |
case lir_membar: s = "membar"; break; |
|
1721 |
case lir_membar_acquire: s = "membar_acquire"; break; |
|
1722 |
case lir_membar_release: s = "membar_release"; break; |
|
11886
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
1723 |
case lir_membar_loadload: s = "membar_loadload"; break; |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
1724 |
case lir_membar_storestore: s = "membar_storestore"; break; |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
1725 |
case lir_membar_loadstore: s = "membar_loadstore"; break; |
feebf5c9f40c
7120481: storeStore barrier in constructor with final field
jiangli
parents:
11433
diff
changeset
|
1726 |
case lir_membar_storeload: s = "membar_storeload"; break; |
1 | 1727 |
case lir_word_align: s = "word_align"; break; |
1728 |
case lir_label: s = "label"; break; |
|
1729 |
case lir_nop: s = "nop"; break; |
|
1730 |
case lir_backwardbranch_target: s = "backbranch"; break; |
|
1731 |
case lir_std_entry: s = "std_entry"; break; |
|
1732 |
case lir_osr_entry: s = "osr_entry"; break; |
|
1733 |
case lir_build_frame: s = "build_frm"; break; |
|
1734 |
case lir_fpop_raw: s = "fpop_raw"; break; |
|
1735 |
case lir_24bit_FPU: s = "24bit_FPU"; break; |
|
1736 |
case lir_reset_FPU: s = "reset_FPU"; break; |
|
1737 |
case lir_breakpoint: s = "breakpoint"; break; |
|
1738 |
case lir_get_thread: s = "get_thread"; break; |
|
1739 |
// LIR_Op1 |
|
1740 |
case lir_fxch: s = "fxch"; break; |
|
1741 |
case lir_fld: s = "fld"; break; |
|
1742 |
case lir_ffree: s = "ffree"; break; |
|
1743 |
case lir_push: s = "push"; break; |
|
1744 |
case lir_pop: s = "pop"; break; |
|
1745 |
case lir_null_check: s = "null_check"; break; |
|
1746 |
case lir_return: s = "return"; break; |
|
1747 |
case lir_safepoint: s = "safepoint"; break; |
|
1748 |
case lir_neg: s = "neg"; break; |
|
1749 |
case lir_leal: s = "leal"; break; |
|
1750 |
case lir_branch: s = "branch"; break; |
|
1751 |
case lir_cond_float_branch: s = "flt_cond_br"; break; |
|
1752 |
case lir_move: s = "move"; break; |
|
1753 |
case lir_roundfp: s = "roundfp"; break; |
|
1754 |
case lir_rtcall: s = "rtcall"; break; |
|
1755 |
case lir_throw: s = "throw"; break; |
|
1756 |
case lir_unwind: s = "unwind"; break; |
|
1757 |
case lir_convert: s = "convert"; break; |
|
1758 |
case lir_alloc_object: s = "alloc_obj"; break; |
|
1759 |
case lir_monaddr: s = "mon_addr"; break; |
|
6453 | 1760 |
case lir_pack64: s = "pack64"; break; |
1761 |
case lir_unpack64: s = "unpack64"; break; |
|
1 | 1762 |
// LIR_Op2 |
1763 |
case lir_cmp: s = "cmp"; break; |
|
1764 |
case lir_cmp_l2i: s = "cmp_l2i"; break; |
|
1765 |
case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; |
|
1766 |
case lir_cmp_fd2i: s = "comp_fd2i"; break; |
|
1767 |
case lir_cmove: s = "cmove"; break; |
|
1768 |
case lir_add: s = "add"; break; |
|
1769 |
case lir_sub: s = "sub"; break; |
|
1770 |
case lir_mul: s = "mul"; break; |
|
1771 |
case lir_mul_strictfp: s = "mul_strictfp"; break; |
|
1772 |
case lir_div: s = "div"; break; |
|
1773 |
case lir_div_strictfp: s = "div_strictfp"; break; |
|
1774 |
case lir_rem: s = "rem"; break; |
|
1775 |
case lir_abs: s = "abs"; break; |
|
1776 |
case lir_sqrt: s = "sqrt"; break; |
|
1777 |
case lir_sin: s = "sin"; break; |
|
1778 |
case lir_cos: s = "cos"; break; |
|
1779 |
case lir_tan: s = "tan"; break; |
|
1780 |
case lir_log: s = "log"; break; |
|
1781 |
case lir_log10: s = "log10"; break; |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
1782 |
case lir_exp: s = "exp"; break; |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11886
diff
changeset
|
1783 |
case lir_pow: s = "pow"; break; |
1 | 1784 |
case lir_logic_and: s = "logic_and"; break; |
1785 |
case lir_logic_or: s = "logic_or"; break; |
|
1786 |
case lir_logic_xor: s = "logic_xor"; break; |
|
1787 |
case lir_shl: s = "shift_left"; break; |
|
1788 |
case lir_shr: s = "shift_right"; break; |
|
1789 |
case lir_ushr: s = "ushift_right"; break; |
|
1790 |
case lir_alloc_array: s = "alloc_array"; break; |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
1791 |
case lir_xadd: s = "xadd"; break; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13742
diff
changeset
|
1792 |
case lir_xchg: s = "xchg"; break; |
1 | 1793 |
// LIR_Op3 |
1794 |
case lir_idiv: s = "idiv"; break; |
|
1795 |
case lir_irem: s = "irem"; break; |
|
1796 |
// LIR_OpJavaCall |
|
1797 |
case lir_static_call: s = "static"; break; |
|
1798 |
case lir_optvirtual_call: s = "optvirtual"; break; |
|
1799 |
case lir_icvirtual_call: s = "icvirtual"; break; |
|
1800 |
case lir_virtual_call: s = "virtual"; break; |
|
5046 | 1801 |
case lir_dynamic_call: s = "dynamic"; break; |
1 | 1802 |
// LIR_OpArrayCopy |
1803 |
case lir_arraycopy: s = "arraycopy"; break; |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1804 |
// LIR_OpUpdateCRC32 |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18104
diff
changeset
|
1805 |
case lir_updatecrc32: s = "updatecrc32"; break; |
1 | 1806 |
// LIR_OpLock |
1807 |
case lir_lock: s = "lock"; break; |
|
1808 |
case lir_unlock: s = "unlock"; break; |
|
1809 |
// LIR_OpDelay |
|
1810 |
case lir_delay_slot: s = "delay"; break; |
|
1811 |
// LIR_OpTypeCheck |
|
1812 |
case lir_instanceof: s = "instanceof"; break; |
|
1813 |
case lir_checkcast: s = "checkcast"; break; |
|
1814 |
case lir_store_check: s = "store_check"; break; |
|
1815 |
// LIR_OpCompareAndSwap |
|
1816 |
case lir_cas_long: s = "cas_long"; break; |
|
1817 |
case lir_cas_obj: s = "cas_obj"; break; |
|
1818 |
case lir_cas_int: s = "cas_int"; break; |
|
1819 |
// LIR_OpProfileCall |
|
1820 |
case lir_profile_call: s = "profile_call"; break; |
|
20702
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1821 |
// LIR_OpProfileType |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
1822 |
case lir_profile_type: s = "profile_type"; break; |
16611 | 1823 |
// LIR_OpAssert |
17011
def8879c5b81
8011648: C1: optimized build is broken after 7153771
roland
parents:
16611
diff
changeset
|
1824 |
#ifdef ASSERT |
16611 | 1825 |
case lir_assert: s = "assert"; break; |
17011
def8879c5b81
8011648: C1: optimized build is broken after 7153771
roland
parents:
16611
diff
changeset
|
1826 |
#endif |
1 | 1827 |
case lir_none: ShouldNotReachHere();break; |
1828 |
default: s = "illegal_op"; break; |
|
1829 |
} |
|
1830 |
return s; |
|
1831 |
} |
|
1832 |
||
1833 |
// LIR_OpJavaCall |
|
1834 |
void LIR_OpJavaCall::print_instr(outputStream* out) const { |
|
1835 |
out->print("call: "); |
|
24424
2658d7834c6e
8037816: Fix for 8036122 breaks build with Xcode5/clang
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|
1836 |
out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); |
1 | 1837 |
if (receiver()->is_valid()) { |
1838 |
out->print(" [recv: "); receiver()->print(out); out->print("]"); |
|
1839 |
} |
|
1840 |
if (result_opr()->is_valid()) { |
|
1841 |
out->print(" [result: "); result_opr()->print(out); out->print("]"); |
|
1842 |
} |
|
1843 |
} |
|
1844 |
||
1845 |
// LIR_OpLabel |
|
1846 |
void LIR_OpLabel::print_instr(outputStream* out) const { |
|
24424
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|
1847 |
out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); |
1 | 1848 |
} |
1849 |
||
1850 |
// LIR_OpArrayCopy |
|
1851 |
void LIR_OpArrayCopy::print_instr(outputStream* out) const { |
|
1852 |
src()->print(out); out->print(" "); |
|
1853 |
src_pos()->print(out); out->print(" "); |
|
1854 |
dst()->print(out); out->print(" "); |
|
1855 |
dst_pos()->print(out); out->print(" "); |
|
1856 |
length()->print(out); out->print(" "); |
|
1857 |
tmp()->print(out); out->print(" "); |
|
1858 |
} |
|
1859 |
||
18507
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|
1860 |
// LIR_OpUpdateCRC32 |
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|
1861 |
void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { |
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changeset
|
1862 |
crc()->print(out); out->print(" "); |
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|
1863 |
val()->print(out); out->print(" "); |
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|
1864 |
result_opr()->print(out); out->print(" "); |
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|
1865 |
} |
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|
1866 |
|
1 | 1867 |
// LIR_OpCompareAndSwap |
1868 |
void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { |
|
1869 |
addr()->print(out); out->print(" "); |
|
1870 |
cmp_value()->print(out); out->print(" "); |
|
1871 |
new_value()->print(out); out->print(" "); |
|
1872 |
tmp1()->print(out); out->print(" "); |
|
1873 |
tmp2()->print(out); out->print(" "); |
|
1874 |
||
1875 |
} |
|
1876 |
||
1877 |
// LIR_Op0 |
|
1878 |
void LIR_Op0::print_instr(outputStream* out) const { |
|
1879 |
result_opr()->print(out); |
|
1880 |
} |
|
1881 |
||
1882 |
// LIR_Op1 |
|
1883 |
const char * LIR_Op1::name() const { |
|
1884 |
if (code() == lir_move) { |
|
1885 |
switch (move_kind()) { |
|
1886 |
case lir_move_normal: |
|
1887 |
return "move"; |
|
1888 |
case lir_move_unaligned: |
|
1889 |
return "unaligned move"; |
|
1890 |
case lir_move_volatile: |
|
1891 |
return "volatile_move"; |
|
7427 | 1892 |
case lir_move_wide: |
1893 |
return "wide_move"; |
|
1 | 1894 |
default: |
1895 |
ShouldNotReachHere(); |
|
1896 |
return "illegal_op"; |
|
1897 |
} |
|
1898 |
} else { |
|
1899 |
return LIR_Op::name(); |
|
1900 |
} |
|
1901 |
} |
|
1902 |
||
1903 |
||
1904 |
void LIR_Op1::print_instr(outputStream* out) const { |
|
1905 |
_opr->print(out); out->print(" "); |
|
1906 |
result_opr()->print(out); out->print(" "); |
|
1907 |
print_patch_code(out, patch_code()); |
|
1908 |
} |
|
1909 |
||
1910 |
||
1911 |
// LIR_Op1 |
|
1912 |
void LIR_OpRTCall::print_instr(outputStream* out) const { |
|
1913 |
intx a = (intx)addr(); |
|
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|
1914 |
out->print("%s", Runtime1::name_for_address(addr())); |
1 | 1915 |
out->print(" "); |
1916 |
tmp()->print(out); |
|
1917 |
} |
|
1918 |
||
1919 |
void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { |
|
1920 |
switch(code) { |
|
1921 |
case lir_patch_none: break; |
|
1922 |
case lir_patch_low: out->print("[patch_low]"); break; |
|
1923 |
case lir_patch_high: out->print("[patch_high]"); break; |
|
1924 |
case lir_patch_normal: out->print("[patch_normal]"); break; |
|
1925 |
default: ShouldNotReachHere(); |
|
1926 |
} |
|
1927 |
} |
|
1928 |
||
1929 |
// LIR_OpBranch |
|
1930 |
void LIR_OpBranch::print_instr(outputStream* out) const { |
|
1931 |
print_condition(out, cond()); out->print(" "); |
|
1932 |
if (block() != NULL) { |
|
1933 |
out->print("[B%d] ", block()->block_id()); |
|
1934 |
} else if (stub() != NULL) { |
|
1935 |
out->print("["); |
|
1936 |
stub()->print_name(out); |
|
24424
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|
1937 |
out->print(": " INTPTR_FORMAT "]", p2i(stub())); |
6745 | 1938 |
if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); |
1 | 1939 |
} else { |
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|
1940 |
out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); |
1 | 1941 |
} |
1942 |
if (ublock() != NULL) { |
|
1943 |
out->print("unordered: [B%d] ", ublock()->block_id()); |
|
1944 |
} |
|
1945 |
} |
|
1946 |
||
1947 |
void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { |
|
1948 |
switch(cond) { |
|
1949 |
case lir_cond_equal: out->print("[EQ]"); break; |
|
1950 |
case lir_cond_notEqual: out->print("[NE]"); break; |
|
1951 |
case lir_cond_less: out->print("[LT]"); break; |
|
1952 |
case lir_cond_lessEqual: out->print("[LE]"); break; |
|
1953 |
case lir_cond_greaterEqual: out->print("[GE]"); break; |
|
1954 |
case lir_cond_greater: out->print("[GT]"); break; |
|
1955 |
case lir_cond_belowEqual: out->print("[BE]"); break; |
|
1956 |
case lir_cond_aboveEqual: out->print("[AE]"); break; |
|
1957 |
case lir_cond_always: out->print("[AL]"); break; |
|
1958 |
default: out->print("[%d]",cond); break; |
|
1959 |
} |
|
1960 |
} |
|
1961 |
||
1962 |
// LIR_OpConvert |
|
1963 |
void LIR_OpConvert::print_instr(outputStream* out) const { |
|
1964 |
print_bytecode(out, bytecode()); |
|
1965 |
in_opr()->print(out); out->print(" "); |
|
1966 |
result_opr()->print(out); out->print(" "); |
|
6176
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|
1967 |
#ifdef PPC |
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|
1968 |
if(tmp1()->is_valid()) { |
4d9030fe341f
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|
1969 |
tmp1()->print(out); out->print(" "); |
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|
1970 |
tmp2()->print(out); out->print(" "); |
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|
1971 |
} |
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|
1972 |
#endif |
1 | 1973 |
} |
1974 |
||
1975 |
void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { |
|
1976 |
switch(code) { |
|
1977 |
case Bytecodes::_d2f: out->print("[d2f] "); break; |
|
1978 |
case Bytecodes::_d2i: out->print("[d2i] "); break; |
|
1979 |
case Bytecodes::_d2l: out->print("[d2l] "); break; |
|
1980 |
case Bytecodes::_f2d: out->print("[f2d] "); break; |
|
1981 |
case Bytecodes::_f2i: out->print("[f2i] "); break; |
|
1982 |
case Bytecodes::_f2l: out->print("[f2l] "); break; |
|
1983 |
case Bytecodes::_i2b: out->print("[i2b] "); break; |
|
1984 |
case Bytecodes::_i2c: out->print("[i2c] "); break; |
|
1985 |
case Bytecodes::_i2d: out->print("[i2d] "); break; |
|
1986 |
case Bytecodes::_i2f: out->print("[i2f] "); break; |
|
1987 |
case Bytecodes::_i2l: out->print("[i2l] "); break; |
|
1988 |
case Bytecodes::_i2s: out->print("[i2s] "); break; |
|
1989 |
case Bytecodes::_l2i: out->print("[l2i] "); break; |
|
1990 |
case Bytecodes::_l2f: out->print("[l2f] "); break; |
|
1991 |
case Bytecodes::_l2d: out->print("[l2d] "); break; |
|
1992 |
default: |
|
1993 |
out->print("[?%d]",code); |
|
1994 |
break; |
|
1995 |
} |
|
1996 |
} |
|
1997 |
||
1998 |
void LIR_OpAllocObj::print_instr(outputStream* out) const { |
|
1999 |
klass()->print(out); out->print(" "); |
|
2000 |
obj()->print(out); out->print(" "); |
|
2001 |
tmp1()->print(out); out->print(" "); |
|
2002 |
tmp2()->print(out); out->print(" "); |
|
2003 |
tmp3()->print(out); out->print(" "); |
|
2004 |
tmp4()->print(out); out->print(" "); |
|
2005 |
out->print("[hdr:%d]", header_size()); out->print(" "); |
|
2006 |
out->print("[obj:%d]", object_size()); out->print(" "); |
|
24424
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changeset
|
2007 |
out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
1 | 2008 |
} |
2009 |
||
2010 |
void LIR_OpRoundFP::print_instr(outputStream* out) const { |
|
2011 |
_opr->print(out); out->print(" "); |
|
2012 |
tmp()->print(out); out->print(" "); |
|
2013 |
result_opr()->print(out); out->print(" "); |
|
2014 |
} |
|
2015 |
||
2016 |
// LIR_Op2 |
|
2017 |
void LIR_Op2::print_instr(outputStream* out) const { |
|
2018 |
if (code() == lir_cmove) { |
|
2019 |
print_condition(out, condition()); out->print(" "); |
|
2020 |
} |
|
2021 |
in_opr1()->print(out); out->print(" "); |
|
2022 |
in_opr2()->print(out); out->print(" "); |
|
12739
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|
2023 |
if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } |
09f26b73ae66
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diff
changeset
|
2024 |
if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
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diff
changeset
|
2025 |
if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } |
09f26b73ae66
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diff
changeset
|
2026 |
if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
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diff
changeset
|
2027 |
if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } |
1 | 2028 |
result_opr()->print(out); |
2029 |
} |
|
2030 |
||
2031 |
void LIR_OpAllocArray::print_instr(outputStream* out) const { |
|
2032 |
klass()->print(out); out->print(" "); |
|
2033 |
len()->print(out); out->print(" "); |
|
2034 |
obj()->print(out); out->print(" "); |
|
2035 |
tmp1()->print(out); out->print(" "); |
|
2036 |
tmp2()->print(out); out->print(" "); |
|
2037 |
tmp3()->print(out); out->print(" "); |
|
2038 |
tmp4()->print(out); out->print(" "); |
|
2039 |
out->print("[type:0x%x]", type()); out->print(" "); |
|
24424
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8037816: Fix for 8036122 breaks build with Xcode5/clang
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diff
changeset
|
2040 |
out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
1 | 2041 |
} |
2042 |
||
2043 |
||
2044 |
void LIR_OpTypeCheck::print_instr(outputStream* out) const { |
|
2045 |
object()->print(out); out->print(" "); |
|
2046 |
if (code() == lir_store_check) { |
|
2047 |
array()->print(out); out->print(" "); |
|
2048 |
} |
|
2049 |
if (code() != lir_store_check) { |
|
2050 |
klass()->print_name_on(out); out->print(" "); |
|
2051 |
if (fast_check()) out->print("fast_check "); |
|
2052 |
} |
|
2053 |
tmp1()->print(out); out->print(" "); |
|
2054 |
tmp2()->print(out); out->print(" "); |
|
2055 |
tmp3()->print(out); out->print(" "); |
|
2056 |
result_opr()->print(out); out->print(" "); |
|
6745 | 2057 |
if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); |
1 | 2058 |
} |
2059 |
||
2060 |
||
2061 |
// LIR_Op3 |
|
2062 |
void LIR_Op3::print_instr(outputStream* out) const { |
|
2063 |
in_opr1()->print(out); out->print(" "); |
|
2064 |
in_opr2()->print(out); out->print(" "); |
|
2065 |
in_opr3()->print(out); out->print(" "); |
|
2066 |
result_opr()->print(out); |
|
2067 |
} |
|
2068 |
||
2069 |
||
2070 |
void LIR_OpLock::print_instr(outputStream* out) const { |
|
2071 |
hdr_opr()->print(out); out->print(" "); |
|
2072 |
obj_opr()->print(out); out->print(" "); |
|
2073 |
lock_opr()->print(out); out->print(" "); |
|
2074 |
if (_scratch->is_valid()) { |
|
2075 |
_scratch->print(out); out->print(" "); |
|
2076 |
} |
|
24424
2658d7834c6e
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changeset
|
2077 |
out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); |
1 | 2078 |
} |
2079 |
||
17011
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changeset
|
2080 |
#ifdef ASSERT |
16611 | 2081 |
void LIR_OpAssert::print_instr(outputStream* out) const { |
2082 |
print_condition(out, condition()); out->print(" "); |
|
2083 |
in_opr1()->print(out); out->print(" "); |
|
2084 |
in_opr2()->print(out); out->print(", \""); |
|
24424
2658d7834c6e
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diff
changeset
|
2085 |
out->print("%s", msg()); out->print("\""); |
16611 | 2086 |
} |
17011
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changeset
|
2087 |
#endif |
16611 | 2088 |
|
1 | 2089 |
|
2090 |
void LIR_OpDelay::print_instr(outputStream* out) const { |
|
2091 |
_op->print_on(out); |
|
2092 |
} |
|
2093 |
||
2094 |
||
2095 |
// LIR_OpProfileCall |
|
2096 |
void LIR_OpProfileCall::print_instr(outputStream* out) const { |
|
2097 |
profiled_method()->name()->print_symbol_on(out); |
|
2098 |
out->print("."); |
|
2099 |
profiled_method()->holder()->name()->print_symbol_on(out); |
|
2100 |
out->print(" @ %d ", profiled_bci()); |
|
2101 |
mdo()->print(out); out->print(" "); |
|
2102 |
recv()->print(out); out->print(" "); |
|
2103 |
tmp1()->print(out); out->print(" "); |
|
2104 |
} |
|
2105 |
||
20702
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2106 |
// LIR_OpProfileType |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2107 |
void LIR_OpProfileType::print_instr(outputStream* out) const { |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2108 |
out->print("exact = "); exact_klass()->print_name_on(out); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
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diff
changeset
|
2109 |
out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass()); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
2110 |
mdp()->print(out); out->print(" "); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
roland
parents:
18507
diff
changeset
|
2111 |
obj()->print(out); out->print(" "); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2112 |
tmp()->print(out); out->print(" "); |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2113 |
} |
bbe0fcde6e13
8023657: New type profiling points: arguments to call
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parents:
18507
diff
changeset
|
2114 |
|
1 | 2115 |
#endif // PRODUCT |
2116 |
||
2117 |
// Implementation of LIR_InsertionBuffer |
|
2118 |
||
2119 |
void LIR_InsertionBuffer::append(int index, LIR_Op* op) { |
|
2120 |
assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); |
|
2121 |
||
2122 |
int i = number_of_insertion_points() - 1; |
|
2123 |
if (i < 0 || index_at(i) < index) { |
|
2124 |
append_new(index, 1); |
|
2125 |
} else { |
|
2126 |
assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); |
|
2127 |
assert(count_at(i) > 0, "check"); |
|
2128 |
set_count_at(i, count_at(i) + 1); |
|
2129 |
} |
|
2130 |
_ops.push(op); |
|
2131 |
||
2132 |
DEBUG_ONLY(verify()); |
|
2133 |
} |
|
2134 |
||
2135 |
#ifdef ASSERT |
|
2136 |
void LIR_InsertionBuffer::verify() { |
|
2137 |
int sum = 0; |
|
2138 |
int prev_idx = -1; |
|
2139 |
||
2140 |
for (int i = 0; i < number_of_insertion_points(); i++) { |
|
2141 |
assert(prev_idx < index_at(i), "index must be ordered ascending"); |
|
2142 |
sum += count_at(i); |
|
2143 |
} |
|
2144 |
assert(sum == number_of_ops(), "wrong total sum"); |
|
2145 |
} |
|
2146 |
#endif |