hotspot/src/cpu/sparc/vm/sparc.ad
author lana
Thu, 16 Oct 2014 14:15:58 -0700
changeset 27113 28c10766cfac
parent 26804 4b23f22faae6
child 28719 5a9aedf87213
permissions -rw-r--r--
Merge
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//
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// Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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//
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// This code is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License version 2 only, as
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// published by the Free Software Foundation.
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//
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// This code is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// version 2 for more details (a copy is included in the LICENSE file that
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// accompanied this code).
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//
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// You should have received a copy of the GNU General Public License version
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// 2 along with this work; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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// or visit www.oracle.com if you need additional information or have any
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// questions.
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//
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//
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// SPARC Architecture Description File
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//----------REGISTER DEFINITION BLOCK------------------------------------------
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// This information is used by the matcher and the register allocator to
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// describe individual registers and classes of registers within the target
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// archtecture.
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register %{
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//----------Architecture Description Register Definitions----------------------
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// General Registers
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// "reg_def"  name ( register save type, C convention save type,
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//                   ideal register type, encoding, vm name );
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// Register Save Types:
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//
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// NS  = No-Save:       The register allocator assumes that these registers
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//                      can be used without saving upon entry to the method, &
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//                      that they do not need to be saved at call sites.
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//
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// SOC = Save-On-Call:  The register allocator assumes that these registers
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//                      can be used without saving upon entry to the method,
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//                      but that they must be saved at call sites.
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//
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// SOE = Save-On-Entry: The register allocator assumes that these registers
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//                      must be saved before using them upon entry to the
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//                      method, but they do not need to be saved at call
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//                      sites.
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//
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// AS  = Always-Save:   The register allocator assumes that these registers
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//                      must be saved before using them upon entry to the
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//                      method, & that they must be saved at call sites.
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//
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// Ideal Register Type is used to determine how to save & restore a
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// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
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//
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// The encoding number is the actual bit-pattern placed into the opcodes.
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// ----------------------------
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// Integer/Long Registers
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// ----------------------------
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// Need to expose the hi/lo aspect of 64-bit registers
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// This register set is used for both the 64-bit build and
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// the 32-bit build with 1-register longs.
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// Global Registers 0-7
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reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
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reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
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reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
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reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
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reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
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reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
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reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
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reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
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reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
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reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
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reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
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reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
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reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
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reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
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reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
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reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
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// Output Registers 0-7
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reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
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reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
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reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
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reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
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reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
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reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
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reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
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reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
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reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
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reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
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reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
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reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
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reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
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reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
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reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
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reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
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// Local Registers 0-7
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reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
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reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
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reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
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reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
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reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
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reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
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reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
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reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
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reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
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reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
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reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
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reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
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reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
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reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
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reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
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reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
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// Input Registers 0-7
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reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
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reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
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reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
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reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
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reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
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reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
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reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
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reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
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reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
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reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
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reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
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reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
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reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
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reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
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reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
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reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
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// ----------------------------
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// Float/Double Registers
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// ----------------------------
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// Float Registers
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reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
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reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
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reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
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reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
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reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
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reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
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reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
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reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
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reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
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reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
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reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
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reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
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reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
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reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
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reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
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reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
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reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
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reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
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reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
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reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
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reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
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reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
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reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
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reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
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reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
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reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
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reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
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reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
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reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
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reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
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reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
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reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
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// Double Registers
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// The rules of ADL require that double registers be defined in pairs.
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// Each pair must be two 32-bit values, but not necessarily a pair of
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// single float registers.  In each pair, ADLC-assigned register numbers
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// must be adjacent, with the lower number even.  Finally, when the
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// CPU stores such a register pair to memory, the word associated with
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// the lower ADLC-assigned number must be stored to the lower address.
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// These definitions specify the actual bit encodings of the sparc
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// double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
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// wants 0-63, so we have to convert every time we want to use fp regs
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// with the macroassembler, using reg_to_DoubleFloatRegister_object().
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// 255 is a flag meaning "don't go here".
1
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// I believe we can't handle callee-save doubles D32 and up until
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// the place in the sparc stack crawler that asserts on the 255 is
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// fixed up.
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reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
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reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
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reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
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reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
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reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
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reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
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reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
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reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
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reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
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reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
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reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
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reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
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reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
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reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
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reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
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reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
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reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
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reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
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reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
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reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
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reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
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reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
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reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
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reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
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reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
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reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
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reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
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reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
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reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
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reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
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reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
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reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
1
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// ----------------------------
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// Special Registers
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// Condition Codes Flag Registers
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// I tried to break out ICC and XCC but it's not very pretty.
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// Every Sparc instruction which defs/kills one also kills the other.
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// Hence every compare instruction which defs one kind of flags ends
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// up needing a kill of the other.
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reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
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reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
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reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
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reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
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reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
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// ----------------------------
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// Specify the enum values for the registers.  These enums are only used by the
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// OptoReg "class". We can convert these enum values at will to VMReg when needed
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// for visibility to the rest of the vm. The order of this enum influences the
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// register allocator so having the freedom to set this order and not be stuck
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// with the order that is natural for the rest of the vm is worth it.
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alloc_class chunk0(
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  R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
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  R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
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  R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
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  R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
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// Note that a register is not allocatable unless it is also mentioned
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// in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
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alloc_class chunk1(
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  // The first registers listed here are those most likely to be used
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  // as temporaries.  We move F0..F7 away from the front of the list,
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  // to reduce the likelihood of interferences with parameters and
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  // return values.  Likewise, we avoid using F0/F1 for parameters,
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  // since they are used for return values.
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  // This FPU fine-tuning is worth about 1% on the SPEC geomean.
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  R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
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  R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
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  R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
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  R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
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  R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
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  R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
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  R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
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  R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
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alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
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//----------Architecture Description Register Classes--------------------------
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// Several register classes are automatically defined based upon information in
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// this architecture description.
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// 1) reg_class inline_cache_reg           ( as defined in frame section )
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// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
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// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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//
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// G0 is not included in integer class since it has special meaning.
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reg_class g0_reg(R_G0);
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// ----------------------------
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// Integer Register Classes
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// ----------------------------
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// Exclusions from i_reg:
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// R_G0: hardwired zero
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// R_G2: reserved by HotSpot to the TLS register (invariant within Java)
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// R_G6: reserved by Solaris ABI to tools
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// R_G7: reserved by Solaris ABI to libthread
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// R_O7: Used as a temp in many encodings
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reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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// Class for all integer registers, except the G registers.  This is used for
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// encodings which use G registers as temps.  The regular inputs to such
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// instructions use a "notemp_" prefix, as a hack to ensure that the allocator
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// will not put an input into a temp register.
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   303
reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   304
489c9b5090e2 Initial load
duke
parents:
diff changeset
   305
reg_class g1_regI(R_G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   306
reg_class g3_regI(R_G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   307
reg_class g4_regI(R_G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   308
reg_class o0_regI(R_O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   309
reg_class o7_regI(R_O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   310
489c9b5090e2 Initial load
duke
parents:
diff changeset
   311
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   312
// Pointer Register Classes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   313
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   314
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   315
// 64-bit build means 64-bit pointers means hi/lo pairs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   316
reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   317
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   318
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   319
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   320
// Lock encodings use G3 and G4 internally
489c9b5090e2 Initial load
duke
parents:
diff changeset
   321
reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   322
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   323
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   324
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   325
// Special class for storeP instructions, which can store SP or RPC to TLS.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   326
// It is also used for memory addressing, allowing direct TLS addressing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   327
reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   328
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   329
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   330
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   331
// R_L7 is the lowest-priority callee-save (i.e., NS) register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   332
// We use it to save R_G2 across calls out of Java.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   333
reg_class l7_regP(R_L7H,R_L7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   334
489c9b5090e2 Initial load
duke
parents:
diff changeset
   335
// Other special pointer regs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   336
reg_class g1_regP(R_G1H,R_G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   337
reg_class g2_regP(R_G2H,R_G2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   338
reg_class g3_regP(R_G3H,R_G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   339
reg_class g4_regP(R_G4H,R_G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   340
reg_class g5_regP(R_G5H,R_G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   341
reg_class i0_regP(R_I0H,R_I0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   342
reg_class o0_regP(R_O0H,R_O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   343
reg_class o1_regP(R_O1H,R_O1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   344
reg_class o2_regP(R_O2H,R_O2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   345
reg_class o7_regP(R_O7H,R_O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   346
489c9b5090e2 Initial load
duke
parents:
diff changeset
   347
#else // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   348
// 32-bit build means 32-bit pointers means 1 register.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   349
reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   350
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   351
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   352
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   353
// Lock encodings use G3 and G4 internally
489c9b5090e2 Initial load
duke
parents:
diff changeset
   354
reg_class lock_ptr_reg(R_G1,               R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   355
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   356
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   357
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   358
// Special class for storeP instructions, which can store SP or RPC to TLS.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   359
// It is also used for memory addressing, allowing direct TLS addressing.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   360
reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   361
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   362
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   363
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   364
// R_L7 is the lowest-priority callee-save (i.e., NS) register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   365
// We use it to save R_G2 across calls out of Java.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
reg_class l7_regP(R_L7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   367
489c9b5090e2 Initial load
duke
parents:
diff changeset
   368
// Other special pointer regs
489c9b5090e2 Initial load
duke
parents:
diff changeset
   369
reg_class g1_regP(R_G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   370
reg_class g2_regP(R_G2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   371
reg_class g3_regP(R_G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   372
reg_class g4_regP(R_G4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
reg_class g5_regP(R_G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   374
reg_class i0_regP(R_I0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
reg_class o0_regP(R_O0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
reg_class o1_regP(R_O1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
reg_class o2_regP(R_O2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
reg_class o7_regP(R_O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   379
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   380
489c9b5090e2 Initial load
duke
parents:
diff changeset
   381
489c9b5090e2 Initial load
duke
parents:
diff changeset
   382
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   383
// Long Register Classes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   384
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   385
// Longs in 1 register.  Aligned adjacent hi/lo pairs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   386
// Note:  O7 is never in this class; it is sometimes used as an encoding temp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   387
reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
489c9b5090e2 Initial load
duke
parents:
diff changeset
   388
                   ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
489c9b5090e2 Initial load
duke
parents:
diff changeset
   389
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   390
// 64-bit, longs in 1 register: use all 64-bit integer registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
   391
// 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   392
                   ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
489c9b5090e2 Initial load
duke
parents:
diff changeset
   393
                   ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
489c9b5090e2 Initial load
duke
parents:
diff changeset
   394
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   395
                  );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
reg_class g1_regL(R_G1H,R_G1);
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
   398
reg_class g3_regL(R_G3H,R_G3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   399
reg_class o2_regL(R_O2H,R_O2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
reg_class o7_regL(R_O7H,R_O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
// Special Class for Condition Code Flags Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
reg_class int_flags(CCR);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   405
reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
reg_class float_flag0(FCC0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
489c9b5090e2 Initial load
duke
parents:
diff changeset
   408
489c9b5090e2 Initial load
duke
parents:
diff changeset
   409
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
// Float Point Register Classes
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
// ----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
// Skip F30/F31, they are reserved for mem-mem copies
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
// Paired floating point registers--they show up in the same order as the floats,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
                   /* Use extra V9 double registers; this AD file does not support V8 */
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
                   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
                   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
                   );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   423
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
// Paired floating point registers--they show up in the same order as the floats,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
// This class is usable for mis-aligned loads as happen in I2C adapters.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
   428
                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
//----------DEFINITION BLOCK---------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
// Define name --> value mappings to inform the ADLC of an integer valued name
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
// Current support includes integer values in the range [0, 0x7FFFFFFF]
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
// Format:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   435
//        int_def  <name>         ( <int_value>, <expression>);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
// Generated Code in ad_<arch>.hpp
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
//        #define  <name>   (<expression>)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   438
//        // value == <int_value>
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
// Generated code in ad_<arch>.cpp adlc_verification()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
//        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
definitions %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
// The default cost (of an ALU instruction).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
  int_def DEFAULT_COST      (    100,     100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
  int_def HUGE_COST         (1000000, 1000000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
// Memory refs are twice as expensive as run-of-the-mill.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
  int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
// Branches are even more expensive.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   451
  int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   452
  int_def CALL_COST         (    300, DEFAULT_COST * 3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   453
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   454
489c9b5090e2 Initial load
duke
parents:
diff changeset
   455
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
//----------SOURCE BLOCK-------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   457
// This is a block of C++ code which provides values, functions, and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   458
// definitions necessary in the rest of the architecture description
489c9b5090e2 Initial load
duke
parents:
diff changeset
   459
source_hpp %{
23498
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   460
// Header information of the source block.
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   461
// Method declarations/definitions which are used outside
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   462
// the ad-scope can conveniently be defined here.
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   463
//
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   464
// To keep related declarations/definitions/uses close together,
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   465
// we switch between source %{ }% and source_hpp %{ }% freely as needed.
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   466
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
// Must be visible to the DFA in dfa_sparc.cpp
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
extern bool can_branch_register( Node *bol, Node *cmp );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   470
extern bool use_block_zeroing(Node* count);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   471
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
// Macros to extract hi & lo halves from a long pair.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   473
// G0 is not part of any long pair, so assert on that.
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
   474
// Prevents accidentally using G1 instead of G0.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
#define LONG_HI_REG(x) (x)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
#define LONG_LO_REG(x) (x)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
23498
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   478
class CallStubImpl {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   479
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   480
  //--------------------------------------------------------------
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   481
  //---<  Used for optimization in Compile::Shorten_branches  >---
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   482
  //--------------------------------------------------------------
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   483
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   484
 public:
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   485
  // Size of call trampoline stub.
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   486
  static uint size_call_trampoline() {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   487
    return 0; // no call trampolines on this platform
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   488
  }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   489
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   490
  // number of relocations needed by a call trampoline stub
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   491
  static uint reloc_call_trampoline() {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   492
    return 0; // no call trampolines on this platform
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   493
  }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   494
};
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   495
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   496
class HandlerImpl {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   497
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   498
 public:
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   499
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   500
  static int emit_exception_handler(CodeBuffer &cbuf);
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   501
  static int emit_deopt_handler(CodeBuffer& cbuf);
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   502
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   503
  static uint size_exception_handler() {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   504
    if (TraceJumps) {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   505
      return (400); // just a guess
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   506
    }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   507
    return ( NativeJump::instruction_size ); // sethi;jmp;nop
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   508
  }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   509
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   510
  static uint size_deopt_handler() {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   511
    if (TraceJumps) {
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   512
      return (400); // just a guess
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   513
    }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   514
    return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   515
  }
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   516
};
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
   517
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
source %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
#define __ _masm.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
// tertiary op of a LoadP or StoreP encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
#define REGP_OP true
489c9b5090e2 Initial load
duke
parents:
diff changeset
   525
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   528
static Register reg_to_register_object(int register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   529
489c9b5090e2 Initial load
duke
parents:
diff changeset
   530
// Used by the DFA in dfa_sparc.cpp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
// Check for being able to use a V9 branch-on-register.  Requires a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
// compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
// extended.  Doesn't work following an integer ADD, for example, because of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
// overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
// replace them with zero, which could become sign-extension in a different OS
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
// release.  There's no obvious reason why an interrupt will ever fill these
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
// bits with non-zero junk (the registers are reloaded with standard LD
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
// instructions which either zero-fill or sign-fill).
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
bool can_branch_register( Node *bol, Node *cmp ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
  if( !BranchOnRegister ) return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
  if( cmp->Opcode() == Op_CmpP )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
    return true;  // No problems with pointer compares
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
  if( cmp->Opcode() == Op_CmpL )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
    return true;  // No problems with long compares
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
  if( !SparcV9RegsHiBitsZero ) return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
  if( bol->as_Bool()->_test._test != BoolTest::ne &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
      bol->as_Bool()->_test._test != BoolTest::eq )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
     return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
  // Check for comparing against a 'safe' value.  Any operation which
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
  // clears out the high word is safe.  Thus, loads and certain shifts
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
  // are safe, as are non-negative constants.  Any operation which
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
  // preserves zero bits in the high word is safe as long as each of its
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
  // inputs are safe.  Thus, phis and bitwise booleans are safe if their
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
  // inputs are safe.  At present, the only important case to recognize
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
  // seems to be loads.  Constants should fold away, and shifts &
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
  // logicals can use the 'cc' forms.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
  Node *x = cmp->in(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
  if( x->is_Load() ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
  if( x->is_Phi() ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
    for( uint i = 1; i < x->req(); i++ )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
      if( !x->in(i)->is_Load() )
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
        return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
    return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   572
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   573
bool use_block_zeroing(Node* count) {
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   574
  // Use BIS for zeroing if count is not constant
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   575
  // or it is >= BlockZeroingLowLimit.
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   576
  return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   577
}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
   578
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
// ****************************************************************************
489c9b5090e2 Initial load
duke
parents:
diff changeset
   580
489c9b5090e2 Initial load
duke
parents:
diff changeset
   581
// REQUIRED FUNCTIONALITY
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
// !!!!! Special hack to get all type of calls to specify the byte offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
   584
//       from the start of the call to the point where the return address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   585
//       will point.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
//       The "return address" is the address of the call instruction, plus 8.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
int MachCallStaticJavaNode::ret_addr_offset() {
5690
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
   589
  int offset = NativeCall::instruction_size;  // call; delay slot
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
   590
  if (_method_handle_invoke)
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
   591
    offset += 4;  // restore SP
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
   592
  return offset;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
int MachCallDynamicJavaNode::ret_addr_offset() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
  int vtable_index = this->_vtable_index;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
  if (vtable_index < 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
    // must be invalid_vtable_index, not nonvirtual_vtable_index
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
   599
    assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
    return (NativeMovConstReg::instruction_size +
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
           NativeCall::instruction_size);  // sethi; setlo; call; delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
    assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
   604
    int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
    int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   606
    int klass_load_size;
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 19319
diff changeset
   607
    if (UseCompressedClassPointers) {
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2150
diff changeset
   608
      assert(Universe::heap() != NULL, "java heap should be initialized");
19319
0ad35be0733a 8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents: 18097
diff changeset
   609
      klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   610
    } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   611
      klass_load_size = 1*BytesPerInstWord;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   612
    }
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
   613
    if (Assembler::is_simm13(v_off)) {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   614
      return klass_load_size +
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   615
             (2*BytesPerInstWord +           // ld_ptr, ld_ptr
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
             NativeCall::instruction_size);  // call; delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   617
    } else {
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   618
      return klass_load_size +
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
   619
             (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   620
             NativeCall::instruction_size);  // call; delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   621
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   622
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   623
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   624
489c9b5090e2 Initial load
duke
parents:
diff changeset
   625
int MachCallRuntimeNode::ret_addr_offset() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   626
#ifdef _LP64
7892
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
   627
  if (MacroAssembler::is_far_target(entry_point())) {
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
   628
    return NativeFarCall::instruction_size;
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
   629
  } else {
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
   630
    return NativeCall::instruction_size;
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
   631
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   632
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   633
  return NativeCall::instruction_size;  // call; delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
   634
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   635
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   636
489c9b5090e2 Initial load
duke
parents:
diff changeset
   637
// Indicate if the safepoint node needs the polling page as an input.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   638
// Since Sparc does not have absolute addressing, it does.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   639
bool SafePointNode::needs_polling_address_input() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   640
  return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   641
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   642
489c9b5090e2 Initial load
duke
parents:
diff changeset
   643
// emit an interrupt that is caught by the debugger (for debugging compiler)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   644
void emit_break(CodeBuffer &cbuf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   645
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
  __ breakpoint_trap();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  st->print("TA");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
  emit_break(cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
  return MachNode::size(ra_);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
// Traceable jump
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
  Register rdest = reg_to_register_object(jump_target);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   667
  __ JMP(rdest, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
  __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
// Traceable jump and set exception pc
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
  Register rdest = reg_to_register_object(jump_target);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  __ JMP(rdest, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
  __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
void emit_nop(CodeBuffer &cbuf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
  __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
void emit_illtrap(CodeBuffer &cbuf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
  __ illtrap(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
  assert(n->rule() != loadUB_rule, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
  intptr_t offset = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
  const Node* addr = n->get_base_and_disp(offset, adr_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
  assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
  assert(addr != NULL && addr != (Node*)-1, "invalid addr");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
  assert(addr->bottom_type()->isa_oopptr() == atype, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
  atype = atype->add_offset(offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   700
  assert(disp32 == offset, "wrong disp32");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   701
  return atype->_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
489c9b5090e2 Initial load
duke
parents:
diff changeset
   704
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   706
  assert(n->rule() != loadUB_rule, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   707
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
  intptr_t offset = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
  Node* addr = n->in(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
  assert(addr->bottom_type()->isa_oopptr() == atype, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
  if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
    Node* a = addr->in(2/*AddPNode::Address*/);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
    Node* o = addr->in(3/*AddPNode::Offset*/);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
    offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
    atype = a->bottom_type()->is_ptr()->add_offset(offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
    assert(atype->isa_oop_ptr(), "still an oop");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
  offset = atype->is_ptr()->_offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
  if (offset != Type::OffsetBot)  offset += disp32;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
  return offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   721
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   723
static inline jdouble replicate_immI(int con, int count, int width) {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   724
  // Load a constant replicated "count" times with width "width"
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   725
  assert(count*width == 8 && width <= 4, "sanity");
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   726
  int bit_width = width * 8;
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   727
  jlong val = con;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   728
  val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   729
  for (int i = 0; i < count - 1; i++) {
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   730
    val |= (val << bit_width);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   731
  }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   732
  jdouble dval = *((jdouble*) &val);  // coerce to double type
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   733
  return dval;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   734
}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
   735
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   736
static inline jdouble replicate_immF(float con) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   737
  // Replicate float con 2 times and pack into vector.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   738
  int val = *((int*)&con);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   739
  jlong lval = val;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   740
  lval = (lval << 32) | (lval & 0xFFFFFFFFl);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   741
  jdouble dval = *((jdouble*) &lval);  // coerce to double type
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   742
  return dval;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   743
}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   744
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
// Standard Sparc opcode form2 field breakdown
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
  f0 &= (1<<19)-1;     // Mask displacement to 19 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   748
  int op = (f30 << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   749
           (f29 << 29) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   750
           (f25 << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   751
           (f22 << 22) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   752
           (f20 << 20) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   753
           (f19 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   754
           (f0  <<  0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
   755
  cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   756
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   757
489c9b5090e2 Initial load
duke
parents:
diff changeset
   758
// Standard Sparc opcode form2 field breakdown
489c9b5090e2 Initial load
duke
parents:
diff changeset
   759
static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   760
  f0 >>= 10;           // Drop 10 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   761
  f0 &= (1<<22)-1;     // Mask displacement to 22 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   762
  int op = (f30 << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
           (f25 << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
           (f22 << 22) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
           (f0  <<  0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
   766
  cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
// Standard Sparc opcode form3 field breakdown
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
  int op = (f30 << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
           (f25 << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
           (f19 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
           (f14 << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
           (f5  <<  5) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
           (f0  <<  0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
   777
  cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   778
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   779
489c9b5090e2 Initial load
duke
parents:
diff changeset
   780
// Standard Sparc opcode form3 field breakdown
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
  simm13 &= (1<<13)-1; // Mask to 13 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
  int op = (f30 << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   784
           (f25 << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
           (f19 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
           (f14 << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
           (1   << 13) | // bit to indicate immediate-mode
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
           (simm13<<0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
   789
  cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
489c9b5090e2 Initial load
duke
parents:
diff changeset
   792
static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   793
  simm10 &= (1<<10)-1; // Mask to 10 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
  emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
// Helper function for VerifyOops in emit_form3_mem_reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
  warning("VerifyOops encountered unexpected instruction:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
  n->dump(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
  warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   807
void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
                        int src1_enc, int disp32, int src2_enc, int dst_enc) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   809
489c9b5090e2 Initial load
duke
parents:
diff changeset
   810
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   811
  // The following code implements the +VerifyOops feature.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   812
  // It verifies oop values which are loaded into or stored out of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
  // the current method activation.  +VerifyOops complements techniques
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
  // like ScavengeALot, because it eagerly inspects oops in transit,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
  // as they enter or leave the stack, as opposed to ScavengeALot,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
  // which inspects oops "at rest", in the stack or heap, at safepoints.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
  // For this reason, +VerifyOops can sometimes detect bugs very close
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
  // to their point of creation.  It can also serve as a cross-check
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
  // on the validity of oop maps, when used toegether with ScavengeALot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
  // It would be good to verify oops at other points, especially
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
  // when an oop is used as a base pointer for a load or store.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
  // This is presently difficult, because it is hard to know when
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
  // a base address is biased or not.  (If we had such information,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
  // it would be easy and useful to make a two-argument version of
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
  // verify_oop which unbiases the base, and performs verification.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   827
489c9b5090e2 Initial load
duke
parents:
diff changeset
   828
  assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   829
  bool is_verified_oop_base  = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   830
  bool is_verified_oop_load  = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   831
  bool is_verified_oop_store = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   832
  int tmp_enc = -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
  if (VerifyOops && src1_enc != R_SP_enc) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
    // classify the op, mainly for an assert check
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
    int st_op = 0, ld_op = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
    switch (primary) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
    case Assembler::stb_op3:  st_op = Op_StoreB; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
    case Assembler::sth_op3:  st_op = Op_StoreC; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
    case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
    case Assembler::stw_op3:  st_op = Op_StoreI; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
    case Assembler::std_op3:  st_op = Op_StoreL; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
    case Assembler::stf_op3:  st_op = Op_StoreF; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
    case Assembler::stdf_op3: st_op = Op_StoreD; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
    case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   846
    case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
2022
28ce8115a91d 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 2015
diff changeset
   847
    case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   848
    case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   849
    case Assembler::ldx_op3:  // may become LoadP or stay LoadI
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
    case Assembler::ldsw_op3: // may become LoadP or stay LoadI
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
    case Assembler::lduw_op3: ld_op = Op_LoadI; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
    case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
    case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
    case Assembler::lddf_op3: ld_op = Op_LoadD; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
    case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
    default: ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
    if (tertiary == REGP_OP) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
      if      (st_op == Op_StoreI)  st_op = Op_StoreP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   861
      else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
      else                          ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
      if (st_op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   864
        // a store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   865
        // inputs are (0:control, 1:memory, 2:address, 3:value)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   866
        Node* n2 = n->in(3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   867
        if (n2 != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   868
          const Type* t = n2->bottom_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   869
          is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
        // a load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
        const Type* t = n->bottom_type();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
        is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
    if (ld_op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
      // a Load
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
      // inputs are (0:control, 1:memory, 2:address)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
      if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
          !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
          !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   884
          !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   885
          !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   886
          !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   887
          !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   888
          !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
          !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
          !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
          !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
          !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   893
          !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
10507
4b1c5c1cf1b8 7085137: -XX:+VerifyOops is broken
kvn
parents: 10501
diff changeset
   894
          !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   895
          !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   896
          !(n->rule() == loadUB_rule)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
        verify_oops_warning(n, n->ideal_Opcode(), ld_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
    } else if (st_op) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
      // a Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
      // inputs are (0:control, 1:memory, 2:address, 3:value)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
      if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
          !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   904
          !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
          !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
          !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
   907
          !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
          !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
        verify_oops_warning(n, n->ideal_Opcode(), st_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   910
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   911
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   912
489c9b5090e2 Initial load
duke
parents:
diff changeset
   913
    if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   914
      Node* addr = n->in(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   915
      if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   916
        const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
        if (atype != NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
          intptr_t offset = get_offset_from_base(n, atype, disp32);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
          intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
          if (offset != offset_2) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
            get_offset_from_base(n, atype, disp32);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
            get_offset_from_base_2(n, atype, disp32);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
          assert(offset == offset_2, "different offsets");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
          if (offset == disp32) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
            // we now know that src1 is a true oop pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
            is_verified_oop_base = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
            if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
              if( primary == Assembler::ldd_op3 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
                is_verified_oop_base = false; // Cannot 'ldd' into O7
489c9b5090e2 Initial load
duke
parents:
diff changeset
   931
              } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   932
                tmp_enc = dst_enc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   933
                dst_enc = R_O7_enc; // Load into O7; preserve source oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   934
                assert(src1_enc != dst_enc, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   935
              }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
            }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
          if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
                       || offset == oopDesc::mark_offset_in_bytes())) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   940
                      // loading the mark should not be allowed either, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
   941
                      // we don't check this since it conflicts with InlineObjectHash
489c9b5090e2 Initial load
duke
parents:
diff changeset
   942
                      // usage of LoadINode to get the mark. We could keep the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   943
                      // check if we create a new LoadMarkNode
489c9b5090e2 Initial load
duke
parents:
diff changeset
   944
            // but do not verify the object before its header is initialized
489c9b5090e2 Initial load
duke
parents:
diff changeset
   945
            ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   946
          }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   947
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   948
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
  uint instr;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
  instr = (Assembler::ldst_op << 30)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
        | (dst_enc        << 25)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
        | (primary        << 19)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
        | (src1_enc       << 14);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
489c9b5090e2 Initial load
duke
parents:
diff changeset
   959
  uint index = src2_enc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   960
  int disp = disp32;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   961
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   962
  if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   963
    disp += STACK_BIAS;
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   964
    // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   965
    if (!Assembler::is_simm13(disp)) {
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   966
      ra->C->record_method_not_compilable("unable to handle large constant offsets");
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   967
      return;
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   968
    }
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
   969
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
489c9b5090e2 Initial load
duke
parents:
diff changeset
   971
  // We should have a compiler bailout here rather than a guarantee.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
  // Better yet would be some mechanism to handle variable-size matches correctly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
  guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
  if( disp == 0 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
    // use reg-reg form
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
    // bit 13 is already zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
    instr |= index;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
    // use reg-imm form
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
    instr |= 0x00002000;          // set bit 13 to one
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
    instr |= disp & 0x1FFF;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   984
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
   985
  cbuf.insts()->emit_int32(instr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   986
489c9b5090e2 Initial load
duke
parents:
diff changeset
   987
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   988
  {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   989
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   990
    if (is_verified_oop_base) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   991
      __ verify_oop(reg_to_register_object(src1_enc));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   992
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   993
    if (is_verified_oop_store) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   994
      __ verify_oop(reg_to_register_object(dst_enc));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   995
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
    if (tmp_enc != -1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
      __ mov(O7, reg_to_register_object(tmp_enc));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
    if (is_verified_oop_load) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
      __ verify_oop(reg_to_register_object(dst_enc));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1003
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
7892
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
  1006
void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1007
  // The method which records debug information at every safepoint
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
  // expects the call to be the first instruction in the snippet as
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1009
  // it creates a PcDesc structure which tracks the offset of a call
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1010
  // from the start of the codeBlob. This offset is computed as
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
  // code_end() - code_begin() of the code which has been emitted
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1012
  // so far.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1013
  // In this particular case we have skirted around the problem by
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1014
  // putting the "mov" instruction in the delay slot but the problem
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1015
  // may bite us again at some other point and a cleaner/generic
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1016
  // solution using relocations would be needed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1017
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1018
  __ set_inst_mark();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1019
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1020
  // We flush the current window just so that there is a valid stack copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1021
  // the fact that the current window becomes active again instantly is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1022
  // not a problem there is nothing live in it.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1024
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
  int startpos = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
#endif /* ASSERT */
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1027
7892
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
  1028
  __ call((address)entry_point, rtype);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1030
  if (preserve_g2)   __ delayed()->mov(G2, L7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1031
  else __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1032
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1033
  if (preserve_g2)   __ mov(L7, G2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1034
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
  if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1037
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1038
    // Trash argument dump slots.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1039
    __ set(0xb0b8ac0db0b8ac0d, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1040
    __ mov(G1, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1041
    __ stx(G1, SP, STACK_BIAS + 0x80);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1042
    __ stx(G1, SP, STACK_BIAS + 0x88);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
    __ stx(G1, SP, STACK_BIAS + 0x90);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
    __ stx(G1, SP, STACK_BIAS + 0x98);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
    __ stx(G1, SP, STACK_BIAS + 0xA0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
    __ stx(G1, SP, STACK_BIAS + 0xA8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1047
#else // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1048
    // this is also a native call, so smash the first 7 stack locations,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1049
    // and the various registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1050
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1051
    // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1052
    // while [SP+0x44..0x58] are the argument dump slots.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1053
    __ set((intptr_t)0xbaadf00d, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
    __ mov(G1, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
    __ sllx(G1, 32, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
    __ or3(G1, G5, G1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1057
    __ mov(G1, G5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1058
    __ stx(G1, SP, 0x40);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1059
    __ stx(G1, SP, 0x48);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1060
    __ stx(G1, SP, 0x50);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1061
    __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1062
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
#endif /*ASSERT*/
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1065
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1068
// REQUIRED FUNCTIONALITY for encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
void emit_lo(CodeBuffer &cbuf, int val) {  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1070
void emit_hi(CodeBuffer &cbuf, int val) {  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1073
//=============================================================================
11197
158eecd6b330 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 11190
diff changeset
  1074
const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1075
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1076
int Compile::ConstantTable::calculate_table_base_offset() const {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1077
  if (UseRDPCForConstantTableBase) {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1078
    // The table base offset might be less but then it fits into
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1079
    // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1080
    return Assembler::min_simm13();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1081
  } else {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1082
    int offset = -(size() / 2);
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1083
    if (!Assembler::is_simm13(offset)) {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1084
      offset = Assembler::min_simm13();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1085
    }
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1086
    return offset;
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1087
  }
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1088
}
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1089
22844
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1090
bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1091
void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1092
  ShouldNotReachHere();
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1093
}
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1094
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1095
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1096
  Compile* C = ra_->C;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1097
  Compile::ConstantTable& constant_table = C->constant_table();
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1098
  MacroAssembler _masm(&cbuf);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1099
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1100
  Register r = as_Register(ra_->get_encode(this));
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1101
  CodeSection* consts_section = __ code()->consts();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1102
  int consts_size = consts_section->align_at_start(consts_section->size());
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1103
  assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1104
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1105
  if (UseRDPCForConstantTableBase) {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1106
    // For the following RDPC logic to work correctly the consts
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1107
    // section must be allocated right before the insts section.  This
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1108
    // assert checks for that.  The layout and the SECT_* constants
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1109
    // are defined in src/share/vm/asm/codeBuffer.hpp.
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1110
    assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1111
    int insts_offset = __ offset();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1112
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1113
    // Layout:
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1114
    //
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1115
    // |----------- consts section ------------|----------- insts section -----------...
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1116
    // |------ constant table -----|- padding -|------------------x----
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1117
    //                                                            \ current PC (RDPC instruction)
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1118
    // |<------------- consts_size ----------->|<- insts_offset ->|
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1119
    //                                                            \ table base
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1120
    // The table base offset is later added to the load displacement
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1121
    // so it has to be negative.
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1122
    int table_base_offset = -(consts_size + insts_offset);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1123
    int disp;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1124
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1125
    // If the displacement from the current PC to the constant table
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1126
    // base fits into simm13 we set the constant table base to the
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1127
    // current PC.
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1128
    if (Assembler::is_simm13(table_base_offset)) {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1129
      constant_table.set_table_base_offset(table_base_offset);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1130
      disp = 0;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1131
    } else {
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1132
      // Otherwise we set the constant table base offset to the
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1133
      // maximum negative displacement of load instructions to keep
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1134
      // the disp as small as possible:
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1135
      //
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1136
      // |<------------- consts_size ----------->|<- insts_offset ->|
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1137
      // |<--------- min_simm13 --------->|<-------- disp --------->|
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1138
      //                                  \ table base
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1139
      table_base_offset = Assembler::min_simm13();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1140
      constant_table.set_table_base_offset(table_base_offset);
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1141
      disp = (consts_size + insts_offset) + table_base_offset;
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1142
    }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1143
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1144
    __ rdpc(r);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1145
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1146
    if (disp != 0) {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1147
      assert(r != O7, "need temporary");
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1148
      __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1149
    }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1150
  }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1151
  else {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1152
    // Materialize the constant table base.
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1153
    address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1154
    RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1155
    AddressLiteral base(baseaddr, rspec);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1156
    __ set(base, r);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1157
  }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1158
}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1159
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1160
uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1161
  if (UseRDPCForConstantTableBase) {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1162
    // This is really the worst case but generally it's only 1 instruction.
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  1163
    return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1164
  } else {
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  1165
    return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1166
  }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1167
}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1168
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1169
#ifndef PRODUCT
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1170
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1171
  char reg[128];
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1172
  ra_->dump_register(this, reg);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1173
  if (UseRDPCForConstantTableBase) {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1174
    st->print("RDPC   %s\t! constant table base", reg);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1175
  } else {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1176
    st->print("SET    &constanttable,%s\t! constant table base", reg);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1177
  }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1178
}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1179
#endif
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1180
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1181
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  1182
//=============================================================================
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
  Compile* C = ra_->C;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1188
  for (int i = 0; i < OptoPrologueNops; i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1189
    st->print_cr("NOP"); st->print("\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
  if( VerifyThread ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
    st->print_cr("Verify_Thread"); st->print("\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1196
  size_t framesize = C->frame_size_in_bytes();
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1197
  int bangsize = C->bang_size_in_bytes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
  // Calls to C2R adapters often do not accept exceptional returns.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
  // We require that their callers must bang for them.  But be careful, because
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1201
  // some VM calls (such as call site linkage) can use several kilobytes of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
  // stack.  But the stack safety zone should account for that.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
  // See bugs 4446381, 4468289, 4497237.
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1204
  if (C->need_stack_bang(bangsize)) {
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1205
    st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1206
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1207
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1208
  if (Assembler::is_simm13(-framesize)) {
24932
374cc5d929fb 8044735: Print format/argument warnings
mikael
parents: 24018
diff changeset
  1209
    st->print   ("SAVE   R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1210
  } else {
24932
374cc5d929fb 8044735: Print format/argument warnings
mikael
parents: 24018
diff changeset
  1211
    st->print_cr("SETHI  R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
374cc5d929fb 8044735: Print format/argument warnings
mikael
parents: 24018
diff changeset
  1212
    st->print_cr("ADD    R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1213
    st->print   ("SAVE   R_SP,R_G3,R_SP");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1214
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1215
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1216
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1217
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1218
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1219
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1220
  Compile* C = ra_->C;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1221
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1222
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1223
  for (int i = 0; i < OptoPrologueNops; i++) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1224
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1225
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1226
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1227
  __ verify_thread();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1228
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1229
  size_t framesize = C->frame_size_in_bytes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1230
  assert(framesize >= 16*wordSize, "must have room for reg. save area");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1231
  assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1232
  int bangsize = C->bang_size_in_bytes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1233
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1234
  // Calls to C2R adapters often do not accept exceptional returns.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1235
  // We require that their callers must bang for them.  But be careful, because
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
  // some VM calls (such as call site linkage) can use several kilobytes of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1237
  // stack.  But the stack safety zone should account for that.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1238
  // See bugs 4446381, 4468289, 4497237.
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1239
  if (C->need_stack_bang(bangsize)) {
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  1240
    __ generate_stack_overflow_check(bangsize);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
  if (Assembler::is_simm13(-framesize)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
    __ save(SP, -framesize, SP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
    __ sethi(-framesize & ~0x3ff, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
    __ add(G3, -framesize & 0x3ff, G3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
    __ save(SP, G3, SP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
  C->set_frame_complete( __ offset() );
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1251
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1252
  if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1253
    // NOTE: We set the table base offset here because users might be
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1254
    // emitted before MachConstantBaseNode.
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1255
    Compile::ConstantTable& constant_table = C->constant_table();
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1256
    constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1257
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1260
uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
  return MachNode::size(ra_);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1262
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1263
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1264
int MachPrologNode::reloc() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1265
  return 10; // a large enough number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1266
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1267
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1268
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1269
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1270
void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1271
  Compile* C = ra_->C;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1272
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1273
  if(do_polling() && ra_->C->is_method_compilation()) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
    st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1276
    st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1278
    st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1279
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1280
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1281
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1282
  if(do_polling()) {
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1283
    if (UseCBCond && !ra_->C->is_method_compilation()) {
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1284
      st->print("NOP\n\t");
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1285
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1286
    st->print("RET\n\t");
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1287
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1288
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1289
  st->print("RESTORE");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1290
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1291
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1292
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1295
  Compile* C = ra_->C;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1297
  __ verify_thread();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1299
  // If this does safepoint polling, then do it here
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1300
  if(do_polling() && ra_->C->is_method_compilation()) {
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  1301
    AddressLiteral polling_page(os::get_polling_page());
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  1302
    __ sethi(polling_page, L0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1303
    __ relocate(relocInfo::poll_return_type);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1304
    __ ld_ptr(L0, 0, G0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1306
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
  // If this is a return, then stuff the restore in the delay slot
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1308
  if(do_polling()) {
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1309
    if (UseCBCond && !ra_->C->is_method_compilation()) {
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1310
      // Insert extra padding for the case when the epilogue is preceded by
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1311
      // a cbcond jump, which can't be followed by a CTI instruction
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1312
      __ nop();
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  1313
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1314
    __ ret();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
    __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1317
    __ restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1319
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1322
  return MachNode::size(ra_);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1323
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1324
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1325
int MachEpilogNode::reloc() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1326
  return 16; // a large enough number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1327
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1328
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1329
const Pipeline * MachEpilogNode::pipeline() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1330
  return MachNode::pipeline_class();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1331
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1332
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1333
int MachEpilogNode::safepoint_offset() const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1334
  assert( do_polling(), "no return for this epilog node");
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  1335
  return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1336
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1337
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1338
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1339
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1340
// Figure out which register class each belongs in: rc_int, rc_float, rc_stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1341
enum RC { rc_bad, rc_int, rc_float, rc_stack };
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1342
static enum RC rc_class( OptoReg::Name reg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1343
  if( !OptoReg::is_valid(reg)  ) return rc_bad;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1344
  if (OptoReg::is_stack(reg)) return rc_stack;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1345
  VMReg r = OptoReg::as_VMReg(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1346
  if (r->is_Register()) return rc_int;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1347
  assert(r->is_FloatRegister(), "must be");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1348
  return rc_float;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1349
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1350
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1351
static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1352
  if (cbuf) {
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1353
    emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1354
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1355
#ifndef PRODUCT
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1356
  else if (!do_size) {
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1357
    if (size != 0) st->print("\n\t");
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1358
    if (is_load) st->print("%s   [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  1359
    else         st->print("%s   R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1360
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1361
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1362
  return size+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1363
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1364
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1365
static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1366
  if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1367
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1368
  else if( !do_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1369
    if( size != 0 ) st->print("\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1370
    st->print("%s  R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1371
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1372
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1373
  return size+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1374
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1375
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1376
uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1377
                                        PhaseRegAlloc *ra_,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1378
                                        bool do_size,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1379
                                        outputStream* st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1380
  // Get registers to move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1381
  OptoReg::Name src_second = ra_->get_reg_second(in(1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1382
  OptoReg::Name src_first = ra_->get_reg_first(in(1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1383
  OptoReg::Name dst_second = ra_->get_reg_second(this );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1384
  OptoReg::Name dst_first = ra_->get_reg_first(this );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1385
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1386
  enum RC src_second_rc = rc_class(src_second);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1387
  enum RC src_first_rc = rc_class(src_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
  enum RC dst_second_rc = rc_class(dst_second);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
  enum RC dst_first_rc = rc_class(dst_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
  assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
  // Generate spill code!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
  int size = 0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
  if( src_first == dst_first && src_second == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
    return size;            // Self copy, no move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1398
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
  // --------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
  // Check for mem-mem move.  Load into unused float registers and fall into
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1401
  // the float-store case.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
  if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1403
    int offset = ra_->reg2offset(src_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
    // Further check for aligned-adjacent pair, so we can use a double load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
    if( (src_first&1)==0 && src_first+1 == src_second ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1406
      src_second    = OptoReg::Name(R_F31_num);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1407
      src_second_rc = rc_float;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1408
      size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1409
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1410
      size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1411
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1412
    src_first    = OptoReg::Name(R_F30_num);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1413
    src_first_rc = rc_float;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1414
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1415
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1416
  if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1417
    int offset = ra_->reg2offset(src_second);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1418
    size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1419
    src_second    = OptoReg::Name(R_F31_num);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1420
    src_second_rc = rc_float;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1421
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1422
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1423
  // --------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1424
  // Check for float->int copy; requires a trip through memory
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1425
  if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1426
    int offset = frame::register_save_words*wordSize;
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1427
    if (cbuf) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1428
      emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1429
      impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1430
      impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1431
      emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1432
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1433
#ifndef PRODUCT
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1434
    else if (!do_size) {
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1435
      if (size != 0) st->print("\n\t");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1436
      st->print(  "SUB    R_SP,16,R_SP\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1437
      impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1438
      impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1439
      st->print("\tADD    R_SP,16,R_SP\n");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1440
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1441
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1442
    size += 16;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1443
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1444
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1445
  // Check for float->int copy on T4
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1446
  if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1447
    // Further check for aligned-adjacent pair, so we can use a double move
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1448
    if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1449
      return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1450
    size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1451
  }
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1452
  // Check for int->float copy on T4
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1453
  if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1454
    // Further check for aligned-adjacent pair, so we can use a double move
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1455
    if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1456
      return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1457
    size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1458
  }
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  1459
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1460
  // --------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1461
  // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1462
  // In such cases, I have to do the big-endian swap.  For aligned targets, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1463
  // hardware does the flop for me.  Doubles are always aligned, so no problem
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1464
  // there.  Misaligned sources only come from native-long-returns (handled
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1465
  // special below).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1466
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1467
  if( src_first_rc == rc_int &&     // source is already big-endian
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1468
      src_second_rc != rc_bad &&    // 64-bit move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1469
      ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1470
    assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1471
    // Do the big-endian flop.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1472
    OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
    enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1474
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1475
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1476
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
  // --------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
  // Check for integer reg-reg copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
  if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
    if( src_first == R_O0_num && src_second == R_O1_num ) {  // Check for the evil O0/O1 native long-return case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
      // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
      //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
      //       operand contains the least significant word of the 64-bit value and vice versa.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
      OptoReg::Name tmp = OptoReg::Name(R_O7_num);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
      assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
      // Shift O0 left in-place, zero-extend O1, then OR them into the dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
      if( cbuf ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
        emit3       ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
      } else if( !do_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
        if( size != 0 ) st->print("\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
        st->print("SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1496
        st->print("SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
        st->print("OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
      return size+12;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1501
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
    else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
      // returning a long value in I0/I1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
      // a SpillCopy must be able to target a return instruction's reg_class
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
      // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
      //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
      //       operand contains the least significant word of the 64-bit value and vice versa.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
      OptoReg::Name tdest = dst_first;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
      if (src_first == dst_first) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
        tdest = OptoReg::Name(R_O7_num);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
        size += 4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
      if( cbuf ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1516
        assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1517
        // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1518
        // ShrL_reg_imm6
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1519
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1520
        // ShrR_reg_imm6  src, 0, dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
        if (tdest != dst_first) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1523
          emit3     ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1525
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1526
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1527
      else if( !do_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
        if( size != 0 ) st->print("\n\t");  // %%%%% !!!!!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
        st->print("SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1530
        st->print("SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1531
        if (tdest != dst_first) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1532
          st->print("MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1533
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1534
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
#endif // PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
      return size+8;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
#endif // !_LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1539
    // Else normal reg-reg copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
    assert( src_second != dst_first, "smashed second before evacuating it" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1541
    size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV  ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1542
    assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1543
    // This moves an aligned adjacent pair.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1544
    // See if we are done.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
    if( src_first+1 == src_second && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
      return size;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1549
  // Check for integer store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1550
  if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
    int offset = ra_->reg2offset(dst_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
    // Further check for aligned-adjacent pair, so we can use a double store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1554
      return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
    size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
  // Check for integer load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1559
  if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1560
    int offset = ra_->reg2offset(src_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
    // Further check for aligned-adjacent pair, so we can use a double load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
      return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1564
    size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1566
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1567
  // Check for float reg-reg copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
  if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
    // Further check for aligned-adjacent pair, so we can use a double move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1570
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1571
      return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1572
    size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1573
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
  // Check for float store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
  if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1577
    int offset = ra_->reg2offset(dst_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1578
    // Further check for aligned-adjacent pair, so we can use a double store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
      return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
    size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1583
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1584
  // Check for float load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1585
  if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1586
    int offset = ra_->reg2offset(src_first);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1587
    // Further check for aligned-adjacent pair, so we can use a double load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1588
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
      return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1590
    size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1591
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1592
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1593
  // --------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1594
  // Check for hi bits still needing moving.  Only happens for misaligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
  // arguments to native calls.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
  if( src_second == dst_second )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
    return size;               // Self copy; no move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
  assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1599
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1600
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1601
  // In the LP64 build, all registers can be moved as aligned/adjacent
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
  1602
  // pairs, so there's never any need to move the high bits separately.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
  // The 32-bit builds have to deal with the 32-bit ABI which can force
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
  // all sorts of silly alignment problems.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1605
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
  // Check for integer reg-reg copy.  Hi bits are stuck up in the top
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
  // 32-bits of a 64-bit register, but are needed in low bits of another
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
  // register (else it's a hi-bits-to-hi-bits copy which should have
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
  // happened already as part of a 64-bit move)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
  if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
    assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
    assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
    // Shift src_second down to dst_second's low bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1614
    if( cbuf ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1615
      emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1616
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1617
    } else if( !do_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1618
      if( size != 0 ) st->print("\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1619
      st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1620
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1621
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
    return size+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1623
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1624
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
  // Check for high word integer store.  Must down-shift the hi bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1626
  // into a temp register, then fall into the case of storing int bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1627
  if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
    // Shift src_second down to dst_second's low bits.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
    if( cbuf ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
      emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1632
    } else if( !do_size ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
      if( size != 0 ) st->print("\n\t");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
      st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1636
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
    size+=4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1638
    src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1639
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1640
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
  // Check for high word integer load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
  if( dst_second_rc == rc_int && src_second_rc == rc_stack )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1643
    return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1644
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1645
  // Check for high word integer store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1646
  if( src_second_rc == rc_int && dst_second_rc == rc_stack )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1647
    return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1648
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1649
  // Check for high word float store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1650
  if( src_second_rc == rc_float && dst_second_rc == rc_stack )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1651
    return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1653
#endif // !_LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1654
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1655
  Unimplemented();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1657
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
  implementation( NULL, ra_, false, st );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1661
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1662
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1663
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1665
  implementation( &cbuf, ra_, false, NULL );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1666
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1667
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1668
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1669
  return implementation( NULL, ra_, true, NULL );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1670
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1671
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1672
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1673
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1674
void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1675
  st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1676
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1677
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1678
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1679
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1680
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1681
  for(int i = 0; i < _count; i += 1) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1682
    __ nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1683
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1684
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1685
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1686
uint MachNopNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1687
  return 4 * _count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1688
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1689
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1690
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1691
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1692
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1693
void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1694
  int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1695
  int reg = ra_->get_reg_first(this);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1696
  st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1697
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1699
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1700
void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1701
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1702
  int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
  int reg = ra_->get_encode(this);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1704
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
  if (Assembler::is_simm13(offset)) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
     __ add(SP, offset, reg_to_register_object(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1707
  } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1708
     __ set(offset, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
     __ add(SP, O7, reg_to_register_object(reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
  // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
  assert(ra_ == ra_->C->regalloc(), "sanity");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1716
  return ra_->C->scratch_emit_size(this);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1717
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1718
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1719
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1720
#ifndef PRODUCT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1721
void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1722
  st->print_cr("\nUEP:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
#ifdef    _LP64
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 19319
diff changeset
  1724
  if (UseCompressedClassPointers) {
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2150
diff changeset
  1725
    assert(Universe::heap() != NULL, "java heap should be initialized");
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  1726
    st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
21188
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1727
    if (Universe::narrow_klass_base() != 0) {
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1728
      st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1729
      if (Universe::narrow_klass_shift() != 0) {
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1730
        st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1731
      }
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1732
      st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1733
      st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1734
    } else {
d053e4e8f901 8024927: Nashorn performance regression with CompressedOops
coleenp
parents: 20289
diff changeset
  1735
      st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
19319
0ad35be0733a 8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents: 18097
diff changeset
  1736
    }
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  1737
  } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  1738
    st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  1739
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1740
  st->print_cr("\tCMP    R_G5,R_G3" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1741
  st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1742
#else  // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1743
  st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1744
  st->print_cr("\tCMP    R_G5,R_G3" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1745
  st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1746
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1747
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1748
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1749
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1750
void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1751
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1752
  Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1753
  Register temp_reg   = G3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1754
  assert( G5_ic_reg != temp_reg, "conflicting registers" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1755
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
  1756
  // Load klass from receiver
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  1757
  __ load_klass(O0, temp_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1758
  // Compare against expected klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1759
  __ cmp(temp_reg, G5_ic_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1760
  // Branch to miss code, checks xcc or icc depending
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1761
  __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1762
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1763
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1764
uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1765
  return MachNode::size(ra_);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1766
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1768
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
//=============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1771
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1772
// Emit exception handler code.
23498
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
  1773
int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1774
  Register temp_reg = G3;
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  1775
  AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
  address base =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1779
  __ start_a_stub(size_exception_handler());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1780
  if (base == NULL)  return 0;  // CodeBuffer::expand failed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1781
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1782
  int offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1783
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  1784
  __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1785
  __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1786
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1787
  assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1788
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1789
  __ end_a_stub();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1790
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1791
  return offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1792
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1793
23498
a0e67b766e5c 8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents: 22911
diff changeset
  1794
int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1795
  // Can't use any of the current frame's registers as we may have deopted
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1796
  // at a poll and everything (including G3) can be live.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1797
  Register temp_reg = L0;
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  1798
  AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1799
  MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
  address base =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
  __ start_a_stub(size_deopt_handler());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
  if (base == NULL)  return 0;  // CodeBuffer::expand failed
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
  int offset = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
  __ save_frame(0);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  1807
  __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
  __ delayed()->restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
  assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
  __ end_a_stub();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
  return offset;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1815
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
// Given a register encoding, produce a Integer Register object
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1818
static Register reg_to_register_object(int register_encoding) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
  assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1820
  return as_Register(register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1821
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
// Given a register encoding, produce a single-precision Float Register object
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
  assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
  return as_SingleFloatRegister(register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
// Given a register encoding, produce a double-precision Float Register object
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1831
  assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1832
  assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1833
  return as_DoubleFloatRegister(register_encoding);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1834
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1835
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1836
const bool Matcher::match_rule_supported(int opcode) {
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1837
  if (!has_match_rule(opcode))
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1838
    return false;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1839
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1840
  switch (opcode) {
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1841
  case Op_CountLeadingZerosI:
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1842
  case Op_CountLeadingZerosL:
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1843
  case Op_CountTrailingZerosI:
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1844
  case Op_CountTrailingZerosL:
12113
71f302d5c8ee 7152957: VM crashes with assert(false) failed: bad AD file
never
parents: 11445
diff changeset
  1845
  case Op_PopCountI:
71f302d5c8ee 7152957: VM crashes with assert(false) failed: bad AD file
never
parents: 11445
diff changeset
  1846
  case Op_PopCountL:
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1847
    if (!UsePopCountInstruction)
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1848
      return false;
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1849
  case Op_CompareAndSwapL:
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1850
#ifdef _LP64
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1851
  case Op_CompareAndSwapP:
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1852
#endif
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1853
    if (!VM_Version::supports_cx8())
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  1854
      return false;
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1855
    break;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1856
  }
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1857
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1858
  return true;  // Per default match rules are supported.
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1859
}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
  1860
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
int Matcher::regnum_to_fpu_offset(int regnum) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
  return regnum - 32; // The FP registers are in the second chunk
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1864
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1865
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1866
address last_rethrow = NULL;  // debugging aid for Rethrow encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1869
// Vector width in bytes
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1870
const int Matcher::vector_width_in_bytes(BasicType bt) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1871
  assert(MaxVectorSize == 8, "");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
  return 8;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1875
// Vector ideal reg
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1876
const int Matcher::vector_ideal_reg(int size) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1877
  assert(MaxVectorSize == 8, "");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
  return Op_RegD;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1879
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1880
13930
8df570f94294 7201026: add vector for shift count
kvn
parents: 13886
diff changeset
  1881
const int Matcher::vector_shift_count_ideal_reg(int size) {
8df570f94294 7201026: add vector for shift count
kvn
parents: 13886
diff changeset
  1882
  fatal("vector shift is not supported");
8df570f94294 7201026: add vector for shift count
kvn
parents: 13886
diff changeset
  1883
  return Node::NotAMachineReg;
8df570f94294 7201026: add vector for shift count
kvn
parents: 13886
diff changeset
  1884
}
8df570f94294 7201026: add vector for shift count
kvn
parents: 13886
diff changeset
  1885
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1886
// Limits on vector size (number of elements) loaded into vector.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1887
const int Matcher::max_vector_size(const BasicType bt) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1888
  assert(is_java_primitive(bt), "only primitive type vectors");
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1889
  return vector_width_in_bytes(bt)/type2aelembytes(bt);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1890
}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1891
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1892
const int Matcher::min_vector_size(const BasicType bt) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1893
  return max_vector_size(bt); // Same as max.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1894
}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1895
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1896
// SPARC doesn't support misaligned vectors store/load.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1897
const bool Matcher::misaligned_vectors_ok() {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1898
  return false;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1899
}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
  1900
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1901
// Current (2013) SPARC platforms need to read original key
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1902
// to construct decryption expanded key 
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1903
const bool Matcher::pass_original_key_for_aes() {
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1904
  return true;
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1905
}
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 22228
diff changeset
  1906
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1907
// USII supports fxtof through the whole range of number, USIII doesn't
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1908
const bool Matcher::convL2FSupported(void) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
  return VM_Version::has_fast_fxtof();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
// Is this branch offset short enough that a short branch can be used?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1913
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1914
// NOTE: If the platform does not provide any short branch variants, then
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1915
//       this method should return false for offset 0.
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  1916
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  1917
  // The passed offset is relative to address of the branch.
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  1918
  // Don't need to adjust the offset.
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  1919
  return UseCBCond && Assembler::is_simm12(offset);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1920
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1921
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1922
const bool Matcher::isSimpleConstant64(jlong value) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1923
  // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1924
  // Depends on optimizations in MacroAssembler::setx.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1925
  int hi = (int)(value >> 32);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1926
  int lo = (int)(value & ~0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1927
  return (hi == 0) || (hi == -1) || (lo == 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1928
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1929
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1930
// No scaling for the parameter the ClearArray node.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1931
const bool Matcher::init_array_count_is_in_bytes = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1932
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1933
// Threshold size for cleararray.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1934
const int Matcher::init_array_short_size = 8 * BytesPerLong;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1935
10971
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1936
// No additional cost for CMOVL.
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1937
const int Matcher::long_cmove_cost() { return 0; }
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1938
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1939
// CMOVF/CMOVD are expensive on T4 and on SPARC64.
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1940
const int Matcher::float_cmove_cost() {
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1941
  return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1942
}
db45f6ab9a75 7097546: Optimize use of CMOVE instructions
kvn
parents: 10736
diff changeset
  1943
22844
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1944
// Does the CPU require late expand (see block.cpp for description of late expand)?
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1945
const bool Matcher::require_postalloc_expand = false;
90f76a40ed8a 8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents: 22838
diff changeset
  1946
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1947
// Should the Matcher clone shifts on addressing modes, expecting them to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1948
// be subsumed into complex addressing expressions or compute them into
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1949
// registers?  True for Intel but false for most RISCs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
const bool Matcher::clone_shift_expressions = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1951
8868
1bae515b806b 7029017: Additional architecture support for c2 compiler
roland
parents: 8324
diff changeset
  1952
// Do we need to mask the count passed to shift instructions or does
1bae515b806b 7029017: Additional architecture support for c2 compiler
roland
parents: 8324
diff changeset
  1953
// the cpu only look at the lower 5/6 bits anyway?
1bae515b806b 7029017: Additional architecture support for c2 compiler
roland
parents: 8324
diff changeset
  1954
const bool Matcher::need_masked_shift_count = false;
1bae515b806b 7029017: Additional architecture support for c2 compiler
roland
parents: 8324
diff changeset
  1955
5698
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1956
bool Matcher::narrow_oop_use_complex_address() {
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1957
  NOT_LP64(ShouldNotCallThis());
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1958
  assert(UseCompressedOops, "only for compressed oops code");
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1959
  return false;
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1960
}
091095915ee6 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 5694
diff changeset
  1961
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  1962
bool Matcher::narrow_klass_use_complex_address() {
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  1963
  NOT_LP64(ShouldNotCallThis());
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 19319
diff changeset
  1964
  assert(UseCompressedClassPointers, "only for compressed klass code");
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  1965
  return false;
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  1966
}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  1967
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1968
// Is it better to copy float constants, or load them directly from memory?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1969
// Intel can load a float constant from a direct address, requiring no
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1970
// extra registers.  Most RISCs will have to materialize an address into a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1971
// register first, so they would do better to copy the constant from stack.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1972
const bool Matcher::rematerialize_float_constants = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1973
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
// If CPU can load and store mis-aligned doubles directly then no fixup is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
// needed.  Else we split the double into 2 integer pieces and move it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1976
// piece-by-piece.  Only happens when passing doubles into C code as the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1977
// Java calling convention forces doubles to be aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1979
const bool Matcher::misaligned_doubles_ok = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1981
const bool Matcher::misaligned_doubles_ok = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1983
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1984
// No-op on SPARC.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1985
void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1986
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1987
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1988
// Advertise here if the CPU requires explicit rounding operations
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
// to implement the UseStrictFP mode.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1990
const bool Matcher::strict_fp_requires_explicit_rounding = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
26804
4b23f22faae6 8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents: 25933
diff changeset
  1992
// Are floats converted to double when stored to stack during deoptimization?
5025
05adc9b8f96a 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 4589
diff changeset
  1993
// Sparc does not handle callee-save floats.
05adc9b8f96a 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 4589
diff changeset
  1994
bool Matcher::float_in_double() { return false; }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
// Do ints take an entire long register or just half?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
// Note that we if-def off of _LP64.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1998
// The relevant question is how the int is callee-saved.  In _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1999
// the whole long is written but de-opt'ing will have to extract
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2000
// the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2002
const bool Matcher::int_in_long = true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
const bool Matcher::int_in_long = false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2005
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
// Return whether or not this register is ever used as an argument.  This
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
// function is used on startup to build the trampoline stubs in generateOptoStub.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
// Registers not mentioned will be killed by the VM call in the trampoline, and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
// arguments in those registers not be available to the callee.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
bool Matcher::can_be_java_arg( int reg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
  // Standard sparc 6 args in registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2013
  if( reg == R_I0_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2014
      reg == R_I1_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2015
      reg == R_I2_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2016
      reg == R_I3_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2017
      reg == R_I4_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2018
      reg == R_I5_num ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2019
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2020
  // 64-bit builds can pass 64-bit pointers and longs in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2021
  // the high I registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2022
  if( reg == R_I0H_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2023
      reg == R_I1H_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2024
      reg == R_I2H_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2025
      reg == R_I3H_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2026
      reg == R_I4H_num ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2027
      reg == R_I5H_num ) return true;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2028
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2029
  if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2030
    return true;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2031
  }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2032
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2033
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2034
  // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2035
  // Longs cannot be passed in O regs, because O regs become I regs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2036
  // after a 'save' and I regs get their high bits chopped off on
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
  // interrupt.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2038
  if( reg == R_G1H_num || reg == R_G1_num ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2039
  if( reg == R_G4H_num || reg == R_G4_num ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
  // A few float args in registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2042
  if( reg >= R_F0_num && reg <= R_F7_num ) return true;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2043
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2044
  return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2045
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2046
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2047
bool Matcher::is_spillable_arg( int reg ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2048
  return can_be_java_arg(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2050
7115
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2051
bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2052
  // Use hardware SDIVX instruction when it is
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2053
  // faster than a code which use multiply.
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2054
  return VM_Version::has_fast_idiv();
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2055
}
32300e243300 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 6418
diff changeset
  2056
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2057
// Register for DIVI projection of divmodI
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2058
RegMask Matcher::divI_proj_mask() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2059
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2060
  return RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2061
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2062
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
// Register for MODI projection of divmodI
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2064
RegMask Matcher::modI_proj_mask() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2065
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2066
  return RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2067
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2069
// Register for DIVL projection of divmodL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2070
RegMask Matcher::divL_proj_mask() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2071
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
  return RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2075
// Register for MODL projection of divmodL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2076
RegMask Matcher::modL_proj_mask() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2077
  ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
  return RegMask();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2079
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2080
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4096
diff changeset
  2081
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
11197
158eecd6b330 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 11190
diff changeset
  2082
  return L7_REGP_mask();
4566
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4096
diff changeset
  2083
}
b363f6ef4068 6829187: compiler optimizations required for JSR 292
twisti
parents: 4096
diff changeset
  2084
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2086
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
// The intptr_t operand types, defined by textual substitution.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2089
// (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
#ifdef _LP64
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2091
#define immX      immL
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2092
#define immX13    immL13
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2093
#define immX13m7  immL13m7
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2094
#define iRegX     iRegL
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2095
#define g1RegX    g1RegL
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2096
#else
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2097
#define immX      immI
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2098
#define immX13    immI13
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2099
#define immX13m7  immI13m7
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2100
#define iRegX     iRegI
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  2101
#define g1RegX    g1RegI
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2104
//----------ENCODING BLOCK-----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
// This block specifies the encoding classes used by the compiler to output
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2106
// byte streams.  Encoding classes are parameterized macros used by
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2107
// Machine Instruction Nodes in order to generate the bit encoding of the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2108
// instruction.  Operands specify their base encoding interface with the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
// interface keyword.  There are currently supported four interfaces,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
// operand to generate a function which returns its register number when
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2112
// queried.   CONST_INTER causes an operand to generate a function which
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2113
// returns the value of the constant when queried.  MEMORY_INTER causes an
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2114
// operand to generate four functions which return the Base Register, the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2115
// Index Register, the Scale Value, and the Offset Value of the operand when
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2116
// queried.  COND_INTER causes an operand to generate six functions which
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2117
// return the encoding code (ie - encoding bits for the instruction)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2118
// associated with each basic boolean condition for a conditional instruction.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2119
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
// Instructions specify two basic values for encoding.  Again, a function
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
// is available to check if the constant displacement is an oop. They use the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
// ins_encode keyword to specify their encoding classes (which must be
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2123
// a sequence of enc_class names, and their parameters, specified in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2124
// the encoding block), and they use the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2125
// opcode keyword to specify, in order, their primary, secondary, and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2126
// tertiary opcode.  Only the opcode sections which a particular instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2127
// needs for encoding need to be specified.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2128
encode %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
  enc_class enc_untested %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2130
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2131
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2132
    __ untested("encoding");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2133
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2134
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2135
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2136
  enc_class form3_mem_reg( memory mem, iRegI dst ) %{
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2137
    emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
                       $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2140
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  2141
  enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2142
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  2143
                       $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  2144
  %}
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  2145
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2146
  enc_class form3_mem_prefetch_read( memory mem ) %{
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2147
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2148
                       $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2149
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2151
  enc_class form3_mem_prefetch_write( memory mem ) %{
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2152
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2153
                       $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2154
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2155
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2156
  enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  2157
    assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  2158
    assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2159
    guarantee($mem$$index == R_G0_enc, "double index?");
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2160
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2161
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2162
    emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2163
    emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2164
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2165
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2166
  enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  2167
    assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  2168
    assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2169
    guarantee($mem$$index == R_G0_enc, "double index?");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2170
    // Load long with 2 instructions
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2171
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2172
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2173
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2174
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2175
  //%%% form3_mem_plus_4_reg is a hack--get rid of it
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2176
  enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2177
    guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
22228
f0a0d6be25c6 8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents: 21523
diff changeset
  2178
    emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2179
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2180
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2181
  enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2182
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2183
    if( $rs2$$reg != $rd$$reg )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2184
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2185
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2186
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2187
  // Target lo half of long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2188
  enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2189
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2190
    if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2191
      emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2192
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2193
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2194
  // Source lo half of long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2195
  enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2196
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2197
    if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2198
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2199
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2200
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2201
  // Target hi half of long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2202
  enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2203
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2204
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2205
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2206
  // Source lo half of long, and leave it sign extended.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2207
  enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2208
    // Sign extend low half
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2209
    emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2210
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2211
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2212
  // Source hi half of long, and leave it sign extended.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2213
  enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2214
    // Shift high half to low half
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2215
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2216
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2217
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2218
  // Source hi half of long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2219
  enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2220
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2221
    if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2222
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2223
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2224
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2225
  enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2226
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2227
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2229
  enc_class enc_to_bool( iRegI src, iRegI dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2230
    emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2231
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2232
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2233
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2234
  enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2235
    emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2236
    // clear if nothing else is happening
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2237
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2238
    // blt,a,pn done
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2239
    emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2240
    // mov dst,-1 in delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2241
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2242
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2243
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2244
  enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2245
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2246
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2247
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2248
  enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2249
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2250
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2251
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2252
  enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2253
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2254
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2255
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2256
  enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2257
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2258
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2259
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2260
  enc_class move_return_pc_to_o1() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2261
    emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2262
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2263
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2264
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2265
  /* %%% merge with enc_to_bool */
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2266
  enc_class enc_convP2B( iRegI dst, iRegP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2267
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2268
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2269
    Register   src_reg = reg_to_register_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2270
    Register   dst_reg = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2271
    __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2272
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2273
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2274
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2275
  enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2276
    // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2277
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2278
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2279
    Register   p_reg = reg_to_register_object($p$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2280
    Register   q_reg = reg_to_register_object($q$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2281
    Register   y_reg = reg_to_register_object($y$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2282
    Register tmp_reg = reg_to_register_object($tmp$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2283
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2284
    __ subcc( p_reg, q_reg,   p_reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2285
    __ add  ( p_reg, y_reg, tmp_reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2286
    __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2287
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2288
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2289
  enc_class form_d2i_helper(regD src, regF dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2290
    // fcmp %fcc0,$src,$src
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2291
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2292
    // branch %fcc0 not-nan, predict taken
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2293
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2294
    // fdtoi $src,$dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2295
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2296
    // fitos $dst,$dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2297
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2298
    // clear $dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2299
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2300
    // carry on here...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2301
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2302
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2303
  enc_class form_d2l_helper(regD src, regD dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2304
    // fcmp %fcc0,$src,$src  check for NAN
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2305
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2306
    // branch %fcc0 not-nan, predict taken
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2307
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2308
    // fdtox $src,$dst   convert in delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2309
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2310
    // fxtod $dst,$dst  (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2311
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2312
    // clear $dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2313
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
    // carry on here...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2315
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2316
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2317
  enc_class form_f2i_helper(regF src, regF dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2318
    // fcmps %fcc0,$src,$src
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2319
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2320
    // branch %fcc0 not-nan, predict taken
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2321
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2322
    // fstoi $src,$dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2323
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2324
    // fitos $dst,$dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2325
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2326
    // clear $dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2327
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
    // carry on here...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2329
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2330
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
  enc_class form_f2l_helper(regF src, regD dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
    // fcmps %fcc0,$src,$src
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2334
    // branch %fcc0 not-nan, predict taken
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2335
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2336
    // fstox $src,$dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2337
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2338
    // fxtod $dst,$dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2339
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2340
    // clear $dst (if nan)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2341
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
    // carry on here...
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2343
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2344
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2345
  enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2346
  enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2347
  enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2348
  enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2349
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2350
  enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2351
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2352
  enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2353
  enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2354
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2355
  enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2356
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2357
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2358
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2359
  enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2360
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2361
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2362
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2363
  enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2364
    emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2365
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2366
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2367
  enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2368
    emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2369
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2370
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2371
  enc_class form3_convI2F(regF rs2, regF rd) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2372
    emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2373
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2374
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2375
  // Encloding class for traceable jumps
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2376
  enc_class form_jmpl(g3RegP dest) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2377
    emit_jmpl(cbuf, $dest$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2378
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2379
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2380
  enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2381
    emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2382
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2383
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2384
  enc_class form2_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2385
    emit_nop(cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2386
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2387
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2388
  enc_class form2_illtrap() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2389
    emit_illtrap(cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2390
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2392
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
  // Compare longs and convert into -1, 0, 1.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
  enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2395
    // CMP $src1,$src2
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2396
    emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2397
    // blt,a,pn done
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2398
    emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2399
    // mov dst,-1 in delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2401
    // bgt,a,pn done
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2402
    emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2403
    // mov dst,1 in delay slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2404
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2405
    // CLR    $dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2406
    emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2407
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2408
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2409
  enc_class enc_PartialSubtypeCheck() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2410
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2411
    __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2412
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2413
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2414
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2415
  enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2416
    MacroAssembler _masm(&cbuf);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2417
    Label* L = $labl$$label;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2418
    Assembler::Predict predict_taken =
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2419
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2420
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2421
    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2422
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2423
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2424
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2425
  enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2426
    MacroAssembler _masm(&cbuf);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2427
    Label* L = $labl$$label;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2428
    Assembler::Predict predict_taken =
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2429
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2430
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  2431
    __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2432
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2433
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2434
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2435
  enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2436
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2437
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2438
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2439
             (1 << 18) |                    // cc2 bit for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2440
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2441
             (0 << 13) |                    // select register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2442
             ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2443
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2444
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2445
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2446
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2447
  enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2448
    int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2449
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2450
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2451
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2452
             (1 << 18) |                    // cc2 bit for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2453
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2454
             (1 << 13) |                    // select immediate move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2455
             ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2456
             (simm11 << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2457
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2458
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2459
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2460
  enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2461
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2462
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2463
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2464
             (0 << 18) |                    // cc2 bit for 'fccX'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2465
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2466
             (0 << 13) |                    // select register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2467
             ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2468
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2469
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2470
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2471
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2472
  enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2473
    int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2474
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2475
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2476
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2477
             (0 << 18) |                    // cc2 bit for 'fccX'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2478
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2479
             (1 << 13) |                    // select immediate move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2480
             ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2481
             (simm11 << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2482
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2483
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2484
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2485
  enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2486
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2487
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2488
             (Assembler::fpop2_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2489
             (0 << 18) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2490
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2491
             (1 << 13) |                    // select register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2492
             ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2493
             ($primary << 5) |              // select single, double or quad
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2494
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2495
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2496
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2497
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2498
  enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2499
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2500
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2501
             (Assembler::fpop2_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2502
             (0 << 18) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2503
             ($cmp$$cmpcode << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2504
             ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2505
             ($primary << 5) |              // select single, double or quad
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2506
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2507
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2508
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2509
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2510
  // Used by the MIN/MAX encodings.  Same as a CMOV, but
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2511
  // the condition comes from opcode-field instead of an argument.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2512
  enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2513
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2514
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2515
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2516
             (1 << 18) |                    // cc2 bit for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2517
             ($primary << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2518
             (0 << 13) |                    // select register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2519
             (0 << 11) |                    // cc1, cc0 bits for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2520
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2521
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2522
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2523
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2524
  enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2525
    int op = (Assembler::arith_op << 30) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2526
             ($dst$$reg << 25) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2527
             (Assembler::movcc_op3 << 19) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2528
             (6 << 16) |                    // cc2 bit for 'xcc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2529
             ($primary << 14) |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2530
             (0 << 13) |                    // select register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2531
             (0 << 11) |                    // cc1, cc0 bits for 'icc'
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2532
             ($src$$reg << 0);
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  2533
    cbuf.insts()->emit_int32(op);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2534
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2535
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2536
  enc_class Set13( immI13 src, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2537
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2538
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2539
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2540
  enc_class SetHi22( immI src, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2541
    emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2542
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2543
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2544
  enc_class Set32( immI src, iRegI rd ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2545
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2546
    __ set($src$$constant, reg_to_register_object($rd$$reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2547
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2548
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2549
  enc_class call_epilog %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2550
    if( VerifyStackAtCalls ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2551
      MacroAssembler _masm(&cbuf);
24018
77b156916bab 8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents: 24008
diff changeset
  2552
      int framesize = ra_->C->frame_size_in_bytes();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2553
      Register temp_reg = G3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2554
      __ add(SP, framesize, temp_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2555
      __ cmp(temp_reg, FP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2556
      __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2557
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2558
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2559
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2560
  // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2561
  // to G1 so the register allocator will not have to deal with the misaligned register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2562
  // pair.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2563
  enc_class adjust_long_from_native_call %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2564
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2565
    if (returns_long()) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2566
      //    sllx  O0,32,O0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2567
      emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2568
      //    srl   O1,0,O1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2569
      emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2570
      //    or    O0,O1,G1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2571
      emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2572
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2573
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2574
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2575
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2576
  enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2577
    // CALL directly to the runtime
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2578
    // The user of this is responsible for ensuring that R_L7 is empty (killed).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2579
    emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
7892
ff4948f95c49 7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents: 7704
diff changeset
  2580
                    /*preserve_g2=*/true);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2581
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2582
5690
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2583
  enc_class preserve_SP %{
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2584
    MacroAssembler _masm(&cbuf);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2585
    __ mov(SP, L7_mh_SP_save);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2586
  %}
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2587
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2588
  enc_class restore_SP %{
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2589
    MacroAssembler _masm(&cbuf);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2590
    __ mov(L7_mh_SP_save, SP);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2591
  %}
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
  2592
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2593
  enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2594
    // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2595
    // who we intended to call.
17094
29c4955396d2 8003853: specify offset of IC load in java_to_interp stub
dlong
parents: 14833
diff changeset
  2596
    if (!_method) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2597
      emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2598
    } else if (_optimized_virtual) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2599
      emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2600
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2601
      emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2602
    }
17094
29c4955396d2 8003853: specify offset of IC load in java_to_interp stub
dlong
parents: 14833
diff changeset
  2603
    if (_method) {  // Emit stub for static call.
29c4955396d2 8003853: specify offset of IC load in java_to_interp stub
dlong
parents: 14833
diff changeset
  2604
      CompiledStaticCall::emit_to_interp_stub(cbuf);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2605
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2606
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2607
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2608
  enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2609
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2610
    __ set_inst_mark();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2611
    int vtable_index = this->_vtable_index;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2612
    // MachCallDynamicJavaNode::ret_addr_offset uses this same test
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2613
    if (vtable_index < 0) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2614
      // must be invalid_vtable_index, not nonvirtual_vtable_index
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  2615
      assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2616
      Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2617
      assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2618
      assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  2619
      __ ic_call((address)$meth$$method);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2620
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2621
      assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2622
      // Just go thru the vtable
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2623
      // get receiver klass (receiver already checked for non-null)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2624
      // If we end up going thru a c2i adapter interpreter expects method in G5
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2625
      int off = __ offset();
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2626
      __ load_klass(O0, G3_scratch);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2627
      int klass_load_size;
19979
ebe1dbb6e1aa 8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents: 19319
diff changeset
  2628
      if (UseCompressedClassPointers) {
2254
f13dda645a4b 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 2150
diff changeset
  2629
        assert(Universe::heap() != NULL, "java heap should be initialized");
19319
0ad35be0733a 8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents: 18097
diff changeset
  2630
        klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2631
      } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2632
        klass_load_size = 1*BytesPerInstWord;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2633
      }
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  2634
      int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2635
      int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  2636
      if (Assembler::is_simm13(v_off)) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2637
        __ ld_ptr(G3, v_off, G5_method);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2638
      } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2639
        // Generate 2 instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2640
        __ Assembler::sethi(v_off & ~0x3ff, G5_method);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2641
        __ or3(G5_method, v_off & 0x3ff, G5_method);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2642
        // ld_ptr, set_hi, set
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2643
        assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  2644
               "Unexpected instruction size(s)");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2645
        __ ld_ptr(G3, G5_method, G5_method);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2646
      }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2647
      // NOTE: for vtable dispatches, the vtable entry will never be null.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2648
      // However it may very well end up in handle_wrong_method if the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2649
      // method is abstract for the particular class.
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  2650
      __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2651
      // jump to target (either compiled code or c2iadapter)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2652
      __ jmpl(G3_scratch, G0, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2653
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2654
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2655
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2656
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2657
  enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2658
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2659
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2660
    Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2661
    Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2662
                              // we might be calling a C2I adapter which needs it.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2663
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2664
    assert(temp_reg != G5_ic_reg, "conflicting registers");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2665
    // Load nmethod
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  2666
    __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2667
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2668
    // CALL to compiled java, indirect the contents of G3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2669
    __ set_inst_mark();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2670
    __ callr(temp_reg, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2671
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2672
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2673
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2674
enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2675
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2676
    Register Rdividend = reg_to_register_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2677
    Register Rdivisor = reg_to_register_object($src2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2678
    Register Rresult = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2679
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2680
    __ sra(Rdivisor, 0, Rdivisor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2681
    __ sra(Rdividend, 0, Rdividend);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2682
    __ sdivx(Rdividend, Rdivisor, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2683
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2684
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2685
enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2686
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2687
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2688
    Register Rdividend = reg_to_register_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2689
    int divisor = $imm$$constant;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2690
    Register Rresult = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2691
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2692
    __ sra(Rdividend, 0, Rdividend);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2693
    __ sdivx(Rdividend, divisor, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2694
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2695
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2696
enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2697
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2698
    Register Rsrc1 = reg_to_register_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2699
    Register Rsrc2 = reg_to_register_object($src2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2700
    Register Rdst  = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2701
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2702
    __ sra( Rsrc1, 0, Rsrc1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2703
    __ sra( Rsrc2, 0, Rsrc2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2704
    __ mulx( Rsrc1, Rsrc2, Rdst );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2705
    __ srlx( Rdst, 32, Rdst );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2706
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2707
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2708
enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2709
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2710
    Register Rdividend = reg_to_register_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2711
    Register Rdivisor = reg_to_register_object($src2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2712
    Register Rresult = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2713
    Register Rscratch = reg_to_register_object($scratch$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2714
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2715
    assert(Rdividend != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2716
    assert(Rdivisor  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2717
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2718
    __ sra(Rdividend, 0, Rdividend);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2719
    __ sra(Rdivisor, 0, Rdivisor);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2720
    __ sdivx(Rdividend, Rdivisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2721
    __ mulx(Rscratch, Rdivisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2722
    __ sub(Rdividend, Rscratch, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2723
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2724
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2725
enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2726
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2727
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2728
    Register Rdividend = reg_to_register_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2729
    int divisor = $imm$$constant;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2730
    Register Rresult = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2731
    Register Rscratch = reg_to_register_object($scratch$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2732
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2733
    assert(Rdividend != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2734
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2735
    __ sra(Rdividend, 0, Rdividend);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2736
    __ sdivx(Rdividend, divisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2737
    __ mulx(Rscratch, divisor, Rscratch);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2738
    __ sub(Rdividend, Rscratch, Rresult);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2739
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2740
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2741
enc_class fabss (sflt_reg dst, sflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2742
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2743
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2744
    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2745
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2746
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2747
    __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2748
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2749
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2750
enc_class fabsd (dflt_reg dst, dflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2751
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2752
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2753
    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2754
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2755
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2756
    __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2757
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2758
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2759
enc_class fnegd (dflt_reg dst, dflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2760
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2761
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2762
    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2763
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2764
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2765
    __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2766
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2768
enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2769
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2770
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2771
    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2772
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2773
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2774
    __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2775
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2776
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2777
enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2778
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2779
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2780
    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2781
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2782
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2783
    __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2784
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2785
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2786
enc_class fmovs (dflt_reg dst, dflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2787
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2788
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2789
    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2790
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2791
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2792
    __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2793
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2794
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2795
enc_class fmovd (dflt_reg dst, dflt_reg src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2796
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2797
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2798
    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2799
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2800
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2801
    __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2802
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2803
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2804
enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2805
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2806
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2807
    Register Roop  = reg_to_register_object($oop$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2808
    Register Rbox  = reg_to_register_object($box$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2809
    Register Rscratch = reg_to_register_object($scratch$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2810
    Register Rmark =    reg_to_register_object($scratch2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2811
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2812
    assert(Roop  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2813
    assert(Roop  != Rmark, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2814
    assert(Rbox  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2815
    assert(Rbox  != Rmark, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2816
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  2817
    __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2818
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2819
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2820
enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2821
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2822
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2823
    Register Roop  = reg_to_register_object($oop$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2824
    Register Rbox  = reg_to_register_object($box$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2825
    Register Rscratch = reg_to_register_object($scratch$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2826
    Register Rmark =    reg_to_register_object($scratch2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2827
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2828
    assert(Roop  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2829
    assert(Roop  != Rmark, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2830
    assert(Rbox  != Rscratch, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2831
    assert(Rbox  != Rmark, "");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2832
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  2833
    __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2834
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2835
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2836
  enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2837
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2838
    Register Rmem = reg_to_register_object($mem$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2839
    Register Rold = reg_to_register_object($old$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2840
    Register Rnew = reg_to_register_object($new$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2841
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 17095
diff changeset
  2842
    __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2843
    __ cmp( Rold, Rnew );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2844
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2845
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2846
  enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2847
    Register Rmem = reg_to_register_object($mem$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2848
    Register Rold = reg_to_register_object($old$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2849
    Register Rnew = reg_to_register_object($new$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2850
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2851
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2852
    __ mov(Rnew, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2853
    __ casx(Rmem, Rold, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2854
    __ cmp( Rold, O7 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2855
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2856
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2857
  // raw int cas, used for compareAndSwap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2858
  enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2859
    Register Rmem = reg_to_register_object($mem$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2860
    Register Rold = reg_to_register_object($old$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2861
    Register Rnew = reg_to_register_object($new$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2862
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2863
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2864
    __ mov(Rnew, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2865
    __ cas(Rmem, Rold, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2866
    __ cmp( Rold, O7 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2867
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2868
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2869
  enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2870
    Register Rres = reg_to_register_object($res$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2871
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2872
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2873
    __ mov(1, Rres);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2874
    __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2875
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2876
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2877
  enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2878
    Register Rres = reg_to_register_object($res$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2879
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2880
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2881
    __ mov(1, Rres);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2882
    __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2883
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2884
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2885
  enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2886
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2887
    Register Rdst = reg_to_register_object($dst$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2888
    FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2889
                                     : reg_to_DoubleFloatRegister_object($src1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2890
    FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2891
                                     : reg_to_DoubleFloatRegister_object($src2$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2892
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2893
    // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2894
    __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2895
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2896
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2897
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2898
  enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2899
    Label Ldone, Lloop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2900
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2901
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2902
    Register   str1_reg = reg_to_register_object($str1$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2903
    Register   str2_reg = reg_to_register_object($str2$$reg);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2904
    Register   cnt1_reg = reg_to_register_object($cnt1$$reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2905
    Register   cnt2_reg = reg_to_register_object($cnt2$$reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2906
    Register result_reg = reg_to_register_object($result$$reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2907
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2908
    assert(result_reg != str1_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2909
           result_reg != str2_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2910
           result_reg != cnt1_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2911
           result_reg != cnt2_reg ,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2912
           "need different registers");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2913
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2914
    // Compute the minimum of the string lengths(str1_reg) and the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2915
    // difference of the string lengths (stack)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2916
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2917
    // See if the lengths are different, and calculate min in str1_reg.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2918
    // Stash diff in O7 in case we need it for a tie-breaker.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2919
    Label Lskip;
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2920
    __ subcc(cnt1_reg, cnt2_reg, O7);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2921
    __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2922
    __ br(Assembler::greater, true, Assembler::pt, Lskip);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2923
    // cnt2 is shorter, so use its count:
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2924
    __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2925
    __ bind(Lskip);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2926
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2927
    // reallocate cnt1_reg, cnt2_reg, result_reg
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2928
    // Note:  limit_reg holds the string length pre-scaled by 2
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2929
    Register limit_reg =   cnt1_reg;
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2930
    Register  chr2_reg =   cnt2_reg;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2931
    Register  chr1_reg = result_reg;
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2932
    // str{12} are the base pointers
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2933
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2934
    // Is the minimum length zero?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2935
    __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2936
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2937
    __ delayed()->mov(O7, result_reg);  // result is difference in lengths
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2938
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2939
    // Load first characters
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2940
    __ lduh(str1_reg, 0, chr1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2941
    __ lduh(str2_reg, 0, chr2_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2942
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2943
    // Compare first characters
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2944
    __ subcc(chr1_reg, chr2_reg, chr1_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2945
    __ br(Assembler::notZero, false, Assembler::pt,  Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2946
    assert(chr1_reg == result_reg, "result must be pre-placed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2947
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2948
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2949
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2950
      // Check after comparing first character to see if strings are equivalent
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2951
      Label LSkip2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2952
      // Check if the strings start at same location
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2953
      __ cmp(str1_reg, str2_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2954
      __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2955
      __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2956
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2957
      // Check if the length difference is zero (in O7)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2958
      __ cmp(G0, O7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2959
      __ br(Assembler::equal, true, Assembler::pn, Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2960
      __ delayed()->mov(G0, result_reg);  // result is zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2961
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2962
      // Strings might not be equal
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2963
      __ bind(LSkip2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2964
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2965
21523
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  2966
    // We have no guarantee that on 64 bit the higher half of limit_reg is 0
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  2967
    __ signx(limit_reg);
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  2968
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2969
    __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2970
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2971
    __ delayed()->mov(O7, result_reg);  // result is difference in lengths
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2972
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2973
    // Shift str1_reg and str2_reg to the end of the arrays, negate limit
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2974
    __ add(str1_reg, limit_reg, str1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2975
    __ add(str2_reg, limit_reg, str2_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2976
    __ neg(chr1_reg, limit_reg);  // limit = -(limit-2)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2977
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2978
    // Compare the rest of the characters
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2979
    __ lduh(str1_reg, limit_reg, chr1_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2980
    __ bind(Lloop);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2981
    // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2982
    __ lduh(str2_reg, limit_reg, chr2_reg);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2983
    __ subcc(chr1_reg, chr2_reg, chr1_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2984
    __ br(Assembler::notZero, false, Assembler::pt, Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2985
    assert(chr1_reg == result_reg, "result must be pre-placed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2986
    __ delayed()->inccc(limit_reg, sizeof(jchar));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2987
    // annul LDUH if branch is not taken to prevent access past end of string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2988
    __ br(Assembler::notZero, true, Assembler::pt, Lloop);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2989
    __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2990
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2991
    // If strings are equal up to min length, return the length difference.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2992
    __ mov(O7, result_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2993
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2994
    // Otherwise, return the difference between the first mismatched chars.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2995
    __ bind(Ldone);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2996
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2997
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2998
enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  2999
    Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3000
    MacroAssembler _masm(&cbuf);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3001
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3002
    Register   str1_reg = reg_to_register_object($str1$$reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3003
    Register   str2_reg = reg_to_register_object($str2$$reg);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3004
    Register    cnt_reg = reg_to_register_object($cnt$$reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3005
    Register   tmp1_reg = O7;
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3006
    Register result_reg = reg_to_register_object($result$$reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3007
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3008
    assert(result_reg != str1_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3009
           result_reg != str2_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3010
           result_reg !=  cnt_reg &&
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3011
           result_reg != tmp1_reg ,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3012
           "need different registers");
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3013
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3014
    __ cmp(str1_reg, str2_reg); //same char[] ?
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3015
    __ brx(Assembler::equal, true, Assembler::pn, Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3016
    __ delayed()->add(G0, 1, result_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3017
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  3018
    __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3019
    __ delayed()->add(G0, 1, result_reg); // count == 0
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3020
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3021
    //rename registers
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3022
    Register limit_reg =    cnt_reg;
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3023
    Register  chr1_reg = result_reg;
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3024
    Register  chr2_reg =   tmp1_reg;
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3025
21523
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  3026
    // We have no guarantee that on 64 bit the higher half of limit_reg is 0
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  3027
    __ signx(limit_reg);
49c80d56e5e3 8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents: 21189
diff changeset
  3028
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3029
    //check for alignment and position the pointers to the ends
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3030
    __ or3(str1_reg, str2_reg, chr1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3031
    __ andcc(chr1_reg, 0x3, chr1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3032
    // notZero means at least one not 4-byte aligned.
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3033
    // We could optimize the case when both arrays are not aligned
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3034
    // but it is not frequent case and it requires additional checks.
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3035
    __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3036
    __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3037
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3038
    // Compare char[] arrays aligned to 4 bytes.
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3039
    __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3040
                          chr1_reg, chr2_reg, Ldone);
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  3041
    __ ba(Ldone);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3042
    __ delayed()->add(G0, 1, result_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3043
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3044
    // char by char compare
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3045
    __ bind(Lchar);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3046
    __ add(str1_reg, limit_reg, str1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3047
    __ add(str2_reg, limit_reg, str2_reg);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3048
    __ neg(limit_reg); //negate count
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3049
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3050
    __ lduh(str1_reg, limit_reg, chr1_reg);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3051
    // Lchar_loop
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3052
    __ bind(Lchar_loop);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3053
    __ lduh(str2_reg, limit_reg, chr2_reg);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3054
    __ cmp(chr1_reg, chr2_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3055
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3056
    __ delayed()->mov(G0, result_reg); //not equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3057
    __ inccc(limit_reg, sizeof(jchar));
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3058
    // annul LDUH if branch is not taken to prevent access past end of string
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3059
    __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3060
    __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3061
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3062
    __ add(G0, 1, result_reg);  //equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3063
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3064
    __ bind(Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3065
  %}
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3066
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3067
enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3068
    Label Lvector, Ldone, Lloop;
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3069
    MacroAssembler _masm(&cbuf);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3070
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3071
    Register   ary1_reg = reg_to_register_object($ary1$$reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3072
    Register   ary2_reg = reg_to_register_object($ary2$$reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3073
    Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3074
    Register   tmp2_reg = O7;
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3075
    Register result_reg = reg_to_register_object($result$$reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3076
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3077
    int length_offset  = arrayOopDesc::length_offset_in_bytes();
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3078
    int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3079
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3080
    // return true if the same array
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3081
    __ cmp(ary1_reg, ary2_reg);
4019
6d6674c9e7d7 6890984: Comparison of 2 arrays could cause VM crash
kvn
parents: 4010
diff changeset
  3082
    __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3083
    __ delayed()->add(G0, 1, result_reg); // equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3084
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3085
    __ br_null(ary1_reg, true, Assembler::pn, Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3086
    __ delayed()->mov(G0, result_reg);    // not equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3087
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3088
    __ br_null(ary2_reg, true, Assembler::pn, Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3089
    __ delayed()->mov(G0, result_reg);    // not equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3090
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3091
    //load the lengths of arrays
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3092
    __ ld(Address(ary1_reg, length_offset), tmp1_reg);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3093
    __ ld(Address(ary2_reg, length_offset), tmp2_reg);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3094
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3095
    // return false if the two arrays are not equal length
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3096
    __ cmp(tmp1_reg, tmp2_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3097
    __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3098
    __ delayed()->mov(G0, result_reg);     // not equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3099
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  3100
    __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3101
    __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3102
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3103
    // load array addresses
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3104
    __ add(ary1_reg, base_offset, ary1_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3105
    __ add(ary2_reg, base_offset, ary2_reg);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3106
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3107
    // renaming registers
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3108
    Register chr1_reg  =  result_reg; // for characters in ary1
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3109
    Register chr2_reg  =  tmp2_reg;   // for characters in ary2
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3110
    Register limit_reg =  tmp1_reg;   // length
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3111
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3112
    // set byte count
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3113
    __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3114
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3115
    // Compare char[] arrays aligned to 4 bytes.
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3116
    __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
  3117
                          chr1_reg, chr2_reg, Ldone);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3118
    __ add(G0, 1, result_reg); // equals
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3119
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3120
    __ bind(Ldone);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3121
  %}
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
  3122
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3123
  enc_class enc_rethrow() %{
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  3124
    cbuf.set_insts_mark();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3125
    Register temp_reg = G3;
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3126
    AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3127
    assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3128
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3129
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3130
    __ save_frame(0);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3131
    AddressLiteral last_rethrow_addrlit(&last_rethrow);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3132
    __ sethi(last_rethrow_addrlit, L1);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3133
    Address addr(L1, last_rethrow_addrlit.low10());
18097
acd70736bd60 8008407: remove SPARC V8 support
morris
parents: 17095
diff changeset
  3134
    __ rdpc(L2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3135
    __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3136
    __ st_ptr(L2, addr);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3137
    __ restore();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3138
#endif
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  3139
    __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3140
    __ delayed()->nop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3141
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3142
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3143
  enc_class emit_mem_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3144
    // Generates the instruction LDUXA [o6,g0],#0x82,g0
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  3145
    cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3146
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3147
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3148
  enc_class emit_fadd_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3149
    // Generates the instruction FMOVS f31,f31
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  3150
    cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3151
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3152
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3153
  enc_class emit_br_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3154
    // Generates the instruction BPN,PN .
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 5702
diff changeset
  3155
    cbuf.insts()->emit_int32((unsigned int) 0x00400000);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3156
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3157
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3158
  enc_class enc_membar_acquire %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3159
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3160
    __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3161
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3162
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3163
  enc_class enc_membar_release %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3164
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3165
    __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3166
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3167
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3168
  enc_class enc_membar_volatile %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3169
    MacroAssembler _masm(&cbuf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3170
    __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3171
  %}
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3172
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3173
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3174
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3175
//----------FRAME--------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3176
// Definition of frame structure and management information.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3177
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3178
//  S T A C K   L A Y O U T    Allocators stack-slot number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3179
//                             |   (to get allocators register number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3180
//  G  Owned by    |        |  v    add VMRegImpl::stack0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3181
//  r   CALLER     |        |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3182
//  o     |        +--------+      pad to even-align allocators stack-slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3183
//  w     V        |  pad0  |        numbers; owned by CALLER
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3184
//  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3185
//  h     ^        |   in   |  5
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3186
//        |        |  args  |  4   Holes in incoming args owned by SELF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3187
//  |     |        |        |  3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3188
//  |     |        +--------+
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3189
//  V     |        | old out|      Empty on Intel, window on Sparc
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3190
//        |    old |preserve|      Must be even aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3191
//        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3192
//        |        |   in   |  3   area for Intel ret address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3193
//     Owned by    |preserve|      Empty on Sparc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3194
//       SELF      +--------+
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3195
//        |        |  pad2  |  2   pad to align old SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3196
//        |        +--------+  1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3197
//        |        | locks  |  0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3198
//        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3199
//        |        |  pad1  | 11   pad to align new SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3200
//        |        +--------+
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3201
//        |        |        | 10
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3202
//        |        | spills |  9   spills
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3203
//        V        |        |  8   (pad0 slot for callee)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3204
//      -----------+--------+----> Matcher::_out_arg_limit, unaligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3205
//        ^        |  out   |  7
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3206
//        |        |  args  |  6   Holes in outgoing args owned by CALLEE
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3207
//     Owned by    +--------+
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3208
//      CALLEE     | new out|  6   Empty on Intel, window on Sparc
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3209
//        |    new |preserve|      Must be even-aligned.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3210
//        |     SP-+--------+----> Matcher::_new_SP, even aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3211
//        |        |        |
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3212
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3213
// Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3214
//         known from SELF's arguments and the Java calling convention.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3215
//         Region 6-7 is determined per call site.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3216
// Note 2: If the calling convention leaves holes in the incoming argument
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3217
//         area, those holes are owned by SELF.  Holes in the outgoing area
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3218
//         are owned by the CALLEE.  Holes should not be nessecary in the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3219
//         incoming area, as the Java calling convention is completely under
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3220
//         the control of the AD file.  Doubles can be sorted and packed to
26804
4b23f22faae6 8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents: 25933
diff changeset
  3221
//         avoid holes.  Holes in the outgoing arguments may be necessary for
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3222
//         varargs C calling conventions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3223
// Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3224
//         even aligned with pad0 as needed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3225
//         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3226
//         region 6-11 is even aligned; it may be padded out more so that
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3227
//         the region from SP to FP meets the minimum stack alignment.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3229
frame %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3230
  // What direction does stack grow in (assumed to be same for native & Java)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3231
  stack_direction(TOWARDS_LOW);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3232
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3233
  // These two registers define part of the calling convention
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3234
  // between compiled code and the interpreter.
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  3235
  inline_cache_reg(R_G5);                // Inline Cache Register or Method* for I2C
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3236
  interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3237
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3238
  // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3239
  cisc_spilling_operand_name(indOffset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3240
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3241
  // Number of stack slots consumed by a Monitor enter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3242
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3243
  sync_stack_slots(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3244
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3245
  sync_stack_slots(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3246
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3247
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3248
  // Compiled code's Frame Pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3249
  frame_pointer(R_SP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3250
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3251
  // Stack alignment requirement
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3252
  stack_alignment(StackAlignmentInBytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3253
  //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3254
  // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3255
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3256
  // Number of stack slots between incoming argument block and the start of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3257
  // a new frame.  The PROLOG must add this many slots to the stack.  The
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3258
  // EPILOG must remove this many slots.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3259
  in_preserve_stack_slots(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3260
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3261
  // Number of outgoing stack slots killed above the out_preserve_stack_slots
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3262
  // for calls to C.  Supports the var-args backing area for register parms.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3263
  // ADLC doesn't support parsing expressions, so I folded the math by hand.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3264
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3265
  // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3266
  varargs_C_out_slots_killed(12);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3267
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3268
  // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3269
  varargs_C_out_slots_killed( 7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3270
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3271
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3272
  // The after-PROLOG location of the return address.  Location of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3273
  // return address specifies a type (REG or STACK) and a number
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3274
  // representing the register number (i.e. - use a register name) or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3275
  // stack slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3276
  return_addr(REG R_I7);          // Ret Addr is in register I7
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3277
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3278
  // Body of function which returns an OptoRegs array locating
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3279
  // arguments either in registers or in stack slots for calling
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3280
  // java
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3281
  calling_convention %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3282
    (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3283
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3284
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3285
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3286
  // Body of function which returns an OptoRegs array locating
26804
4b23f22faae6 8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents: 25933
diff changeset
  3287
  // arguments either in registers or in stack slots for calling
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3288
  // C.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3289
  c_calling_convention %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3290
    // This is obviously always outgoing
22832
03720a5b7595 8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents: 19319
diff changeset
  3291
    (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3292
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3293
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3294
  // Location of native (C/C++) and interpreter return values.  This is specified to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3295
  // be the  same as Java.  In the 32-bit VM, long values are actually returned from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3296
  // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3297
  // to and from the register pairs is done by the appropriate call and epilog
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3298
  // opcodes.  This simplifies the register allocator.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3299
  c_return_value %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3300
    assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3301
#ifdef     _LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3302
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3303
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3304
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3305
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3306
#else  // !_LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3307
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3308
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3309
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3310
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3311
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3312
    return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3313
                        (is_outgoing?lo_out:lo_in)[ideal_reg] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3314
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3315
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3316
  // Location of compiled Java return values.  Same as C
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3317
  return_value %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3318
    assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3319
#ifdef     _LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3320
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3321
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3322
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3323
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3324
#else  // !_LP64
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3325
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3326
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3327
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3328
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3329
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3330
    return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3331
                        (is_outgoing?lo_out:lo_in)[ideal_reg] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3332
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3333
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3334
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3335
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3336
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3337
//----------ATTRIBUTES---------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3338
//----------Operand Attributes-------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3339
op_attrib op_cost(1);          // Required cost attribute
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3340
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3341
//----------Instruction Attributes---------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3342
ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
10255
bab46e6f7661 7069452: Cleanup NodeFlags
kvn
parents: 10252
diff changeset
  3343
ins_attrib ins_size(32);           // Required size attribute (in bits)
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3344
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3345
// avoid_back_to_back attribute is an expression that must return
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3346
// one of the following values defined in MachNode:
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3347
// AVOID_NONE   - instruction can be placed anywhere
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3348
// AVOID_BEFORE - instruction cannot be placed after an
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3349
//                instruction with MachNode::AVOID_AFTER
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3350
// AVOID_AFTER  - the next instruction cannot be the one 
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3351
//                with MachNode::AVOID_BEFORE
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3352
// AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3353
//                          the same time                                
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3354
ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  3355
10255
bab46e6f7661 7069452: Cleanup NodeFlags
kvn
parents: 10252
diff changeset
  3356
ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
bab46e6f7661 7069452: Cleanup NodeFlags
kvn
parents: 10252
diff changeset
  3357
                                   // non-matching short branch variant of some
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3358
                                                            // long branch?
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3359
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3360
//----------OPERANDS-----------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3361
// Operand definitions must precede instruction definitions for correct parsing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3362
// in the ADLC because operands constitute user defined types which are used in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3363
// instruction definitions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3364
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3365
//----------Simple Operands----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3366
// Immediate Operands
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3367
// Integer Immediate: 32-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3368
operand immI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3369
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3370
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3371
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3372
  // formats are generated automatically for constants and base registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3373
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3374
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3375
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3376
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3377
// Integer Immediate: 8-bit
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3378
operand immI8() %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  3379
  predicate(Assembler::is_simm8(n->get_int()));
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3380
  match(ConI);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3381
  op_cost(0);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3382
  format %{ %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3383
  interface(CONST_INTER);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3384
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3385
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3386
// Integer Immediate: 13-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3387
operand immI13() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3388
  predicate(Assembler::is_simm13(n->get_int()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3389
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3390
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3391
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3392
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3393
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3394
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3395
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3396
// Integer Immediate: 13-bit minus 7
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3397
operand immI13m7() %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3398
  predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3399
  match(ConI);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3400
  op_cost(0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3401
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3402
  format %{ %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3403
  interface(CONST_INTER);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3404
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3405
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3406
// Integer Immediate: 16-bit
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3407
operand immI16() %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  3408
  predicate(Assembler::is_simm16(n->get_int()));
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3409
  match(ConI);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3410
  op_cost(0);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3411
  format %{ %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3412
  interface(CONST_INTER);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3413
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  3414
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3415
// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3416
operand immU12() %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3417
  predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3418
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3419
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3420
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3421
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3422
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3423
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3424
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3425
// Integer Immediate: 6-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3426
operand immU6() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3427
  predicate(n->get_int() >= 0 && n->get_int() <= 63);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3428
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3429
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3430
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3431
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3432
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3433
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3434
// Integer Immediate: 11-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3435
operand immI11() %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  3436
  predicate(Assembler::is_simm11(n->get_int()));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3437
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3438
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3439
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3440
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3441
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3442
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3443
// Integer Immediate: 5-bit
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3444
operand immI5() %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  3445
  predicate(Assembler::is_simm5(n->get_int()));
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3446
  match(ConI);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3447
  op_cost(0);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3448
  format %{ %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3449
  interface(CONST_INTER);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3450
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3451
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3452
// Int Immediate non-negative
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3453
operand immU31()
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3454
%{
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3455
  predicate(n->get_int() >= 0);
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3456
  match(ConI);
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3457
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3458
  op_cost(0);
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3459
  format %{ %}
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3460
  interface(CONST_INTER);
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3461
%}
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  3462
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3463
// Integer Immediate: 0-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3464
operand immI0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3465
  predicate(n->get_int() == 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3466
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3467
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3468
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3469
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3470
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3471
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3472
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3473
// Integer Immediate: the value 10
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3474
operand immI10() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3475
  predicate(n->get_int() == 10);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3476
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3477
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3478
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3479
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3480
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3481
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3482
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3483
// Integer Immediate: the values 0-31
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3484
operand immU5() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3485
  predicate(n->get_int() >= 0 && n->get_int() <= 31);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3486
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3487
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3488
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3489
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3490
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3491
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3492
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3493
// Integer Immediate: the values 1-31
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3494
operand immI_1_31() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3495
  predicate(n->get_int() >= 1 && n->get_int() <= 31);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3496
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3497
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3498
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3499
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3500
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3501
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3502
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3503
// Integer Immediate: the values 32-63
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3504
operand immI_32_63() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3505
  predicate(n->get_int() >= 32 && n->get_int() <= 63);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3506
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3507
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3508
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3509
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3510
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3511
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3512
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3513
// Immediates for special shifts (sign extend)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3514
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3515
// Integer Immediate: the value 16
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3516
operand immI_16() %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3517
  predicate(n->get_int() == 16);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3518
  match(ConI);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3519
  op_cost(0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3520
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3521
  format %{ %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3522
  interface(CONST_INTER);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3523
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3524
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3525
// Integer Immediate: the value 24
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3526
operand immI_24() %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3527
  predicate(n->get_int() == 24);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3528
  match(ConI);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3529
  op_cost(0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3530
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3531
  format %{ %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3532
  interface(CONST_INTER);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3533
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3534
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3535
// Integer Immediate: the value 255
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3536
operand immI_255() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3537
  predicate( n->get_int() == 255 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3538
  match(ConI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3539
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3540
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3541
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3542
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3543
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3544
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3545
// Integer Immediate: the value 65535
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3546
operand immI_65535() %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3547
  predicate(n->get_int() == 65535);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3548
  match(ConI);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3549
  op_cost(0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3550
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3551
  format %{ %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3552
  interface(CONST_INTER);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3553
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3554
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3555
// Long Immediate: the value FF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3556
operand immL_FF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3557
  predicate( n->get_long() == 0xFFL );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3558
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3559
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3560
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3561
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3562
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3563
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3564
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3565
// Long Immediate: the value FFFF
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3566
operand immL_FFFF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3567
  predicate( n->get_long() == 0xFFFFL );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3568
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3569
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3570
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3571
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3572
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3573
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3574
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3575
// Pointer Immediate: 32 or 64-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3576
operand immP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3577
  match(ConP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3578
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3579
  op_cost(5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3580
  // formats are generated automatically for constants and base registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3581
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3582
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3583
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3584
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3585
#ifdef _LP64
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3586
// Pointer Immediate: 64-bit
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3587
operand immP_set() %{
7704
cc9d3ed42704 7006505: Use kstat info to identify SPARC processor
kvn
parents: 7700
diff changeset
  3588
  predicate(!VM_Version::is_niagara_plus());
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3589
  match(ConP);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3590
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3591
  op_cost(5);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3592
  // formats are generated automatically for constants and base registers
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3593
  format %{ %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3594
  interface(CONST_INTER);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3595
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3596
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3597
// Pointer Immediate: 64-bit
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3598
// From Niagara2 processors on a load should be better than materializing.
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3599
operand immP_load() %{
7704
cc9d3ed42704 7006505: Use kstat info to identify SPARC processor
kvn
parents: 7700
diff changeset
  3600
  predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3601
  match(ConP);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3602
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3603
  op_cost(5);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3604
  // formats are generated automatically for constants and base registers
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3605
  format %{ %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3606
  interface(CONST_INTER);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3607
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3608
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3609
// Pointer Immediate: 64-bit
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3610
operand immP_no_oop_cheap() %{
7704
cc9d3ed42704 7006505: Use kstat info to identify SPARC processor
kvn
parents: 7700
diff changeset
  3611
  predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3612
  match(ConP);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3613
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3614
  op_cost(5);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3615
  // formats are generated automatically for constants and base registers
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3616
  format %{ %}
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3617
  interface(CONST_INTER);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3618
%}
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3619
#endif
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  3620
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3621
operand immP13() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3622
  predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3623
  match(ConP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3624
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3625
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3626
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3627
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3628
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3629
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3630
operand immP0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3631
  predicate(n->get_ptr() == 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3632
  match(ConP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3633
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3634
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3635
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3636
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3637
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3638
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3639
operand immP_poll() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3640
  predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3641
  match(ConP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3642
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3643
  // formats are generated automatically for constants and base registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3644
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3645
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3646
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3647
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3648
// Pointer Immediate
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3649
operand immN()
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3650
%{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3651
  match(ConN);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3652
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3653
  op_cost(10);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3654
  format %{ %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3655
  interface(CONST_INTER);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3656
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3657
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3658
operand immNKlass()
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3659
%{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3660
  match(ConNKlass);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3661
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3662
  op_cost(10);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3663
  format %{ %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3664
  interface(CONST_INTER);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3665
%}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  3666
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3667
// NULL Pointer Immediate
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3668
operand immN0()
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3669
%{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3670
  predicate(n->get_narrowcon() == 0);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3671
  match(ConN);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3672
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3673
  op_cost(0);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3674
  format %{ %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3675
  interface(CONST_INTER);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3676
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3677
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3678
operand immL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3679
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3680
  op_cost(40);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3681
  // formats are generated automatically for constants and base registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3682
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3683
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3684
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3685
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3686
operand immL0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3687
  predicate(n->get_long() == 0L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3688
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3689
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3690
  // formats are generated automatically for constants and base registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3691
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3692
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3693
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3694
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3695
// Integer Immediate: 5-bit
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3696
operand immL5() %{
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  3697
  predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3698
  match(ConL);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3699
  op_cost(0);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3700
  format %{ %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3701
  interface(CONST_INTER);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3702
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  3703
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3704
// Long Immediate: 13-bit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3705
operand immL13() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3706
  predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3707
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3708
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3709
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3710
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3711
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3712
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3713
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3714
// Long Immediate: 13-bit minus 7
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3715
operand immL13m7() %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3716
  predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3717
  match(ConL);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3718
  op_cost(0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3719
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3720
  format %{ %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3721
  interface(CONST_INTER);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3722
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  3723
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3724
// Long Immediate: low 32-bit mask
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3725
operand immL_32bits() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3726
  predicate(n->get_long() == 0xFFFFFFFFL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3727
  match(ConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3728
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3729
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3730
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3731
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3732
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3733
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3734
// Long Immediate: cheap (materialize in <= 3 instructions)
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3735
operand immL_cheap() %{
7704
cc9d3ed42704 7006505: Use kstat info to identify SPARC processor
kvn
parents: 7700
diff changeset
  3736
  predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3737
  match(ConL);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3738
  op_cost(0);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3739
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3740
  format %{ %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3741
  interface(CONST_INTER);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3742
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3743
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3744
// Long Immediate: expensive (materialize in > 3 instructions)
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3745
operand immL_expensive() %{
7704
cc9d3ed42704 7006505: Use kstat info to identify SPARC processor
kvn
parents: 7700
diff changeset
  3746
  predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3747
  match(ConL);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3748
  op_cost(0);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3749
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3750
  format %{ %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3751
  interface(CONST_INTER);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3752
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  3753
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3754
// Double Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3755
operand immD() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3756
  match(ConD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3757
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3758
  op_cost(40);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3759
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3760
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3761
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3762
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3763
operand immD0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3764
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3765
  // on 64-bit architectures this comparision is faster
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3766
  predicate(jlong_cast(n->getd()) == 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3767
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3768
  predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3769
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3770
  match(ConD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3771
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3772
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3773
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3774
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3775
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3776
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3777
// Float Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3778
operand immF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3779
  match(ConF);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3780
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3781
  op_cost(20);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3782
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3783
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3784
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3785
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3786
// Float Immediate: 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3787
operand immF0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3788
  predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3789
  match(ConF);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3790
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3791
  op_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3792
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3793
  interface(CONST_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3794
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3795
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3796
// Integer Register Operands
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3797
// Integer Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3798
operand iRegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3799
  constraint(ALLOC_IN_RC(int_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3800
  match(RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3801
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3802
  match(notemp_iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3803
  match(g1RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3804
  match(o0RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3805
  match(iRegIsafe);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3806
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3807
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3808
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3809
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3810
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3811
operand notemp_iRegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3812
  constraint(ALLOC_IN_RC(notemp_int_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3813
  match(RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3814
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3815
  match(o0RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3817
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3818
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3819
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3820
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3821
operand o0RegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3822
  constraint(ALLOC_IN_RC(o0_regI));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3823
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3824
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3825
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3826
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3827
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3828
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3829
// Pointer Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3830
operand iRegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3831
  constraint(ALLOC_IN_RC(ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3832
  match(RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3833
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3834
  match(lock_ptr_RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3835
  match(g1RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3836
  match(g2RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3837
  match(g3RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3838
  match(g4RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3839
  match(i0RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3840
  match(o0RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3841
  match(o1RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3842
  match(l7RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3843
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3844
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3845
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3846
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3847
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3848
operand sp_ptr_RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3849
  constraint(ALLOC_IN_RC(sp_ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3850
  match(RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3851
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3852
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3853
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3854
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3855
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3856
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3857
operand lock_ptr_RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3858
  constraint(ALLOC_IN_RC(lock_ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3859
  match(RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3860
  match(i0RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3861
  match(o0RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3862
  match(o1RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3863
  match(l7RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3864
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3865
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3866
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3867
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3868
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3869
operand g1RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3870
  constraint(ALLOC_IN_RC(g1_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3871
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3872
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3873
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3874
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3875
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3876
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3877
operand g2RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3878
  constraint(ALLOC_IN_RC(g2_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3879
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3880
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3881
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3882
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3883
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3884
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3885
operand g3RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3886
  constraint(ALLOC_IN_RC(g3_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3887
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3888
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3889
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3890
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3891
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3892
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3893
operand g1RegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3894
  constraint(ALLOC_IN_RC(g1_regI));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3895
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3896
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3897
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3898
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3899
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3900
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3901
operand g3RegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3902
  constraint(ALLOC_IN_RC(g3_regI));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3903
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3904
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3905
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3906
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3907
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3908
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3909
operand g4RegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3910
  constraint(ALLOC_IN_RC(g4_regI));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3911
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3912
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3913
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3914
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3915
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3916
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3917
operand g4RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3918
  constraint(ALLOC_IN_RC(g4_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3919
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3920
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3921
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3922
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3923
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3924
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3925
operand i0RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3926
  constraint(ALLOC_IN_RC(i0_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3927
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3928
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3929
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3930
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3931
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3932
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3933
operand o0RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3934
  constraint(ALLOC_IN_RC(o0_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3935
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3936
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3937
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3938
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3939
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3940
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3941
operand o1RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3942
  constraint(ALLOC_IN_RC(o1_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3943
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3944
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3945
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3946
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3947
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3948
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3949
operand o2RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3950
  constraint(ALLOC_IN_RC(o2_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3951
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3953
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3954
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3955
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3956
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3957
operand o7RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3958
  constraint(ALLOC_IN_RC(o7_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3959
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3960
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3961
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3962
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3963
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3964
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3965
operand l7RegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3966
  constraint(ALLOC_IN_RC(l7_regP));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3967
  match(iRegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3968
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3969
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3970
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3971
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3972
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3973
operand o7RegI() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3974
  constraint(ALLOC_IN_RC(o7_regI));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3975
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3976
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3977
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3978
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3979
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3980
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3981
operand iRegN() %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3982
  constraint(ALLOC_IN_RC(int_reg));
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3983
  match(RegN);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3984
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3985
  format %{ %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3986
  interface(REG_INTER);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3987
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  3988
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3989
// Long Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3990
operand iRegL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3991
  constraint(ALLOC_IN_RC(long_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3992
  match(RegL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3993
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3994
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3995
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3996
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3997
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3998
operand o2RegL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  3999
  constraint(ALLOC_IN_RC(o2_regL));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4000
  match(iRegL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4001
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4002
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4003
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4004
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4005
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4006
operand o7RegL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4007
  constraint(ALLOC_IN_RC(o7_regL));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4008
  match(iRegL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4009
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4010
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4011
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4012
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4013
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4014
operand g1RegL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4015
  constraint(ALLOC_IN_RC(g1_regL));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4016
  match(iRegL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4017
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4018
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4019
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4020
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4021
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4022
operand g3RegL() %{
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4023
  constraint(ALLOC_IN_RC(g3_regL));
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4024
  match(iRegL);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4025
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4026
  format %{ %}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4027
  interface(REG_INTER);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4028
%}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  4029
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4030
// Int Register safe
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4031
// This is 64bit safe
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4032
operand iRegIsafe() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4033
  constraint(ALLOC_IN_RC(long_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4034
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4035
  match(iRegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4036
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4037
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4038
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4039
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4040
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4041
// Condition Code Flag Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4042
operand flagsReg() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4043
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4044
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4045
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4046
  format %{ "ccr" %} // both ICC and XCC
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4047
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4048
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4050
// Condition Code Register, unsigned comparisons.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4051
operand flagsRegU() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4052
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4053
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4054
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4055
  format %{ "icc_U" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4056
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4057
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4058
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4059
// Condition Code Register, pointer comparisons.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4060
operand flagsRegP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4061
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4062
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4063
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4064
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4065
  format %{ "xcc_P" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4066
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4067
  format %{ "icc_P" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4068
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4069
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4070
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4071
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4072
// Condition Code Register, long comparisons.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4073
operand flagsRegL() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4074
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4075
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4076
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4077
  format %{ "xcc_L" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4078
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4079
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4080
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4081
// Condition Code Register, floating comparisons, unordered same as "less".
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4082
operand flagsRegF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4083
  constraint(ALLOC_IN_RC(float_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4084
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4085
  match(flagsRegF0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4086
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4087
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4088
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4089
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4090
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4091
operand flagsRegF0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4092
  constraint(ALLOC_IN_RC(float_flag0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4093
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4094
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4095
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4096
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4097
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4098
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4099
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4100
// Condition Code Flag Register used by long compare
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4101
operand flagsReg_long_LTGE() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4102
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4103
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4104
  format %{ "icc_LTGE" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4105
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4106
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4107
operand flagsReg_long_EQNE() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4108
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4109
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4110
  format %{ "icc_EQNE" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4111
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4112
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4113
operand flagsReg_long_LEGT() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4114
  constraint(ALLOC_IN_RC(int_flags));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4115
  match(RegFlags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4116
  format %{ "icc_LEGT" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4117
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4118
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4119
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4120
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4121
operand regD() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4122
  constraint(ALLOC_IN_RC(dflt_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4123
  match(RegD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4124
2015
580165b3f277 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 1500
diff changeset
  4125
  match(regD_low);
580165b3f277 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 1500
diff changeset
  4126
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4127
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4128
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4129
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4130
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4131
operand regF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4132
  constraint(ALLOC_IN_RC(sflt_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4133
  match(RegF);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4134
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4135
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4136
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4137
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4138
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4139
operand regD_low() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4140
  constraint(ALLOC_IN_RC(dflt_low_reg));
2015
580165b3f277 6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents: 1500
diff changeset
  4141
  match(regD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4142
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4143
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4144
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4145
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4146
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4147
// Special Registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4148
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4149
// Method Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4150
operand inline_cache_regP(iRegP reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4151
  constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4152
  match(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4153
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4154
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4155
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4156
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4157
operand interpreter_method_oop_regP(iRegP reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4158
  constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4159
  match(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4160
  format %{ %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4161
  interface(REG_INTER);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4162
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4163
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4164
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4165
//----------Complex Operands---------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4166
// Indirect Memory Reference
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4167
operand indirect(sp_ptr_RegP reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4168
  constraint(ALLOC_IN_RC(sp_ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4169
  match(reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4170
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4171
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4172
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4173
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4174
    base($reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4175
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4176
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4177
    disp(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4178
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4179
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4180
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4181
// Indirect with simm13 Offset
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4182
operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4183
  constraint(ALLOC_IN_RC(sp_ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4184
  match(AddP reg offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4185
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4186
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4187
  format %{ "[$reg + $offset]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4188
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4189
    base($reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4190
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4191
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4192
    disp($offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4193
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4194
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4195
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4196
// Indirect with simm13 Offset minus 7
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4197
operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4198
  constraint(ALLOC_IN_RC(sp_ptr_reg));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4199
  match(AddP reg offset);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4200
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4201
  op_cost(100);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4202
  format %{ "[$reg + $offset]" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4203
  interface(MEMORY_INTER) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4204
    base($reg);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4205
    index(0x0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4206
    scale(0x0);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4207
    disp($offset);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4208
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4209
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  4210
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4211
// Note:  Intel has a swapped version also, like this:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4212
//operand indOffsetX(iRegI reg, immP offset) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4213
//  constraint(ALLOC_IN_RC(int_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4214
//  match(AddP offset reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4215
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4216
//  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4217
//  format %{ "[$reg + $offset]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4218
//  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4219
//    base($reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4220
//    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4221
//    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4222
//    disp($offset);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4223
//  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4224
//%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4225
//// However, it doesn't make sense for SPARC, since
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4226
// we have no particularly good way to embed oops in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4227
// single instructions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4229
// Indirect with Register Index
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4230
operand indIndex(iRegP addr, iRegX index) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4231
  constraint(ALLOC_IN_RC(ptr_reg));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4232
  match(AddP addr index);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4233
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4234
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4235
  format %{ "[$addr + $index]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4236
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4237
    base($addr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4238
    index($index);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4239
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4240
    disp(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4241
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4242
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4243
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4244
//----------Special Memory Operands--------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4245
// Stack Slot Operand - This operand is used for loading and storing temporary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4246
//                      values on the stack where a match requires a value to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4247
//                      flow through memory.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4248
operand stackSlotI(sRegI reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4249
  constraint(ALLOC_IN_RC(stack_slots));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4250
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4251
  //match(RegI);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4252
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4253
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4254
    base(0xE);   // R_SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4255
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4256
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4257
    disp($reg);  // Stack Offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4258
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4259
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4260
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4261
operand stackSlotP(sRegP reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4262
  constraint(ALLOC_IN_RC(stack_slots));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4263
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4264
  //match(RegP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4265
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4266
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4267
    base(0xE);   // R_SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4268
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4269
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4270
    disp($reg);  // Stack Offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4271
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4272
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4273
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4274
operand stackSlotF(sRegF reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4275
  constraint(ALLOC_IN_RC(stack_slots));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4276
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4277
  //match(RegF);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4278
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4279
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4280
    base(0xE);   // R_SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4281
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4282
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4283
    disp($reg);  // Stack Offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4284
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4285
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4286
operand stackSlotD(sRegD reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4287
  constraint(ALLOC_IN_RC(stack_slots));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4288
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4289
  //match(RegD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4290
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4291
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4292
    base(0xE);   // R_SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4293
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4294
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4295
    disp($reg);  // Stack Offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4296
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4297
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4298
operand stackSlotL(sRegL reg) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4299
  constraint(ALLOC_IN_RC(stack_slots));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4300
  op_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4301
  //match(RegL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4302
  format %{ "[$reg]" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4303
  interface(MEMORY_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4304
    base(0xE);   // R_SP
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4305
    index(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4306
    scale(0x0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4307
    disp($reg);  // Stack Offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4308
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4309
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4310
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4311
// Operands for expressing Control Flow
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4312
// NOTE:  Label is a predefined operand which should not be redefined in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4313
//        the AD file.  It is generically handled within the ADLC.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4314
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4315
//----------Conditional Branch Operands----------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4316
// Comparison Op  - This is the operation of the comparison, and is limited to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4317
//                  the following set of codes:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4318
//                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4319
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4320
// Other attributes of the comparison, such as unsignedness, are specified
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4321
// by the comparison instruction that sets a condition code flags register.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4322
// That result is represented by a flags operand whose subtype is appropriate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4323
// to the unsignedness (etc.) of the comparison.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4324
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4325
// Later, the instruction which matches both the Comparison Op (a Bool) and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4326
// the flags (produced by the Cmp) specifies the coding of the comparison op
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4327
// by matching a specific subtype of Bool operand below, such as cmpOpU.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4328
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4329
operand cmpOp() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4330
  match(Bool);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4331
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4332
  format %{ "" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4333
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4334
    equal(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4335
    not_equal(0x9);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4336
    less(0x3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4337
    greater_equal(0xB);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4338
    less_equal(0x2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4339
    greater(0xA);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4340
    overflow(0x7);
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4341
    no_overflow(0xF);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4342
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4343
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4344
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4345
// Comparison Op, unsigned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4346
operand cmpOpU() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4347
  match(Bool);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4348
  predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4349
            n->as_Bool()->_test._test != BoolTest::no_overflow);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4350
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4351
  format %{ "u" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4352
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4353
    equal(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4354
    not_equal(0x9);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4355
    less(0x5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4356
    greater_equal(0xD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4357
    less_equal(0x4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4358
    greater(0xC);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4359
    overflow(0x7);
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4360
    no_overflow(0xF);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4361
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4362
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4363
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4364
// Comparison Op, pointer (same as unsigned)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4365
operand cmpOpP() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4366
  match(Bool);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4367
  predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4368
            n->as_Bool()->_test._test != BoolTest::no_overflow);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4369
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4370
  format %{ "p" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4371
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4372
    equal(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4373
    not_equal(0x9);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4374
    less(0x5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4375
    greater_equal(0xD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4376
    less_equal(0x4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4377
    greater(0xC);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4378
    overflow(0x7);
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4379
    no_overflow(0xF);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4380
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4381
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4382
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4383
// Comparison Op, branch-register encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4384
operand cmpOp_reg() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4385
  match(Bool);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4386
  predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4387
            n->as_Bool()->_test._test != BoolTest::no_overflow);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4388
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4389
  format %{ "" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4390
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4391
    equal        (0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4392
    not_equal    (0x5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4393
    less         (0x3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4394
    greater_equal(0x7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4395
    less_equal   (0x2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4396
    greater      (0x6);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4397
    overflow(0x7); // not supported
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4398
    no_overflow(0xF); // not supported
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4399
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4400
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4401
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4402
// Comparison Code, floating, unordered same as less
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4403
operand cmpOpF() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4404
  match(Bool);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4405
  predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4406
            n->as_Bool()->_test._test != BoolTest::no_overflow);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4407
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4408
  format %{ "fl" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4409
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4410
    equal(0x9);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4411
    not_equal(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4412
    less(0x3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4413
    greater_equal(0xB);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4414
    less_equal(0xE);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4415
    greater(0x6);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4416
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4417
    overflow(0x7); // not supported
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4418
    no_overflow(0xF); // not supported
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4419
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4420
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4421
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4422
// Used by long compare
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4423
operand cmpOp_commute() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4424
  match(Bool);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4425
  predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4426
            n->as_Bool()->_test._test != BoolTest::no_overflow);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4427
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4428
  format %{ "" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4429
  interface(COND_INTER) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4430
    equal(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4431
    not_equal(0x9);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4432
    less(0xA);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4433
    greater_equal(0x2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4434
    less_equal(0xB);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4435
    greater(0x3);
20289
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4436
    overflow(0x7);
35d78de0c547 8024924: Intrinsify java.lang.Math.addExact
rbackman
parents: 19979
diff changeset
  4437
    no_overflow(0xF);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4438
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4439
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4440
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4441
//----------OPERAND CLASSES----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4442
// Operand Classes are groups of operands that are used to simplify
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
  4443
// instruction definitions by not requiring the AD writer to specify separate
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4444
// instructions for every form of operand when the instruction accepts
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4445
// multiple operand types with the same basic encoding and format.  The classic
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4446
// case of this is memory operands.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4447
opclass memory( indirect, indOffset13, indIndex );
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
  4448
opclass indIndexMemory( indIndex );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4449
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4450
//----------PIPELINE-----------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4451
pipeline %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4452
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4453
//----------ATTRIBUTES---------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4454
attributes %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4455
  fixed_size_instructions;           // Fixed size instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4456
  branch_has_delay_slot;             // Branch has delay slot following
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4457
  max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4458
  instruction_unit_size = 4;         // An instruction is 4 bytes long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4459
  instruction_fetch_unit_size = 16;  // The processor fetches one line
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4460
  instruction_fetch_units = 1;       // of 16 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4461
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4462
  // List of nop instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4463
  nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4464
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4465
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4466
//----------RESOURCES----------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4467
// Resources are the functional units available to the machine
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4468
resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4469
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4470
//----------PIPELINE DESCRIPTION-----------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4471
// Pipeline Description specifies the stages in the machine's pipeline
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4472
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4473
pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4474
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4475
//----------PIPELINE CLASSES---------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4476
// Pipeline Classes describe the stages in which input and output are
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4477
// referenced by the hardware pipeline.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4478
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4479
// Integer ALU reg-reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4480
pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4481
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4482
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4483
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4484
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4485
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4486
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4487
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4488
// Integer ALU reg-reg long operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4489
pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4490
    instruction_count(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4491
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4492
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4493
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4494
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4495
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4496
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4497
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4498
// Integer ALU reg-reg long dependent operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4499
pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4500
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4501
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4502
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4503
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4504
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4505
    IALU  : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4506
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4507
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4508
// Integer ALU reg-imm operaion
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4509
pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4510
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4511
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4512
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4513
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4514
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4516
// Integer ALU reg-reg operation with condition code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4517
pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4518
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4519
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4520
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4521
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4522
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4523
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4524
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4525
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4526
// Integer ALU reg-imm operation with condition code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4527
pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4528
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4529
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4530
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4531
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4532
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4533
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4534
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4535
// Integer ALU zero-reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4536
pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4537
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4538
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4539
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4540
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4541
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4542
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4543
// Integer ALU zero-reg operation with condition code only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4544
pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4545
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4546
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4547
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4548
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4549
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4550
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4551
// Integer ALU reg-reg operation with condition code only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4552
pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4553
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4554
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4555
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4556
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4557
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4558
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4559
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4560
// Integer ALU reg-imm operation with condition code only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4561
pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4562
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4563
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4564
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4565
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4566
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4567
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4568
// Integer ALU reg-reg-zero operation with condition code only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4569
pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4570
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4571
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4572
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4573
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4574
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4575
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4576
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4577
// Integer ALU reg-imm-zero operation with condition code only
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4578
pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4579
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4580
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4581
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4582
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4583
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4584
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4585
// Integer ALU reg-reg operation with condition code, src1 modified
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4586
pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4587
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4588
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4589
    src1  : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4590
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4591
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4592
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4593
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4594
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4595
// Integer ALU reg-imm operation with condition code, src1 modified
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4596
pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4597
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4598
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4599
    src1  : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4600
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4601
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4602
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4603
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4604
pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4605
    multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4606
    dst   : E(write)+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4607
    cr    : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4608
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4609
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4610
    IALU  : R(3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4611
    BR    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4612
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4613
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4614
// Integer ALU operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4615
pipe_class ialu_none(iRegI dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4616
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4617
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4618
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4619
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4620
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4621
// Integer ALU reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4622
pipe_class ialu_reg(iRegI dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4623
    single_instruction; may_have_no_code;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4624
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4625
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4626
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4627
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4628
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4629
// Integer ALU reg conditional operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4630
// This instruction has a 1 cycle stall, and cannot execute
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4631
// in the same cycle as the instruction setting the condition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4632
// code. We kludge this by pretending to read the condition code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4633
// 1 cycle earlier, and by marking the functional units as busy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4634
// for 2 cycles with the result available 1 cycle later than
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4635
// is really the case.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4636
pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4637
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4638
    op2_out : C(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4639
    op1     : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4640
    cr      : R(read);       // This is really E, with a 1 cycle stall
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4641
    BR      : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4642
    MS      : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4643
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4644
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4645
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4646
pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4647
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4648
    dst     : C(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4649
    src     : R(read)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4650
    IALU    : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4651
    BR      : E(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4652
    MS      : E(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4653
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4654
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4655
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4656
// Integer ALU reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4657
pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4658
    single_instruction; may_have_no_code;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4659
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4660
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4661
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4662
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4663
pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4664
    single_instruction; may_have_no_code;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4665
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4666
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4667
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4668
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4669
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4670
// Two integer ALU reg operations
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4671
pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4672
    instruction_count(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4673
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4674
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4675
    A0    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4676
    A1    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4677
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4678
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4679
// Two integer ALU reg operations
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4680
pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4681
    instruction_count(2); may_have_no_code;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4682
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4683
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4684
    A0    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4685
    A1    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4686
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4687
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4688
// Integer ALU imm operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4689
pipe_class ialu_imm(iRegI dst, immI13 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4690
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4691
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4692
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4693
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4694
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4695
// Integer ALU reg-reg with carry operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4696
pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4697
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4698
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4699
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4700
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4701
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4702
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4703
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4704
// Integer ALU cc operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4705
pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4706
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4707
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4708
    cc    : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4709
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4710
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4711
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4712
// Integer ALU cc / second IALU operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4713
pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4714
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4715
    dst   : E(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4716
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4717
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4718
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4719
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4720
// Integer ALU cc / second IALU operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4721
pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4722
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4723
    dst   : E(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4724
    p     : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4725
    q     : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4726
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4727
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4728
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4729
// Integer ALU hi-lo-reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4730
pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4731
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4732
    dst   : E(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4733
    IALU  : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4734
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4735
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4736
// Float ALU hi-lo-reg operation (with temp)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4737
pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4738
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4739
    dst   : E(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4740
    IALU  : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4741
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4742
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4743
// Long Constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4744
pipe_class loadConL( iRegL dst, immL src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4745
    instruction_count(2); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4746
    dst   : E(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4747
    IALU  : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4748
    IALU  : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4749
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4750
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4751
// Pointer Constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4752
pipe_class loadConP( iRegP dst, immP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4753
    instruction_count(0); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4754
    fixed_latency(6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4755
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4756
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4757
// Polling Address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4758
pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4759
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4760
    instruction_count(0); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4761
    fixed_latency(6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4762
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4763
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4764
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4765
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4766
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4768
// Long Constant small
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4769
pipe_class loadConLlo( iRegL dst, immL src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4770
    instruction_count(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4771
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4772
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4773
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4774
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4775
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4776
// [PHH] This is wrong for 64-bit.  See LdImmF/D.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4777
pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4778
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4779
    src   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4780
    dst   : M(write)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4781
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4782
    MS    : E;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4783
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4784
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4785
// Integer ALU nop operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4786
pipe_class ialu_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4787
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4788
    IALU  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4789
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4790
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4791
// Integer ALU nop operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4792
pipe_class ialu_nop_A0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4793
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4794
    A0    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4795
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4796
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4797
// Integer ALU nop operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4798
pipe_class ialu_nop_A1() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4799
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4800
    A1    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4801
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4802
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4803
// Integer Multiply reg-reg operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4804
pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4805
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4806
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4807
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4808
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4809
    MS    : R(5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4810
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4811
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4812
// Integer Multiply reg-imm operation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4813
pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4814
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4815
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4816
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4817
    MS    : R(5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4818
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4819
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4820
pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4821
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4822
    dst   : E(write)+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4823
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4824
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4825
    MS    : R(6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4826
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4827
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4828
pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4829
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4830
    dst   : E(write)+4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4831
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4832
    MS    : R(6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4833
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4834
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4835
// Integer Divide reg-reg
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4836
pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4837
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4838
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4839
    temp  : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4840
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4841
    src2  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4842
    temp  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4843
    MS    : R(38);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4844
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4845
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4846
// Integer Divide reg-imm
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4847
pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4848
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4849
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4850
    temp  : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4851
    src1  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4852
    temp  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4853
    MS    : R(38);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4854
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4855
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4856
// Long Divide
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4857
pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4858
    dst  : E(write)+71;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4859
    src1 : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4860
    src2 : R(read)+1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4861
    MS   : R(70);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4862
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4863
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4864
pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4865
    dst  : E(write)+71;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4866
    src1 : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4867
    MS   : R(70);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4868
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4869
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4870
// Floating Point Add Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4871
pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4872
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4873
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4874
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4875
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4876
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4877
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4878
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4879
// Floating Point Add Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4880
pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4881
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4882
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4883
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4884
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4885
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4886
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4887
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4888
// Floating Point Conditional Move based on integer flags
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4889
pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4890
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4891
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4892
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4893
    cr    : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4894
    FA    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4895
    BR    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4896
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4897
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4898
// Floating Point Conditional Move based on integer flags
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4899
pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4900
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4901
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4902
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4903
    cr    : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4904
    FA    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4905
    BR    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4906
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4907
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4908
// Floating Point Multiply Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4909
pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4910
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4911
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4912
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4913
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4914
    FM    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4915
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4916
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4917
// Floating Point Multiply Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4918
pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4919
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4920
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4921
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4922
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4923
    FM    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4924
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4925
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4926
// Floating Point Divide Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4927
pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4928
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4929
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4930
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4931
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4932
    FM    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4933
    FDIV  : C(14);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4934
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4935
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4936
// Floating Point Divide Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4937
pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4938
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4939
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4940
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4941
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4942
    FM    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4943
    FDIV  : C(17);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4944
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4945
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4946
// Floating Point Move/Negate/Abs Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4947
pipe_class faddF_reg(regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4948
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4949
    dst   : W(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4950
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4951
    FA    : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4952
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4953
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4954
// Floating Point Move/Negate/Abs Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4955
pipe_class faddD_reg(regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4956
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4957
    dst   : W(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4958
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4959
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4960
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4961
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4962
// Floating Point Convert F->D
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4963
pipe_class fcvtF2D(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4964
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4965
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4966
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4967
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4968
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4969
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4970
// Floating Point Convert I->D
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4971
pipe_class fcvtI2D(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4972
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4973
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4974
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4975
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4976
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4977
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4978
// Floating Point Convert LHi->D
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4979
pipe_class fcvtLHi2D(regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4980
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4981
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4982
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4983
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4984
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4985
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4986
// Floating Point Convert L->D
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4987
pipe_class fcvtL2D(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4988
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4989
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4990
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4991
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4992
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4993
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4994
// Floating Point Convert L->F
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4995
pipe_class fcvtL2F(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4996
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4997
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4998
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4999
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5000
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5001
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5002
// Floating Point Convert D->F
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5003
pipe_class fcvtD2F(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5004
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5005
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5006
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5007
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5008
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5009
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5010
// Floating Point Convert I->L
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5011
pipe_class fcvtI2L(regD dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5012
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5013
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5014
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5015
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5016
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5017
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5018
// Floating Point Convert D->F
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5019
pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5020
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5021
    dst   : X(write)+6;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5022
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5023
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5024
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5025
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5026
// Floating Point Convert D->L
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5027
pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5028
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5029
    dst   : X(write)+6;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5030
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5031
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5032
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5033
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5034
// Floating Point Convert F->I
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5035
pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5036
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5037
    dst   : X(write)+6;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5038
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5039
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5040
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5041
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5042
// Floating Point Convert F->L
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5043
pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5044
    instruction_count(1); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5045
    dst   : X(write)+6;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5046
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5047
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5048
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5050
// Floating Point Convert I->F
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5051
pipe_class fcvtI2F(regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5052
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5053
    dst   : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5054
    src   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5055
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5056
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5057
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5058
// Floating Point Compare
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5059
pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5060
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5061
    cr    : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5062
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5063
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5064
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5065
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5066
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5067
// Floating Point Compare
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5068
pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5069
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5070
    cr    : X(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5071
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5072
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5073
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5074
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5075
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5076
// Floating Add Nop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5077
pipe_class fadd_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5078
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5079
    FA  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5080
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5081
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5082
// Integer Store to Memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5083
pipe_class istore_mem_reg(memory mem, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5084
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5085
    mem   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5086
    src   : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5087
    MS    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5088
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5089
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5090
// Integer Store to Memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5091
pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5092
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5093
    mem   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5094
    src   : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5095
    MS    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5096
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5097
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5098
// Integer Store Zero to Memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5099
pipe_class istore_mem_zero(memory mem, immI0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5100
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5101
    mem   : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5102
    MS    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5103
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5104
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5105
// Special Stack Slot Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5106
pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5107
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5108
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5109
    src     : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5110
    MS      : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5111
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5112
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5113
// Special Stack Slot Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5114
pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5115
    instruction_count(2); multiple_bundles;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5116
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5117
    src     : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5118
    MS      : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5119
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5120
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5121
// Float Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5122
pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5123
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5124
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5125
    src : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5126
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5127
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5128
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5129
// Float Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5130
pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5131
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5132
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5133
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5134
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5135
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5136
// Double Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5137
pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5138
    instruction_count(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5139
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5140
    src : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5141
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5142
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5143
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5144
// Double Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5145
pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5146
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5147
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5148
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5149
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5151
// Special Stack Slot Float Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5152
pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5153
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5154
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5155
    src     : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5156
    MS      : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5157
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5158
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5159
// Special Stack Slot Double Store
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5160
pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5161
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5162
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5163
    src     : C(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5164
    MS      : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5165
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5166
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5167
// Integer Load (when sign bit propagation not needed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5168
pipe_class iload_mem(iRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5169
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5170
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5171
    dst : C(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5172
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5173
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5174
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5175
// Integer Load from stack operand
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5176
pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5177
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5178
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5179
    dst : C(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5180
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5181
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5182
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5183
// Integer Load (when sign bit propagation or masking is needed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5184
pipe_class iload_mask_mem(iRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5185
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5186
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5187
    dst : M(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5188
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5189
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5190
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5191
// Float Load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5192
pipe_class floadF_mem(regF dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5193
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5194
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5195
    dst : M(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5196
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5197
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5198
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5199
// Float Load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5200
pipe_class floadD_mem(regD dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5201
    instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5202
    mem : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5203
    dst : M(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5204
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5205
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5206
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5207
// Float Load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5208
pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5209
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5210
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5211
    dst : M(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5212
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5213
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5214
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5215
// Float Load
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5216
pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5217
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5218
    stkSlot : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5219
    dst : M(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5220
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5221
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5222
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5223
// Memory Nop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5224
pipe_class mem_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5225
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5226
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5227
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5228
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5229
pipe_class sethi(iRegP dst, immI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5230
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5231
    dst  : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5232
    IALU : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5233
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5234
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5235
pipe_class loadPollP(iRegP poll) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5236
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5237
    poll : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5238
    MS   : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5239
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5240
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5241
pipe_class br(Universe br, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5242
    single_instruction_with_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5243
    BR  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5244
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5245
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5246
pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5247
    single_instruction_with_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5248
    cr    : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5249
    BR    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5250
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5251
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5252
pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5253
    single_instruction_with_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5254
    op1 : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5255
    BR  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5256
    MS  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5257
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5258
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5259
// Compare and branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5260
pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5261
    instruction_count(2); has_delay_slot;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5262
    cr    : E(write);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5263
    src1  : R(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5264
    src2  : R(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5265
    IALU  : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5266
    BR    : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5267
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5268
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5269
// Compare and branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5270
pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5271
    instruction_count(2); has_delay_slot;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5272
    cr    : E(write);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5273
    src1  : R(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5274
    IALU  : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5275
    BR    : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5276
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5277
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5278
// Compare and branch using cbcond
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5279
pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5280
    single_instruction;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5281
    src1  : E(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5282
    src2  : E(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5283
    IALU  : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5284
    BR    : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5285
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5286
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5287
// Compare and branch using cbcond
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5288
pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5289
    single_instruction;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5290
    src1  : E(read);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5291
    IALU  : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5292
    BR    : R;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5293
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  5294
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5295
pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5296
    single_instruction_with_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5297
    cr    : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5298
    BR    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5299
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5300
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5301
pipe_class br_nop() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5302
    single_instruction;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5303
    BR  : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5304
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5305
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5306
pipe_class simple_call(method meth) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5307
    instruction_count(2); multiple_bundles; force_serialization;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5308
    fixed_latency(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5309
    BR  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5310
    MS  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5311
    A0  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5312
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5313
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5314
pipe_class compiled_call(method meth) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5315
    instruction_count(1); multiple_bundles; force_serialization;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5316
    fixed_latency(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5317
    MS  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5318
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5319
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5320
pipe_class call(method meth) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5321
    instruction_count(0); multiple_bundles; force_serialization;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5322
    fixed_latency(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5323
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5324
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5325
pipe_class tail_call(Universe ignore, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5326
    single_instruction; has_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5327
    fixed_latency(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5328
    BR  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5329
    MS  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5330
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5331
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5332
pipe_class ret(Universe ignore) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5333
    single_instruction; has_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5334
    BR  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5335
    MS  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5336
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5337
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5338
pipe_class ret_poll(g3RegP poll) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5339
    instruction_count(3); has_delay_slot;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5340
    poll : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5341
    MS   : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5342
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5343
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5344
// The real do-nothing guy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5345
pipe_class empty( ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5346
    instruction_count(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5347
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5348
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5349
pipe_class long_memory_op() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5350
    instruction_count(0); multiple_bundles; force_serialization;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5351
    fixed_latency(25);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5352
    MS  : R(1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5353
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5354
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5355
// Check-cast
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5356
pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5357
    array : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5358
    match  : R(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5359
    IALU   : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5360
    BR     : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5361
    MS     : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5362
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5363
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5364
// Convert FPU flags into +1,0,-1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5365
pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5366
    src1  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5367
    src2  : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5368
    dst   : E(write);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5369
    FA    : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5370
    MS    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5371
    BR    : R(2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5372
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5373
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5374
// Compare for p < q, and conditionally add y
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5375
pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5376
    p     : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5377
    q     : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5378
    y     : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5379
    IALU  : R(3)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5380
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5381
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5382
// Perform a compare, then move conditionally in a branch delay slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5383
pipe_class min_max( iRegI src2, iRegI srcdst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5384
    src2   : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5385
    srcdst : E(read);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5386
    IALU   : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5387
    BR     : R;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5388
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5389
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5390
// Define the class for the Nop node
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5391
define %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5392
   MachNop = ialu_nop;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5393
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5394
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5395
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5396
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5397
//----------INSTRUCTIONS-------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5398
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5399
//------------Special Stack Slot instructions - no match rules-----------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5400
instruct stkI_to_regF(regF dst, stackSlotI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5401
  // No match rule to avoid chain rule match.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5402
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5403
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5404
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5405
  format %{ "LDF    $src,$dst\t! stkI to regF" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5406
  opcode(Assembler::ldf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5407
  ins_encode(simple_form3_mem_reg(src, dst));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5408
  ins_pipe(floadF_stk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5409
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5410
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5411
instruct stkL_to_regD(regD dst, stackSlotL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5412
  // No match rule to avoid chain rule match.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5413
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5414
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5415
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5416
  format %{ "LDDF   $src,$dst\t! stkL to regD" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5417
  opcode(Assembler::lddf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5418
  ins_encode(simple_form3_mem_reg(src, dst));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5419
  ins_pipe(floadD_stk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5420
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5421
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5422
instruct regF_to_stkI(stackSlotI dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5423
  // No match rule to avoid chain rule match.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5424
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5425
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5426
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5427
  format %{ "STF    $src,$dst\t! regF to stkI" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5428
  opcode(Assembler::stf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5429
  ins_encode(simple_form3_mem_reg(dst, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5430
  ins_pipe(fstoreF_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5431
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5432
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5433
instruct regD_to_stkL(stackSlotL dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5434
  // No match rule to avoid chain rule match.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5435
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5436
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5437
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5438
  format %{ "STDF   $src,$dst\t! regD to stkL" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5439
  opcode(Assembler::stdf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5440
  ins_encode(simple_form3_mem_reg(dst, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5441
  ins_pipe(fstoreD_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5442
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5443
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5444
instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5445
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5446
  ins_cost(MEMORY_REF_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5447
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5448
  format %{ "STW    $src,$dst.hi\t! long\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5449
            "STW    R_G0,$dst.lo" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5450
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5451
  ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5452
  ins_pipe(lstoreI_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5453
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5454
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5455
instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5456
  // No match rule to avoid chain rule match.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5457
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5458
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5459
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5460
  format %{ "STX    $src,$dst\t! regL to stkD" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5461
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5462
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5463
  ins_pipe(istore_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5464
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5465
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5466
//---------- Chain stack slots between similar types --------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5467
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5468
// Load integer from stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5469
instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5470
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5471
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5472
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5473
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5474
  format %{ "LDUW   $src,$dst\t!stk" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5475
  opcode(Assembler::lduw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5476
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5477
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5478
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5479
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5480
// Store integer to stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5481
instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5482
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5483
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5484
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5485
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5486
  format %{ "STW    $src,$dst\t!stk" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5487
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5488
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5489
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5490
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5491
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5492
// Load long from stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5493
instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5494
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5495
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5496
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5497
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5498
  format %{ "LDX    $src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5499
  opcode(Assembler::ldx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5500
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5501
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5502
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5503
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5504
// Store long to stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5505
instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5506
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5507
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5508
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5509
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5510
  format %{ "STX    $src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5511
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5512
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5513
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5514
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5516
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5517
// Load pointer from stack slot, 64-bit encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5518
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5519
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5520
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5521
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5522
  format %{ "LDX    $src,$dst\t!ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5523
  opcode(Assembler::ldx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5524
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5525
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5526
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5527
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5528
// Store pointer to stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5529
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5530
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5531
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5532
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5533
  format %{ "STX    $src,$dst\t!ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5534
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5535
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5536
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5537
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5538
#else // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5539
// Load pointer from stack slot, 32-bit encoding
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5540
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5541
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5542
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5543
  format %{ "LDUW   $src,$dst\t!ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5544
  opcode(Assembler::lduw_op3, Assembler::ldst_op);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5545
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5546
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5547
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5548
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5549
// Store pointer to stack slot
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5550
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5551
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5552
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5553
  format %{ "STW    $src,$dst\t!ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5554
  opcode(Assembler::stw_op3, Assembler::ldst_op);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5555
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5556
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5557
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5558
#endif // _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5559
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5560
//------------Special Nop instructions for bundling - no match rules-----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5561
// Nop using the A0 functional unit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5562
instruct Nop_A0() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5563
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5564
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5565
  format %{ "NOP    ! Alu Pipeline" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5566
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5567
  ins_encode( form2_nop() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5568
  ins_pipe(ialu_nop_A0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5569
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5570
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5571
// Nop using the A1 functional unit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5572
instruct Nop_A1( ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5573
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5574
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5575
  format %{ "NOP    ! Alu Pipeline" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5576
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5577
  ins_encode( form2_nop() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5578
  ins_pipe(ialu_nop_A1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5579
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5580
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5581
// Nop using the memory functional unit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5582
instruct Nop_MS( ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5583
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5584
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5585
  format %{ "NOP    ! Memory Pipeline" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5586
  ins_encode( emit_mem_nop );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5587
  ins_pipe(mem_nop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5588
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5589
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5590
// Nop using the floating add functional unit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5591
instruct Nop_FA( ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5592
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5593
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5594
  format %{ "NOP    ! Floating Add Pipeline" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5595
  ins_encode( emit_fadd_nop );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5596
  ins_pipe(fadd_nop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5597
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5598
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5599
// Nop using the branch functional unit
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5600
instruct Nop_BR( ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5601
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5602
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5603
  format %{ "NOP    ! Branch Pipeline" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5604
  ins_encode( emit_br_nop );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5605
  ins_pipe(br_nop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5606
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5607
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5608
//----------Load/Store/Move Instructions---------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5609
//----------Load Instructions--------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5610
// Load Byte (8bit signed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5611
instruct loadB(iRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5612
  match(Set dst (LoadB mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5613
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5614
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5615
  size(4);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5616
  format %{ "LDSB   $mem,$dst\t! byte" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5617
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5618
    __ ldsb($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5619
  %}
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5620
  ins_pipe(iload_mask_mem);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5621
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5622
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5623
// Load Byte (8bit signed) into a Long Register
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5624
instruct loadB2L(iRegL dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5625
  match(Set dst (ConvI2L (LoadB mem)));
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5626
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5627
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5628
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5629
  format %{ "LDSB   $mem,$dst\t! byte -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5630
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5631
    __ ldsb($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5632
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5633
  ins_pipe(iload_mask_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5634
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5635
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5636
// Load Unsigned Byte (8bit UNsigned) into an int reg
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5637
instruct loadUB(iRegI dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5638
  match(Set dst (LoadUB mem));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5639
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5640
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5641
  size(4);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5642
  format %{ "LDUB   $mem,$dst\t! ubyte" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5643
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5644
    __ ldub($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5645
  %}
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5646
  ins_pipe(iload_mem);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5647
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5648
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5649
// Load Unsigned Byte (8bit UNsigned) into a Long Register
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5650
instruct loadUB2L(iRegL dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5651
  match(Set dst (ConvI2L (LoadUB mem)));
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5652
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5653
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5654
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5655
  format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5656
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5657
    __ ldub($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5658
  %}
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5659
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5660
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5661
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5662
// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5663
instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5664
  match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5665
  ins_cost(MEMORY_REF_COST + DEFAULT_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5666
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5667
  size(2*4);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5668
  format %{ "LDUB   $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5669
            "AND    $dst,$mask,$dst" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5670
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5671
    __ ldub($mem$$Address, $dst$$Register);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5672
    __ and3($dst$$Register, $mask$$constant, $dst$$Register);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5673
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5674
  ins_pipe(iload_mem);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5675
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5676
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5677
// Load Short (16bit signed)
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5678
instruct loadS(iRegI dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5679
  match(Set dst (LoadS mem));
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5680
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5681
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5682
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5683
  format %{ "LDSH   $mem,$dst\t! short" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5684
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5685
    __ ldsh($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5686
  %}
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5687
  ins_pipe(iload_mask_mem);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5688
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5689
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5690
// Load Short (16 bit signed) to Byte (8 bit signed)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5691
instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5692
  match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5693
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5694
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5695
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5696
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5697
  format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5698
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5699
    __ ldsb($mem$$Address, $dst$$Register, 1);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5700
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5701
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5702
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5703
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5704
// Load Short (16bit signed) into a Long Register
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5705
instruct loadS2L(iRegL dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5706
  match(Set dst (ConvI2L (LoadS mem)));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5707
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5708
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5709
  size(4);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5710
  format %{ "LDSH   $mem,$dst\t! short -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5711
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5712
    __ ldsh($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5713
  %}
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5714
  ins_pipe(iload_mask_mem);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5715
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5716
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5717
// Load Unsigned Short/Char (16bit UNsigned)
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5718
instruct loadUS(iRegI dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5719
  match(Set dst (LoadUS mem));
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5720
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5721
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5722
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5723
  format %{ "LDUH   $mem,$dst\t! ushort/char" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5724
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5725
    __ lduh($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5726
  %}
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5727
  ins_pipe(iload_mem);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5728
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5729
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5730
// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5731
instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5732
  match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5733
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5734
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5735
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5736
  format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5737
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5738
    __ ldsb($mem$$Address, $dst$$Register, 1);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5739
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5740
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5741
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5742
2022
28ce8115a91d 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 2015
diff changeset
  5743
// Load Unsigned Short/Char (16bit UNsigned) into a Long Register
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5744
instruct loadUS2L(iRegL dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5745
  match(Set dst (ConvI2L (LoadUS mem)));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5746
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5747
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5748
  size(4);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5749
  format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5750
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5751
    __ lduh($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5752
  %}
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5753
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5754
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5755
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5756
// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5757
instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5758
  match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5759
  ins_cost(MEMORY_REF_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5760
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5761
  size(4);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5762
  format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5763
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5764
    __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5765
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5766
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5767
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5768
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5769
// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5770
instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5771
  match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5772
  ins_cost(MEMORY_REF_COST + DEFAULT_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5773
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5774
  size(2*4);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5775
  format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5776
            "AND    $dst,$mask,$dst" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5777
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5778
    Register Rdst = $dst$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5779
    __ lduh($mem$$Address, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5780
    __ and3(Rdst, $mask$$constant, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5781
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5782
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5783
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5784
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5785
// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5786
instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5787
  match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5788
  effect(TEMP dst, TEMP tmp);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5789
  ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5790
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5791
  format %{ "LDUH   $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5792
            "SET    $mask,$tmp\n\t"
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5793
            "AND    $dst,$tmp,$dst" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5794
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5795
    Register Rdst = $dst$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5796
    Register Rtmp = $tmp$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5797
    __ lduh($mem$$Address, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5798
    __ set($mask$$constant, Rtmp);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5799
    __ and3(Rdst, Rtmp, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5800
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5801
  ins_pipe(iload_mem);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5802
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5803
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5804
// Load Integer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5805
instruct loadI(iRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5806
  match(Set dst (LoadI mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5807
  ins_cost(MEMORY_REF_COST);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5808
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5809
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5810
  format %{ "LDUW   $mem,$dst\t! int" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5811
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5812
    __ lduw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5813
  %}
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5814
  ins_pipe(iload_mem);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5815
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5816
2872
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5817
// Load Integer to Byte (8 bit signed)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5818
instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5819
  match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5820
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5821
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5822
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5823
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5824
  format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5825
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5826
    __ ldsb($mem$$Address, $dst$$Register, 3);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5827
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5828
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5829
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5830
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5831
// Load Integer to Unsigned Byte (8 bit UNsigned)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5832
instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5833
  match(Set dst (AndI (LoadI mem) mask));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5834
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5835
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5836
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5837
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5838
  format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5839
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5840
    __ ldub($mem$$Address, $dst$$Register, 3);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5841
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5842
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5843
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5844
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5845
// Load Integer to Short (16 bit signed)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5846
instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5847
  match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5848
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5849
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5850
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5851
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5852
  format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5853
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5854
    __ ldsh($mem$$Address, $dst$$Register, 2);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5855
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5856
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5857
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5858
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5859
// Load Integer to Unsigned Short (16 bit UNsigned)
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5860
instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5861
  match(Set dst (AndI (LoadI mem) mask));
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5862
  ins_cost(MEMORY_REF_COST);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5863
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5864
  size(4);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5865
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5866
  format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5867
  ins_encode %{
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5868
    __ lduh($mem$$Address, $dst$$Register, 2);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5869
  %}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5870
  ins_pipe(iload_mask_mem);
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5871
%}
93eb5ac6cfb0 6814842: Load shortening optimizations
twisti
parents: 2862
diff changeset
  5872
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5873
// Load Integer into a Long Register
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5874
instruct loadI2L(iRegL dst, memory mem) %{
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5875
  match(Set dst (ConvI2L (LoadI mem)));
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5876
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5877
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5878
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5879
  format %{ "LDSW   $mem,$dst\t! int -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5880
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5881
    __ ldsw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5882
  %}
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5883
  ins_pipe(iload_mask_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5884
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5885
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5886
// Load Integer with mask 0xFF into a Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5887
instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5888
  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5889
  ins_cost(MEMORY_REF_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5890
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5891
  size(4);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5892
  format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5893
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5894
    __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5895
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5896
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5897
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5898
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5899
// Load Integer with mask 0xFFFF into a Long Register
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5900
instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5901
  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5902
  ins_cost(MEMORY_REF_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5903
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5904
  size(4);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5905
  format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5906
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5907
    __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5908
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5909
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5910
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5911
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5912
// Load Integer with a 12-bit mask into a Long Register
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5913
instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5914
  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5915
  ins_cost(MEMORY_REF_COST + DEFAULT_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5916
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5917
  size(2*4);
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5918
  format %{ "LDUW   $mem,$dst\t! int & 12-bit mask -> long\n\t"
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5919
            "AND    $dst,$mask,$dst" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5920
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5921
    Register Rdst = $dst$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5922
    __ lduw($mem$$Address, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5923
    __ and3(Rdst, $mask$$constant, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5924
  %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5925
  ins_pipe(iload_mem);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5926
%}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5927
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5928
// Load Integer with a 31-bit mask into a Long Register
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5929
instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5930
  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5931
  effect(TEMP dst, TEMP tmp);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5932
  ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5933
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  5934
  format %{ "LDUW   $mem,$dst\t! int & 31-bit mask -> long\n\t"
3177
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5935
            "SET    $mask,$tmp\n\t"
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5936
            "AND    $dst,$tmp,$dst" %}
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5937
  ins_encode %{
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5938
    Register Rdst = $dst$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5939
    Register Rtmp = $tmp$$Register;
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5940
    __ lduw($mem$$Address, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5941
    __ set($mask$$constant, Rtmp);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5942
    __ and3(Rdst, Rtmp, Rdst);
f467776fc753 5057225: Remove useless I2L conversions
twisti
parents: 2872
diff changeset
  5943
  %}
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5944
  ins_pipe(iload_mem);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5945
%}
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5946
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5947
// Load Unsigned Integer into a Long Register
13970
11a9630698a6 7199654: Remove LoadUI2LNode
vlivanov
parents: 13969
diff changeset
  5948
instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
11a9630698a6 7199654: Remove LoadUI2LNode
vlivanov
parents: 13969
diff changeset
  5949
  match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5950
  ins_cost(MEMORY_REF_COST);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5951
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5952
  size(4);
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5953
  format %{ "LDUW   $mem,$dst\t! uint -> long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5954
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5955
    __ lduw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5956
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5957
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5958
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5959
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5960
// Load Long - aligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5961
instruct loadL(iRegL dst, memory mem ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5962
  match(Set dst (LoadL mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5963
  ins_cost(MEMORY_REF_COST);
2150
0d91d17158cc 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 2131
diff changeset
  5964
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5965
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5966
  format %{ "LDX    $mem,$dst\t! long" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5967
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5968
    __ ldx($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  5969
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5970
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5971
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5972
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5973
// Load Long - UNaligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5974
instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5975
  match(Set dst (LoadL_unaligned mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5976
  effect(KILL tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5977
  ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5978
  size(16);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5979
  format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5980
          "\tLDUW   $mem  ,$dst\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5981
          "\tSLLX   #32, $dst, $dst\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5982
          "\tOR     $dst, R_O7, $dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5983
  opcode(Assembler::lduw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5984
  ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5985
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5986
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5987
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5988
// Load Range
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5989
instruct loadRange(iRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5990
  match(Set dst (LoadRange mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5991
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5992
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5993
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5994
  format %{ "LDUW   $mem,$dst\t! range" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5995
  opcode(Assembler::lduw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  5996
  ins_encode(simple_form3_mem_reg( mem, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5997
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5998
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5999
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6000
// Load Integer into %f register (for fitos/fitod)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6001
instruct loadI_freg(regF dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6002
  match(Set dst (LoadI mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6003
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6004
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6005
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6006
  format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6007
  opcode(Assembler::ldf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6008
  ins_encode(simple_form3_mem_reg( mem, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6009
  ins_pipe(floadF_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6010
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6011
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6012
// Load Pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6013
instruct loadP(iRegP dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6014
  match(Set dst (LoadP mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6015
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6016
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6017
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6018
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6019
  format %{ "LDUW   $mem,$dst\t! ptr" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6020
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6021
    __ lduw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6022
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6023
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6024
  format %{ "LDX    $mem,$dst\t! ptr" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6025
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6026
    __ ldx($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6027
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6028
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6029
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6030
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6031
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6032
// Load Compressed Pointer
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6033
instruct loadN(iRegN dst, memory mem) %{
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6034
  match(Set dst (LoadN mem));
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6035
  ins_cost(MEMORY_REF_COST);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6036
  size(4);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6037
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6038
  format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6039
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6040
    __ lduw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6041
  %}
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6042
  ins_pipe(iload_mem);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6043
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6044
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6045
// Load Klass Pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6046
instruct loadKlass(iRegP dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6047
  match(Set dst (LoadKlass mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6048
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6049
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6050
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6051
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6052
  format %{ "LDUW   $mem,$dst\t! klass ptr" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6053
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6054
    __ lduw($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6055
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6056
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6057
  format %{ "LDX    $mem,$dst\t! klass ptr" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6058
  ins_encode %{
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6059
    __ ldx($mem$$Address, $dst$$Register);
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6060
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6061
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6062
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6063
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6064
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6065
// Load narrow Klass Pointer
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6066
instruct loadNKlass(iRegN dst, memory mem) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6067
  match(Set dst (LoadNKlass mem));
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6068
  ins_cost(MEMORY_REF_COST);
591
04d2e26e6d69 6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents: 590
diff changeset
  6069
  size(4);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6070
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6071
  format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6072
  ins_encode %{
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6073
    __ lduw($mem$$Address, $dst$$Register);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6074
  %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6075
  ins_pipe(iload_mem);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6076
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6077
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6078
// Load Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6079
instruct loadD(regD dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6080
  match(Set dst (LoadD mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6081
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6082
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6083
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6084
  format %{ "LDDF   $mem,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6085
  opcode(Assembler::lddf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6086
  ins_encode(simple_form3_mem_reg( mem, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6087
  ins_pipe(floadD_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6088
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6089
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6090
// Load Double - UNaligned
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6091
instruct loadD_unaligned(regD_low dst, memory mem ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6092
  match(Set dst (LoadD_unaligned mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6093
  ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6094
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6095
  format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6096
          "\tLDF    $mem+4,$dst.lo\t!" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6097
  opcode(Assembler::ldf_op3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6098
  ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6099
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6100
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6101
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6102
// Load Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6103
instruct loadF(regF dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6104
  match(Set dst (LoadF mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6105
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6106
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6107
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6108
  format %{ "LDF    $mem,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6109
  opcode(Assembler::ldf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6110
  ins_encode(simple_form3_mem_reg( mem, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6111
  ins_pipe(floadF_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6112
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6113
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6114
// Load Constant
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6115
instruct loadConI( iRegI dst, immI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6116
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6117
  ins_cost(DEFAULT_COST * 3/2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6118
  format %{ "SET    $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6119
  ins_encode( Set32(src, dst) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6120
  ins_pipe(ialu_hi_lo_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6121
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6122
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6123
instruct loadConI13( iRegI dst, immI13 src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6124
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6125
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6126
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6127
  format %{ "MOV    $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6128
  ins_encode( Set13( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6129
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6130
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6131
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6132
#ifndef _LP64
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6133
instruct loadConP(iRegP dst, immP con) %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6134
  match(Set dst con);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6135
  ins_cost(DEFAULT_COST * 3/2);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6136
  format %{ "SET    $con,$dst\t!ptr" %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6137
  ins_encode %{
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6138
    relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6139
      intptr_t val = $con$$constant;
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6140
    if (constant_reloc == relocInfo::oop_type) {
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6141
      __ set_oop_constant((jobject) val, $dst$$Register);
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6142
    } else if (constant_reloc == relocInfo::metadata_type) {
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6143
      __ set_metadata_constant((Metadata*)val, $dst$$Register);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6144
    } else {          // non-oop pointers, e.g. card mark base, heap top
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6145
      assert(constant_reloc == relocInfo::none, "unexpected reloc type");
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6146
      __ set(val, $dst$$Register);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6147
    }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6148
  %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6149
  ins_pipe(loadConP);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6150
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6151
#else
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6152
instruct loadConP_set(iRegP dst, immP_set con) %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6153
  match(Set dst con);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6154
  ins_cost(DEFAULT_COST * 3/2);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6155
  format %{ "SET    $con,$dst\t! ptr" %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6156
  ins_encode %{
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6157
    relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6158
      intptr_t val = $con$$constant;
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6159
    if (constant_reloc == relocInfo::oop_type) {
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6160
      __ set_oop_constant((jobject) val, $dst$$Register);
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6161
    } else if (constant_reloc == relocInfo::metadata_type) {
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6162
      __ set_metadata_constant((Metadata*)val, $dst$$Register);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6163
    } else {          // non-oop pointers, e.g. card mark base, heap top
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6164
      assert(constant_reloc == relocInfo::none, "unexpected reloc type");
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13104
diff changeset
  6165
      __ set(val, $dst$$Register);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6166
    }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6167
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6168
  ins_pipe(loadConP);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6169
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6170
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6171
instruct loadConP_load(iRegP dst, immP_load con) %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6172
  match(Set dst con);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6173
  ins_cost(MEMORY_REF_COST);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6174
  format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6175
  ins_encode %{
7700
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6176
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6177
    __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6178
  %}
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6179
  ins_pipe(loadConP);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6180
%}
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6181
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6182
instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6183
  match(Set dst con);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6184
  ins_cost(DEFAULT_COST * 3/2);
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6185
  format %{ "SET    $con,$dst\t! non-oop ptr" %}
3252c02e23b8 7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents: 7437
diff changeset
  6186
  ins_encode %{
25933
ea319da89b55 8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents: 25741
diff changeset
  6187
    if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
ea319da89b55 8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents: 25741
diff changeset
  6188
      __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
ea319da89b55 8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents: 25741
diff changeset
  6189
    } else {
ea319da89b55 8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents: 25741
diff changeset
  6190
      __ set($con$$constant, $dst$$Register);
ea319da89b55 8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents: 25741
diff changeset
  6191
    }
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6192
  %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6193
  ins_pipe(loadConP);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6194
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6195
#endif // _LP64
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6196
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6197
instruct loadConP0(iRegP dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6198
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6199
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6200
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6201
  format %{ "CLR    $dst\t!ptr" %}
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6202
  ins_encode %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6203
    __ clr($dst$$Register);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6204
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6205
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6206
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6207
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6208
instruct loadConP_poll(iRegP dst, immP_poll src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6209
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6210
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6211
  format %{ "SET    $src,$dst\t!ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6212
  ins_encode %{
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6213
    AddressLiteral polling_page(os::get_polling_page());
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6214
    __ sethi(polling_page, reg_to_register_object($dst$$reg));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6215
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6216
  ins_pipe(loadConP_poll);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6217
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6218
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6219
instruct loadConN0(iRegN dst, immN0 src) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6220
  match(Set dst src);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6221
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6222
  size(4);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6223
  format %{ "CLR    $dst\t! compressed NULL ptr" %}
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6224
  ins_encode %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6225
    __ clr($dst$$Register);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6226
  %}
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6227
  ins_pipe(ialu_imm);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6228
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6229
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6230
instruct loadConN(iRegN dst, immN src) %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6231
  match(Set dst src);
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6232
  ins_cost(DEFAULT_COST * 3/2);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6233
  format %{ "SET    $src,$dst\t! compressed ptr" %}
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6234
  ins_encode %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6235
    Register dst = $dst$$Register;
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6236
    __ set_narrow_oop((jobject)$src$$constant, dst);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6237
  %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6238
  ins_pipe(ialu_hi_lo_reg);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6239
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6240
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6241
instruct loadConNKlass(iRegN dst, immNKlass src) %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6242
  match(Set dst src);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6243
  ins_cost(DEFAULT_COST * 3/2);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6244
  format %{ "SET    $src,$dst\t! compressed klass ptr" %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6245
  ins_encode %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6246
    Register dst = $dst$$Register;
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6247
    __ set_narrow_klass((Klass*)$src$$constant, dst);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6248
  %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6249
  ins_pipe(ialu_hi_lo_reg);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6250
%}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6251
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6252
// Materialize long value (predicated by immL_cheap).
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6253
instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6254
  match(Set dst con);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6255
  effect(KILL tmp);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6256
  ins_cost(DEFAULT_COST * 3);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6257
  format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6258
  ins_encode %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6259
    __ set64($con$$constant, $dst$$Register, $tmp$$Register);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6260
  %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6261
  ins_pipe(loadConL);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6262
%}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6263
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6264
// Load long value from constant table (predicated by immL_expensive).
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6265
instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6266
  match(Set dst con);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6267
  ins_cost(MEMORY_REF_COST);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6268
  format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6269
  ins_encode %{
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6270
      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6271
    __ ldx($constanttablebase, con_offset, $dst$$Register);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6272
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6273
  ins_pipe(loadConL);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6274
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6275
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6276
instruct loadConL0( iRegL dst, immL0 src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6277
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6278
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6279
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6280
  format %{ "CLR    $dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6281
  ins_encode( Set13( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6282
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6283
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6284
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6285
instruct loadConL13( iRegL dst, immL13 src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6286
  match(Set dst src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6287
  ins_cost(DEFAULT_COST * 2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6288
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6289
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6290
  format %{ "MOV    $src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6291
  ins_encode( Set13( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6292
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6293
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6294
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6295
instruct loadConF(regF dst, immF con, o7RegI tmp) %{
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6296
  match(Set dst con);
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6297
  effect(KILL tmp);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6298
  format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6299
  ins_encode %{
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6300
      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6301
    __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6302
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6303
  ins_pipe(loadConFD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6304
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6305
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6306
instruct loadConD(regD dst, immD con, o7RegI tmp) %{
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6307
  match(Set dst con);
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6308
  effect(KILL tmp);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6309
  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6310
  ins_encode %{
2576
a3babdbbca51 6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents: 2571
diff changeset
  6311
    // XXX This is a quick fix for 6833573.
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  6312
    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6313
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  6314
    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
2571
d602ad6538bd 6822110: Add AddressLiteral class on SPARC
twisti
parents: 2348
diff changeset
  6315
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6316
  ins_pipe(loadConFD);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6317
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6318
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6319
// Prefetch instructions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6320
// Must be safe to execute with invalid address (cannot fault).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6321
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6322
instruct prefetchr( memory mem ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6323
  match( PrefetchRead mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6324
  ins_cost(MEMORY_REF_COST);
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6325
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6326
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6327
  format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6328
  opcode(Assembler::prefetch_op3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6329
  ins_encode( form3_mem_prefetch_read( mem ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6330
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6331
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6332
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6333
instruct prefetchw( memory mem ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6334
  match( PrefetchWrite mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6335
  ins_cost(MEMORY_REF_COST);
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6336
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6337
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6338
  format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6339
  opcode(Assembler::prefetch_op3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6340
  ins_encode( form3_mem_prefetch_write( mem ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6341
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6342
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6343
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6344
// Prefetch instructions for allocation.
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6345
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6346
instruct prefetchAlloc( memory mem ) %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6347
  predicate(AllocatePrefetchInstr == 0);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6348
  match( PrefetchAllocation mem );
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6349
  ins_cost(MEMORY_REF_COST);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6350
  size(4);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6351
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6352
  format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6353
  opcode(Assembler::prefetch_op3);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6354
  ins_encode( form3_mem_prefetch_write( mem ) );
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6355
  ins_pipe(iload_mem);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6356
%}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6357
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6358
// Use BIS instruction to prefetch for allocation.
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6359
// Could fault, need space at the end of TLAB.
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6360
instruct prefetchAlloc_bis( iRegP dst ) %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6361
  predicate(AllocatePrefetchInstr == 1);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6362
  match( PrefetchAllocation dst );
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6363
  ins_cost(MEMORY_REF_COST);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6364
  size(4);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6365
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6366
  format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6367
  ins_encode %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6368
    __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
5251
f86f7a86d761 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 5025
diff changeset
  6369
  %}
f86f7a86d761 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 5025
diff changeset
  6370
  ins_pipe(istore_mem_reg);
f86f7a86d761 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 5025
diff changeset
  6371
%}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6372
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6373
// Next code is used for finding next cache line address to prefetch.
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6374
#ifndef _LP64
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6375
instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6376
  match(Set dst (CastX2P (AndI (CastP2X src) mask)));
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6377
  ins_cost(DEFAULT_COST);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6378
  size(4);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6379
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6380
  format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6381
  ins_encode %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6382
    __ and3($src$$Register, $mask$$constant, $dst$$Register);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6383
  %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6384
  ins_pipe(ialu_reg_imm);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6385
%}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6386
#else
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6387
instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6388
  match(Set dst (CastX2P (AndL (CastP2X src) mask)));
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6389
  ins_cost(DEFAULT_COST);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6390
  size(4);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6391
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6392
  format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6393
  ins_encode %{
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6394
    __ and3($src$$Register, $mask$$constant, $dst$$Register);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6395
  %}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6396
  ins_pipe(ialu_reg_imm);
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6397
%}
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6398
#endif
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10264
diff changeset
  6399
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6400
//----------Store Instructions-------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6401
// Store Byte
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6402
instruct storeB(memory mem, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6403
  match(Set mem (StoreB mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6404
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6405
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6406
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6407
  format %{ "STB    $src,$mem\t! byte" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6408
  opcode(Assembler::stb_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6409
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6410
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6411
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6412
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6413
instruct storeB0(memory mem, immI0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6414
  match(Set mem (StoreB mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6415
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6416
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6417
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6418
  format %{ "STB    $src,$mem\t! byte" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6419
  opcode(Assembler::stb_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6420
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6421
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6422
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6423
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6424
instruct storeCM0(memory mem, immI0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6425
  match(Set mem (StoreCM mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6426
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6427
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6428
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6429
  format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6430
  opcode(Assembler::stb_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6431
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6432
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6433
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6434
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6435
// Store Char/Short
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6436
instruct storeC(memory mem, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6437
  match(Set mem (StoreC mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6438
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6439
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6440
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6441
  format %{ "STH    $src,$mem\t! short" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6442
  opcode(Assembler::sth_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6443
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6444
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6445
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6446
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6447
instruct storeC0(memory mem, immI0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6448
  match(Set mem (StoreC mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6449
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6450
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6451
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6452
  format %{ "STH    $src,$mem\t! short" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6453
  opcode(Assembler::sth_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6454
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6455
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6456
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6457
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6458
// Store Integer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6459
instruct storeI(memory mem, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6460
  match(Set mem (StoreI mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6461
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6462
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6463
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6464
  format %{ "STW    $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6465
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6466
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6467
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6468
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6469
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6470
// Store Long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6471
instruct storeL(memory mem, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6472
  match(Set mem (StoreL mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6473
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6474
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6475
  format %{ "STX    $src,$mem\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6476
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6477
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6478
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6479
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6480
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6481
instruct storeI0(memory mem, immI0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6482
  match(Set mem (StoreI mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6483
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6484
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6485
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6486
  format %{ "STW    $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6487
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6488
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6489
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6490
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6491
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6492
instruct storeL0(memory mem, immL0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6493
  match(Set mem (StoreL mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6494
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6495
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6496
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6497
  format %{ "STX    $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6498
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6499
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6500
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6501
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6502
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6503
// Store Integer from float register (used after fstoi)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6504
instruct storeI_Freg(memory mem, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6505
  match(Set mem (StoreI mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6506
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6507
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6508
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6509
  format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6510
  opcode(Assembler::stf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6511
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6512
  ins_pipe(fstoreF_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6513
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6514
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6515
// Store Pointer
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6516
instruct storeP(memory dst, sp_ptr_RegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6517
  match(Set dst (StoreP dst src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6518
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6519
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6520
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6521
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6522
  format %{ "STW    $src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6523
  opcode(Assembler::stw_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6524
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6525
  format %{ "STX    $src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6526
  opcode(Assembler::stx_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6527
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6528
  ins_encode( form3_mem_reg( dst, src ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6529
  ins_pipe(istore_mem_spORreg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6530
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6531
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6532
instruct storeP0(memory dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6533
  match(Set dst (StoreP dst src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6534
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6535
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6536
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6537
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6538
  format %{ "STW    $src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6539
  opcode(Assembler::stw_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6540
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6541
  format %{ "STX    $src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6542
  opcode(Assembler::stx_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6543
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6544
  ins_encode( form3_mem_reg( dst, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6545
  ins_pipe(istore_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6546
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6547
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6548
// Store Compressed Pointer
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6549
instruct storeN(memory dst, iRegN src) %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6550
   match(Set dst (StoreN dst src));
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6551
   ins_cost(MEMORY_REF_COST);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6552
   size(4);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6553
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6554
   format %{ "STW    $src,$dst\t! compressed ptr" %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6555
   ins_encode %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6556
     Register base = as_Register($dst$$base);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6557
     Register index = as_Register($dst$$index);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6558
     Register src = $src$$Register;
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6559
     if (index != G0) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6560
       __ stw(src, base, index);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6561
     } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6562
       __ stw(src, base, $dst$$disp);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6563
     }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6564
   %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6565
   ins_pipe(istore_mem_spORreg);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6566
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6567
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6568
instruct storeNKlass(memory dst, iRegN src) %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6569
   match(Set dst (StoreNKlass dst src));
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6570
   ins_cost(MEMORY_REF_COST);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6571
   size(4);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6572
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6573
   format %{ "STW    $src,$dst\t! compressed klass ptr" %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6574
   ins_encode %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6575
     Register base = as_Register($dst$$base);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6576
     Register index = as_Register($dst$$index);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6577
     Register src = $src$$Register;
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6578
     if (index != G0) {
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6579
       __ stw(src, base, index);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6580
     } else {
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6581
       __ stw(src, base, $dst$$disp);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6582
     }
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6583
   %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6584
   ins_pipe(istore_mem_spORreg);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6585
%}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6586
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6587
instruct storeN0(memory dst, immN0 src) %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6588
   match(Set dst (StoreN dst src));
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6589
   ins_cost(MEMORY_REF_COST);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6590
   size(4);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6591
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6592
   format %{ "STW    $src,$dst\t! compressed ptr" %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6593
   ins_encode %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6594
     Register base = as_Register($dst$$base);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6595
     Register index = as_Register($dst$$index);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6596
     if (index != G0) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6597
       __ stw(0, base, index);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6598
     } else {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6599
       __ stw(0, base, $dst$$disp);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6600
     }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6601
   %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6602
   ins_pipe(istore_mem_zero);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6603
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6604
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6605
// Store Double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6606
instruct storeD( memory mem, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6607
  match(Set mem (StoreD mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6608
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6609
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6610
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6611
  format %{ "STDF   $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6612
  opcode(Assembler::stdf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6613
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6614
  ins_pipe(fstoreD_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6615
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6616
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6617
instruct storeD0( memory mem, immD0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6618
  match(Set mem (StoreD mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6619
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6620
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6621
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6622
  format %{ "STX    $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6623
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6624
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6625
  ins_pipe(fstoreD_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6626
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6627
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6628
// Store Float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6629
instruct storeF( memory mem, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6630
  match(Set mem (StoreF mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6631
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6632
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6633
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6634
  format %{ "STF    $src,$mem" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6635
  opcode(Assembler::stf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6636
  ins_encode(simple_form3_mem_reg( mem, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6637
  ins_pipe(fstoreF_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6638
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6639
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6640
instruct storeF0( memory mem, immF0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6641
  match(Set mem (StoreF mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6642
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6643
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6644
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6645
  format %{ "STW    $src,$mem\t! storeF0" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6646
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6647
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6648
  ins_pipe(fstoreF_mem_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6649
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6650
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6651
// Convert oop pointer into compressed form
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6652
instruct encodeHeapOop(iRegN dst, iRegP src) %{
767
64fb1fd7186d 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 608
diff changeset
  6653
  predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6654
  match(Set dst (EncodeP src));
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6655
  format %{ "encode_heap_oop $src, $dst" %}
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6656
  ins_encode %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6657
    __ encode_heap_oop($src$$Register, $dst$$Register);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6658
  %}
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  6659
  ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6660
  ins_pipe(ialu_reg);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6661
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6662
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6663
instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
767
64fb1fd7186d 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 608
diff changeset
  6664
  predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6665
  match(Set dst (EncodeP src));
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6666
  format %{ "encode_heap_oop_not_null $src, $dst" %}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6667
  ins_encode %{
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6668
    __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6669
  %}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6670
  ins_pipe(ialu_reg);
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6671
%}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6672
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6673
instruct decodeHeapOop(iRegP dst, iRegN src) %{
608
fe8c5fbbc54e 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 607
diff changeset
  6674
  predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
fe8c5fbbc54e 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 607
diff changeset
  6675
            n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6676
  match(Set dst (DecodeN src));
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6677
  format %{ "decode_heap_oop $src, $dst" %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6678
  ins_encode %{
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6679
    __ decode_heap_oop($src$$Register, $dst$$Register);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6680
  %}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6681
  ins_pipe(ialu_reg);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6682
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6683
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6684
instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
608
fe8c5fbbc54e 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 607
diff changeset
  6685
  predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
fe8c5fbbc54e 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 607
diff changeset
  6686
            n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6687
  match(Set dst (DecodeN src));
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6688
  format %{ "decode_heap_oop_not_null $src, $dst" %}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6689
  ins_encode %{
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6690
    __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6691
  %}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6692
  ins_pipe(ialu_reg);
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6693
%}
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  6694
13969
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6695
instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6696
  match(Set dst (EncodePKlass src));
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6697
  format %{ "encode_klass_not_null $src, $dst" %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6698
  ins_encode %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6699
    __ encode_klass_not_null($src$$Register, $dst$$Register);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6700
  %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6701
  ins_pipe(ialu_reg);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6702
%}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6703
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6704
instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6705
  match(Set dst (DecodeNKlass src));
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6706
  format %{ "decode_klass_not_null $src, $dst" %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6707
  ins_encode %{
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6708
    __ decode_klass_not_null($src$$Register, $dst$$Register);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6709
  %}
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6710
  ins_pipe(ialu_reg);
d2a189b83b87 7054512: Compress class pointers after perm gen removal
roland
parents: 13930
diff changeset
  6711
%}
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  6712
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6713
//----------MemBar Instructions-----------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6714
// Memory barrier flavors
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6715
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6716
instruct membar_acquire() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6717
  match(MemBarAcquire);
22855
d637fd28a6c3 8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents: 22851
diff changeset
  6718
  match(LoadFence);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6719
  ins_cost(4*MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6720
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6721
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6722
  format %{ "MEMBAR-acquire" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6723
  ins_encode( enc_membar_acquire );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6724
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6725
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6726
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6727
instruct membar_acquire_lock() %{
10262
c5f62d314bee 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 10255
diff changeset
  6728
  match(MemBarAcquireLock);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6729
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6730
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6731
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6732
  format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6733
  ins_encode( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6734
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6735
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6736
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6737
instruct membar_release() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6738
  match(MemBarRelease);
22855
d637fd28a6c3 8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents: 22851
diff changeset
  6739
  match(StoreFence);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6740
  ins_cost(4*MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6741
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6742
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6743
  format %{ "MEMBAR-release" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6744
  ins_encode( enc_membar_release );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6745
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6746
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6747
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6748
instruct membar_release_lock() %{
10262
c5f62d314bee 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 10255
diff changeset
  6749
  match(MemBarReleaseLock);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6750
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6751
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6752
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6753
  format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6754
  ins_encode( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6755
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6756
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6757
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6758
instruct membar_volatile() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6759
  match(MemBarVolatile);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6760
  ins_cost(4*MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6761
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6762
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6763
  format %{ "MEMBAR-volatile" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6764
  ins_encode( enc_membar_volatile );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6765
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6766
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6767
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6768
instruct unnecessary_membar_volatile() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6769
  match(MemBarVolatile);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6770
  predicate(Matcher::post_store_load_barrier(n));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6771
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6772
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6773
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6774
  format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6775
  ins_encode( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6776
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6777
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6778
11431
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6779
instruct membar_storestore() %{
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6780
  match(MemBarStoreStore);
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6781
  ins_cost(0);
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6782
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6783
  size(0);
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6784
  format %{ "!MEMBAR-storestore (empty encoding)" %}
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6785
  ins_encode( );
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6786
  ins_pipe(empty);
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6787
%}
5ca3a19e559a 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 11197
diff changeset
  6788
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6789
//----------Register Move Instructions-----------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6790
instruct roundDouble_nop(regD dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6791
  match(Set dst (RoundDouble dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6792
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6793
  // SPARC results are already "rounded" (i.e., normal-format IEEE)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6794
  ins_encode( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6795
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6796
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6797
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6798
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6799
instruct roundFloat_nop(regF dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6800
  match(Set dst (RoundFloat dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6801
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6802
  // SPARC results are already "rounded" (i.e., normal-format IEEE)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6803
  ins_encode( );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6804
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6805
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6806
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6807
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6808
// Cast Index to Pointer for unsafe natives
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6809
instruct castX2P(iRegX src, iRegP dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6810
  match(Set dst (CastX2P src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6811
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6812
  format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6813
  ins_encode( form3_g0_rs2_rd_move( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6814
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6815
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6817
// Cast Pointer to Index for unsafe natives
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6818
instruct castP2X(iRegP src, iRegX dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6819
  match(Set dst (CastP2X src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6820
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6821
  format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6822
  ins_encode( form3_g0_rs2_rd_move( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6823
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6824
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6825
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6826
instruct stfSSD(stackSlotD stkSlot, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6827
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6828
  match(Set stkSlot src);   // chain rule
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6829
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6830
  format %{ "STDF   $src,$stkSlot\t!stk" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6831
  opcode(Assembler::stdf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6832
  ins_encode(simple_form3_mem_reg(stkSlot, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6833
  ins_pipe(fstoreD_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6834
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6835
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6836
instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6837
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6838
  match(Set dst stkSlot);   // chain rule
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6839
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6840
  format %{ "LDDF   $stkSlot,$dst\t!stk" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6841
  opcode(Assembler::lddf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6842
  ins_encode(simple_form3_mem_reg(stkSlot, dst));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6843
  ins_pipe(floadD_stk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6844
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6845
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6846
instruct stfSSF(stackSlotF stkSlot, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6847
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6848
  match(Set stkSlot src);   // chain rule
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6849
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6850
  format %{ "STF   $src,$stkSlot\t!stk" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6851
  opcode(Assembler::stf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  6852
  ins_encode(simple_form3_mem_reg(stkSlot, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6853
  ins_pipe(fstoreF_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6854
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6855
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6856
//----------Conditional Move---------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6857
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6858
instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6859
  match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6860
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6861
  format %{ "MOV$cmp $pcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6862
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6863
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6864
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6865
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6866
instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6867
  match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6868
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6869
  format %{ "MOV$cmp $pcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6870
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6871
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6872
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6873
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6874
instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6875
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6876
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6877
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6878
  format %{ "MOV$cmp  $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6879
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6880
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6881
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6882
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6883
instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6884
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6885
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6886
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6887
  format %{ "MOV$cmp  $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6888
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6889
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6890
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6891
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6892
instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6893
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6894
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6895
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6896
  format %{ "MOV$cmp  $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6897
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6898
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6899
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6900
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6901
instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6902
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6903
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6904
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6905
  format %{ "MOV$cmp  $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6906
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6907
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6908
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6909
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6910
instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6911
  match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6912
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6913
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6914
  format %{ "MOV$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6915
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6916
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6917
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6918
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6919
instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6920
  match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6921
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6922
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6923
  format %{ "MOV$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6924
  ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6925
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6926
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6927
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6928
// Conditional move for RegN. Only cmov(reg,reg).
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6929
instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6930
  match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6931
  ins_cost(150);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6932
  format %{ "MOV$cmp $pcc,$src,$dst" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6933
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6934
  ins_pipe(ialu_reg);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6935
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6936
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6937
// This instruction also works with CmpN so we don't need cmovNN_reg.
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6938
instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6939
  match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6940
  ins_cost(150);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6941
  size(4);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6942
  format %{ "MOV$cmp  $icc,$src,$dst" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6943
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6944
  ins_pipe(ialu_reg);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6945
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6946
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6947
// This instruction also works with CmpN so we don't need cmovNN_reg.
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6948
instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6949
  match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6950
  ins_cost(150);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6951
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6952
  format %{ "MOV$cmp  $icc,$src,$dst" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6953
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6954
  ins_pipe(ialu_reg);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6955
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6956
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6957
instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6958
  match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6959
  ins_cost(150);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6960
  size(4);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6961
  format %{ "MOV$cmp $fcc,$src,$dst" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6962
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6963
  ins_pipe(ialu_reg);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6964
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6965
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6966
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6967
instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6968
  match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6969
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6970
  format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6971
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6972
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6973
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6974
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6975
instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6976
  match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6977
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6978
  format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6979
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6980
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6981
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6982
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  6983
// This instruction also works with CmpN so we don't need cmovPN_reg.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6984
instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6985
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6986
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6987
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6988
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6989
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6990
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6991
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6992
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  6993
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6994
instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6995
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6996
  ins_cost(150);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6997
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6998
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  6999
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7000
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7001
  ins_pipe(ialu_reg);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7002
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7003
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7004
instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7005
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7006
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7007
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7008
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7009
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7010
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7011
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7012
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7013
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7014
instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7015
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7016
  ins_cost(140);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7017
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7018
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7019
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7020
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7021
  ins_pipe(ialu_imm);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7022
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7023
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7024
instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7025
  match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7026
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7027
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7028
  format %{ "MOV$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7029
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7030
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7031
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7032
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7033
instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7034
  match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7035
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7036
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7037
  format %{ "MOV$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7038
  ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7039
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7040
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7041
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7042
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7043
instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7044
  match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7045
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7046
  opcode(0x101);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7047
  format %{ "FMOVD$cmp $pcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7048
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7049
  ins_pipe(int_conditional_float_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7050
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7051
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7052
instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7053
  match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7054
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7055
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7056
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7057
  format %{ "FMOVS$cmp $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7058
  opcode(0x101);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7059
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7060
  ins_pipe(int_conditional_float_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7061
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7062
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7063
instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7064
  match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7065
  ins_cost(150);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7066
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7067
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7068
  format %{ "FMOVS$cmp $icc,$src,$dst" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7069
  opcode(0x101);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7070
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7071
  ins_pipe(int_conditional_float_move);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7072
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7073
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7074
// Conditional move,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7075
instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7076
  match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7077
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7078
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7079
  format %{ "FMOVF$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7080
  opcode(0x1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7081
  ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7082
  ins_pipe(int_conditional_double_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7083
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7084
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7085
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7086
instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7087
  match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7088
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7089
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7090
  opcode(0x102);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7091
  format %{ "FMOVD$cmp $pcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7092
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7093
  ins_pipe(int_conditional_double_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7094
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7095
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7096
instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7097
  match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7098
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7099
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7100
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7101
  format %{ "FMOVD$cmp $icc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7102
  opcode(0x102);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7103
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7104
  ins_pipe(int_conditional_double_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7105
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7106
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7107
instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7108
  match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7109
  ins_cost(150);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7110
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7111
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7112
  format %{ "FMOVD$cmp $icc,$src,$dst" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7113
  opcode(0x102);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7114
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7115
  ins_pipe(int_conditional_double_move);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7116
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7117
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7118
// Conditional move,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7119
instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7120
  match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7121
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7122
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7123
  format %{ "FMOVD$cmp $fcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7124
  opcode(0x2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7125
  ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7126
  ins_pipe(int_conditional_double_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7127
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7128
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7129
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7130
instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7131
  match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7132
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7133
  format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7134
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7135
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7136
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7137
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7138
instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7139
  match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7140
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7141
  format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7142
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7143
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7144
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7145
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7146
instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7147
  match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7148
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7149
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7150
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7151
  format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7152
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7153
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7154
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7155
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7156
4589
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7157
instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7158
  match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7159
  ins_cost(150);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7160
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7161
  size(4);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7162
  format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7163
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7164
  ins_pipe(ialu_reg);
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7165
%}
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7166
2621c7da5a88 6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents: 4566
diff changeset
  7167
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7168
instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7169
  match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7170
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7171
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7172
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7173
  format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7174
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7175
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7176
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7177
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7178
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7179
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7180
//----------OS and Locking Instructions----------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7181
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7182
// This name is KNOWN by the ADLC and cannot be changed.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7183
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7184
// for this guy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7185
instruct tlsLoadP(g2RegP dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7186
  match(Set dst (ThreadLocal));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7187
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7188
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7189
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7190
  format %{ "# TLS is in G2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7191
  ins_encode( /*empty encoding*/ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7192
  ins_pipe(ialu_none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7193
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7194
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7195
instruct checkCastPP( iRegP dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7196
  match(Set dst (CheckCastPP dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7197
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7198
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7199
  format %{ "# checkcastPP of $dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7200
  ins_encode( /*empty encoding*/ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7201
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7202
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7203
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7204
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7205
instruct castPP( iRegP dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7206
  match(Set dst (CastPP dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7207
  format %{ "# castPP of $dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7208
  ins_encode( /*empty encoding*/ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7209
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7210
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7211
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7212
instruct castII( iRegI dst ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7213
  match(Set dst (CastII dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7214
  format %{ "# castII of $dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7215
  ins_encode( /*empty encoding*/ );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7216
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7217
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7218
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7219
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7220
//----------Arithmetic Instructions--------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7221
// Addition Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7222
// Register Addition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7223
instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7224
  match(Set dst (AddI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7225
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7226
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7227
  format %{ "ADD    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7228
  ins_encode %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7229
    __ add($src1$$Register, $src2$$Register, $dst$$Register);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7230
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7231
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7232
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7233
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7234
// Immediate Addition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7235
instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7236
  match(Set dst (AddI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7237
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7238
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7239
  format %{ "ADD    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7240
  opcode(Assembler::add_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7241
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7242
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7243
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7244
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7245
// Pointer Register Addition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7246
instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7247
  match(Set dst (AddP src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7248
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7249
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7250
  format %{ "ADD    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7251
  opcode(Assembler::add_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7252
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7253
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7254
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7255
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7256
// Pointer Immediate Addition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7257
instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7258
  match(Set dst (AddP src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7259
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7260
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7261
  format %{ "ADD    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7262
  opcode(Assembler::add_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7263
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7264
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7265
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7266
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7267
// Long Addition
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7268
instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7269
  match(Set dst (AddL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7270
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7271
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7272
  format %{ "ADD    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7273
  opcode(Assembler::add_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7274
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7275
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7276
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7277
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7278
instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7279
  match(Set dst (AddL src1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7280
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7281
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7282
  format %{ "ADD    $src1,$con,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7283
  opcode(Assembler::add_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7284
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7285
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7286
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7287
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7288
//----------Conditional_store--------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7289
// Conditional-store of the updated heap-top.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7290
// Used during allocation of the shared heap.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7291
// Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7292
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7293
// LoadP-locked.  Same as a regular pointer load when used with a compare-swap
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7294
instruct loadPLocked(iRegP dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7295
  match(Set dst (LoadPLocked mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7296
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7297
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7298
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7299
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7300
  format %{ "LDUW   $mem,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7301
  opcode(Assembler::lduw_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7302
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7303
  format %{ "LDX    $mem,$dst\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7304
  opcode(Assembler::ldx_op3, 0, REGP_OP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7305
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7306
  ins_encode( form3_mem_reg( mem, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7307
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7308
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7309
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7310
instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7311
  match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7312
  effect( KILL newval );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7313
  format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7314
            "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7315
  ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7316
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7317
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7318
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7319
// Conditional-store of an int value.
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7320
instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7321
  match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7322
  effect( KILL newval );
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7323
  format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7324
            "CMP    $oldval,$newval\t\t! See if we made progress"  %}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7325
  ins_encode( enc_cas(mem_ptr,oldval,newval) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7326
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7327
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7328
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7329
// Conditional-store of a long value.
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7330
instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7331
  match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7332
  effect( KILL newval );
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7333
  format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7334
            "CMP    $oldval,$newval\t\t! See if we made progress"  %}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  7335
  ins_encode( enc_cas(mem_ptr,oldval,newval) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7336
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7337
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7338
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7339
// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7340
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7341
instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7342
  predicate(VM_Version::supports_cx8());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7343
  match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7344
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7345
  format %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7346
            "MOV    $newval,O7\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7347
            "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7348
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7349
            "MOV    1,$res\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7350
            "MOVne  xcc,R_G0,$res"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7351
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7352
  ins_encode( enc_casx(mem_ptr, oldval, newval),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7353
              enc_lflags_ne_to_boolean(res) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7354
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7355
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7356
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7357
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7358
instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7359
  match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7360
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7361
  format %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7362
            "MOV    $newval,O7\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7363
            "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7364
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7365
            "MOV    1,$res\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7366
            "MOVne  icc,R_G0,$res"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7367
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7368
  ins_encode( enc_casi(mem_ptr, oldval, newval),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7369
              enc_iflags_ne_to_boolean(res) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7370
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7371
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7372
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7373
instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7374
#ifdef _LP64
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7375
  predicate(VM_Version::supports_cx8());
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7376
#endif
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7377
  match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7378
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7379
  format %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7380
            "MOV    $newval,O7\n\t"
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7381
            "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7382
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7383
            "MOV    1,$res\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7384
            "MOVne  xcc,R_G0,$res"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7385
  %}
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7386
#ifdef _LP64
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7387
  ins_encode( enc_casx(mem_ptr, oldval, newval),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7388
              enc_lflags_ne_to_boolean(res) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7389
#else
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7390
  ins_encode( enc_casi(mem_ptr, oldval, newval),
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7391
              enc_iflags_ne_to_boolean(res) );
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7392
#endif
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7393
  ins_pipe( long_memory_op );
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7394
%}
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7395
607
3edc58bab61e 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 591
diff changeset
  7396
instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
  7397
  match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
607
3edc58bab61e 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 591
diff changeset
  7398
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7399
  format %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7400
            "MOV    $newval,O7\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7401
            "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7402
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7403
            "MOV    1,$res\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7404
            "MOVne  icc,R_G0,$res"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7405
  %}
607
3edc58bab61e 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 591
diff changeset
  7406
  ins_encode( enc_casi(mem_ptr, oldval, newval),
3edc58bab61e 6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents: 591
diff changeset
  7407
              enc_iflags_ne_to_boolean(res) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7408
  ins_pipe( long_memory_op );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7409
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7410
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7411
instruct xchgI( memory mem, iRegI newval) %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7412
  match(Set newval (GetAndSetI mem newval));
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7413
  format %{ "SWAP  [$mem],$newval" %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7414
  size(4);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7415
  ins_encode %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7416
    __ swap($mem$$Address, $newval$$Register);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7417
  %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7418
  ins_pipe( long_memory_op );
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7419
%}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7420
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7421
#ifndef _LP64
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7422
instruct xchgP( memory mem, iRegP newval) %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7423
  match(Set newval (GetAndSetP mem newval));
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7424
  format %{ "SWAP  [$mem],$newval" %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7425
  size(4);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7426
  ins_encode %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7427
    __ swap($mem$$Address, $newval$$Register);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7428
  %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7429
  ins_pipe( long_memory_op );
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7430
%}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7431
#endif
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7432
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7433
instruct xchgN( memory mem, iRegN newval) %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7434
  match(Set newval (GetAndSetN mem newval));
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7435
  format %{ "SWAP  [$mem],$newval" %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7436
  size(4);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7437
  ins_encode %{
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7438
    __ swap($mem$$Address, $newval$$Register);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7439
  %}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7440
  ins_pipe( long_memory_op );
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7441
%}
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13728
diff changeset
  7442
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7443
//---------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7444
// Subtraction Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7445
// Register Subtraction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7446
instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7447
  match(Set dst (SubI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7448
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7449
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7450
  format %{ "SUB    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7451
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7452
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7453
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7454
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7455
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7456
// Immediate Subtraction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7457
instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7458
  match(Set dst (SubI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7459
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7460
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7461
  format %{ "SUB    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7462
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7463
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7464
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7465
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7466
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7467
instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7468
  match(Set dst (SubI zero src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7469
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7470
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7471
  format %{ "NEG    $src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7472
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7473
  ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7474
  ins_pipe(ialu_zero_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7475
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7476
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7477
// Long subtraction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7478
instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7479
  match(Set dst (SubL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7480
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7481
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7482
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7483
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7484
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7485
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7486
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7487
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7488
// Immediate Subtraction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7489
instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7490
  match(Set dst (SubL src1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7491
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7492
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7493
  format %{ "SUB    $src1,$con,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7494
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7495
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7496
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7497
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7498
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7499
// Long negation
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7500
instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7501
  match(Set dst (SubL zero src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7502
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7503
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7504
  format %{ "NEG    $src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7505
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7506
  ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7507
  ins_pipe(ialu_zero_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7508
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7509
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7510
// Multiplication Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7511
// Integer Multiplication
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7512
// Register Multiplication
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7513
instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7514
  match(Set dst (MulI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7516
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7517
  format %{ "MULX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7518
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7519
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7520
  ins_pipe(imul_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7521
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7522
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7523
// Immediate Multiplication
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7524
instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7525
  match(Set dst (MulI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7526
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7527
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7528
  format %{ "MULX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7529
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7530
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7531
  ins_pipe(imul_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7532
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7533
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7534
instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7535
  match(Set dst (MulL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7536
  ins_cost(DEFAULT_COST * 5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7537
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7538
  format %{ "MULX   $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7539
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7540
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7541
  ins_pipe(mulL_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7542
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7543
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7544
// Immediate Multiplication
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7545
instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7546
  match(Set dst (MulL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7547
  ins_cost(DEFAULT_COST * 5);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7548
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7549
  format %{ "MULX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7550
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7551
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7552
  ins_pipe(mulL_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7553
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7554
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7555
// Integer Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7556
// Register Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7557
instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7558
  match(Set dst (DivI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7559
  ins_cost((2+71)*DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7560
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7561
  format %{ "SRA     $src2,0,$src2\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7562
            "SRA     $src1,0,$src1\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7563
            "SDIVX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7564
  ins_encode( idiv_reg( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7565
  ins_pipe(sdiv_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7566
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7567
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7568
// Immediate Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7569
instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7570
  match(Set dst (DivI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7571
  ins_cost((2+71)*DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7572
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7573
  format %{ "SRA     $src1,0,$src1\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7574
            "SDIVX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7575
  ins_encode( idiv_imm( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7576
  ins_pipe(sdiv_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7577
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7578
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7579
//----------Div-By-10-Expansion------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7580
// Extract hi bits of a 32x32->64 bit multiply.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7581
// Expand rule only, not matched
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7582
instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7583
  effect( DEF dst, USE src1, USE src2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7584
  format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7585
            "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7586
  ins_encode( enc_mul_hi(dst,src1,src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7587
  ins_pipe(sdiv_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7588
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7589
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
  7590
// Magic constant, reciprocal of 10
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7591
instruct loadConI_x66666667(iRegIsafe dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7592
  effect( DEF dst );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7593
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7594
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7595
  format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7596
  ins_encode( Set32(0x66666667, dst) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7597
  ins_pipe(ialu_hi_lo_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7598
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7599
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
  7600
// Register Shift Right Arithmetic Long by 32-63
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7601
instruct sra_31( iRegI dst, iRegI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7602
  effect( DEF dst, USE src );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7603
  format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7604
  ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7605
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7606
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7607
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7608
// Arithmetic Shift Right by 8-bit immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7609
instruct sra_reg_2( iRegI dst, iRegI src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7610
  effect( DEF dst, USE src );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7611
  format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7612
  opcode(Assembler::sra_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7613
  ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7614
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7615
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7616
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7617
// Integer DIV with 10
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7618
instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7619
  match(Set dst (DivI src div));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7620
  ins_cost((6+6)*DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7621
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7622
    iRegIsafe tmp1;               // Killed temps;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7623
    iRegIsafe tmp2;               // Killed temps;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7624
    iRegI tmp3;                   // Killed temps;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7625
    iRegI tmp4;                   // Killed temps;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7626
    loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7627
    mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7628
    sra_31( tmp3, src );          // SRA  src,31 -> tmp3
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7629
    sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7630
    subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7631
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7632
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7633
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7634
// Register Long Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7635
instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7636
  match(Set dst (DivL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7637
  ins_cost(DEFAULT_COST*71);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7638
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7639
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7640
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7641
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7642
  ins_pipe(divL_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7643
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7644
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7645
// Register Long Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7646
instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7647
  match(Set dst (DivL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7648
  ins_cost(DEFAULT_COST*71);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7649
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7650
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7651
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7652
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7653
  ins_pipe(divL_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7654
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7655
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7656
// Integer Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7657
// Register Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7658
instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7659
  match(Set dst (ModI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7660
  effect( KILL ccr, KILL temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7661
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7662
  format %{ "SREM   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7663
  ins_encode( irem_reg(src1, src2, dst, temp) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7664
  ins_pipe(sdiv_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7665
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7666
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7667
// Immediate Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7668
instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7669
  match(Set dst (ModI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7670
  effect( KILL ccr, KILL temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7671
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7672
  format %{ "SREM   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7673
  ins_encode( irem_imm(src1, src2, dst, temp) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7674
  ins_pipe(sdiv_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7675
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7676
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7677
// Register Long Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7678
instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7679
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7680
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7681
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7682
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7683
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7684
  ins_pipe(divL_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7685
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7686
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7687
// Register Long Division
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7688
instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7689
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7690
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7691
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7692
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7693
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7694
  ins_pipe(divL_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7695
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7696
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7697
instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7698
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7699
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7700
  format %{ "MULX   $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7701
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7702
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7703
  ins_pipe(mulL_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7704
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7705
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7706
// Immediate Multiplication
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7707
instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7708
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7709
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7710
  format %{ "MULX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7711
  opcode(Assembler::mulx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7712
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7713
  ins_pipe(mulL_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7714
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7715
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7716
instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7717
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7718
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7719
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7720
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7721
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7722
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7723
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7724
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7725
instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7726
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7727
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7728
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7729
  opcode(Assembler::sub_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7730
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7731
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7732
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7733
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7734
// Register Long Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7735
instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7736
  match(Set dst (ModL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7737
  ins_cost(DEFAULT_COST*(71 + 6 + 1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7738
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7739
    iRegL tmp1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7740
    iRegL tmp2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7741
    divL_reg_reg_1(tmp1, src1, src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7742
    mulL_reg_reg_1(tmp2, tmp1, src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7743
    subL_reg_reg_1(dst,  src1, tmp2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7744
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7745
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7746
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7747
// Register Long Remainder
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7748
instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7749
  match(Set dst (ModL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7750
  ins_cost(DEFAULT_COST*(71 + 6 + 1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7751
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7752
    iRegL tmp1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7753
    iRegL tmp2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7754
    divL_reg_imm13_1(tmp1, src1, src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7755
    mulL_reg_imm13_1(tmp2, tmp1, src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7756
    subL_reg_reg_2  (dst,  src1, tmp2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7757
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7758
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7759
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7760
// Integer Shift Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7761
// Register Shift Left
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7762
instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7763
  match(Set dst (LShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7764
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7765
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7766
  format %{ "SLL    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7767
  opcode(Assembler::sll_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7768
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7769
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7770
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7771
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7772
// Register Shift Left Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7773
instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7774
  match(Set dst (LShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7775
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7776
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7777
  format %{ "SLL    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7778
  opcode(Assembler::sll_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7779
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7780
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7781
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7782
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7783
// Register Shift Left
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7784
instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7785
  match(Set dst (LShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7786
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7787
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7788
  format %{ "SLLX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7789
  opcode(Assembler::sllx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7790
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7791
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7792
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7793
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7794
// Register Shift Left Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7795
instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7796
  match(Set dst (LShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7797
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7798
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7799
  format %{ "SLLX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7800
  opcode(Assembler::sllx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7801
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7802
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7803
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7804
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7805
// Register Arithmetic Shift Right
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7806
instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7807
  match(Set dst (RShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7808
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7809
  format %{ "SRA    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7810
  opcode(Assembler::sra_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7811
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7812
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7813
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7814
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7815
// Register Arithmetic Shift Right Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7816
instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7817
  match(Set dst (RShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7818
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7819
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7820
  format %{ "SRA    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7821
  opcode(Assembler::sra_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7822
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7823
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7824
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7825
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7826
// Register Shift Right Arithmatic Long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7827
instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7828
  match(Set dst (RShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7829
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7830
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7831
  format %{ "SRAX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7832
  opcode(Assembler::srax_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7833
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7834
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7835
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7836
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7837
// Register Shift Left Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7838
instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7839
  match(Set dst (RShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7840
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7841
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7842
  format %{ "SRAX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7843
  opcode(Assembler::srax_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7844
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7845
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7846
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7847
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7848
// Register Shift Right
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7849
instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7850
  match(Set dst (URShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7851
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7852
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7853
  format %{ "SRL    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7854
  opcode(Assembler::srl_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7855
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7856
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7857
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7858
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7859
// Register Shift Right Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7860
instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7861
  match(Set dst (URShiftI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7862
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7863
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7864
  format %{ "SRL    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7865
  opcode(Assembler::srl_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7866
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7867
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7868
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7869
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7870
// Register Shift Right
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7871
instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7872
  match(Set dst (URShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7873
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7874
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7875
  format %{ "SRLX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7876
  opcode(Assembler::srlx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7877
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7878
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7879
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7880
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7881
// Register Shift Right Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7882
instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7883
  match(Set dst (URShiftL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7884
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7885
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7886
  format %{ "SRLX   $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7887
  opcode(Assembler::srlx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7888
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7889
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7890
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7891
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7892
// Register Shift Right Immediate with a CastP2X
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7893
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7894
instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7895
  match(Set dst (URShiftL (CastP2X src1) src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7896
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7897
  format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7898
  opcode(Assembler::srlx_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7899
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7900
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7901
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7902
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7903
instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7904
  match(Set dst (URShiftI (CastP2X src1) src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7905
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7906
  format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7907
  opcode(Assembler::srl_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7908
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7909
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7910
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7911
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7912
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7913
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7914
//----------Floating Point Arithmetic Instructions-----------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7915
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7916
//  Add float single precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7917
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7918
  match(Set dst (AddF src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7919
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7920
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7921
  format %{ "FADDS  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7922
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7923
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7924
  ins_pipe(faddF_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7925
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7926
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7927
//  Add float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7928
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7929
  match(Set dst (AddD src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7930
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7931
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7932
  format %{ "FADDD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7933
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7934
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7935
  ins_pipe(faddD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7936
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7937
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7938
//  Sub float single precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7939
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7940
  match(Set dst (SubF src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7941
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7942
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7943
  format %{ "FSUBS  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7944
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7945
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7946
  ins_pipe(faddF_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7947
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7948
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7949
//  Sub float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7950
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7951
  match(Set dst (SubD src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7953
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7954
  format %{ "FSUBD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7955
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7956
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7957
  ins_pipe(faddD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7958
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7959
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7960
//  Mul float single precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7961
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7962
  match(Set dst (MulF src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7963
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7964
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7965
  format %{ "FMULS  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7966
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7967
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7968
  ins_pipe(fmulF_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7969
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7970
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7971
//  Mul float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7972
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7973
  match(Set dst (MulD src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7974
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7975
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7976
  format %{ "FMULD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7977
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7978
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7979
  ins_pipe(fmulD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7980
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7981
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7982
//  Div float single precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7983
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7984
  match(Set dst (DivF src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7985
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7986
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7987
  format %{ "FDIVS  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7988
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7989
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7990
  ins_pipe(fdivF_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7991
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7992
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7993
//  Div float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7994
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7995
  match(Set dst (DivD src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7996
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7997
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7998
  format %{ "FDIVD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  7999
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8000
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8001
  ins_pipe(fdivD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8002
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8003
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8004
//  Absolute float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8005
instruct absD_reg(regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8006
  match(Set dst (AbsD src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8007
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8008
  format %{ "FABSd  $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8009
  ins_encode(fabsd(dst, src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8010
  ins_pipe(faddD_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8011
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8012
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8013
//  Absolute float single precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8014
instruct absF_reg(regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8015
  match(Set dst (AbsF src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8016
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8017
  format %{ "FABSs  $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8018
  ins_encode(fabss(dst, src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8019
  ins_pipe(faddF_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8020
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8021
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8022
instruct negF_reg(regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8023
  match(Set dst (NegF src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8024
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8025
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8026
  format %{ "FNEGs  $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8027
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8028
  ins_encode(form3_opf_rs2F_rdF(src, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8029
  ins_pipe(faddF_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8030
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8031
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8032
instruct negD_reg(regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8033
  match(Set dst (NegD src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8034
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8035
  format %{ "FNEGd  $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8036
  ins_encode(fnegd(dst, src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8037
  ins_pipe(faddD_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8038
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8039
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8040
//  Sqrt float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8041
instruct sqrtF_reg_reg(regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8042
  match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8043
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8044
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8045
  format %{ "FSQRTS $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8046
  ins_encode(fsqrts(dst, src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8047
  ins_pipe(fdivF_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8048
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8050
//  Sqrt float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8051
instruct sqrtD_reg_reg(regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8052
  match(Set dst (SqrtD src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8053
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8054
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8055
  format %{ "FSQRTD $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8056
  ins_encode(fsqrtd(dst, src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8057
  ins_pipe(fdivD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8058
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8059
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8060
//----------Logical Instructions-----------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8061
// And Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8062
// Register And
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8063
instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8064
  match(Set dst (AndI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8065
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8066
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8067
  format %{ "AND    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8068
  opcode(Assembler::and_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8069
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8070
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8071
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8072
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8073
// Immediate And
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8074
instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8075
  match(Set dst (AndI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8076
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8077
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8078
  format %{ "AND    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8079
  opcode(Assembler::and_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8080
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8081
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8082
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8083
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8084
// Register And Long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8085
instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8086
  match(Set dst (AndL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8087
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8088
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8089
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8090
  format %{ "AND    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8091
  opcode(Assembler::and_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8092
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8093
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8094
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8095
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8096
instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8097
  match(Set dst (AndL src1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8098
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8099
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8100
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8101
  format %{ "AND    $src1,$con,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8102
  opcode(Assembler::and_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8103
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8104
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8105
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8106
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8107
// Or Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8108
// Register Or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8109
instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8110
  match(Set dst (OrI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8111
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8112
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8113
  format %{ "OR     $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8114
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8115
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8116
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8117
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8118
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8119
// Immediate Or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8120
instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8121
  match(Set dst (OrI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8122
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8123
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8124
  format %{ "OR     $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8125
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8126
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8127
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8128
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8129
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8130
// Register Or Long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8131
instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8132
  match(Set dst (OrL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8133
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8134
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8135
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8136
  format %{ "OR     $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8137
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8138
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8139
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8140
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8141
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8142
instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8143
  match(Set dst (OrL src1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8144
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8145
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8146
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8147
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8148
  format %{ "OR     $src1,$con,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8149
  opcode(Assembler::or_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8150
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8151
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8152
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8153
1500
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8154
#ifndef _LP64
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8155
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8156
// Use sp_ptr_RegP to match G2 (TLS register) without spilling.
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8157
instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8158
  match(Set dst (OrI src1 (CastP2X src2)));
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8159
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8160
  size(4);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8161
  format %{ "OR     $src1,$src2,$dst" %}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8162
  opcode(Assembler::or_op3, Assembler::arith_op);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8163
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8164
  ins_pipe(ialu_reg_reg);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8165
%}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8166
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8167
#else
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8168
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8169
instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8170
  match(Set dst (OrL src1 (CastP2X src2)));
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8171
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8172
  ins_cost(DEFAULT_COST);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8173
  size(4);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8174
  format %{ "OR     $src1,$src2,$dst\t! long" %}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8175
  opcode(Assembler::or_op3, Assembler::arith_op);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8176
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8177
  ins_pipe(ialu_reg_reg);
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8178
%}
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8179
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8180
#endif
bea9a90f3e8f 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 1495
diff changeset
  8181
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8182
// Xor Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8183
// Register Xor
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8184
instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8185
  match(Set dst (XorI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8186
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8187
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8188
  format %{ "XOR    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8189
  opcode(Assembler::xor_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8190
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8191
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8192
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8193
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8194
// Immediate Xor
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8195
instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8196
  match(Set dst (XorI src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8197
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8198
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8199
  format %{ "XOR    $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8200
  opcode(Assembler::xor_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8201
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8202
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8203
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8204
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8205
// Register Xor Long
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8206
instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8207
  match(Set dst (XorL src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8208
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8209
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8210
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8211
  format %{ "XOR    $src1,$src2,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8212
  opcode(Assembler::xor_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8213
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8214
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8215
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8216
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8217
instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8218
  match(Set dst (XorL src1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8219
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8220
  ins_cost(DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8221
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8222
  format %{ "XOR    $src1,$con,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8223
  opcode(Assembler::xor_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8224
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8225
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8226
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8227
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8228
//----------Convert to Boolean-------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8229
// Nice hack for 32-bit tests but doesn't work for
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8230
// 64-bit pointers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8231
instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8232
  match(Set dst (Conv2B src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8233
  effect( KILL ccr );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8234
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8235
  format %{ "CMP    R_G0,$src\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8236
            "ADDX   R_G0,0,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8237
  ins_encode( enc_to_bool( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8238
  ins_pipe(ialu_reg_ialu);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8239
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8240
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8241
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8242
instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8243
  match(Set dst (Conv2B src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8244
  effect( KILL ccr );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8245
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8246
  format %{ "CMP    R_G0,$src\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8247
            "ADDX   R_G0,0,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8248
  ins_encode( enc_to_bool( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8249
  ins_pipe(ialu_reg_ialu);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8250
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8251
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8252
instruct convP2B( iRegI dst, iRegP src ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8253
  match(Set dst (Conv2B src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8254
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8255
  format %{ "MOV    $src,$dst\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8256
            "MOVRNZ $src,1,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8257
  ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8258
  ins_pipe(ialu_clr_and_mover);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8259
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8260
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8261
8324
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8262
instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8263
  match(Set dst (CmpLTMask src zero));
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8264
  effect(KILL ccr);
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8265
  size(4);
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8266
  format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8267
  ins_encode %{
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8268
    __ sra($src$$Register, 31, $dst$$Register);
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8269
  %}
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8270
  ins_pipe(ialu_reg_imm);
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8271
%}
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8272
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8273
instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8274
  match(Set dst (CmpLTMask p q));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8275
  effect( KILL ccr );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8276
  ins_cost(DEFAULT_COST*4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8277
  format %{ "CMP    $p,$q\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8278
            "MOV    #0,$dst\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8279
            "BLT,a  .+8\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8280
            "MOV    #-1,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8281
  ins_encode( enc_ltmask(p,q,dst) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8282
  ins_pipe(ialu_reg_reg_ialu);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8283
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8284
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8285
instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8286
  match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8287
  effect(KILL ccr, TEMP tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8288
  ins_cost(DEFAULT_COST*3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8289
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8290
  format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8291
            "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8324
a9933c6c5a95 7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents: 7892
diff changeset
  8292
            "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
17008
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8293
  ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8294
  ins_pipe(cadd_cmpltmask);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8295
%}
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8296
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8297
instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8298
  match(Set p (AndI (CmpLTMask p q) y));
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8299
  effect(KILL ccr);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8300
  ins_cost(DEFAULT_COST*3);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8301
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8302
  format %{ "CMP  $p,$q\n\t"
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8303
            "MOV  $y,$p\n\t"
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8304
            "MOVge G0,$p" %}
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8305
  ins_encode %{
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8306
    __ cmp($p$$Register, $q$$Register);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8307
    __ mov($y$$Register, $p$$Register);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8308
    __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8309
  %}
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8310
  ins_pipe(ialu_reg_reg_ialu);
fe66415573bf 6443505: Ideal() function for CmpLTMask
drchase
parents: 14833
diff changeset
  8311
%}
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8312
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8313
//-----------------------------------------------------------------
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8314
// Direct raw moves between float and general registers using VIS3.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8315
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8316
//  ins_pipe(faddF_reg);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8317
instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8318
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8319
  match(Set dst (MoveF2I src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8320
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8321
  format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8322
  ins_encode %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8323
    __ movstouw($src$$FloatRegister, $dst$$Register);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8324
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8325
  ins_pipe(ialu_reg_reg);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8326
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8327
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8328
instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8329
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8330
  match(Set dst (MoveI2F src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8331
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8332
  format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8333
  ins_encode %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8334
    __ movwtos($src$$Register, $dst$$FloatRegister);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8335
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8336
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8337
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8338
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8339
instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8340
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8341
  match(Set dst (MoveD2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8342
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8343
  format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8344
  ins_encode %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8345
    __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8346
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8347
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8348
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8349
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8350
instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8351
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8352
  match(Set dst (MoveL2D src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8353
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8354
  format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8355
  ins_encode %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8356
    __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8357
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8358
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8359
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8360
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8361
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8362
// Raw moves between float and general registers using stack.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8363
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8364
instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8365
  match(Set dst (MoveF2I src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8366
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8367
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8368
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8369
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8370
  format %{ "LDUW   $src,$dst\t! MoveF2I" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8371
  opcode(Assembler::lduw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8372
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8373
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8374
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8375
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8376
instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8377
  match(Set dst (MoveI2F src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8378
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8379
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8380
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8381
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8382
  format %{ "LDF    $src,$dst\t! MoveI2F" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8383
  opcode(Assembler::ldf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8384
  ins_encode(simple_form3_mem_reg(src, dst));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8385
  ins_pipe(floadF_stk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8386
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8387
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8388
instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8389
  match(Set dst (MoveD2L src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8390
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8391
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8392
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8393
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8394
  format %{ "LDX    $src,$dst\t! MoveD2L" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8395
  opcode(Assembler::ldx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8396
  ins_encode(simple_form3_mem_reg( src, dst ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8397
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8398
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8399
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8400
instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8401
  match(Set dst (MoveL2D src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8402
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8403
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8404
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8405
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8406
  format %{ "LDDF   $src,$dst\t! MoveL2D" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8407
  opcode(Assembler::lddf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8408
  ins_encode(simple_form3_mem_reg(src, dst));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8409
  ins_pipe(floadD_stk);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8410
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8411
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8412
instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8413
  match(Set dst (MoveF2I src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8414
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8415
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8416
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8417
  size(4);
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8418
  format %{ "STF   $src,$dst\t! MoveF2I" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8419
  opcode(Assembler::stf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8420
  ins_encode(simple_form3_mem_reg(dst, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8421
  ins_pipe(fstoreF_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8422
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8423
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8424
instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8425
  match(Set dst (MoveI2F src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8426
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8427
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8428
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8429
  size(4);
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8430
  format %{ "STW    $src,$dst\t! MoveI2F" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8431
  opcode(Assembler::stw_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8432
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8433
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8434
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8435
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8436
instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8437
  match(Set dst (MoveD2L src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8438
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8439
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8440
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8441
  size(4);
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8442
  format %{ "STDF   $src,$dst\t! MoveD2L" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8443
  opcode(Assembler::stdf_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8444
  ins_encode(simple_form3_mem_reg(dst, src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8445
  ins_pipe(fstoreD_stk_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8446
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8447
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8448
instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8449
  match(Set dst (MoveL2D src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8450
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8451
  ins_cost(MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8452
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8453
  size(4);
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8454
  format %{ "STX    $src,$dst\t! MoveL2D" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8455
  opcode(Assembler::stx_op3);
1495
128fe18951ed 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 781
diff changeset
  8456
  ins_encode(simple_form3_mem_reg( dst, src ) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8457
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8458
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8459
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8460
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8461
//----------Arithmetic Conversion Instructions---------------------------------
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8462
// The conversions operations are all Alpha sorted.  Please keep it that way!
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8463
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8464
instruct convD2F_reg(regF dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8465
  match(Set dst (ConvD2F src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8466
  size(4);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8467
  format %{ "FDTOS  $src,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8468
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8469
  ins_encode(form3_opf_rs2D_rdF(src, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8470
  ins_pipe(fcvtD2F);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8471
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8472
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8473
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8474
// Convert a double to an int in a float register.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8475
// If the double is a NAN, stuff a zero in instead.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8476
instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8477
  effect(DEF dst, USE src, KILL fcc0);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8478
  format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8479
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8480
            "FDTOI  $src,$dst\t! convert in delay slot\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8481
            "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8482
            "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8483
      "skip:" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8484
  ins_encode(form_d2i_helper(src,dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8485
  ins_pipe(fcvtD2I);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8486
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8487
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8488
instruct convD2I_stk(stackSlotI dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8489
  match(Set dst (ConvD2I src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8490
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8491
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8492
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8493
    convD2I_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8494
    regF_to_stkI(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8495
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8496
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8497
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8498
instruct convD2I_reg(iRegI dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8499
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8500
  match(Set dst (ConvD2I src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8501
  ins_cost(DEFAULT_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8502
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8503
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8504
    convD2I_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8505
    MoveF2I_reg_reg(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8506
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8507
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8508
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8509
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8510
// Convert a double to a long in a double register.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8511
// If the double is a NAN, stuff a zero in instead.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8512
instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8513
  effect(DEF dst, USE src, KILL fcc0);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8514
  format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8515
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8516
            "FDTOX  $src,$dst\t! convert in delay slot\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8517
            "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8518
            "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8519
      "skip:" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8520
  ins_encode(form_d2l_helper(src,dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8521
  ins_pipe(fcvtD2L);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8522
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8523
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8524
instruct convD2L_stk(stackSlotL dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8525
  match(Set dst (ConvD2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8526
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8527
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8528
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8529
    convD2L_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8530
    regD_to_stkL(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8531
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8532
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8533
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8534
instruct convD2L_reg(iRegL dst, regD src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8535
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8536
  match(Set dst (ConvD2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8537
  ins_cost(DEFAULT_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8538
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8539
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8540
    convD2L_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8541
    MoveD2L_reg_reg(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8542
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8543
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8544
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8545
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8546
instruct convF2D_reg(regD dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8547
  match(Set dst (ConvF2D src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8548
  format %{ "FSTOD  $src,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8549
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8550
  ins_encode(form3_opf_rs2F_rdD(src, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8551
  ins_pipe(fcvtF2D);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8552
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8553
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8554
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8555
// Convert a float to an int in a float register.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8556
// If the float is a NAN, stuff a zero in instead.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8557
instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8558
  effect(DEF dst, USE src, KILL fcc0);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8559
  format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8560
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8561
            "FSTOI  $src,$dst\t! convert in delay slot\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8562
            "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8563
            "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8564
      "skip:" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8565
  ins_encode(form_f2i_helper(src,dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8566
  ins_pipe(fcvtF2I);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8567
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8568
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8569
instruct convF2I_stk(stackSlotI dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8570
  match(Set dst (ConvF2I src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8571
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8572
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8573
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8574
    convF2I_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8575
    regF_to_stkI(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8576
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8577
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8578
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8579
instruct convF2I_reg(iRegI dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8580
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8581
  match(Set dst (ConvF2I src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8582
  ins_cost(DEFAULT_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8583
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8584
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8585
    convF2I_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8586
    MoveF2I_reg_reg(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8587
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8588
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8589
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8590
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8591
// Convert a float to a long in a float register.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8592
// If the float is a NAN, stuff a zero in instead.
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8593
instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8594
  effect(DEF dst, USE src, KILL fcc0);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8595
  format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8596
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8597
            "FSTOX  $src,$dst\t! convert in delay slot\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8598
            "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8599
            "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8600
      "skip:" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8601
  ins_encode(form_f2l_helper(src,dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8602
  ins_pipe(fcvtF2L);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8603
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8604
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8605
instruct convF2L_stk(stackSlotL dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8606
  match(Set dst (ConvF2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8607
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8608
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8609
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8610
    convF2L_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8611
    regD_to_stkL(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8612
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8613
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8614
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8615
instruct convF2L_reg(iRegL dst, regF src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8616
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8617
  match(Set dst (ConvF2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8618
  ins_cost(DEFAULT_COST*2 + BRANCH_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8619
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8620
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8621
    convF2L_helper(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8622
    MoveD2L_reg_reg(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8623
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8624
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8625
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8626
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8627
instruct convI2D_helper(regD dst, regF tmp) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8628
  effect(USE tmp, DEF dst);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8629
  format %{ "FITOD  $tmp,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8630
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8631
  ins_encode(form3_opf_rs2F_rdD(tmp, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8632
  ins_pipe(fcvtI2D);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8633
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8634
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8635
instruct convI2D_stk(stackSlotI src, regD dst) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8636
  match(Set dst (ConvI2D src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8637
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8638
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8639
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8640
    stkI_to_regF(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8641
    convI2D_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8642
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8643
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8644
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8645
instruct convI2D_reg(regD_low dst, iRegI src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8646
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8647
  match(Set dst (ConvI2D src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8648
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8649
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8650
    MoveI2F_reg_reg(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8651
    convI2D_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8652
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8653
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8654
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8655
instruct convI2D_mem(regD_low dst, memory mem) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8656
  match(Set dst (ConvI2D (LoadI mem)));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8657
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8658
  size(8);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8659
  format %{ "LDF    $mem,$dst\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8660
            "FITOD  $dst,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8661
  opcode(Assembler::ldf_op3, Assembler::fitod_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8662
  ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8663
  ins_pipe(floadF_mem);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8664
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8665
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8666
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8667
instruct convI2F_helper(regF dst, regF tmp) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8668
  effect(DEF dst, USE tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8669
  format %{ "FITOS  $tmp,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8670
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8671
  ins_encode(form3_opf_rs2F_rdF(tmp, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8672
  ins_pipe(fcvtI2F);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8673
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8674
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8675
instruct convI2F_stk(regF dst, stackSlotI src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8676
  match(Set dst (ConvI2F src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8677
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8678
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8679
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8680
    stkI_to_regF(tmp,src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8681
    convI2F_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8682
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8683
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8684
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8685
instruct convI2F_reg(regF dst, iRegI src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8686
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8687
  match(Set dst (ConvI2F src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8688
  ins_cost(DEFAULT_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8689
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8690
    regF tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8691
    MoveI2F_reg_reg(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8692
    convI2F_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8693
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8694
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8695
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8696
instruct convI2F_mem( regF dst, memory mem ) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8697
  match(Set dst (ConvI2F (LoadI mem)));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8698
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8699
  size(8);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8700
  format %{ "LDF    $mem,$dst\n\t"
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8701
            "FITOS  $dst,$dst" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8702
  opcode(Assembler::ldf_op3, Assembler::fitos_opf);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8703
  ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8704
  ins_pipe(floadF_mem);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8705
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8706
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8707
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8708
instruct convI2L_reg(iRegL dst, iRegI src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8709
  match(Set dst (ConvI2L src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8710
  size(4);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8711
  format %{ "SRA    $src,0,$dst\t! int->long" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8712
  opcode(Assembler::sra_op3, Assembler::arith_op);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8713
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8714
  ins_pipe(ialu_reg_reg);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8715
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8716
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8717
// Zero-extend convert int to long
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8718
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8719
  match(Set dst (AndL (ConvI2L src) mask) );
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8720
  size(4);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8721
  format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8722
  opcode(Assembler::srl_op3, Assembler::arith_op);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8723
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8724
  ins_pipe(ialu_reg_reg);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8725
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8726
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8727
// Zero-extend long
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8728
instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8729
  match(Set dst (AndL src mask) );
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8730
  size(4);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8731
  format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8732
  opcode(Assembler::srl_op3, Assembler::arith_op);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8733
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8734
  ins_pipe(ialu_reg_reg);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8735
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8736
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8737
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8738
//-----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8739
// Long to Double conversion using V8 opcodes.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8740
// Still useful because cheetah traps and becomes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8741
// amazingly slow for some common numbers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8742
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8743
// Magic constant, 0x43300000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8744
instruct loadConI_x43300000(iRegI dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8745
  effect(DEF dst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8746
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8747
  format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8748
  ins_encode(SetHi22(0x43300000, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8749
  ins_pipe(ialu_none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8750
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8751
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8752
// Magic constant, 0x41f00000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8753
instruct loadConI_x41f00000(iRegI dst) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8754
  effect(DEF dst);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8755
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8756
  format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8757
  ins_encode(SetHi22(0x41f00000, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8758
  ins_pipe(ialu_none);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8759
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8760
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8761
// Construct a double from two float halves
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8762
instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8763
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8764
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8765
  format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8766
            "FMOVS  $src2.lo,$dst.lo" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8767
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8768
  ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8769
  ins_pipe(faddD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8770
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8771
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8772
// Convert integer in high half of a double register (in the lower half of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8773
// the double register file) to double
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8774
instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8775
  effect(DEF dst, USE src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8776
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8777
  format %{ "FITOD  $src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8778
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8779
  ins_encode(form3_opf_rs2D_rdD(src, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8780
  ins_pipe(fcvtLHi2D);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8781
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8782
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8783
// Add float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8784
instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8785
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8786
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8787
  format %{ "FADDD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8788
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8789
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8790
  ins_pipe(faddD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8791
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8792
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8793
// Sub float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8794
instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8795
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8796
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8797
  format %{ "FSUBD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8798
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8799
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8800
  ins_pipe(faddD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8801
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8802
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8803
// Mul float double precision
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8804
instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8805
  effect(DEF dst, USE src1, USE src2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8806
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8807
  format %{ "FMULD  $src1,$src2,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8808
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8809
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8810
  ins_pipe(fmulD_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8811
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8812
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8813
instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8814
  match(Set dst (ConvL2D src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8815
  ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8817
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8818
    regD_low   tmpsrc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8819
    iRegI      ix43300000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8820
    iRegI      ix41f00000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8821
    stackSlotL lx43300000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8822
    stackSlotL lx41f00000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8823
    regD_low   dx43300000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8824
    regD       dx41f00000;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8825
    regD       tmp1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8826
    regD_low   tmp2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8827
    regD       tmp3;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8828
    regD       tmp4;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8829
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8830
    stkL_to_regD(tmpsrc, src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8831
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8832
    loadConI_x43300000(ix43300000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8833
    loadConI_x41f00000(ix41f00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8834
    regI_to_stkLHi(lx43300000, ix43300000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8835
    regI_to_stkLHi(lx41f00000, ix41f00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8836
    stkL_to_regD(dx43300000, lx43300000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8837
    stkL_to_regD(dx41f00000, lx41f00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8838
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8839
    convI2D_regDHi_regD(tmp1, tmpsrc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8840
    regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8841
    subD_regD_regD(tmp3, tmp2, dx43300000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8842
    mulD_regD_regD(tmp4, tmp1, dx41f00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8843
    addD_regD_regD(dst, tmp3, tmp4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8844
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8845
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8846
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8847
// Long to Double conversion using fast fxtof
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8848
instruct convL2D_helper(regD dst, regD tmp) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8849
  effect(DEF dst, USE tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8850
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8851
  format %{ "FXTOD  $tmp,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8852
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8853
  ins_encode(form3_opf_rs2D_rdD(tmp, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8854
  ins_pipe(fcvtL2D);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8855
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8856
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8857
instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8858
  predicate(VM_Version::has_fast_fxtof());
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8859
  match(Set dst (ConvL2D src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8860
  ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8861
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8862
    regD tmp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8863
    stkL_to_regD(tmp, src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8864
    convL2D_helper(dst, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8865
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8866
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8867
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8868
instruct convL2D_reg(regD dst, iRegL src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8869
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8870
  match(Set dst (ConvL2D src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8871
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8872
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8873
    MoveL2D_reg_reg(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8874
    convL2D_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8875
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8876
%}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8877
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8878
// Long to Float conversion using fast fxtof
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8879
instruct convL2F_helper(regF dst, regD tmp) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8880
  effect(DEF dst, USE tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8881
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8882
  format %{ "FXTOS  $tmp,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8883
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8884
  ins_encode(form3_opf_rs2D_rdF(tmp, dst));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8885
  ins_pipe(fcvtL2F);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8886
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8887
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8888
instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8889
  match(Set dst (ConvL2F src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8890
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8891
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8892
    regD tmp;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8893
    stkL_to_regD(tmp, src);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8894
    convL2F_helper(dst, tmp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8895
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8896
%}
10027
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8897
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8898
instruct convL2F_reg(regF dst, iRegL src) %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8899
  predicate(UseVIS >= 3);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8900
  match(Set dst (ConvL2F src));
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8901
  ins_cost(DEFAULT_COST);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8902
  expand %{
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8903
    regD tmp;
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8904
    MoveL2D_reg_reg(tmp, src);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8905
    convL2F_helper(dst, tmp);
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8906
  %}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8907
%}
20cd71f29262 7059034: Use movxtod/movdtox on T4
kvn
parents: 8868
diff changeset
  8908
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8909
//-----------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8910
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8911
instruct convL2I_reg(iRegI dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8912
  match(Set dst (ConvL2I src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8913
#ifndef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8914
  format %{ "MOV    $src.lo,$dst\t! long->int" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8915
  ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8916
  ins_pipe(ialu_move_reg_I_to_L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8917
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8918
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8919
  format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8920
  ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8921
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8922
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8923
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8924
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8925
// Register Shift Right Immediate
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8926
instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8927
  match(Set dst (ConvL2I (RShiftL src cnt)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8928
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8929
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8930
  format %{ "SRAX   $src,$cnt,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8931
  opcode(Assembler::srax_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8932
  ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8933
  ins_pipe(ialu_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8934
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8935
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8936
//----------Control Flow Instructions------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8937
// Compare Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8938
// Compare Integers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8939
instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8940
  match(Set icc (CmpI op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8941
  effect( DEF icc, USE op1, USE op2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8942
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8943
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8944
  format %{ "CMP    $op1,$op2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8945
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8946
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8947
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8948
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8949
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8950
instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8951
  match(Set icc (CmpU op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8953
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8954
  format %{ "CMP    $op1,$op2\t! unsigned" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8955
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8956
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8957
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8958
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8959
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8960
instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8961
  match(Set icc (CmpI op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8962
  effect( DEF icc, USE op1 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8963
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8964
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8965
  format %{ "CMP    $op1,$op2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8966
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8967
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8968
  ins_pipe(ialu_cconly_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8969
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8970
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8971
instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8972
  match(Set icc (CmpI (AndI op1 op2) zero));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8973
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8974
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8975
  format %{ "BTST   $op2,$op1" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8976
  opcode(Assembler::andcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8977
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8978
  ins_pipe(ialu_cconly_reg_reg_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8979
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8980
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8981
instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8982
  match(Set icc (CmpI (AndI op1 op2) zero));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8983
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8984
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8985
  format %{ "BTST   $op2,$op1" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8986
  opcode(Assembler::andcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8987
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8988
  ins_pipe(ialu_cconly_reg_imm_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8989
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8990
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8991
instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8992
  match(Set xcc (CmpL op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8993
  effect( DEF xcc, USE op1, USE op2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8994
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8995
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8996
  format %{ "CMP    $op1,$op2\t\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8997
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8998
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  8999
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9000
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9001
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9002
instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9003
  match(Set xcc (CmpL op1 con));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9004
  effect( DEF xcc, USE op1, USE con );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9005
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9006
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9007
  format %{ "CMP    $op1,$con\t\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9008
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9009
  ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9010
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9011
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9012
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9013
instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9014
  match(Set xcc (CmpL (AndL op1 op2) zero));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9015
  effect( DEF xcc, USE op1, USE op2 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9016
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9017
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9018
  format %{ "BTST   $op1,$op2\t\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9019
  opcode(Assembler::andcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9020
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9021
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9022
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9023
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9024
// useful for checking the alignment of a pointer:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9025
instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9026
  match(Set xcc (CmpL (AndL op1 con) zero));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9027
  effect( DEF xcc, USE op1, USE con );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9028
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9029
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9030
  format %{ "BTST   $op1,$con\t\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9031
  opcode(Assembler::andcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9032
  ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9033
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9034
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9035
22513
dc47bc8ecb75 8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents: 22512
diff changeset
  9036
instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9037
  match(Set icc (CmpU op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9038
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9039
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9040
  format %{ "CMP    $op1,$op2\t! unsigned" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9041
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9042
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9043
  ins_pipe(ialu_cconly_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9044
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9045
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9046
// Compare Pointers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9047
instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9048
  match(Set pcc (CmpP op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9049
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9050
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9051
  format %{ "CMP    $op1,$op2\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9052
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9053
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9054
  ins_pipe(ialu_cconly_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9055
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9056
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9057
instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9058
  match(Set pcc (CmpP op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9059
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9060
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9061
  format %{ "CMP    $op1,$op2\t! ptr" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9062
  opcode(Assembler::subcc_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9063
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9064
  ins_pipe(ialu_cconly_reg_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9065
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9066
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9067
// Compare Narrow oops
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9068
instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9069
  match(Set icc (CmpN op1 op2));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9070
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9071
  size(4);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9072
  format %{ "CMP    $op1,$op2\t! compressed ptr" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9073
  opcode(Assembler::subcc_op3, Assembler::arith_op);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9074
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9075
  ins_pipe(ialu_cconly_reg_reg);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9076
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9077
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9078
instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9079
  match(Set icc (CmpN op1 op2));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9080
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9081
  size(4);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9082
  format %{ "CMP    $op1,$op2\t! compressed ptr" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9083
  opcode(Assembler::subcc_op3, Assembler::arith_op);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9084
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9085
  ins_pipe(ialu_cconly_reg_imm);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9086
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9087
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9088
//----------Max and Min--------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9089
// Min Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9090
// Conditional move for min
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9091
instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9092
  effect( USE_DEF op2, USE op1, USE icc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9093
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9094
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9095
  format %{ "MOVlt  icc,$op1,$op2\t! min" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9096
  opcode(Assembler::less);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9097
  ins_encode( enc_cmov_reg_minmax(op2,op1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9098
  ins_pipe(ialu_reg_flags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9099
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9100
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9101
// Min Register with Register.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9102
instruct minI_eReg(iRegI op1, iRegI op2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9103
  match(Set op2 (MinI op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9104
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9105
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9106
    flagsReg icc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9107
    compI_iReg(icc,op1,op2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9108
    cmovI_reg_lt(op2,op1,icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9109
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9110
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9111
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9112
// Max Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9113
// Conditional move for max
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9114
instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9115
  effect( USE_DEF op2, USE op1, USE icc );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9116
  format %{ "MOVgt  icc,$op1,$op2\t! max" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9117
  opcode(Assembler::greater);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9118
  ins_encode( enc_cmov_reg_minmax(op2,op1) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9119
  ins_pipe(ialu_reg_flags);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9120
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9121
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9122
// Max Register with Register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9123
instruct maxI_eReg(iRegI op1, iRegI op2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9124
  match(Set op2 (MaxI op1 op2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9125
  ins_cost(DEFAULT_COST*2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9126
  expand %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9127
    flagsReg icc;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9128
    compI_iReg(icc,op1,op2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9129
    cmovI_reg_gt(op2,op1,icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9130
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9131
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9132
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9133
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9134
//----------Float Compares----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9135
// Compare floating, generate condition code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9136
instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9137
  match(Set fcc (CmpF src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9138
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9139
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9140
  format %{ "FCMPs  $fcc,$src1,$src2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9141
  opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9142
  ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9143
  ins_pipe(faddF_fcc_reg_reg_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9144
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9145
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9146
instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9147
  match(Set fcc (CmpD src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9148
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9149
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9150
  format %{ "FCMPd  $fcc,$src1,$src2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9151
  opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9152
  ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9153
  ins_pipe(faddD_fcc_reg_reg_zero);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9154
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9155
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9156
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9157
// Compare floating, generate -1,0,1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9158
instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9159
  match(Set dst (CmpF3 src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9160
  effect(KILL fcc0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9161
  ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9162
  format %{ "fcmpl  $dst,$src1,$src2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9163
  // Primary = float
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9164
  opcode( true );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9165
  ins_encode( floating_cmp( dst, src1, src2 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9166
  ins_pipe( floating_cmp );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9167
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9168
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9169
instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9170
  match(Set dst (CmpD3 src1 src2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9171
  effect(KILL fcc0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9172
  ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9173
  format %{ "dcmpl  $dst,$src1,$src2" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9174
  // Primary = double (not float)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9175
  opcode( false );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9176
  ins_encode( floating_cmp( dst, src1, src2 ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9177
  ins_pipe( floating_cmp );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9178
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9179
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9180
//----------Branches---------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9181
// Jump
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9182
// (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9183
instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9184
  match(Jump switch_val);
11444
8a2619fd3fca 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM
kvn
parents: 11431
diff changeset
  9185
  effect(TEMP table);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9186
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9187
  ins_cost(350);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9188
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9189
  format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9190
             "LD     [O7 + $switch_val], O7\n\t"
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9191
             "JUMP   O7" %}
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9192
  ins_encode %{
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9193
    // Calculate table address into a register.
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9194
    Register table_reg;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9195
    Register label_reg = O7;
11190
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9196
    // If we are calculating the size of this instruction don't trust
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9197
    // zero offsets because they might change when
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9198
    // MachConstantBaseNode decides to optimize the constant table
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9199
    // base.
d561d41f241a 7003454: order constants in constant table by number of references in code
twisti
parents: 10971
diff changeset
  9200
    if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9201
      table_reg = $constanttablebase;
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9202
    } else {
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9203
      table_reg = O7;
7437
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  9204
      RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
270cb0bf17af 7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents: 7433
diff changeset
  9205
      __ add($constanttablebase, con_offset, table_reg);
7433
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9206
    }
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9207
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9208
    // Jump to base address + switch value
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9209
    __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9210
    __ jmp(label_reg, G0);
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9211
    __ delayed()->nop();
b418028612ad 6961690: load oops from constant table on SPARC
twisti
parents: 7116
diff changeset
  9212
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9213
  ins_pipe(ialu_reg_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9214
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9215
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9216
// Direct Branch.  Use V8 version with longer range.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9217
instruct branch(label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9218
  match(Goto);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9219
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9220
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9221
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9222
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9223
  format %{ "BA     $labl" %}
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9224
  ins_encode %{
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9225
    Label* L = $labl$$label;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9226
    __ ba(*L);
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9227
    __ delayed()->nop();
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9228
  %}
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9229
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9230
  ins_pipe(br);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9231
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9232
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9233
// Direct Branch, short with no delay slot
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9234
instruct branch_short(label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9235
  match(Goto);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9236
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9237
  effect(USE labl);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9238
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9239
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9240
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9241
  format %{ "BA     $labl\t! short branch" %}
22832
03720a5b7595 8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents: 19319
diff changeset
  9242
  ins_encode %{
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9243
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9244
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9245
    __ ba_short(*L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9246
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9247
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9248
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9249
  ins_pipe(cbcond_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9250
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9251
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9252
// Conditional Direct Branch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9253
instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9254
  match(If cmp icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9255
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9256
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9257
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9258
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9259
  format %{ "BP$cmp   $icc,$labl" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9260
  // Prim = bits 24-22, Secnd = bits 31-30
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9261
  ins_encode( enc_bp( labl, cmp, icc ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9262
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9263
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9264
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9265
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9266
instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9267
  match(If cmp icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9268
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9269
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9270
  ins_cost(BRANCH_COST);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9271
  format %{ "BP$cmp  $icc,$labl" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9272
  // Prim = bits 24-22, Secnd = bits 31-30
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9273
  ins_encode( enc_bp( labl, cmp, icc ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9274
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9275
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9276
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9277
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9278
instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9279
  match(If cmp pcc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9280
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9281
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9282
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9283
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9284
  format %{ "BP$cmp  $pcc,$labl" %}
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9285
  ins_encode %{
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9286
    Label* L = $labl$$label;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9287
    Assembler::Predict predict_taken =
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9288
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9289
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9290
    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9291
    __ delayed()->nop();
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9292
  %}
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9293
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9294
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9295
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9296
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9297
instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9298
  match(If cmp fcc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9299
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9300
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9301
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9302
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9303
  format %{ "FBP$cmp $fcc,$labl" %}
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9304
  ins_encode %{
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9305
    Label* L = $labl$$label;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9306
    Assembler::Predict predict_taken =
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9307
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9308
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9309
    __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9310
    __ delayed()->nop();
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9311
  %}
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9312
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9313
  ins_pipe(br_fcc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9314
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9315
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9316
instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9317
  match(CountedLoopEnd cmp icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9318
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9319
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9320
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9321
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9322
  format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9323
  // Prim = bits 24-22, Secnd = bits 31-30
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9324
  ins_encode( enc_bp( labl, cmp, icc ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9325
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9326
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9327
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9328
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9329
instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9330
  match(CountedLoopEnd cmp icc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9331
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9332
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9333
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9334
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9335
  format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9336
  // Prim = bits 24-22, Secnd = bits 31-30
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9337
  ins_encode( enc_bp( labl, cmp, icc ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9338
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9339
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9340
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9341
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9342
// Compare and branch instructions
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9343
instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9344
  match(If cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9345
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9346
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9347
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9348
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9349
  format %{ "CMP    $op1,$op2\t! int\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9350
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9351
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9352
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9353
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9354
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9355
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9356
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9357
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9358
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9359
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9360
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9361
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9362
instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9363
  match(If cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9364
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9365
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9366
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9367
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9368
  format %{ "CMP    $op1,$op2\t! int\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9369
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9370
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9371
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9372
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9373
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9374
    __ cmp($op1$$Register, $op2$$constant);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9375
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9376
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9377
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9378
  ins_pipe(cmp_br_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9379
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9380
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9381
instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9382
  match(If cmp (CmpU op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9383
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9384
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9385
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9386
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9387
  format %{ "CMP    $op1,$op2\t! unsigned\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9388
            "BP$cmp  $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9389
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9390
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9391
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9392
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9393
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9394
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9395
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9396
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9397
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9398
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9399
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9400
instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9401
  match(If cmp (CmpU op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9402
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9403
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9404
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9405
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9406
  format %{ "CMP    $op1,$op2\t! unsigned\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9407
            "BP$cmp  $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9408
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9409
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9410
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9411
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9412
    __ cmp($op1$$Register, $op2$$constant);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9413
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9414
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9415
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9416
  ins_pipe(cmp_br_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9417
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9418
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9419
instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9420
  match(If cmp (CmpL op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9421
  effect(USE labl, KILL xcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9422
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9423
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9424
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9425
  format %{ "CMP    $op1,$op2\t! long\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9426
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9427
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9428
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9429
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9430
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9431
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9432
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9433
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9434
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9435
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9436
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9437
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9438
instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9439
  match(If cmp (CmpL op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9440
  effect(USE labl, KILL xcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9441
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9442
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9443
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9444
  format %{ "CMP    $op1,$op2\t! long\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9445
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9446
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9447
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9448
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9449
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9450
    __ cmp($op1$$Register, $op2$$constant);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9451
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9452
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9453
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9454
  ins_pipe(cmp_br_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9455
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9456
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9457
// Compare Pointers and branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9458
instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9459
  match(If cmp (CmpP op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9460
  effect(USE labl, KILL pcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9461
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9462
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9463
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9464
  format %{ "CMP    $op1,$op2\t! ptr\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9465
            "B$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9466
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9467
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9468
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9469
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9470
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9471
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9472
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9473
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9474
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9475
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9476
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9477
instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9478
  match(If cmp (CmpP op1 null));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9479
  effect(USE labl, KILL pcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9480
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9481
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9482
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9483
  format %{ "CMP    $op1,0\t! ptr\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9484
            "B$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9485
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9486
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9487
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9488
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9489
    __ cmp($op1$$Register, G0);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9490
    // bpr() is not used here since it has shorter distance.
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9491
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9492
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9493
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9494
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9495
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9496
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9497
instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9498
  match(If cmp (CmpN op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9499
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9500
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9501
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9502
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9503
  format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9504
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9505
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9506
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9507
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9508
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9509
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9510
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9511
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9512
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9513
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9514
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9515
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9516
instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9517
  match(If cmp (CmpN op1 null));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9518
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9519
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9520
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9521
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9522
  format %{ "CMP    $op1,0\t! compressed ptr\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9523
            "BP$cmp   $labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9524
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9525
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9526
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9527
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9528
    __ cmp($op1$$Register, G0);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9529
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9530
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9531
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9532
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9533
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9534
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9535
// Loop back branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9536
instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9537
  match(CountedLoopEnd cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9538
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9539
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9540
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9541
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9542
  format %{ "CMP    $op1,$op2\t! int\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9543
            "BP$cmp   $labl\t! Loop end" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9544
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9545
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9546
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9547
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9548
    __ cmp($op1$$Register, $op2$$Register);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9549
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9550
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9551
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9552
  ins_pipe(cmp_br_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9553
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9554
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9555
instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9556
  match(CountedLoopEnd cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9557
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9558
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9559
  size(12);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9560
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9561
  format %{ "CMP    $op1,$op2\t! int\n\t"
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9562
            "BP$cmp   $labl\t! Loop end" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9563
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9564
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9565
    Assembler::Predict predict_taken =
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9566
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9567
    __ cmp($op1$$Register, $op2$$constant);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9568
    __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9569
    __ delayed()->nop();
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9570
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9571
  ins_pipe(cmp_br_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9572
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9573
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9574
// Short compare and branch instructions
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9575
instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9576
  match(If cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9577
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9578
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9579
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9580
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9581
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9582
  format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9583
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9584
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9585
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9586
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9587
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9588
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9589
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9590
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9591
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9592
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9593
instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9594
  match(If cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9595
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9596
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9597
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9598
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9599
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9600
  format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9601
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9602
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9603
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9604
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9605
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9606
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9607
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9608
  ins_pipe(cbcond_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9609
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9610
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9611
instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9612
  match(If cmp (CmpU op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9613
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9614
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9615
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9616
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9617
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9618
  format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9619
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9620
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9621
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9622
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9623
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9624
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9625
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9626
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9627
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9628
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9629
instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9630
  match(If cmp (CmpU op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9631
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9632
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9633
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9634
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9635
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9636
  format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9637
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9638
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9639
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9640
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9641
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9642
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9643
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9644
  ins_pipe(cbcond_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9645
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9646
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9647
instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9648
  match(If cmp (CmpL op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9649
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9650
  effect(USE labl, KILL xcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9651
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9652
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9653
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9654
  format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9655
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9656
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9657
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9658
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9659
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9660
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9661
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9662
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9663
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9664
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9665
instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9666
  match(If cmp (CmpL op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9667
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9668
  effect(USE labl, KILL xcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9669
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9670
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9671
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9672
  format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9673
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9674
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9675
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9676
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9677
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9678
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9679
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9680
  ins_pipe(cbcond_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9681
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9682
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9683
// Compare Pointers and branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9684
instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9685
  match(If cmp (CmpP op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9686
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9687
  effect(USE labl, KILL pcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9688
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9689
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9690
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9691
#ifdef _LP64
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9692
  format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9693
#else
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9694
  format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9695
#endif
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9696
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9697
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9698
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9699
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9700
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9701
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9702
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9703
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9704
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9705
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9706
instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9707
  match(If cmp (CmpP op1 null));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9708
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9709
  effect(USE labl, KILL pcc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9710
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9711
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9712
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9713
#ifdef _LP64
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9714
  format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9715
#else
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9716
  format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9717
#endif
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9718
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9719
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9720
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9721
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9722
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9723
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9724
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9725
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9726
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9727
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9728
instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9729
  match(If cmp (CmpN op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9730
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9731
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9732
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9733
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9734
  ins_cost(BRANCH_COST);
25741
aa6844e3ab10 8051550: Printing of 'cmpN_reg_branch_short' instruction shows wrong 'op2' register
thartmann
parents: 24932
diff changeset
  9735
  format %{ "CWB$cmp  $op1,$op2,$labl\t! compressed ptr" %}
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9736
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9737
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9738
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9739
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9740
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9741
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9742
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9743
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9744
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9745
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9746
instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9747
  match(If cmp (CmpN op1 null));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9748
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9749
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9750
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9751
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9752
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9753
  format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9754
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9755
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9756
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9757
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9758
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9759
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9760
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9761
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9762
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9763
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9764
// Loop back branch
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9765
instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9766
  match(CountedLoopEnd cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9767
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9768
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9769
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9770
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9771
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9772
  format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9773
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9774
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9775
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9776
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9777
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9778
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9779
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9780
  ins_pipe(cbcond_reg_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9781
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9782
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9783
instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9784
  match(CountedLoopEnd cmp (CmpI op1 op2));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9785
  predicate(UseCBCond);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9786
  effect(USE labl, KILL icc);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9787
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9788
  size(4);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9789
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9790
  format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9791
  ins_encode %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9792
    Label* L = $labl$$label;
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9793
    assert(__ use_cbcond(*L), "back to back cbcond");
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9794
    __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9795
  %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9796
  ins_short_branch(1);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9797
  ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9798
  ins_pipe(cbcond_reg_imm);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9799
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9800
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9801
// Branch-on-register tests all 64 bits.  We assume that values
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9802
// in 64-bit registers always remains zero or sign extended
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9803
// unless our code munges the high bits.  Interrupts can chop
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9804
// the high order bits to zero or sign at any time.
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9805
instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9806
  match(If cmp (CmpI op1 zero));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9807
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9808
  effect(USE labl);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9809
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9810
  size(8);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9811
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9812
  format %{ "BR$cmp   $op1,$labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9813
  ins_encode( enc_bpr( labl, cmp, op1 ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9814
  ins_avoid_back_to_back(AVOID_BEFORE);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9815
  ins_pipe(br_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9816
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9817
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9818
instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9819
  match(If cmp (CmpP op1 null));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9820
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9821
  effect(USE labl);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9822
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9823
  size(8);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9824
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9825
  format %{ "BR$cmp   $op1,$labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9826
  ins_encode( enc_bpr( labl, cmp, op1 ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9827
  ins_avoid_back_to_back(AVOID_BEFORE);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9828
  ins_pipe(br_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9829
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9830
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9831
instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9832
  match(If cmp (CmpL op1 zero));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9833
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9834
  effect(USE labl);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9835
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9836
  size(8);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9837
  ins_cost(BRANCH_COST);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9838
  format %{ "BR$cmp   $op1,$labl" %}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9839
  ins_encode( enc_bpr( labl, cmp, op1 ) );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9840
  ins_avoid_back_to_back(AVOID_BEFORE);
10264
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9841
  ins_pipe(br_reg);
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9842
%}
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9843
6879f93d268d 7063629: use cbcond in C2 generated code on T4
kvn
parents: 10262
diff changeset
  9844
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9845
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9846
// Long Compare
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9847
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9848
// Currently we hold longs in 2 registers.  Comparing such values efficiently
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9849
// is tricky.  The flavor of compare used depends on whether we are testing
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9850
// for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9851
// The GE test is the negated LT test.  The LE test can be had by commuting
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9852
// the operands (yielding a GE test) and then negating; negate again for the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9853
// GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9854
// NE test is negated from that.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9855
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9856
// Due to a shortcoming in the ADLC, it mixes up expressions like:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9857
// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9858
// difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9859
// are collapsed internally in the ADLC's dfa-gen code.  The match for
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9860
// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9861
// foo match ends up with the wrong leaf.  One fix is to not match both
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9862
// reg-reg and reg-zero forms of long-compare.  This is unfortunate because
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9863
// both forms beat the trinary form of long-compare and both are very useful
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9864
// on Intel which has so few registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9865
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9866
instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9867
  match(If cmp xcc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9868
  effect(USE labl);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9869
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9870
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9871
  ins_cost(BRANCH_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9872
  format %{ "BP$cmp   $xcc,$labl" %}
10252
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9873
  ins_encode %{
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9874
    Label* L = $labl$$label;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9875
    Assembler::Predict predict_taken =
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9876
      cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9877
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9878
    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9879
    __ delayed()->nop();
0981ce1c3eef 7063628: Use cbcond on T4
kvn
parents: 10027
diff changeset
  9880
  %}
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
  9881
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9882
  ins_pipe(br_cc);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9883
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9884
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9885
// Manifest a CmpL3 result in an integer register.  Very painful.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9886
// This is the test to avoid.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9887
instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9888
  match(Set dst (CmpL3 src1 src2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9889
  effect( KILL ccr );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9890
  ins_cost(6*DEFAULT_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9891
  size(24);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9892
  format %{ "CMP    $src1,$src2\t\t! long\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9893
          "\tBLT,a,pn done\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9894
          "\tMOV    -1,$dst\t! delay slot\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9895
          "\tBGT,a,pn done\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9896
          "\tMOV    1,$dst\t! delay slot\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9897
          "\tCLR    $dst\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9898
    "done:"     %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9899
  ins_encode( cmpl_flag(src1,src2,dst) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9900
  ins_pipe(cmpL_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9901
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9902
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9903
// Conditional move
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9904
instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9905
  match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9906
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9907
  format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9908
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9909
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9910
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9911
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9912
instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9913
  match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9914
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9915
  format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9916
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9917
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9918
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9919
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9920
instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9921
  match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9922
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9923
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9924
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9925
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9926
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9927
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9928
instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9929
  match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9930
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9931
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9932
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9933
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9934
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9935
590
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9936
instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9937
  match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9938
  ins_cost(150);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9939
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9940
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9941
  ins_pipe(ialu_reg);
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9942
%}
2954744d7bba 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 589
diff changeset
  9943
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9944
instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9945
  match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9946
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9947
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9948
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9949
  ins_pipe(ialu_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9950
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9951
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9952
instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9953
  match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9954
  ins_cost(140);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9955
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9956
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9957
  ins_pipe(ialu_imm);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9958
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9959
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9960
instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9961
  match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9962
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9963
  opcode(0x101);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9964
  format %{ "FMOVS$cmp $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9965
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9966
  ins_pipe(int_conditional_float_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9967
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9968
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9969
instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9970
  match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9971
  ins_cost(150);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9972
  opcode(0x102);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9973
  format %{ "FMOVD$cmp $xcc,$src,$dst" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9974
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9975
  ins_pipe(int_conditional_float_move);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9976
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9977
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9978
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9979
// Safepoint Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9980
instruct safePoint_poll(iRegP poll) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9981
  match(SafePoint poll);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9982
  effect(USE poll);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9983
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9984
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9985
#ifdef _LP64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9986
  format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9987
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9988
  format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9989
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9990
  ins_encode %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9991
    __ relocate(relocInfo::poll_type);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9992
    __ ld_ptr($poll$$Register, 0, G0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9993
  %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9994
  ins_pipe(loadPollP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9995
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9996
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9997
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9998
// Call Instructions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  9999
// Call Java Static Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10000
instruct CallStaticJavaDirect( method meth ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10001
  match(CallStaticJava);
5690
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10002
  predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10003
  effect(USE meth);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10004
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10005
  size(8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10006
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10007
  format %{ "CALL,static  ; NOP ==> " %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10008
  ins_encode( Java_Static_Call( meth ), call_epilog );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10009
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10010
  ins_pipe(simple_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10011
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10012
5690
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10013
// Call Java Static Instruction (method handle version)
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10014
instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10015
  match(CallStaticJava);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10016
  predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10017
  effect(USE meth, KILL l7_mh_SP_save);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10018
10269
8a1ab847ebea 7079769: JSR 292: incorrect size() for CallStaticJavaHandle on sparc
twisti
parents: 10267
diff changeset
 10019
  size(16);
5690
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10020
  ins_cost(CALL_COST);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10021
  format %{ "CALL,static/MethodHandle" %}
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10022
  ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10023
  ins_pipe(simple_call);
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10024
%}
796ff3814b23 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 5352
diff changeset
 10025
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10026
// Call Java Dynamic Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10027
instruct CallDynamicJavaDirect( method meth ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10028
  match(CallDynamicJava);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10029
  effect(USE meth);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10030
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10031
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10032
  format %{ "SET    (empty),R_G5\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10033
            "CALL,dynamic  ; NOP ==> " %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10034
  ins_encode( Java_Dynamic_Call( meth ), call_epilog );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10035
  ins_pipe(call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10036
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10037
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10038
// Call Runtime Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10039
instruct CallRuntimeDirect(method meth, l7RegP l7) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10040
  match(CallRuntime);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10041
  effect(USE meth, KILL l7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10042
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10043
  format %{ "CALL,runtime" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10044
  ins_encode( Java_To_Runtime( meth ),
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10045
              call_epilog, adjust_long_from_native_call );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10046
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10047
  ins_pipe(simple_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10048
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10049
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10050
// Call runtime without safepoint - same as CallRuntime
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10051
instruct CallLeafDirect(method meth, l7RegP l7) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10052
  match(CallLeaf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10053
  effect(USE meth, KILL l7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10054
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10055
  format %{ "CALL,runtime leaf" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10056
  ins_encode( Java_To_Runtime( meth ),
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10057
              call_epilog,
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10058
              adjust_long_from_native_call );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10059
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10060
  ins_pipe(simple_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10061
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10062
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10063
// Call runtime without safepoint - same as CallLeaf
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10064
instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10065
  match(CallLeafNoFP);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10066
  effect(USE meth, KILL l7);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10067
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10068
  format %{ "CALL,runtime leaf nofp" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10069
  ins_encode( Java_To_Runtime( meth ),
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10070
              call_epilog,
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10071
              adjust_long_from_native_call );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10072
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10073
  ins_pipe(simple_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10074
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10075
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10076
// Tail Call; Jump from runtime stub to Java code.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10077
// Also known as an 'interprocedural jump'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10078
// Target of jump will eventually return to caller.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10079
// TailJump below removes the return address.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10080
instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10081
  match(TailCall jump_target method_oop );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10082
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10083
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10084
  format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10085
  ins_encode(form_jmpl(jump_target));
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10086
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10087
  ins_pipe(tail_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10088
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10089
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10090
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10091
// Return Instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10092
instruct Ret() %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10093
  match(Return);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10094
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10095
  // The epilogue node did the ret already.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10096
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10097
  format %{ "! return" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10098
  ins_encode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10099
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10100
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10101
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10102
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10103
// Tail Jump; remove the return address; jump to target.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10104
// TailCall above leaves the return address around.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10105
// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10106
// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10107
// "restore" before this instruction (in Epilogue), we need to materialize it
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10108
// in %i0.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10109
instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10110
  match( TailJump jump_target ex_oop );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10111
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10112
  format %{ "! discard R_O7\n\t"
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10113
            "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10114
  ins_encode(form_jmpl_set_exception_pc(jump_target));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10115
  // opcode(Assembler::jmpl_op3, Assembler::arith_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10116
  // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10117
  // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10118
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10119
  ins_pipe(tail_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10120
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10121
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10122
// Create exception oop: created by stack-crawling runtime code.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10123
// Created exception is now available to this handler, and is setup
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10124
// just prior to jumping to this handler.  No code emitted.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10125
instruct CreateException( o0RegP ex_oop )
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10126
%{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10127
  match(Set ex_oop (CreateEx));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10128
  ins_cost(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10129
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10130
  size(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10131
  // use the following format syntax
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10132
  format %{ "! exception oop is in R_O0; no code emitted" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10133
  ins_encode();
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10134
  ins_pipe(empty);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10135
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10136
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10137
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10138
// Rethrow exception:
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10139
// The exception oop will come in the first argument position.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10140
// Then JUMP (not call) to the rethrow stub code.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10141
instruct RethrowException()
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10142
%{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10143
  match(Rethrow);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10144
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10145
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10146
  // use the following format syntax
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10147
  format %{ "Jmp    rethrow_stub" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10148
  ins_encode(enc_rethrow);
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10149
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10150
  ins_pipe(tail_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10151
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10152
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10153
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10154
// Die now
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10155
instruct ShouldNotReachHere( )
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10156
%{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10157
  match(Halt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10158
  ins_cost(CALL_COST);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10159
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10160
  size(4);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10161
  // Use the following format syntax
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10162
  format %{ "ILLTRAP   ; ShouldNotReachHere" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10163
  ins_encode( form2_illtrap() );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10164
  ins_pipe(tail_call);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10165
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10166
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10167
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10168
// The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10169
// array for an instance of the superklass.  Set a hidden internal cache on a
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10170
// hit (cache is checked with exposed code in gen_subtype_check()).  Return
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10171
// not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10172
instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10173
  match(Set index (PartialSubtypeCheck sub super));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10174
  effect( KILL pcc, KILL o7 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10175
  ins_cost(DEFAULT_COST*10);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10176
  format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10177
  ins_encode( enc_PartialSubtypeCheck() );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10178
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10179
  ins_pipe(partial_subtype_check_pipe);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10180
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10181
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10182
instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10183
  match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10184
  effect( KILL idx, KILL o7 );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10185
  ins_cost(DEFAULT_COST*10);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10186
  format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10187
  ins_encode( enc_PartialSubtypeCheck() );
24008
da7059252295 8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents: 23498
diff changeset
 10188
  ins_avoid_back_to_back(AVOID_BEFORE);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10189
  ins_pipe(partial_subtype_check_pipe);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10190
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10191
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 254
diff changeset
 10192
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10193
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10194
// inlined locking and unlocking
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10195
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10196
instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10197
  match(Set pcc (FastLock object box));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10198
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10199
  effect(TEMP scratch2, USE_KILL box, KILL scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10200
  ins_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10201
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10202
  format %{ "FASTLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10203
  ins_encode( Fast_Lock(object, box, scratch, scratch2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10204
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10205
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10206
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10207
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10208
instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10209
  match(Set pcc (FastUnlock object box));
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10210
  effect(TEMP scratch2, USE_KILL box, KILL scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10211
  ins_cost(100);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10212
11445
3c768dca60f5 7125896: Eliminate nested locks
kvn
parents: 11444
diff changeset
 10213
  format %{ "FASTUNLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10214
  ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10215
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10216
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10217
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10218
// The encodings are generic.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10219
instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10220
  predicate(!use_block_zeroing(n->in(2)) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10221
  match(Set dummy (ClearArray cnt base));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10222
  effect(TEMP temp, KILL ccr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10223
  ins_cost(300);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10224
  format %{ "MOV    $cnt,$temp\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10225
    "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10226
    "        BRge   loop\t\t! Clearing loop\n"
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10227
    "        STX    G0,[$base+$temp]\t! delay slot" %}
10501
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10228
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10229
  ins_encode %{
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10230
    // Compiler ensures base is doubleword aligned and cnt is count of doublewords
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10231
    Register nof_bytes_arg    = $cnt$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10232
    Register nof_bytes_tmp    = $temp$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10233
    Register base_pointer_arg = $base$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10234
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10235
    Label loop;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10236
    __ mov(nof_bytes_arg, nof_bytes_tmp);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10237
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10238
    // Loop and clear, walking backwards through the array.
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10239
    // nof_bytes_tmp (if >0) is always the number of bytes to zero
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10240
    __ bind(loop);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10241
    __ deccc(nof_bytes_tmp, 8);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10242
    __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10243
    __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10244
    // %%%% this mini-loop must not cross a cache boundary!
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10245
  %}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10246
  ins_pipe(long_memory_op);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10247
%}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10248
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10249
instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10250
  predicate(use_block_zeroing(n->in(2)));
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10251
  match(Set dummy (ClearArray cnt base));
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10252
  effect(USE_KILL cnt, USE_KILL base, KILL ccr);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10253
  ins_cost(300);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10254
  format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10255
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10256
  ins_encode %{
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10257
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10258
    assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10259
    Register to    = $base$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10260
    Register count = $cnt$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10261
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10262
    Label Ldone;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10263
    __ nop(); // Separate short branches
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10264
    // Use BIS for zeroing (temp is not used).
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10265
    __ bis_zeroing(to, count, G0, Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10266
    __ bind(Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10267
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10268
  %}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10269
  ins_pipe(long_memory_op);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10270
%}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10271
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10272
instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10273
  predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10274
  match(Set dummy (ClearArray cnt base));
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10275
  effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10276
  ins_cost(300);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10277
  format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10278
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10279
  ins_encode %{
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10280
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10281
    assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10282
    Register to    = $base$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10283
    Register count = $cnt$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10284
    Register temp  = $tmp$$Register;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10285
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10286
    Label Ldone;
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10287
    __ nop(); // Separate short branches
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10288
    // Use BIS for zeroing
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10289
    __ bis_zeroing(to, count, temp, Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10290
    __ bind(Ldone);
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10291
5bce84af0883 7059037: Use BIS for zeroing on T4
kvn
parents: 10269
diff changeset
 10292
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10293
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10294
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10295
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10296
instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10297
                        o7RegI tmp, flagsReg ccr) %{
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10298
  match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10299
  effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10300
  ins_cost(300);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10301
  format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10302
  ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10303
  ins_pipe(long_memory_op);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10304
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10305
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10306
instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10307
                       o7RegI tmp, flagsReg ccr) %{
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10308
  match(Set result (StrEquals (Binary str1 str2) cnt));
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10309
  effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10310
  ins_cost(300);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10311
  format %{ "String Equals $str1,$str2,$cnt -> $result   // KILL $tmp" %}
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10312
  ins_encode( enc_String_Equals(str1, str2, cnt, result) );
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10313
  ins_pipe(long_memory_op);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10314
%}
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10315
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10316
instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10317
                      o7RegI tmp2, flagsReg ccr) %{
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10318
  match(Set result (AryEq ary1 ary2));
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10319
  effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10320
  ins_cost(300);
3905
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10321
  format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
7d725029ac85 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 3798
diff changeset
 10322
  ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10323
  ins_pipe(long_memory_op);
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2259
diff changeset
 10324
%}
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10325
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10326
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10327
//---------- Zeros Count Instructions ------------------------------------------
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10328
14833
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10329
instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10330
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10331
  match(Set dst (CountLeadingZerosI src));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10332
  effect(TEMP dst, TEMP tmp, KILL cr);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10333
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10334
  // x |= (x >> 1);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10335
  // x |= (x >> 2);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10336
  // x |= (x >> 4);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10337
  // x |= (x >> 8);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10338
  // x |= (x >> 16);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10339
  // return (WORDBITS - popc(x));
4096
5d08743da209 6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents: 4019
diff changeset
 10340
  format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
5d08743da209 6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents: 4019
diff changeset
 10341
            "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
5d08743da209 6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents: 4019
diff changeset
 10342
            "OR      $dst,$tmp,$dst\n\t"
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10343
            "SRL     $dst,2,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10344
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10345
            "SRL     $dst,4,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10346
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10347
            "SRL     $dst,8,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10348
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10349
            "SRL     $dst,16,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10350
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10351
            "POPC    $dst,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10352
            "MOV     32,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10353
            "SUB     $tmp,$dst,$dst" %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10354
  ins_encode %{
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10355
    Register Rdst = $dst$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10356
    Register Rsrc = $src$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10357
    Register Rtmp = $tmp$$Register;
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10358
    __ srl(Rsrc, 1,    Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10359
    __ srl(Rsrc, 0,    Rdst);
4096
5d08743da209 6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents: 4019
diff changeset
 10360
    __ or3(Rdst, Rtmp, Rdst);
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10361
    __ srl(Rdst, 2,    Rtmp);
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10362
    __ or3(Rdst, Rtmp, Rdst);
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10363
    __ srl(Rdst, 4,    Rtmp);
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10364
    __ or3(Rdst, Rtmp, Rdst);
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10365
    __ srl(Rdst, 8,    Rtmp);
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10366
    __ or3(Rdst, Rtmp, Rdst);
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10367
    __ srl(Rdst, 16,   Rtmp);
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10368
    __ or3(Rdst, Rtmp, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10369
    __ popc(Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10370
    __ mov(BitsPerInt, Rtmp);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10371
    __ sub(Rtmp, Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10372
  %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10373
  ins_pipe(ialu_reg);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10374
%}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10375
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10376
instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10377
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10378
  match(Set dst (CountLeadingZerosL src));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10379
  effect(TEMP dst, TEMP tmp, KILL cr);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10380
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10381
  // x |= (x >> 1);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10382
  // x |= (x >> 2);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10383
  // x |= (x >> 4);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10384
  // x |= (x >> 8);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10385
  // x |= (x >> 16);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10386
  // x |= (x >> 32);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10387
  // return (WORDBITS - popc(x));
4096
5d08743da209 6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents: 4019
diff changeset
 10388
  format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10389
            "OR      $src,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10390
            "SRLX    $dst,2,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10391
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10392
            "SRLX    $dst,4,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10393
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10394
            "SRLX    $dst,8,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10395
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10396
            "SRLX    $dst,16,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10397
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10398
            "SRLX    $dst,32,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10399
            "OR      $dst,$tmp,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10400
            "POPC    $dst,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10401
            "MOV     64,$tmp\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10402
            "SUB     $tmp,$dst,$dst" %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10403
  ins_encode %{
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10404
    Register Rdst = $dst$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10405
    Register Rsrc = $src$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10406
    Register Rtmp = $tmp$$Register;
7116
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10407
    __ srlx(Rsrc, 1,    Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10408
    __ or3( Rsrc, Rtmp, Rdst);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10409
    __ srlx(Rdst, 2,    Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10410
    __ or3( Rdst, Rtmp, Rdst);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10411
    __ srlx(Rdst, 4,    Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10412
    __ or3( Rdst, Rtmp, Rdst);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10413
    __ srlx(Rdst, 8,    Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10414
    __ or3( Rdst, Rtmp, Rdst);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10415
    __ srlx(Rdst, 16,   Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10416
    __ or3( Rdst, Rtmp, Rdst);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10417
    __ srlx(Rdst, 32,   Rtmp);
e24b7743e3d4 6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents: 7115
diff changeset
 10418
    __ or3( Rdst, Rtmp, Rdst);
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10419
    __ popc(Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10420
    __ mov(BitsPerLong, Rtmp);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10421
    __ sub(Rtmp, Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10422
  %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10423
  ins_pipe(ialu_reg);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10424
%}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10425
14833
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10426
instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10427
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10428
  match(Set dst (CountTrailingZerosI src));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10429
  effect(TEMP dst, KILL cr);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10430
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10431
  // return popc(~x & (x - 1));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10432
  format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10433
            "ANDN    $dst,$src,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10434
            "SRL     $dst,R_G0,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10435
            "POPC    $dst,$dst" %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10436
  ins_encode %{
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10437
    Register Rdst = $dst$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10438
    Register Rsrc = $src$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10439
    __ sub(Rsrc, 1, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10440
    __ andn(Rdst, Rsrc, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10441
    __ srl(Rdst, G0, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10442
    __ popc(Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10443
  %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10444
  ins_pipe(ialu_reg);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10445
%}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10446
10736
1a11ec86574e 7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents: 10507
diff changeset
 10447
instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10448
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10449
  match(Set dst (CountTrailingZerosL src));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10450
  effect(TEMP dst, KILL cr);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10451
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10452
  // return popc(~x & (x - 1));
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10453
  format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10454
            "ANDN    $dst,$src,$dst\n\t"
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10455
            "POPC    $dst,$dst" %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10456
  ins_encode %{
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10457
    Register Rdst = $dst$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10458
    Register Rsrc = $src$$Register;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10459
    __ sub(Rsrc, 1, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10460
    __ andn(Rdst, Rsrc, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10461
    __ popc(Rdst, Rdst);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10462
  %}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10463
  ins_pipe(ialu_reg);
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10464
%}
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10465
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2576
diff changeset
 10466
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10467
//---------- Population Count Instructions -------------------------------------
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10468
14833
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10469
instruct popCountI(iRegIsafe dst, iRegI src) %{
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10470
  predicate(UsePopCountInstruction);
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10471
  match(Set dst (PopCountI src));
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10472
14833
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10473
  format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10474
            "POPC   $dst, $dst" %}
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10475
  ins_encode %{
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10476
    __ srl($src$$Register, G0, $dst$$Register);
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10477
    __ popc($dst$$Register, $dst$$Register);
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10478
  %}
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10479
  ins_pipe(ialu_reg);
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10480
%}
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10481
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10482
// Note: Long.bitCount(long) returns an int.
14833
3c5e36997f11 8005033: clear high word for integer pop count on SPARC
twisti
parents: 13970
diff changeset
 10483
instruct popCountL(iRegIsafe dst, iRegL src) %{
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10484
  predicate(UsePopCountInstruction);
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10485
  match(Set dst (PopCountL src));
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10486
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10487
  format %{ "POPC   $src, $dst" %}
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10488
  ins_encode %{
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10489
    __ popc($src$$Register, $dst$$Register);
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10490
  %}
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10491
  ins_pipe(ialu_reg);
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10492
%}
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10493
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2254
diff changeset
 10494
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10495
// ============================================================================
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10496
//------------Bytes reverse--------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10497
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10498
instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10499
  match(Set dst (ReverseBytesI src));
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10500
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10501
  // Op cost is artificially doubled to make sure that load or store
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10502
  // instructions are preferred over this one which requires a spill
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10503
  // onto a stack slot.
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10504
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10505
  format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10506
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10507
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10508
    __ set($src$$disp + STACK_BIAS, O7);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10509
    __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10510
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10511
  ins_pipe( iload_mem );
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10512
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10513
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10514
instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10515
  match(Set dst (ReverseBytesL src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10516
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10517
  // Op cost is artificially doubled to make sure that load or store
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10518
  // instructions are preferred over this one which requires a spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10519
  // onto a stack slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10520
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10521
  format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10522
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10523
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10524
    __ set($src$$disp + STACK_BIAS, O7);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10525
    __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10526
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10527
  ins_pipe( iload_mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10528
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10529
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10530
instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10531
  match(Set dst (ReverseBytesUS src));
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10532
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10533
  // Op cost is artificially doubled to make sure that load or store
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10534
  // instructions are preferred over this one which requires a spill
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10535
  // onto a stack slot.
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10536
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10537
  format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10538
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10539
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10540
    // the value was spilled as an int so bias the load
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10541
    __ set($src$$disp + STACK_BIAS + 2, O7);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10542
    __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10543
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10544
  ins_pipe( iload_mem );
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10545
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10546
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10547
instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10548
  match(Set dst (ReverseBytesS src));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10549
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10550
  // Op cost is artificially doubled to make sure that load or store
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10551
  // instructions are preferred over this one which requires a spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10552
  // onto a stack slot.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10553
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10554
  format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10555
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10556
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10557
    // the value was spilled as an int so bias the load
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10558
    __ set($src$$disp + STACK_BIAS + 2, O7);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10559
    __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10560
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10561
  ins_pipe( iload_mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10562
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10563
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10564
// Load Integer reversed byte order
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10565
instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10566
  match(Set dst (ReverseBytesI (LoadI src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10567
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10568
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10569
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10570
  format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10571
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10572
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10573
    __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10574
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10575
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10576
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10577
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10578
// Load Long - aligned and reversed
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10579
instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10580
  match(Set dst (ReverseBytesL (LoadL src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10581
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10582
  ins_cost(MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10583
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10584
  format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10585
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10586
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10587
    __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10588
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10589
  ins_pipe(iload_mem);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10590
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10591
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10592
// Load unsigned short / char reversed byte order
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10593
instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10594
  match(Set dst (ReverseBytesUS (LoadUS src)));
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10595
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10596
  ins_cost(MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10597
  size(4);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10598
  format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10599
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10600
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10601
    __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10602
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10603
  ins_pipe(iload_mem);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10604
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10605
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10606
// Load short reversed byte order
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10607
instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10608
  match(Set dst (ReverseBytesS (LoadS src)));
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10609
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10610
  ins_cost(MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10611
  size(4);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10612
  format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10613
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10614
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10615
    __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10616
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10617
  ins_pipe(iload_mem);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10618
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10619
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10620
// Store Integer reversed byte order
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10621
instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10622
  match(Set dst (StoreI dst (ReverseBytesI src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10623
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10624
  ins_cost(MEMORY_REF_COST);
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10625
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10626
  format %{ "STWA   $src, $dst\t!asi=primary_little" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10627
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10628
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10629
    __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10630
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10631
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10632
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10633
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10634
// Store Long reversed byte order
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10635
instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10636
  match(Set dst (StoreL dst (ReverseBytesL src)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10637
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10638
  ins_cost(MEMORY_REF_COST);
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10639
  size(4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10640
  format %{ "STXA   $src, $dst\t!asi=primary_little" %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10641
5352
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10642
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10643
    __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10644
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10645
  ins_pipe(istore_mem_reg);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10646
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10647
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10648
// Store unsighed short/char reversed byte order
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10649
instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10650
  match(Set dst (StoreC dst (ReverseBytesUS src)));
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10651
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10652
  ins_cost(MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10653
  size(4);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10654
  format %{ "STHA   $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10655
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10656
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10657
    __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10658
  %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10659
  ins_pipe(istore_mem_reg);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10660
%}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10661
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10662
// Store short reversed byte order
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10663
instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10664
  match(Set dst (StoreC dst (ReverseBytesS src)));
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10665
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10666
  ins_cost(MEMORY_REF_COST);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10667
  size(4);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10668
  format %{ "STHA   $src, $dst\t!asi=primary_little" %}
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10669
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10670
  ins_encode %{
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10671
    __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
cee8f7acb7bc 6946040: add intrinsic for short and char reverseBytes
never
parents: 5251
diff changeset
 10672
  %}
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10673
  ins_pipe(istore_mem_reg);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10674
%}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10675
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10676
// ====================VECTOR INSTRUCTIONS=====================================
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10677
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10678
// Load Aligned Packed values into a Double Register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10679
instruct loadV8(regD dst, memory mem) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10680
  predicate(n->as_LoadVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10681
  match(Set dst (LoadVector mem));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10682
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10683
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10684
  format %{ "LDDF   $mem,$dst\t! load vector (8 bytes)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10685
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10686
    __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10687
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10688
  ins_pipe(floadD_mem);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10689
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10690
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10691
// Store Vector in Double register to memory
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10692
instruct storeV8(memory mem, regD src) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10693
  predicate(n->as_StoreVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10694
  match(Set mem (StoreVector mem src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10695
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10696
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10697
  format %{ "STDF   $src,$mem\t! store vector (8 bytes)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10698
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10699
    __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10700
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10701
  ins_pipe(fstoreD_mem_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10702
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10703
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10704
// Store Zero into vector in memory
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10705
instruct storeV8B_zero(memory mem, immI0 zero) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10706
  predicate(n->as_StoreVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10707
  match(Set mem (StoreVector mem (ReplicateB zero)));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10708
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10709
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10710
  format %{ "STX    $zero,$mem\t! store zero vector (8 bytes)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10711
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10712
    __ stx(G0, $mem$$Address);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10713
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10714
  ins_pipe(fstoreD_mem_zero);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10715
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10716
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10717
instruct storeV4S_zero(memory mem, immI0 zero) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10718
  predicate(n->as_StoreVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10719
  match(Set mem (StoreVector mem (ReplicateS zero)));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10720
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10721
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10722
  format %{ "STX    $zero,$mem\t! store zero vector (4 shorts)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10723
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10724
    __ stx(G0, $mem$$Address);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10725
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10726
  ins_pipe(fstoreD_mem_zero);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10727
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10728
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10729
instruct storeV2I_zero(memory mem, immI0 zero) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10730
  predicate(n->as_StoreVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10731
  match(Set mem (StoreVector mem (ReplicateI zero)));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10732
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10733
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10734
  format %{ "STX    $zero,$mem\t! store zero vector (2 ints)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10735
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10736
    __ stx(G0, $mem$$Address);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10737
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10738
  ins_pipe(fstoreD_mem_zero);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10739
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10740
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10741
instruct storeV2F_zero(memory mem, immF0 zero) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10742
  predicate(n->as_StoreVector()->memory_size() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10743
  match(Set mem (StoreVector mem (ReplicateF zero)));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10744
  ins_cost(MEMORY_REF_COST);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10745
  size(4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10746
  format %{ "STX    $zero,$mem\t! store zero vector (2 floats)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10747
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10748
    __ stx(G0, $mem$$Address);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10749
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10750
  ins_pipe(fstoreD_mem_zero);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10751
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10752
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10753
// Replicate scalar to packed byte values into Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10754
instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10755
  predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10756
  match(Set dst (ReplicateB src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10757
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10758
  format %{ "SLLX  $src,56,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10759
            "SRLX  $tmp, 8,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10760
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10761
            "SRLX  $tmp,16,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10762
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10763
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10764
            "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10765
            "MOVXTOD $tmp,$dst\t! MoveL2D" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10766
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10767
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10768
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10769
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10770
    __ sllx(Rsrc,    56, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10771
    __ srlx(Rtmp,     8, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10772
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10773
    __ srlx(Rtmp,    16, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10774
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10775
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10776
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10777
    __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10778
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10779
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10780
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10781
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10782
// Replicate scalar to packed byte values into Double stack
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10783
instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10784
  predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10785
  match(Set dst (ReplicateB src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10786
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10787
  format %{ "SLLX  $src,56,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10788
            "SRLX  $tmp, 8,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10789
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10790
            "SRLX  $tmp,16,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10791
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10792
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10793
            "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10794
            "STX   $tmp,$dst\t! regL to stkD" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10795
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10796
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10797
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10798
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10799
    __ sllx(Rsrc,    56, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10800
    __ srlx(Rtmp,     8, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10801
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10802
    __ srlx(Rtmp,    16, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10803
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10804
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10805
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10806
    __ set ($dst$$disp + STACK_BIAS, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10807
    __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10808
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10809
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10810
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10811
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10812
// Replicate scalar constant to packed byte values in Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10813
instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10814
  predicate(n->as_Vector()->length() == 8);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10815
  match(Set dst (ReplicateB con));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10816
  effect(KILL tmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10817
  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10818
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10819
    // XXX This is a quick fix for 6833573.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10820
    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10821
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10822
    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10823
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10824
  ins_pipe(loadConFD);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10825
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10826
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10827
// Replicate scalar to packed char/short values into Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10828
instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10829
  predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10830
  match(Set dst (ReplicateS src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10831
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10832
  format %{ "SLLX  $src,48,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10833
            "SRLX  $tmp,16,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10834
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10835
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10836
            "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10837
            "MOVXTOD $tmp,$dst\t! MoveL2D" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10838
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10839
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10840
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10841
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10842
    __ sllx(Rsrc,    48, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10843
    __ srlx(Rtmp,    16, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10844
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10845
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10846
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10847
    __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10848
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10849
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10850
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10851
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10852
// Replicate scalar to packed char/short values into Double stack
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10853
instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10854
  predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10855
  match(Set dst (ReplicateS src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10856
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10857
  format %{ "SLLX  $src,48,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10858
            "SRLX  $tmp,16,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10859
            "OR    $tmp,$tmp2,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10860
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10861
            "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10862
            "STX   $tmp,$dst\t! regL to stkD" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10863
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10864
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10865
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10866
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10867
    __ sllx(Rsrc,    48, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10868
    __ srlx(Rtmp,    16, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10869
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10870
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10871
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10872
    __ set ($dst$$disp + STACK_BIAS, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10873
    __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10874
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10875
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10876
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10877
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10878
// Replicate scalar constant to packed char/short values in Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10879
instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10880
  predicate(n->as_Vector()->length() == 4);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10881
  match(Set dst (ReplicateS con));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10882
  effect(KILL tmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10883
  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10884
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10885
    // XXX This is a quick fix for 6833573.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10886
    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10887
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10888
    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10889
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10890
  ins_pipe(loadConFD);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10891
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10892
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10893
// Replicate scalar to packed int values into Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10894
instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10895
  predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10896
  match(Set dst (ReplicateI src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10897
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10898
  format %{ "SLLX  $src,32,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10899
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10900
            "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10901
            "MOVXTOD $tmp,$dst\t! MoveL2D" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10902
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10903
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10904
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10905
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10906
    __ sllx(Rsrc,    32, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10907
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10908
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10909
    __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10910
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10911
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10912
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10913
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10914
// Replicate scalar to packed int values into Double stack
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10915
instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10916
  predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10917
  match(Set dst (ReplicateI src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10918
  effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10919
  format %{ "SLLX  $src,32,$tmp\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10920
            "SRLX  $tmp,32,$tmp2\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10921
            "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10922
            "STX   $tmp,$dst\t! regL to stkD" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10923
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10924
    Register Rsrc = $src$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10925
    Register Rtmp = $tmp$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10926
    Register Rtmp2 = $tmp2$$Register;
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10927
    __ sllx(Rsrc,    32, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10928
    __ srlx(Rtmp,    32, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10929
    __ or3 (Rtmp, Rtmp2, Rtmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10930
    __ set ($dst$$disp + STACK_BIAS, Rtmp2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10931
    __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10932
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10933
  ins_pipe(ialu_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10934
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10935
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10936
// Replicate scalar zero constant to packed int values in Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10937
instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10938
  predicate(n->as_Vector()->length() == 2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10939
  match(Set dst (ReplicateI con));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10940
  effect(KILL tmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10941
  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10942
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10943
    // XXX This is a quick fix for 6833573.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10944
    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10945
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10946
    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10947
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10948
  ins_pipe(loadConFD);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10949
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10950
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10951
// Replicate scalar to packed float values into Double stack
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10952
instruct Repl2F_stk(stackSlotD dst, regF src) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10953
  predicate(n->as_Vector()->length() == 2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10954
  match(Set dst (ReplicateF src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10955
  ins_cost(MEMORY_REF_COST*2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10956
  format %{ "STF    $src,$dst.hi\t! packed2F\n\t"
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10957
            "STF    $src,$dst.lo" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10958
  opcode(Assembler::stf_op3);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10959
  ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10960
  ins_pipe(fstoreF_stk_reg);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10961
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10962
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10963
// Replicate scalar zero constant to packed float values in Double register
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10964
instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10965
  predicate(n->as_Vector()->length() == 2);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10966
  match(Set dst (ReplicateF con));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10967
  effect(KILL tmp);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10968
  format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10969
  ins_encode %{
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10970
    // XXX This is a quick fix for 6833573.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10971
    //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10972
    RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10973
    __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10974
  %}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10975
  ins_pipe(loadConFD);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10976
%}
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 12957
diff changeset
 10977
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10978
//----------PEEPHOLE RULES-----------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10979
// These must follow all instruction definitions as they use the names
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10980
// defined in the instructions definitions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10981
//
2131
98f9cef66a34 6810672: Comment typos
twisti
parents: 2022
diff changeset
 10982
// peepmatch ( root_instr_name [preceding_instruction]* );
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10983
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10984
// peepconstraint %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10985
// (instruction_number.operand_name relational_op instruction_number.operand_name
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10986
//  [, ...] );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10987
// // instruction numbers are zero-based using left to right order in peepmatch
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10988
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10989
// peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10990
// // provide an instruction_number.operand_name for each operand that appears
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10991
// // in the replacement instruction's match rule
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10992
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10993
// ---------VM FLAGS---------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10994
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10995
// All peephole optimizations can be turned off using -XX:-OptoPeephole
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10996
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10997
// Each peephole rule is given an identifying number starting with zero and
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10998
// increasing by one in the order seen by the parser.  An individual peephole
489c9b5090e2 Initial load
duke
parents:
diff changeset
 10999
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11000
// on the command-line.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11001
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11002
// ---------CURRENT LIMITATIONS----------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11003
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11004
// Only match adjacent instructions in same basic block
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11005
// Only equality constraints
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11006
// Only constraints between operands, not (0.dest_reg == EAX_enc)
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11007
// Only one replacement instruction
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11008
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11009
// ---------EXAMPLE----------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11010
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11011
// // pertinent parts of existing instructions in architecture description
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11012
// instruct movI(eRegI dst, eRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11013
//   match(Set dst (CopyI src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11014
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11015
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11016
// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11017
//   match(Set dst (AddI dst src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11018
//   effect(KILL cr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11019
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11020
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11021
// // Change (inc mov) to lea
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11022
// peephole %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11023
//   // increment preceeded by register-register move
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11024
//   peepmatch ( incI_eReg movI );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11025
//   // require that the destination register of the increment
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11026
//   // match the destination register of the move
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11027
//   peepconstraint ( 0.dst == 1.dst );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11028
//   // construct a replacement instruction that sets
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11029
//   // the destination to ( move's source register + one )
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11030
//   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11031
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11032
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11033
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11034
// // Change load of spilled value to only a spill
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11035
// instruct storeI(memory mem, eRegI src) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11036
//   match(Set mem (StoreI mem src));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11037
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11038
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11039
// instruct loadI(eRegI dst, memory mem) %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11040
//   match(Set dst (LoadI mem));
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11041
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11042
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11043
// peephole %{
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11044
//   peepmatch ( loadI storeI );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11045
//   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11046
//   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11047
// %}
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11048
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11049
//----------SMARTSPILL RULES---------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11050
// These must follow all instruction definitions as they use the names
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11051
// defined in the instructions definitions.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11052
//
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11053
// SPARC will probably not have any of these rules due to RISC instruction set.
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11054
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11055
//----------PIPELINE-----------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
 11056
// Rules which define the behavior of the target architectures pipeline.