author | lana |
Thu, 16 Oct 2014 14:15:58 -0700 | |
changeset 27113 | 28c10766cfac |
parent 26804 | 4b23f22faae6 |
child 28719 | 5a9aedf87213 |
permissions | -rw-r--r-- |
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// |
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// Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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// |
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// This code is free software; you can redistribute it and/or modify it |
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// under the terms of the GNU General Public License version 2 only, as |
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// published by the Free Software Foundation. |
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// |
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// This code is distributed in the hope that it will be useful, but WITHOUT |
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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// version 2 for more details (a copy is included in the LICENSE file that |
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// accompanied this code). |
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// |
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// You should have received a copy of the GNU General Public License version |
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// 2 along with this work; if not, write to the Free Software Foundation, |
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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// |
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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// or visit www.oracle.com if you need additional information or have any |
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// questions. |
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// |
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// |
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// SPARC Architecture Description File |
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//----------REGISTER DEFINITION BLOCK------------------------------------------ |
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// This information is used by the matcher and the register allocator to |
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// describe individual registers and classes of registers within the target |
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// archtecture. |
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register %{ |
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//----------Architecture Description Register Definitions---------------------- |
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// General Registers |
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// "reg_def" name ( register save type, C convention save type, |
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// ideal register type, encoding, vm name ); |
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// Register Save Types: |
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// |
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// NS = No-Save: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, & |
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// that they do not need to be saved at call sites. |
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// |
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// SOC = Save-On-Call: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, |
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// but that they must be saved at call sites. |
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// |
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// SOE = Save-On-Entry: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, but they do not need to be saved at call |
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// sites. |
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// |
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// AS = Always-Save: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, & that they must be saved at call sites. |
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// |
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// Ideal Register Type is used to determine how to save & restore a |
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// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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// |
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// The encoding number is the actual bit-pattern placed into the opcodes. |
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// ---------------------------- |
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// Integer/Long Registers |
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// ---------------------------- |
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// Need to expose the hi/lo aspect of 64-bit registers |
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// This register set is used for both the 64-bit build and |
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// the 32-bit build with 1-register longs. |
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// Global Registers 0-7 |
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reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); |
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reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); |
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reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); |
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reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); |
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reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); |
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reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); |
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reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); |
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reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); |
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reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); |
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reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); |
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reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); |
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reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); |
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reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); |
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reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); |
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reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); |
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reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); |
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// Output Registers 0-7 |
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reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); |
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reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); |
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reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); |
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reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); |
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reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); |
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reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); |
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reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); |
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reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); |
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reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); |
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reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); |
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reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); |
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reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); |
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reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); |
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reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); |
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reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); |
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reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); |
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// Local Registers 0-7 |
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reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); |
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reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); |
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reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); |
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reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); |
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reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); |
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reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); |
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reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); |
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reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); |
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reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); |
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reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); |
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reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); |
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reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); |
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reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); |
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reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); |
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reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); |
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reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); |
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// Input Registers 0-7 |
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reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); |
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reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); |
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reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); |
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reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); |
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reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); |
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reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); |
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reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); |
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reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); |
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reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); |
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reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); |
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reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); |
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reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); |
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reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); |
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reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); |
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reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); |
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reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); |
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// ---------------------------- |
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// Float/Double Registers |
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// ---------------------------- |
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// Float Registers |
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reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); |
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reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); |
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reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); |
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reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); |
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reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); |
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reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); |
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reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); |
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reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); |
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reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); |
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reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); |
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reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); |
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reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); |
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reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); |
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reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); |
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reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); |
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reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); |
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reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); |
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reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); |
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reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); |
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reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); |
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reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); |
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reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); |
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reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); |
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reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); |
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reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); |
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reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); |
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reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); |
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reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); |
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reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); |
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reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); |
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reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); |
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reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); |
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// Double Registers |
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// The rules of ADL require that double registers be defined in pairs. |
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// Each pair must be two 32-bit values, but not necessarily a pair of |
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// single float registers. In each pair, ADLC-assigned register numbers |
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// must be adjacent, with the lower number even. Finally, when the |
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// CPU stores such a register pair to memory, the word associated with |
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// the lower ADLC-assigned number must be stored to the lower address. |
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// These definitions specify the actual bit encodings of the sparc |
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// double fp register numbers. FloatRegisterImpl in register_sparc.hpp |
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// wants 0-63, so we have to convert every time we want to use fp regs |
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// with the macroassembler, using reg_to_DoubleFloatRegister_object(). |
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// 255 is a flag meaning "don't go here". |
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// I believe we can't handle callee-save doubles D32 and up until |
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// the place in the sparc stack crawler that asserts on the 255 is |
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// fixed up. |
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reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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|
224 |
reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 |
reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 |
reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 |
reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
1 | 228 |
|
229 |
||
230 |
// ---------------------------- |
|
231 |
// Special Registers |
|
232 |
// Condition Codes Flag Registers |
|
233 |
// I tried to break out ICC and XCC but it's not very pretty. |
|
234 |
// Every Sparc instruction which defs/kills one also kills the other. |
|
235 |
// Hence every compare instruction which defs one kind of flags ends |
|
236 |
// up needing a kill of the other. |
|
237 |
reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); |
|
238 |
||
239 |
reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); |
|
240 |
reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); |
|
241 |
reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); |
|
242 |
reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); |
|
243 |
||
244 |
// ---------------------------- |
|
245 |
// Specify the enum values for the registers. These enums are only used by the |
|
246 |
// OptoReg "class". We can convert these enum values at will to VMReg when needed |
|
247 |
// for visibility to the rest of the vm. The order of this enum influences the |
|
248 |
// register allocator so having the freedom to set this order and not be stuck |
|
249 |
// with the order that is natural for the rest of the vm is worth it. |
|
250 |
alloc_class chunk0( |
|
251 |
R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, |
|
252 |
R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, |
|
253 |
R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, |
|
254 |
R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); |
|
255 |
||
256 |
// Note that a register is not allocatable unless it is also mentioned |
|
257 |
// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. |
|
258 |
||
259 |
alloc_class chunk1( |
|
260 |
// The first registers listed here are those most likely to be used |
|
261 |
// as temporaries. We move F0..F7 away from the front of the list, |
|
262 |
// to reduce the likelihood of interferences with parameters and |
|
263 |
// return values. Likewise, we avoid using F0/F1 for parameters, |
|
264 |
// since they are used for return values. |
|
265 |
// This FPU fine-tuning is worth about 1% on the SPEC geomean. |
|
266 |
R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, |
|
267 |
R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, |
|
268 |
R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, |
|
269 |
R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values |
|
270 |
R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, |
|
271 |
R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, |
|
272 |
R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, |
|
273 |
R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); |
|
274 |
||
275 |
alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); |
|
276 |
||
277 |
//----------Architecture Description Register Classes-------------------------- |
|
278 |
// Several register classes are automatically defined based upon information in |
|
279 |
// this architecture description. |
|
280 |
// 1) reg_class inline_cache_reg ( as defined in frame section ) |
|
281 |
// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) |
|
282 |
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) |
|
283 |
// |
|
284 |
||
285 |
// G0 is not included in integer class since it has special meaning. |
|
286 |
reg_class g0_reg(R_G0); |
|
287 |
||
288 |
// ---------------------------- |
|
289 |
// Integer Register Classes |
|
290 |
// ---------------------------- |
|
291 |
// Exclusions from i_reg: |
|
292 |
// R_G0: hardwired zero |
|
293 |
// R_G2: reserved by HotSpot to the TLS register (invariant within Java) |
|
294 |
// R_G6: reserved by Solaris ABI to tools |
|
295 |
// R_G7: reserved by Solaris ABI to libthread |
|
296 |
// R_O7: Used as a temp in many encodings |
|
297 |
reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); |
|
298 |
||
299 |
// Class for all integer registers, except the G registers. This is used for |
|
300 |
// encodings which use G registers as temps. The regular inputs to such |
|
301 |
// instructions use a "notemp_" prefix, as a hack to ensure that the allocator |
|
302 |
// will not put an input into a temp register. |
|
303 |
reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); |
|
304 |
||
305 |
reg_class g1_regI(R_G1); |
|
306 |
reg_class g3_regI(R_G3); |
|
307 |
reg_class g4_regI(R_G4); |
|
308 |
reg_class o0_regI(R_O0); |
|
309 |
reg_class o7_regI(R_O7); |
|
310 |
||
311 |
// ---------------------------- |
|
312 |
// Pointer Register Classes |
|
313 |
// ---------------------------- |
|
314 |
#ifdef _LP64 |
|
315 |
// 64-bit build means 64-bit pointers means hi/lo pairs |
|
316 |
reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, |
|
317 |
R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, |
|
318 |
R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, |
|
319 |
R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); |
|
320 |
// Lock encodings use G3 and G4 internally |
|
321 |
reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, |
|
322 |
R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, |
|
323 |
R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, |
|
324 |
R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); |
|
325 |
// Special class for storeP instructions, which can store SP or RPC to TLS. |
|
326 |
// It is also used for memory addressing, allowing direct TLS addressing. |
|
327 |
reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, |
|
328 |
R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, |
|
329 |
R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, |
|
330 |
R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); |
|
331 |
// R_L7 is the lowest-priority callee-save (i.e., NS) register |
|
332 |
// We use it to save R_G2 across calls out of Java. |
|
333 |
reg_class l7_regP(R_L7H,R_L7); |
|
334 |
||
335 |
// Other special pointer regs |
|
336 |
reg_class g1_regP(R_G1H,R_G1); |
|
337 |
reg_class g2_regP(R_G2H,R_G2); |
|
338 |
reg_class g3_regP(R_G3H,R_G3); |
|
339 |
reg_class g4_regP(R_G4H,R_G4); |
|
340 |
reg_class g5_regP(R_G5H,R_G5); |
|
341 |
reg_class i0_regP(R_I0H,R_I0); |
|
342 |
reg_class o0_regP(R_O0H,R_O0); |
|
343 |
reg_class o1_regP(R_O1H,R_O1); |
|
344 |
reg_class o2_regP(R_O2H,R_O2); |
|
345 |
reg_class o7_regP(R_O7H,R_O7); |
|
346 |
||
347 |
#else // _LP64 |
|
348 |
// 32-bit build means 32-bit pointers means 1 register. |
|
349 |
reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, |
|
350 |
R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, |
|
351 |
R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, |
|
352 |
R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); |
|
353 |
// Lock encodings use G3 and G4 internally |
|
354 |
reg_class lock_ptr_reg(R_G1, R_G5, |
|
355 |
R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, |
|
356 |
R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, |
|
357 |
R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); |
|
358 |
// Special class for storeP instructions, which can store SP or RPC to TLS. |
|
359 |
// It is also used for memory addressing, allowing direct TLS addressing. |
|
360 |
reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, |
|
361 |
R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, |
|
362 |
R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, |
|
363 |
R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); |
|
364 |
// R_L7 is the lowest-priority callee-save (i.e., NS) register |
|
365 |
// We use it to save R_G2 across calls out of Java. |
|
366 |
reg_class l7_regP(R_L7); |
|
367 |
||
368 |
// Other special pointer regs |
|
369 |
reg_class g1_regP(R_G1); |
|
370 |
reg_class g2_regP(R_G2); |
|
371 |
reg_class g3_regP(R_G3); |
|
372 |
reg_class g4_regP(R_G4); |
|
373 |
reg_class g5_regP(R_G5); |
|
374 |
reg_class i0_regP(R_I0); |
|
375 |
reg_class o0_regP(R_O0); |
|
376 |
reg_class o1_regP(R_O1); |
|
377 |
reg_class o2_regP(R_O2); |
|
378 |
reg_class o7_regP(R_O7); |
|
379 |
#endif // _LP64 |
|
380 |
||
381 |
||
382 |
// ---------------------------- |
|
383 |
// Long Register Classes |
|
384 |
// ---------------------------- |
|
385 |
// Longs in 1 register. Aligned adjacent hi/lo pairs. |
|
386 |
// Note: O7 is never in this class; it is sometimes used as an encoding temp. |
|
387 |
reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 |
|
388 |
,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 |
|
389 |
#ifdef _LP64 |
|
390 |
// 64-bit, longs in 1 register: use all 64-bit integer registers |
|
391 |
// 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. |
|
392 |
,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 |
|
393 |
,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 |
|
394 |
#endif // _LP64 |
|
395 |
); |
|
396 |
||
397 |
reg_class g1_regL(R_G1H,R_G1); |
|
1500
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|
398 |
reg_class g3_regL(R_G3H,R_G3); |
1 | 399 |
reg_class o2_regL(R_O2H,R_O2); |
400 |
reg_class o7_regL(R_O7H,R_O7); |
|
401 |
||
402 |
// ---------------------------- |
|
403 |
// Special Class for Condition Code Flags Register |
|
404 |
reg_class int_flags(CCR); |
|
405 |
reg_class float_flags(FCC0,FCC1,FCC2,FCC3); |
|
406 |
reg_class float_flag0(FCC0); |
|
407 |
||
408 |
||
409 |
// ---------------------------- |
|
410 |
// Float Point Register Classes |
|
411 |
// ---------------------------- |
|
412 |
// Skip F30/F31, they are reserved for mem-mem copies |
|
413 |
reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
|
414 |
||
415 |
// Paired floating point registers--they show up in the same order as the floats, |
|
416 |
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. |
|
417 |
reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, |
|
418 |
R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, |
|
419 |
/* Use extra V9 double registers; this AD file does not support V8 */ |
|
420 |
R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, |
|
421 |
R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x |
|
422 |
); |
|
423 |
||
424 |
// Paired floating point registers--they show up in the same order as the floats, |
|
425 |
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. |
|
426 |
// This class is usable for mis-aligned loads as happen in I2C adapters. |
|
427 |
reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, |
|
10027 | 428 |
R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
1 | 429 |
%} |
430 |
||
431 |
//----------DEFINITION BLOCK--------------------------------------------------- |
|
432 |
// Define name --> value mappings to inform the ADLC of an integer valued name |
|
433 |
// Current support includes integer values in the range [0, 0x7FFFFFFF] |
|
434 |
// Format: |
|
435 |
// int_def <name> ( <int_value>, <expression>); |
|
436 |
// Generated Code in ad_<arch>.hpp |
|
437 |
// #define <name> (<expression>) |
|
438 |
// // value == <int_value> |
|
439 |
// Generated code in ad_<arch>.cpp adlc_verification() |
|
440 |
// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); |
|
441 |
// |
|
442 |
definitions %{ |
|
443 |
// The default cost (of an ALU instruction). |
|
444 |
int_def DEFAULT_COST ( 100, 100); |
|
445 |
int_def HUGE_COST (1000000, 1000000); |
|
446 |
||
447 |
// Memory refs are twice as expensive as run-of-the-mill. |
|
448 |
int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); |
|
449 |
||
450 |
// Branches are even more expensive. |
|
451 |
int_def BRANCH_COST ( 300, DEFAULT_COST * 3); |
|
452 |
int_def CALL_COST ( 300, DEFAULT_COST * 3); |
|
453 |
%} |
|
454 |
||
455 |
||
456 |
//----------SOURCE BLOCK------------------------------------------------------- |
|
457 |
// This is a block of C++ code which provides values, functions, and |
|
458 |
// definitions necessary in the rest of the architecture description |
|
459 |
source_hpp %{ |
|
23498
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|
460 |
// Header information of the source block. |
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goetz
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|
461 |
// Method declarations/definitions which are used outside |
a0e67b766e5c
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|
462 |
// the ad-scope can conveniently be defined here. |
a0e67b766e5c
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|
463 |
// |
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|
464 |
// To keep related declarations/definitions/uses close together, |
a0e67b766e5c
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|
465 |
// we switch between source %{ }% and source_hpp %{ }% freely as needed. |
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|
466 |
|
1 | 467 |
// Must be visible to the DFA in dfa_sparc.cpp |
468 |
extern bool can_branch_register( Node *bol, Node *cmp ); |
|
469 |
||
10501 | 470 |
extern bool use_block_zeroing(Node* count); |
471 |
||
1 | 472 |
// Macros to extract hi & lo halves from a long pair. |
473 |
// G0 is not part of any long pair, so assert on that. |
|
2131 | 474 |
// Prevents accidentally using G1 instead of G0. |
1 | 475 |
#define LONG_HI_REG(x) (x) |
476 |
#define LONG_LO_REG(x) (x) |
|
477 |
||
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
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diff
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|
478 |
class CallStubImpl { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
479 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
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parents:
22911
diff
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|
480 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
481 |
//---< Used for optimization in Compile::Shorten_branches >--- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
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|
482 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
483 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
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|
484 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
485 |
// Size of call trampoline stub. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
486 |
static uint size_call_trampoline() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
487 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
488 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
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parents:
22911
diff
changeset
|
489 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
490 |
// number of relocations needed by a call trampoline stub |
a0e67b766e5c
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goetz
parents:
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diff
changeset
|
491 |
static uint reloc_call_trampoline() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
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parents:
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|
492 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
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parents:
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diff
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|
493 |
} |
a0e67b766e5c
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parents:
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diff
changeset
|
494 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
495 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
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parents:
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diff
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|
496 |
class HandlerImpl { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
497 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
498 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
499 |
|
a0e67b766e5c
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goetz
parents:
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|
500 |
static int emit_exception_handler(CodeBuffer &cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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changeset
|
501 |
static int emit_deopt_handler(CodeBuffer& cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
502 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
503 |
static uint size_exception_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
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|
504 |
if (TraceJumps) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
505 |
return (400); // just a guess |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
506 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
507 |
return ( NativeJump::instruction_size ); // sethi;jmp;nop |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
508 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
509 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
510 |
static uint size_deopt_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
511 |
if (TraceJumps) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
512 |
return (400); // just a guess |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
513 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
514 |
return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
515 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
516 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
517 |
|
1 | 518 |
%} |
519 |
||
520 |
source %{ |
|
521 |
#define __ _masm. |
|
522 |
||
523 |
// tertiary op of a LoadP or StoreP encoding |
|
524 |
#define REGP_OP true |
|
525 |
||
526 |
static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); |
|
527 |
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); |
|
528 |
static Register reg_to_register_object(int register_encoding); |
|
529 |
||
530 |
// Used by the DFA in dfa_sparc.cpp. |
|
531 |
// Check for being able to use a V9 branch-on-register. Requires a |
|
532 |
// compare-vs-zero, equal/not-equal, of a value which was zero- or sign- |
|
533 |
// extended. Doesn't work following an integer ADD, for example, because of |
|
534 |
// overflow (-1 incremented yields 0 plus a carry in the high-order word). On |
|
535 |
// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and |
|
536 |
// replace them with zero, which could become sign-extension in a different OS |
|
537 |
// release. There's no obvious reason why an interrupt will ever fill these |
|
538 |
// bits with non-zero junk (the registers are reloaded with standard LD |
|
539 |
// instructions which either zero-fill or sign-fill). |
|
540 |
bool can_branch_register( Node *bol, Node *cmp ) { |
|
541 |
if( !BranchOnRegister ) return false; |
|
542 |
#ifdef _LP64 |
|
543 |
if( cmp->Opcode() == Op_CmpP ) |
|
544 |
return true; // No problems with pointer compares |
|
545 |
#endif |
|
546 |
if( cmp->Opcode() == Op_CmpL ) |
|
547 |
return true; // No problems with long compares |
|
548 |
||
549 |
if( !SparcV9RegsHiBitsZero ) return false; |
|
550 |
if( bol->as_Bool()->_test._test != BoolTest::ne && |
|
551 |
bol->as_Bool()->_test._test != BoolTest::eq ) |
|
552 |
return false; |
|
553 |
||
554 |
// Check for comparing against a 'safe' value. Any operation which |
|
555 |
// clears out the high word is safe. Thus, loads and certain shifts |
|
556 |
// are safe, as are non-negative constants. Any operation which |
|
557 |
// preserves zero bits in the high word is safe as long as each of its |
|
558 |
// inputs are safe. Thus, phis and bitwise booleans are safe if their |
|
559 |
// inputs are safe. At present, the only important case to recognize |
|
560 |
// seems to be loads. Constants should fold away, and shifts & |
|
561 |
// logicals can use the 'cc' forms. |
|
562 |
Node *x = cmp->in(1); |
|
563 |
if( x->is_Load() ) return true; |
|
564 |
if( x->is_Phi() ) { |
|
565 |
for( uint i = 1; i < x->req(); i++ ) |
|
566 |
if( !x->in(i)->is_Load() ) |
|
567 |
return false; |
|
568 |
return true; |
|
569 |
} |
|
570 |
return false; |
|
571 |
} |
|
572 |
||
10501 | 573 |
bool use_block_zeroing(Node* count) { |
574 |
// Use BIS for zeroing if count is not constant |
|
575 |
// or it is >= BlockZeroingLowLimit. |
|
576 |
return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); |
|
577 |
} |
|
578 |
||
1 | 579 |
// **************************************************************************** |
580 |
||
581 |
// REQUIRED FUNCTIONALITY |
|
582 |
||
583 |
// !!!!! Special hack to get all type of calls to specify the byte offset |
|
584 |
// from the start of the call to the point where the return address |
|
585 |
// will point. |
|
586 |
// The "return address" is the address of the call instruction, plus 8. |
|
587 |
||
588 |
int MachCallStaticJavaNode::ret_addr_offset() { |
|
5690 | 589 |
int offset = NativeCall::instruction_size; // call; delay slot |
590 |
if (_method_handle_invoke) |
|
591 |
offset += 4; // restore SP |
|
592 |
return offset; |
|
1 | 593 |
} |
594 |
||
595 |
int MachCallDynamicJavaNode::ret_addr_offset() { |
|
596 |
int vtable_index = this->_vtable_index; |
|
597 |
if (vtable_index < 0) { |
|
598 |
// must be invalid_vtable_index, not nonvirtual_vtable_index |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
599 |
assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
1 | 600 |
return (NativeMovConstReg::instruction_size + |
601 |
NativeCall::instruction_size); // sethi; setlo; call; delay slot |
|
602 |
} else { |
|
603 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
604 |
int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
1 | 605 |
int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
606 |
int klass_load_size; |
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
19319
diff
changeset
|
607 |
if (UseCompressedClassPointers) { |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
608 |
assert(Universe::heap() != NULL, "java heap should be initialized"); |
19319
0ad35be0733a
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
18097
diff
changeset
|
609 |
klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
610 |
} else { |
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
611 |
klass_load_size = 1*BytesPerInstWord; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
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|
612 |
} |
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
613 |
if (Assembler::is_simm13(v_off)) { |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
614 |
return klass_load_size + |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
615 |
(2*BytesPerInstWord + // ld_ptr, ld_ptr |
1 | 616 |
NativeCall::instruction_size); // call; delay slot |
617 |
} else { |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
618 |
return klass_load_size + |
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
619 |
(4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
1 | 620 |
NativeCall::instruction_size); // call; delay slot |
621 |
} |
|
622 |
} |
|
623 |
} |
|
624 |
||
625 |
int MachCallRuntimeNode::ret_addr_offset() { |
|
626 |
#ifdef _LP64 |
|
7892
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
627 |
if (MacroAssembler::is_far_target(entry_point())) { |
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
628 |
return NativeFarCall::instruction_size; |
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
629 |
} else { |
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
630 |
return NativeCall::instruction_size; |
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
631 |
} |
1 | 632 |
#else |
633 |
return NativeCall::instruction_size; // call; delay slot |
|
634 |
#endif |
|
635 |
} |
|
636 |
||
637 |
// Indicate if the safepoint node needs the polling page as an input. |
|
638 |
// Since Sparc does not have absolute addressing, it does. |
|
639 |
bool SafePointNode::needs_polling_address_input() { |
|
640 |
return true; |
|
641 |
} |
|
642 |
||
643 |
// emit an interrupt that is caught by the debugger (for debugging compiler) |
|
644 |
void emit_break(CodeBuffer &cbuf) { |
|
645 |
MacroAssembler _masm(&cbuf); |
|
646 |
__ breakpoint_trap(); |
|
647 |
} |
|
648 |
||
649 |
#ifndef PRODUCT |
|
650 |
void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { |
|
651 |
st->print("TA"); |
|
652 |
} |
|
653 |
#endif |
|
654 |
||
655 |
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
656 |
emit_break(cbuf); |
|
657 |
} |
|
658 |
||
659 |
uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { |
|
660 |
return MachNode::size(ra_); |
|
661 |
} |
|
662 |
||
663 |
// Traceable jump |
|
664 |
void emit_jmpl(CodeBuffer &cbuf, int jump_target) { |
|
665 |
MacroAssembler _masm(&cbuf); |
|
666 |
Register rdest = reg_to_register_object(jump_target); |
|
667 |
__ JMP(rdest, 0); |
|
668 |
__ delayed()->nop(); |
|
669 |
} |
|
670 |
||
671 |
// Traceable jump and set exception pc |
|
672 |
void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { |
|
673 |
MacroAssembler _masm(&cbuf); |
|
674 |
Register rdest = reg_to_register_object(jump_target); |
|
675 |
__ JMP(rdest, 0); |
|
676 |
__ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); |
|
677 |
} |
|
678 |
||
679 |
void emit_nop(CodeBuffer &cbuf) { |
|
680 |
MacroAssembler _masm(&cbuf); |
|
681 |
__ nop(); |
|
682 |
} |
|
683 |
||
684 |
void emit_illtrap(CodeBuffer &cbuf) { |
|
685 |
MacroAssembler _masm(&cbuf); |
|
686 |
__ illtrap(0); |
|
687 |
} |
|
688 |
||
689 |
||
690 |
intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { |
|
691 |
assert(n->rule() != loadUB_rule, ""); |
|
692 |
||
693 |
intptr_t offset = 0; |
|
694 |
const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP |
|
695 |
const Node* addr = n->get_base_and_disp(offset, adr_type); |
|
696 |
assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); |
|
697 |
assert(addr != NULL && addr != (Node*)-1, "invalid addr"); |
|
698 |
assert(addr->bottom_type()->isa_oopptr() == atype, ""); |
|
699 |
atype = atype->add_offset(offset); |
|
700 |
assert(disp32 == offset, "wrong disp32"); |
|
701 |
return atype->_offset; |
|
702 |
} |
|
703 |
||
704 |
||
705 |
intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { |
|
706 |
assert(n->rule() != loadUB_rule, ""); |
|
707 |
||
708 |
intptr_t offset = 0; |
|
709 |
Node* addr = n->in(2); |
|
710 |
assert(addr->bottom_type()->isa_oopptr() == atype, ""); |
|
711 |
if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { |
|
712 |
Node* a = addr->in(2/*AddPNode::Address*/); |
|
713 |
Node* o = addr->in(3/*AddPNode::Offset*/); |
|
714 |
offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; |
|
715 |
atype = a->bottom_type()->is_ptr()->add_offset(offset); |
|
716 |
assert(atype->isa_oop_ptr(), "still an oop"); |
|
717 |
} |
|
718 |
offset = atype->is_ptr()->_offset; |
|
719 |
if (offset != Type::OffsetBot) offset += disp32; |
|
720 |
return offset; |
|
721 |
} |
|
722 |
||
7433 | 723 |
static inline jdouble replicate_immI(int con, int count, int width) { |
724 |
// Load a constant replicated "count" times with width "width" |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
725 |
assert(count*width == 8 && width <= 4, "sanity"); |
7433 | 726 |
int bit_width = width * 8; |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
727 |
jlong val = con; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
728 |
val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
7433 | 729 |
for (int i = 0; i < count - 1; i++) { |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
730 |
val |= (val << bit_width); |
7433 | 731 |
} |
732 |
jdouble dval = *((jdouble*) &val); // coerce to double type |
|
733 |
return dval; |
|
734 |
} |
|
735 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
736 |
static inline jdouble replicate_immF(float con) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
737 |
// Replicate float con 2 times and pack into vector. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
738 |
int val = *((int*)&con); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
739 |
jlong lval = val; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
740 |
lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
741 |
jdouble dval = *((jdouble*) &lval); // coerce to double type |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
742 |
return dval; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
743 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
744 |
|
1 | 745 |
// Standard Sparc opcode form2 field breakdown |
746 |
static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { |
|
747 |
f0 &= (1<<19)-1; // Mask displacement to 19 bits |
|
748 |
int op = (f30 << 30) | |
|
749 |
(f29 << 29) | |
|
750 |
(f25 << 25) | |
|
751 |
(f22 << 22) | |
|
752 |
(f20 << 20) | |
|
753 |
(f19 << 19) | |
|
754 |
(f0 << 0); |
|
6418 | 755 |
cbuf.insts()->emit_int32(op); |
1 | 756 |
} |
757 |
||
758 |
// Standard Sparc opcode form2 field breakdown |
|
759 |
static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { |
|
760 |
f0 >>= 10; // Drop 10 bits |
|
761 |
f0 &= (1<<22)-1; // Mask displacement to 22 bits |
|
762 |
int op = (f30 << 30) | |
|
763 |
(f25 << 25) | |
|
764 |
(f22 << 22) | |
|
765 |
(f0 << 0); |
|
6418 | 766 |
cbuf.insts()->emit_int32(op); |
1 | 767 |
} |
768 |
||
769 |
// Standard Sparc opcode form3 field breakdown |
|
770 |
static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { |
|
771 |
int op = (f30 << 30) | |
|
772 |
(f25 << 25) | |
|
773 |
(f19 << 19) | |
|
774 |
(f14 << 14) | |
|
775 |
(f5 << 5) | |
|
776 |
(f0 << 0); |
|
6418 | 777 |
cbuf.insts()->emit_int32(op); |
1 | 778 |
} |
779 |
||
780 |
// Standard Sparc opcode form3 field breakdown |
|
781 |
static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { |
|
782 |
simm13 &= (1<<13)-1; // Mask to 13 bits |
|
783 |
int op = (f30 << 30) | |
|
784 |
(f25 << 25) | |
|
785 |
(f19 << 19) | |
|
786 |
(f14 << 14) | |
|
787 |
(1 << 13) | // bit to indicate immediate-mode |
|
788 |
(simm13<<0); |
|
6418 | 789 |
cbuf.insts()->emit_int32(op); |
1 | 790 |
} |
791 |
||
792 |
static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { |
|
793 |
simm10 &= (1<<10)-1; // Mask to 10 bits |
|
794 |
emit3_simm13(cbuf,f30,f25,f19,f14,simm10); |
|
795 |
} |
|
796 |
||
797 |
#ifdef ASSERT |
|
798 |
// Helper function for VerifyOops in emit_form3_mem_reg |
|
799 |
void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { |
|
800 |
warning("VerifyOops encountered unexpected instruction:"); |
|
801 |
n->dump(2); |
|
802 |
warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); |
|
803 |
} |
|
804 |
#endif |
|
805 |
||
806 |
||
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
807 |
void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, |
1 | 808 |
int src1_enc, int disp32, int src2_enc, int dst_enc) { |
809 |
||
810 |
#ifdef ASSERT |
|
811 |
// The following code implements the +VerifyOops feature. |
|
812 |
// It verifies oop values which are loaded into or stored out of |
|
813 |
// the current method activation. +VerifyOops complements techniques |
|
814 |
// like ScavengeALot, because it eagerly inspects oops in transit, |
|
815 |
// as they enter or leave the stack, as opposed to ScavengeALot, |
|
816 |
// which inspects oops "at rest", in the stack or heap, at safepoints. |
|
817 |
// For this reason, +VerifyOops can sometimes detect bugs very close |
|
818 |
// to their point of creation. It can also serve as a cross-check |
|
819 |
// on the validity of oop maps, when used toegether with ScavengeALot. |
|
820 |
||
821 |
// It would be good to verify oops at other points, especially |
|
822 |
// when an oop is used as a base pointer for a load or store. |
|
823 |
// This is presently difficult, because it is hard to know when |
|
824 |
// a base address is biased or not. (If we had such information, |
|
825 |
// it would be easy and useful to make a two-argument version of |
|
826 |
// verify_oop which unbiases the base, and performs verification.) |
|
827 |
||
828 |
assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); |
|
829 |
bool is_verified_oop_base = false; |
|
830 |
bool is_verified_oop_load = false; |
|
831 |
bool is_verified_oop_store = false; |
|
832 |
int tmp_enc = -1; |
|
833 |
if (VerifyOops && src1_enc != R_SP_enc) { |
|
834 |
// classify the op, mainly for an assert check |
|
835 |
int st_op = 0, ld_op = 0; |
|
836 |
switch (primary) { |
|
837 |
case Assembler::stb_op3: st_op = Op_StoreB; break; |
|
838 |
case Assembler::sth_op3: st_op = Op_StoreC; break; |
|
839 |
case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 |
|
840 |
case Assembler::stw_op3: st_op = Op_StoreI; break; |
|
841 |
case Assembler::std_op3: st_op = Op_StoreL; break; |
|
842 |
case Assembler::stf_op3: st_op = Op_StoreF; break; |
|
843 |
case Assembler::stdf_op3: st_op = Op_StoreD; break; |
|
844 |
||
845 |
case Assembler::ldsb_op3: ld_op = Op_LoadB; break; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
846 |
case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
2022
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
2015
diff
changeset
|
847 |
case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
1 | 848 |
case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
849 |
case Assembler::ldx_op3: // may become LoadP or stay LoadI |
|
850 |
case Assembler::ldsw_op3: // may become LoadP or stay LoadI |
|
851 |
case Assembler::lduw_op3: ld_op = Op_LoadI; break; |
|
852 |
case Assembler::ldd_op3: ld_op = Op_LoadL; break; |
|
853 |
case Assembler::ldf_op3: ld_op = Op_LoadF; break; |
|
854 |
case Assembler::lddf_op3: ld_op = Op_LoadD; break; |
|
855 |
case Assembler::prefetch_op3: ld_op = Op_LoadI; break; |
|
856 |
||
857 |
default: ShouldNotReachHere(); |
|
858 |
} |
|
859 |
if (tertiary == REGP_OP) { |
|
860 |
if (st_op == Op_StoreI) st_op = Op_StoreP; |
|
861 |
else if (ld_op == Op_LoadI) ld_op = Op_LoadP; |
|
862 |
else ShouldNotReachHere(); |
|
863 |
if (st_op) { |
|
864 |
// a store |
|
865 |
// inputs are (0:control, 1:memory, 2:address, 3:value) |
|
866 |
Node* n2 = n->in(3); |
|
867 |
if (n2 != NULL) { |
|
868 |
const Type* t = n2->bottom_type(); |
|
869 |
is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; |
|
870 |
} |
|
871 |
} else { |
|
872 |
// a load |
|
873 |
const Type* t = n->bottom_type(); |
|
874 |
is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; |
|
875 |
} |
|
876 |
} |
|
877 |
||
878 |
if (ld_op) { |
|
879 |
// a Load |
|
880 |
// inputs are (0:control, 1:memory, 2:address) |
|
881 |
if (!(n->ideal_Opcode()==ld_op) && // Following are special cases |
|
882 |
!(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && |
|
883 |
!(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && |
|
884 |
!(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && |
|
885 |
!(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && |
|
886 |
!(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && |
|
887 |
!(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && |
|
888 |
!(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && |
|
889 |
!(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && |
|
890 |
!(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && |
|
891 |
!(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && |
|
892 |
!(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && |
|
893 |
!(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && |
|
10507 | 894 |
!(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
895 |
!(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
1 | 896 |
!(n->rule() == loadUB_rule)) { |
897 |
verify_oops_warning(n, n->ideal_Opcode(), ld_op); |
|
898 |
} |
|
899 |
} else if (st_op) { |
|
900 |
// a Store |
|
901 |
// inputs are (0:control, 1:memory, 2:address, 3:value) |
|
902 |
if (!(n->ideal_Opcode()==st_op) && // Following are special cases |
|
903 |
!(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && |
|
904 |
!(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && |
|
905 |
!(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && |
|
906 |
!(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
907 |
!(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
1 | 908 |
!(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
909 |
verify_oops_warning(n, n->ideal_Opcode(), st_op); |
|
910 |
} |
|
911 |
} |
|
912 |
||
913 |
if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { |
|
914 |
Node* addr = n->in(2); |
|
915 |
if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { |
|
916 |
const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? |
|
917 |
if (atype != NULL) { |
|
918 |
intptr_t offset = get_offset_from_base(n, atype, disp32); |
|
919 |
intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); |
|
920 |
if (offset != offset_2) { |
|
921 |
get_offset_from_base(n, atype, disp32); |
|
922 |
get_offset_from_base_2(n, atype, disp32); |
|
923 |
} |
|
924 |
assert(offset == offset_2, "different offsets"); |
|
925 |
if (offset == disp32) { |
|
926 |
// we now know that src1 is a true oop pointer |
|
927 |
is_verified_oop_base = true; |
|
928 |
if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { |
|
929 |
if( primary == Assembler::ldd_op3 ) { |
|
930 |
is_verified_oop_base = false; // Cannot 'ldd' into O7 |
|
931 |
} else { |
|
932 |
tmp_enc = dst_enc; |
|
933 |
dst_enc = R_O7_enc; // Load into O7; preserve source oop |
|
934 |
assert(src1_enc != dst_enc, ""); |
|
935 |
} |
|
936 |
} |
|
937 |
} |
|
938 |
if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) |
|
939 |
|| offset == oopDesc::mark_offset_in_bytes())) { |
|
940 |
// loading the mark should not be allowed either, but |
|
941 |
// we don't check this since it conflicts with InlineObjectHash |
|
942 |
// usage of LoadINode to get the mark. We could keep the |
|
943 |
// check if we create a new LoadMarkNode |
|
944 |
// but do not verify the object before its header is initialized |
|
945 |
ShouldNotReachHere(); |
|
946 |
} |
|
947 |
} |
|
948 |
} |
|
949 |
} |
|
950 |
} |
|
951 |
#endif |
|
952 |
||
953 |
uint instr; |
|
954 |
instr = (Assembler::ldst_op << 30) |
|
955 |
| (dst_enc << 25) |
|
956 |
| (primary << 19) |
|
957 |
| (src1_enc << 14); |
|
958 |
||
959 |
uint index = src2_enc; |
|
960 |
int disp = disp32; |
|
961 |
||
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
962 |
if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { |
1 | 963 |
disp += STACK_BIAS; |
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
964 |
// Quick fix for JDK-8029668: check that stack offset fits, bailout if not |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
965 |
if (!Assembler::is_simm13(disp)) { |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
966 |
ra->C->record_method_not_compilable("unable to handle large constant offsets"); |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
967 |
return; |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
968 |
} |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
969 |
} |
1 | 970 |
|
971 |
// We should have a compiler bailout here rather than a guarantee. |
|
972 |
// Better yet would be some mechanism to handle variable-size matches correctly. |
|
973 |
guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); |
|
974 |
||
975 |
if( disp == 0 ) { |
|
976 |
// use reg-reg form |
|
977 |
// bit 13 is already zero |
|
978 |
instr |= index; |
|
979 |
} else { |
|
980 |
// use reg-imm form |
|
981 |
instr |= 0x00002000; // set bit 13 to one |
|
982 |
instr |= disp & 0x1FFF; |
|
983 |
} |
|
984 |
||
6418 | 985 |
cbuf.insts()->emit_int32(instr); |
1 | 986 |
|
987 |
#ifdef ASSERT |
|
988 |
{ |
|
989 |
MacroAssembler _masm(&cbuf); |
|
990 |
if (is_verified_oop_base) { |
|
991 |
__ verify_oop(reg_to_register_object(src1_enc)); |
|
992 |
} |
|
993 |
if (is_verified_oop_store) { |
|
994 |
__ verify_oop(reg_to_register_object(dst_enc)); |
|
995 |
} |
|
996 |
if (tmp_enc != -1) { |
|
997 |
__ mov(O7, reg_to_register_object(tmp_enc)); |
|
998 |
} |
|
999 |
if (is_verified_oop_load) { |
|
1000 |
__ verify_oop(reg_to_register_object(dst_enc)); |
|
1001 |
} |
|
1002 |
} |
|
1003 |
#endif |
|
1004 |
} |
|
1005 |
||
7892
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
1006 |
void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
1 | 1007 |
// The method which records debug information at every safepoint |
1008 |
// expects the call to be the first instruction in the snippet as |
|
1009 |
// it creates a PcDesc structure which tracks the offset of a call |
|
1010 |
// from the start of the codeBlob. This offset is computed as |
|
1011 |
// code_end() - code_begin() of the code which has been emitted |
|
1012 |
// so far. |
|
1013 |
// In this particular case we have skirted around the problem by |
|
1014 |
// putting the "mov" instruction in the delay slot but the problem |
|
1015 |
// may bite us again at some other point and a cleaner/generic |
|
1016 |
// solution using relocations would be needed. |
|
1017 |
MacroAssembler _masm(&cbuf); |
|
1018 |
__ set_inst_mark(); |
|
1019 |
||
1020 |
// We flush the current window just so that there is a valid stack copy |
|
1021 |
// the fact that the current window becomes active again instantly is |
|
1022 |
// not a problem there is nothing live in it. |
|
1023 |
||
1024 |
#ifdef ASSERT |
|
1025 |
int startpos = __ offset(); |
|
1026 |
#endif /* ASSERT */ |
|
1027 |
||
7892
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
1028 |
__ call((address)entry_point, rtype); |
1 | 1029 |
|
1030 |
if (preserve_g2) __ delayed()->mov(G2, L7); |
|
1031 |
else __ delayed()->nop(); |
|
1032 |
||
1033 |
if (preserve_g2) __ mov(L7, G2); |
|
1034 |
||
1035 |
#ifdef ASSERT |
|
1036 |
if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { |
|
1037 |
#ifdef _LP64 |
|
1038 |
// Trash argument dump slots. |
|
1039 |
__ set(0xb0b8ac0db0b8ac0d, G1); |
|
1040 |
__ mov(G1, G5); |
|
1041 |
__ stx(G1, SP, STACK_BIAS + 0x80); |
|
1042 |
__ stx(G1, SP, STACK_BIAS + 0x88); |
|
1043 |
__ stx(G1, SP, STACK_BIAS + 0x90); |
|
1044 |
__ stx(G1, SP, STACK_BIAS + 0x98); |
|
1045 |
__ stx(G1, SP, STACK_BIAS + 0xA0); |
|
1046 |
__ stx(G1, SP, STACK_BIAS + 0xA8); |
|
1047 |
#else // _LP64 |
|
1048 |
// this is also a native call, so smash the first 7 stack locations, |
|
1049 |
// and the various registers |
|
1050 |
||
1051 |
// Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], |
|
1052 |
// while [SP+0x44..0x58] are the argument dump slots. |
|
1053 |
__ set((intptr_t)0xbaadf00d, G1); |
|
1054 |
__ mov(G1, G5); |
|
1055 |
__ sllx(G1, 32, G1); |
|
1056 |
__ or3(G1, G5, G1); |
|
1057 |
__ mov(G1, G5); |
|
1058 |
__ stx(G1, SP, 0x40); |
|
1059 |
__ stx(G1, SP, 0x48); |
|
1060 |
__ stx(G1, SP, 0x50); |
|
1061 |
__ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot |
|
1062 |
#endif // _LP64 |
|
1063 |
} |
|
1064 |
#endif /*ASSERT*/ |
|
1065 |
} |
|
1066 |
||
1067 |
//============================================================================= |
|
1068 |
// REQUIRED FUNCTIONALITY for encoding |
|
1069 |
void emit_lo(CodeBuffer &cbuf, int val) { } |
|
1070 |
void emit_hi(CodeBuffer &cbuf, int val) { } |
|
1071 |
||
1072 |
||
1073 |
//============================================================================= |
|
11197
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|
1074 |
const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
7433 | 1075 |
|
11190
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|
1076 |
int Compile::ConstantTable::calculate_table_base_offset() const { |
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|
1077 |
if (UseRDPCForConstantTableBase) { |
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|
1078 |
// The table base offset might be less but then it fits into |
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|
1079 |
// simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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|
1080 |
return Assembler::min_simm13(); |
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|
1081 |
} else { |
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|
1082 |
int offset = -(size() / 2); |
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|
1083 |
if (!Assembler::is_simm13(offset)) { |
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|
1084 |
offset = Assembler::min_simm13(); |
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|
1085 |
} |
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|
1086 |
return offset; |
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changeset
|
1087 |
} |
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changeset
|
1088 |
} |
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changeset
|
1089 |
|
22844
90f76a40ed8a
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changeset
|
1090 |
bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
90f76a40ed8a
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
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parents:
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diff
changeset
|
1091 |
void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
90f76a40ed8a
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
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changeset
|
1092 |
ShouldNotReachHere(); |
90f76a40ed8a
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diff
changeset
|
1093 |
} |
90f76a40ed8a
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changeset
|
1094 |
|
7433 | 1095 |
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1096 |
Compile* C = ra_->C; |
|
1097 |
Compile::ConstantTable& constant_table = C->constant_table(); |
|
1098 |
MacroAssembler _masm(&cbuf); |
|
1099 |
||
1100 |
Register r = as_Register(ra_->get_encode(this)); |
|
11190
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parents:
10971
diff
changeset
|
1101 |
CodeSection* consts_section = __ code()->consts(); |
d561d41f241a
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diff
changeset
|
1102 |
int consts_size = consts_section->align_at_start(consts_section->size()); |
d561d41f241a
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twisti
parents:
10971
diff
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|
1103 |
assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
7433 | 1104 |
|
1105 |
if (UseRDPCForConstantTableBase) { |
|
1106 |
// For the following RDPC logic to work correctly the consts |
|
1107 |
// section must be allocated right before the insts section. This |
|
1108 |
// assert checks for that. The layout and the SECT_* constants |
|
1109 |
// are defined in src/share/vm/asm/codeBuffer.hpp. |
|
1110 |
assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); |
|
11190
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7003454: order constants in constant table by number of references in code
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parents:
10971
diff
changeset
|
1111 |
int insts_offset = __ offset(); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1112 |
|
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1113 |
// Layout: |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1114 |
// |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1115 |
// |----------- consts section ------------|----------- insts section -----------... |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1116 |
// |------ constant table -----|- padding -|------------------x---- |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1117 |
// \ current PC (RDPC instruction) |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1118 |
// |<------------- consts_size ----------->|<- insts_offset ->| |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1119 |
// \ table base |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1120 |
// The table base offset is later added to the load displacement |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1121 |
// so it has to be negative. |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1122 |
int table_base_offset = -(consts_size + insts_offset); |
7433 | 1123 |
int disp; |
1124 |
||
1125 |
// If the displacement from the current PC to the constant table |
|
1126 |
// base fits into simm13 we set the constant table base to the |
|
1127 |
// current PC. |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1128 |
if (Assembler::is_simm13(table_base_offset)) { |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1129 |
constant_table.set_table_base_offset(table_base_offset); |
7433 | 1130 |
disp = 0; |
1131 |
} else { |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1132 |
// Otherwise we set the constant table base offset to the |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1133 |
// maximum negative displacement of load instructions to keep |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1134 |
// the disp as small as possible: |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1135 |
// |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1136 |
// |<------------- consts_size ----------->|<- insts_offset ->| |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1137 |
// |<--------- min_simm13 --------->|<-------- disp --------->| |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1138 |
// \ table base |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1139 |
table_base_offset = Assembler::min_simm13(); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1140 |
constant_table.set_table_base_offset(table_base_offset); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1141 |
disp = (consts_size + insts_offset) + table_base_offset; |
7433 | 1142 |
} |
1143 |
||
1144 |
__ rdpc(r); |
|
1145 |
||
1146 |
if (disp != 0) { |
|
1147 |
assert(r != O7, "need temporary"); |
|
1148 |
__ sub(r, __ ensure_simm13_or_reg(disp, O7), r); |
|
1149 |
} |
|
1150 |
} |
|
1151 |
else { |
|
1152 |
// Materialize the constant table base. |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1153 |
address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
7433 | 1154 |
RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1155 |
AddressLiteral base(baseaddr, rspec); |
|
1156 |
__ set(base, r); |
|
1157 |
} |
|
1158 |
} |
|
1159 |
||
1160 |
uint MachConstantBaseNode::size(PhaseRegAlloc*) const { |
|
1161 |
if (UseRDPCForConstantTableBase) { |
|
1162 |
// This is really the worst case but generally it's only 1 instruction. |
|
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
1163 |
return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
7433 | 1164 |
} else { |
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
1165 |
return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
7433 | 1166 |
} |
1167 |
} |
|
1168 |
||
1169 |
#ifndef PRODUCT |
|
1170 |
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
|
1171 |
char reg[128]; |
|
1172 |
ra_->dump_register(this, reg); |
|
1173 |
if (UseRDPCForConstantTableBase) { |
|
1174 |
st->print("RDPC %s\t! constant table base", reg); |
|
1175 |
} else { |
|
1176 |
st->print("SET &constanttable,%s\t! constant table base", reg); |
|
1177 |
} |
|
1178 |
} |
|
1179 |
#endif |
|
1180 |
||
1181 |
||
1182 |
//============================================================================= |
|
1 | 1183 |
|
1184 |
#ifndef PRODUCT |
|
1185 |
void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { |
|
1186 |
Compile* C = ra_->C; |
|
1187 |
||
1188 |
for (int i = 0; i < OptoPrologueNops; i++) { |
|
1189 |
st->print_cr("NOP"); st->print("\t"); |
|
1190 |
} |
|
1191 |
||
1192 |
if( VerifyThread ) { |
|
1193 |
st->print_cr("Verify_Thread"); st->print("\t"); |
|
1194 |
} |
|
1195 |
||
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1196 |
size_t framesize = C->frame_size_in_bytes(); |
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1197 |
int bangsize = C->bang_size_in_bytes(); |
1 | 1198 |
|
1199 |
// Calls to C2R adapters often do not accept exceptional returns. |
|
1200 |
// We require that their callers must bang for them. But be careful, because |
|
1201 |
// some VM calls (such as call site linkage) can use several kilobytes of |
|
1202 |
// stack. But the stack safety zone should account for that. |
|
1203 |
// See bugs 4446381, 4468289, 4497237. |
|
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1204 |
if (C->need_stack_bang(bangsize)) { |
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1205 |
st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); |
1 | 1206 |
} |
1207 |
||
1208 |
if (Assembler::is_simm13(-framesize)) { |
|
24932 | 1209 |
st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); |
1 | 1210 |
} else { |
24932 | 1211 |
st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); |
1212 |
st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); |
|
1 | 1213 |
st->print ("SAVE R_SP,R_G3,R_SP"); |
1214 |
} |
|
1215 |
||
1216 |
} |
|
1217 |
#endif |
|
1218 |
||
1219 |
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1220 |
Compile* C = ra_->C; |
|
1221 |
MacroAssembler _masm(&cbuf); |
|
1222 |
||
1223 |
for (int i = 0; i < OptoPrologueNops; i++) { |
|
1224 |
__ nop(); |
|
1225 |
} |
|
1226 |
||
1227 |
__ verify_thread(); |
|
1228 |
||
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1229 |
size_t framesize = C->frame_size_in_bytes(); |
1 | 1230 |
assert(framesize >= 16*wordSize, "must have room for reg. save area"); |
1231 |
assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); |
|
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1232 |
int bangsize = C->bang_size_in_bytes(); |
1 | 1233 |
|
1234 |
// Calls to C2R adapters often do not accept exceptional returns. |
|
1235 |
// We require that their callers must bang for them. But be careful, because |
|
1236 |
// some VM calls (such as call site linkage) can use several kilobytes of |
|
1237 |
// stack. But the stack safety zone should account for that. |
|
1238 |
// See bugs 4446381, 4468289, 4497237. |
|
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1239 |
if (C->need_stack_bang(bangsize)) { |
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
1240 |
__ generate_stack_overflow_check(bangsize); |
1 | 1241 |
} |
1242 |
||
1243 |
if (Assembler::is_simm13(-framesize)) { |
|
1244 |
__ save(SP, -framesize, SP); |
|
1245 |
} else { |
|
1246 |
__ sethi(-framesize & ~0x3ff, G3); |
|
1247 |
__ add(G3, -framesize & 0x3ff, G3); |
|
1248 |
__ save(SP, G3, SP); |
|
1249 |
} |
|
1250 |
C->set_frame_complete( __ offset() ); |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1251 |
|
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1252 |
if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1253 |
// NOTE: We set the table base offset here because users might be |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1254 |
// emitted before MachConstantBaseNode. |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1255 |
Compile::ConstantTable& constant_table = C->constant_table(); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1256 |
constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
d561d41f241a
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twisti
parents:
10971
diff
changeset
|
1257 |
} |
1 | 1258 |
} |
1259 |
||
1260 |
uint MachPrologNode::size(PhaseRegAlloc *ra_) const { |
|
1261 |
return MachNode::size(ra_); |
|
1262 |
} |
|
1263 |
||
1264 |
int MachPrologNode::reloc() const { |
|
1265 |
return 10; // a large enough number |
|
1266 |
} |
|
1267 |
||
1268 |
//============================================================================= |
|
1269 |
#ifndef PRODUCT |
|
1270 |
void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { |
|
1271 |
Compile* C = ra_->C; |
|
1272 |
||
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1273 |
if(do_polling() && ra_->C->is_method_compilation()) { |
1 | 1274 |
st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); |
1275 |
#ifdef _LP64 |
|
1276 |
st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); |
|
1277 |
#else |
|
1278 |
st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); |
|
1279 |
#endif |
|
1280 |
} |
|
1281 |
||
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1282 |
if(do_polling()) { |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1283 |
if (UseCBCond && !ra_->C->is_method_compilation()) { |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1284 |
st->print("NOP\n\t"); |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1285 |
} |
1 | 1286 |
st->print("RET\n\t"); |
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1287 |
} |
1 | 1288 |
|
1289 |
st->print("RESTORE"); |
|
1290 |
} |
|
1291 |
#endif |
|
1292 |
||
1293 |
void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1294 |
MacroAssembler _masm(&cbuf); |
|
1295 |
Compile* C = ra_->C; |
|
1296 |
||
1297 |
__ verify_thread(); |
|
1298 |
||
1299 |
// If this does safepoint polling, then do it here |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1300 |
if(do_polling() && ra_->C->is_method_compilation()) { |
2571 | 1301 |
AddressLiteral polling_page(os::get_polling_page()); |
1302 |
__ sethi(polling_page, L0); |
|
1 | 1303 |
__ relocate(relocInfo::poll_return_type); |
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1304 |
__ ld_ptr(L0, 0, G0); |
1 | 1305 |
} |
1306 |
||
1307 |
// If this is a return, then stuff the restore in the delay slot |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1308 |
if(do_polling()) { |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1309 |
if (UseCBCond && !ra_->C->is_method_compilation()) { |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1310 |
// Insert extra padding for the case when the epilogue is preceded by |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1311 |
// a cbcond jump, which can't be followed by a CTI instruction |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1312 |
__ nop(); |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
1313 |
} |
1 | 1314 |
__ ret(); |
1315 |
__ delayed()->restore(); |
|
1316 |
} else { |
|
1317 |
__ restore(); |
|
1318 |
} |
|
1319 |
} |
|
1320 |
||
1321 |
uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { |
|
1322 |
return MachNode::size(ra_); |
|
1323 |
} |
|
1324 |
||
1325 |
int MachEpilogNode::reloc() const { |
|
1326 |
return 16; // a large enough number |
|
1327 |
} |
|
1328 |
||
1329 |
const Pipeline * MachEpilogNode::pipeline() const { |
|
1330 |
return MachNode::pipeline_class(); |
|
1331 |
} |
|
1332 |
||
1333 |
int MachEpilogNode::safepoint_offset() const { |
|
1334 |
assert( do_polling(), "no return for this epilog node"); |
|
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
1335 |
return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
1 | 1336 |
} |
1337 |
||
1338 |
//============================================================================= |
|
1339 |
||
1340 |
// Figure out which register class each belongs in: rc_int, rc_float, rc_stack |
|
1341 |
enum RC { rc_bad, rc_int, rc_float, rc_stack }; |
|
1342 |
static enum RC rc_class( OptoReg::Name reg ) { |
|
1343 |
if( !OptoReg::is_valid(reg) ) return rc_bad; |
|
1344 |
if (OptoReg::is_stack(reg)) return rc_stack; |
|
1345 |
VMReg r = OptoReg::as_VMReg(reg); |
|
1346 |
if (r->is_Register()) return rc_int; |
|
1347 |
assert(r->is_FloatRegister(), "must be"); |
|
1348 |
return rc_float; |
|
1349 |
} |
|
1350 |
||
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1351 |
static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1352 |
if (cbuf) { |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1353 |
emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); |
1 | 1354 |
} |
1355 |
#ifndef PRODUCT |
|
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1356 |
else if (!do_size) { |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1357 |
if (size != 0) st->print("\n\t"); |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1358 |
if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
1359 |
else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); |
1 | 1360 |
} |
1361 |
#endif |
|
1362 |
return size+4; |
|
1363 |
} |
|
1364 |
||
1365 |
static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { |
|
1366 |
if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); |
|
1367 |
#ifndef PRODUCT |
|
1368 |
else if( !do_size ) { |
|
1369 |
if( size != 0 ) st->print("\n\t"); |
|
1370 |
st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); |
|
1371 |
} |
|
1372 |
#endif |
|
1373 |
return size+4; |
|
1374 |
} |
|
1375 |
||
1376 |
uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, |
|
1377 |
PhaseRegAlloc *ra_, |
|
1378 |
bool do_size, |
|
1379 |
outputStream* st ) const { |
|
1380 |
// Get registers to move |
|
1381 |
OptoReg::Name src_second = ra_->get_reg_second(in(1)); |
|
1382 |
OptoReg::Name src_first = ra_->get_reg_first(in(1)); |
|
1383 |
OptoReg::Name dst_second = ra_->get_reg_second(this ); |
|
1384 |
OptoReg::Name dst_first = ra_->get_reg_first(this ); |
|
1385 |
||
1386 |
enum RC src_second_rc = rc_class(src_second); |
|
1387 |
enum RC src_first_rc = rc_class(src_first); |
|
1388 |
enum RC dst_second_rc = rc_class(dst_second); |
|
1389 |
enum RC dst_first_rc = rc_class(dst_first); |
|
1390 |
||
1391 |
assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); |
|
1392 |
||
1393 |
// Generate spill code! |
|
1394 |
int size = 0; |
|
1395 |
||
1396 |
if( src_first == dst_first && src_second == dst_second ) |
|
1397 |
return size; // Self copy, no move |
|
1398 |
||
1399 |
// -------------------------------------- |
|
1400 |
// Check for mem-mem move. Load into unused float registers and fall into |
|
1401 |
// the float-store case. |
|
1402 |
if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
1403 |
int offset = ra_->reg2offset(src_first); |
|
1404 |
// Further check for aligned-adjacent pair, so we can use a double load |
|
1405 |
if( (src_first&1)==0 && src_first+1 == src_second ) { |
|
1406 |
src_second = OptoReg::Name(R_F31_num); |
|
1407 |
src_second_rc = rc_float; |
|
1408 |
size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); |
|
1409 |
} else { |
|
1410 |
size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); |
|
1411 |
} |
|
1412 |
src_first = OptoReg::Name(R_F30_num); |
|
1413 |
src_first_rc = rc_float; |
|
1414 |
} |
|
1415 |
||
1416 |
if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { |
|
1417 |
int offset = ra_->reg2offset(src_second); |
|
1418 |
size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); |
|
1419 |
src_second = OptoReg::Name(R_F31_num); |
|
1420 |
src_second_rc = rc_float; |
|
1421 |
} |
|
1422 |
||
1423 |
// -------------------------------------- |
|
1424 |
// Check for float->int copy; requires a trip through memory |
|
10027 | 1425 |
if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
1 | 1426 |
int offset = frame::register_save_words*wordSize; |
10027 | 1427 |
if (cbuf) { |
1 | 1428 |
emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
1429 |
impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); |
|
1430 |
impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); |
|
1431 |
emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); |
|
1432 |
} |
|
1433 |
#ifndef PRODUCT |
|
10027 | 1434 |
else if (!do_size) { |
1435 |
if (size != 0) st->print("\n\t"); |
|
1 | 1436 |
st->print( "SUB R_SP,16,R_SP\n"); |
1437 |
impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); |
|
1438 |
impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); |
|
1439 |
st->print("\tADD R_SP,16,R_SP\n"); |
|
1440 |
} |
|
1441 |
#endif |
|
1442 |
size += 16; |
|
1443 |
} |
|
1444 |
||
10027 | 1445 |
// Check for float->int copy on T4 |
1446 |
if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { |
|
1447 |
// Further check for aligned-adjacent pair, so we can use a double move |
|
1448 |
if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) |
|
1449 |
return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); |
|
1450 |
size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); |
|
1451 |
} |
|
1452 |
// Check for int->float copy on T4 |
|
1453 |
if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { |
|
1454 |
// Further check for aligned-adjacent pair, so we can use a double move |
|
1455 |
if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) |
|
1456 |
return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); |
|
1457 |
size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); |
|
1458 |
} |
|
1459 |
||
1 | 1460 |
// -------------------------------------- |
1461 |
// In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. |
|
1462 |
// In such cases, I have to do the big-endian swap. For aligned targets, the |
|
1463 |
// hardware does the flop for me. Doubles are always aligned, so no problem |
|
1464 |
// there. Misaligned sources only come from native-long-returns (handled |
|
1465 |
// special below). |
|
1466 |
#ifndef _LP64 |
|
1467 |
if( src_first_rc == rc_int && // source is already big-endian |
|
1468 |
src_second_rc != rc_bad && // 64-bit move |
|
1469 |
((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst |
|
1470 |
assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); |
|
1471 |
// Do the big-endian flop. |
|
1472 |
OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; |
|
1473 |
enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; |
|
1474 |
} |
|
1475 |
#endif |
|
1476 |
||
1477 |
// -------------------------------------- |
|
1478 |
// Check for integer reg-reg copy |
|
1479 |
if( src_first_rc == rc_int && dst_first_rc == rc_int ) { |
|
1480 |
#ifndef _LP64 |
|
1481 |
if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case |
|
1482 |
// Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value |
|
1483 |
// as stored in memory. On a big-endian machine like SPARC, this means that the _second |
|
1484 |
// operand contains the least significant word of the 64-bit value and vice versa. |
|
1485 |
OptoReg::Name tmp = OptoReg::Name(R_O7_num); |
|
1486 |
assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); |
|
1487 |
// Shift O0 left in-place, zero-extend O1, then OR them into the dst |
|
1488 |
if( cbuf ) { |
|
1489 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); |
|
1490 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); |
|
1491 |
emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); |
|
1492 |
#ifndef PRODUCT |
|
1493 |
} else if( !do_size ) { |
|
1494 |
if( size != 0 ) st->print("\n\t"); |
|
1495 |
st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); |
|
1496 |
st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); |
|
1497 |
st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); |
|
1498 |
#endif |
|
1499 |
} |
|
1500 |
return size+12; |
|
1501 |
} |
|
1502 |
else if( dst_first == R_I0_num && dst_second == R_I1_num ) { |
|
1503 |
// returning a long value in I0/I1 |
|
1504 |
// a SpillCopy must be able to target a return instruction's reg_class |
|
1505 |
// Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value |
|
1506 |
// as stored in memory. On a big-endian machine like SPARC, this means that the _second |
|
1507 |
// operand contains the least significant word of the 64-bit value and vice versa. |
|
1508 |
OptoReg::Name tdest = dst_first; |
|
1509 |
||
1510 |
if (src_first == dst_first) { |
|
1511 |
tdest = OptoReg::Name(R_O7_num); |
|
1512 |
size += 4; |
|
1513 |
} |
|
1514 |
||
1515 |
if( cbuf ) { |
|
1516 |
assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); |
|
1517 |
// Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 |
|
1518 |
// ShrL_reg_imm6 |
|
1519 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); |
|
1520 |
// ShrR_reg_imm6 src, 0, dst |
|
1521 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); |
|
1522 |
if (tdest != dst_first) { |
|
1523 |
emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); |
|
1524 |
} |
|
1525 |
} |
|
1526 |
#ifndef PRODUCT |
|
1527 |
else if( !do_size ) { |
|
1528 |
if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! |
|
1529 |
st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); |
|
1530 |
st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); |
|
1531 |
if (tdest != dst_first) { |
|
1532 |
st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); |
|
1533 |
} |
|
1534 |
} |
|
1535 |
#endif // PRODUCT |
|
1536 |
return size+8; |
|
1537 |
} |
|
1538 |
#endif // !_LP64 |
|
1539 |
// Else normal reg-reg copy |
|
1540 |
assert( src_second != dst_first, "smashed second before evacuating it" ); |
|
1541 |
size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); |
|
1542 |
assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); |
|
1543 |
// This moves an aligned adjacent pair. |
|
1544 |
// See if we are done. |
|
1545 |
if( src_first+1 == src_second && dst_first+1 == dst_second ) |
|
1546 |
return size; |
|
1547 |
} |
|
1548 |
||
1549 |
// Check for integer store |
|
1550 |
if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { |
|
1551 |
int offset = ra_->reg2offset(dst_first); |
|
1552 |
// Further check for aligned-adjacent pair, so we can use a double store |
|
1553 |
if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) |
|
1554 |
return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); |
|
1555 |
size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); |
|
1556 |
} |
|
1557 |
||
1558 |
// Check for integer load |
|
1559 |
if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { |
|
1560 |
int offset = ra_->reg2offset(src_first); |
|
1561 |
// Further check for aligned-adjacent pair, so we can use a double load |
|
1562 |
if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) |
|
1563 |
return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); |
|
1564 |
size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); |
|
1565 |
} |
|
1566 |
||
1567 |
// Check for float reg-reg copy |
|
1568 |
if( src_first_rc == rc_float && dst_first_rc == rc_float ) { |
|
1569 |
// Further check for aligned-adjacent pair, so we can use a double move |
|
1570 |
if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) |
|
1571 |
return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); |
|
1572 |
size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); |
|
1573 |
} |
|
1574 |
||
1575 |
// Check for float store |
|
1576 |
if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
|
1577 |
int offset = ra_->reg2offset(dst_first); |
|
1578 |
// Further check for aligned-adjacent pair, so we can use a double store |
|
1579 |
if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) |
|
1580 |
return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); |
|
1581 |
size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); |
|
1582 |
} |
|
1583 |
||
1584 |
// Check for float load |
|
1585 |
if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { |
|
1586 |
int offset = ra_->reg2offset(src_first); |
|
1587 |
// Further check for aligned-adjacent pair, so we can use a double load |
|
1588 |
if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) |
|
1589 |
return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); |
|
1590 |
size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); |
|
1591 |
} |
|
1592 |
||
1593 |
// -------------------------------------------------------------------- |
|
1594 |
// Check for hi bits still needing moving. Only happens for misaligned |
|
1595 |
// arguments to native calls. |
|
1596 |
if( src_second == dst_second ) |
|
1597 |
return size; // Self copy; no move |
|
1598 |
assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); |
|
1599 |
||
1600 |
#ifndef _LP64 |
|
1601 |
// In the LP64 build, all registers can be moved as aligned/adjacent |
|
2131 | 1602 |
// pairs, so there's never any need to move the high bits separately. |
1 | 1603 |
// The 32-bit builds have to deal with the 32-bit ABI which can force |
1604 |
// all sorts of silly alignment problems. |
|
1605 |
||
1606 |
// Check for integer reg-reg copy. Hi bits are stuck up in the top |
|
1607 |
// 32-bits of a 64-bit register, but are needed in low bits of another |
|
1608 |
// register (else it's a hi-bits-to-hi-bits copy which should have |
|
1609 |
// happened already as part of a 64-bit move) |
|
1610 |
if( src_second_rc == rc_int && dst_second_rc == rc_int ) { |
|
1611 |
assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); |
|
1612 |
assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); |
|
1613 |
// Shift src_second down to dst_second's low bits. |
|
1614 |
if( cbuf ) { |
|
1615 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); |
|
1616 |
#ifndef PRODUCT |
|
1617 |
} else if( !do_size ) { |
|
1618 |
if( size != 0 ) st->print("\n\t"); |
|
1619 |
st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); |
|
1620 |
#endif |
|
1621 |
} |
|
1622 |
return size+4; |
|
1623 |
} |
|
1624 |
||
1625 |
// Check for high word integer store. Must down-shift the hi bits |
|
1626 |
// into a temp register, then fall into the case of storing int bits. |
|
1627 |
if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { |
|
1628 |
// Shift src_second down to dst_second's low bits. |
|
1629 |
if( cbuf ) { |
|
1630 |
emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); |
|
1631 |
#ifndef PRODUCT |
|
1632 |
} else if( !do_size ) { |
|
1633 |
if( size != 0 ) st->print("\n\t"); |
|
1634 |
st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); |
|
1635 |
#endif |
|
1636 |
} |
|
1637 |
size+=4; |
|
1638 |
src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! |
|
1639 |
} |
|
1640 |
||
1641 |
// Check for high word integer load |
|
1642 |
if( dst_second_rc == rc_int && src_second_rc == rc_stack ) |
|
1643 |
return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); |
|
1644 |
||
1645 |
// Check for high word integer store |
|
1646 |
if( src_second_rc == rc_int && dst_second_rc == rc_stack ) |
|
1647 |
return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); |
|
1648 |
||
1649 |
// Check for high word float store |
|
1650 |
if( src_second_rc == rc_float && dst_second_rc == rc_stack ) |
|
1651 |
return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); |
|
1652 |
||
1653 |
#endif // !_LP64 |
|
1654 |
||
1655 |
Unimplemented(); |
|
1656 |
} |
|
1657 |
||
1658 |
#ifndef PRODUCT |
|
1659 |
void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { |
|
1660 |
implementation( NULL, ra_, false, st ); |
|
1661 |
} |
|
1662 |
#endif |
|
1663 |
||
1664 |
void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1665 |
implementation( &cbuf, ra_, false, NULL ); |
|
1666 |
} |
|
1667 |
||
1668 |
uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
|
1669 |
return implementation( NULL, ra_, true, NULL ); |
|
1670 |
} |
|
1671 |
||
1672 |
//============================================================================= |
|
1673 |
#ifndef PRODUCT |
|
1674 |
void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { |
|
1675 |
st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); |
|
1676 |
} |
|
1677 |
#endif |
|
1678 |
||
1679 |
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { |
|
1680 |
MacroAssembler _masm(&cbuf); |
|
1681 |
for(int i = 0; i < _count; i += 1) { |
|
1682 |
__ nop(); |
|
1683 |
} |
|
1684 |
} |
|
1685 |
||
1686 |
uint MachNopNode::size(PhaseRegAlloc *ra_) const { |
|
1687 |
return 4 * _count; |
|
1688 |
} |
|
1689 |
||
1690 |
||
1691 |
//============================================================================= |
|
1692 |
#ifndef PRODUCT |
|
1693 |
void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { |
|
1694 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1695 |
int reg = ra_->get_reg_first(this); |
|
1696 |
st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); |
|
1697 |
} |
|
1698 |
#endif |
|
1699 |
||
1700 |
void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1701 |
MacroAssembler _masm(&cbuf); |
|
1702 |
int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; |
|
1703 |
int reg = ra_->get_encode(this); |
|
1704 |
||
1705 |
if (Assembler::is_simm13(offset)) { |
|
1706 |
__ add(SP, offset, reg_to_register_object(reg)); |
|
1707 |
} else { |
|
1708 |
__ set(offset, O7); |
|
1709 |
__ add(SP, O7, reg_to_register_object(reg)); |
|
1710 |
} |
|
1711 |
} |
|
1712 |
||
1713 |
uint BoxLockNode::size(PhaseRegAlloc *ra_) const { |
|
1714 |
// BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) |
|
1715 |
assert(ra_ == ra_->C->regalloc(), "sanity"); |
|
1716 |
return ra_->C->scratch_emit_size(this); |
|
1717 |
} |
|
1718 |
||
1719 |
//============================================================================= |
|
1720 |
#ifndef PRODUCT |
|
1721 |
void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { |
|
1722 |
st->print_cr("\nUEP:"); |
|
1723 |
#ifdef _LP64 |
|
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
19319
diff
changeset
|
1724 |
if (UseCompressedClassPointers) { |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
1725 |
assert(Universe::heap() != NULL, "java heap should be initialized"); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
1726 |
st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
21188
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1727 |
if (Universe::narrow_klass_base() != 0) { |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1728 |
st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1729 |
if (Universe::narrow_klass_shift() != 0) { |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1730 |
st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1731 |
} |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1732 |
st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1733 |
st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1734 |
} else { |
d053e4e8f901
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
20289
diff
changeset
|
1735 |
st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
19319
0ad35be0733a
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
18097
diff
changeset
|
1736 |
} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
1737 |
} else { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
1738 |
st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
1739 |
} |
1 | 1740 |
st->print_cr("\tCMP R_G5,R_G3" ); |
1741 |
st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); |
|
1742 |
#else // _LP64 |
|
1743 |
st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
|
1744 |
st->print_cr("\tCMP R_G5,R_G3" ); |
|
1745 |
st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); |
|
1746 |
#endif // _LP64 |
|
1747 |
} |
|
1748 |
#endif |
|
1749 |
||
1750 |
void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1751 |
MacroAssembler _masm(&cbuf); |
|
1752 |
Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
|
1753 |
Register temp_reg = G3; |
|
1754 |
assert( G5_ic_reg != temp_reg, "conflicting registers" ); |
|
1755 |
||
2131 | 1756 |
// Load klass from receiver |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
1757 |
__ load_klass(O0, temp_reg); |
1 | 1758 |
// Compare against expected klass |
1759 |
__ cmp(temp_reg, G5_ic_reg); |
|
1760 |
// Branch to miss code, checks xcc or icc depending |
|
1761 |
__ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); |
|
1762 |
} |
|
1763 |
||
1764 |
uint MachUEPNode::size(PhaseRegAlloc *ra_) const { |
|
1765 |
return MachNode::size(ra_); |
|
1766 |
} |
|
1767 |
||
1768 |
||
1769 |
//============================================================================= |
|
1770 |
||
1771 |
||
1772 |
// Emit exception handler code. |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
1773 |
int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { |
1 | 1774 |
Register temp_reg = G3; |
6418 | 1775 |
AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
1 | 1776 |
MacroAssembler _masm(&cbuf); |
1777 |
||
1778 |
address base = |
|
1779 |
__ start_a_stub(size_exception_handler()); |
|
1780 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
1781 |
||
1782 |
int offset = __ offset(); |
|
1783 |
||
2571 | 1784 |
__ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
1 | 1785 |
__ delayed()->nop(); |
1786 |
||
1787 |
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
|
1788 |
||
1789 |
__ end_a_stub(); |
|
1790 |
||
1791 |
return offset; |
|
1792 |
} |
|
1793 |
||
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22911
diff
changeset
|
1794 |
int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { |
1 | 1795 |
// Can't use any of the current frame's registers as we may have deopted |
1796 |
// at a poll and everything (including G3) can be live. |
|
1797 |
Register temp_reg = L0; |
|
2571 | 1798 |
AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
1 | 1799 |
MacroAssembler _masm(&cbuf); |
1800 |
||
1801 |
address base = |
|
1802 |
__ start_a_stub(size_deopt_handler()); |
|
1803 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
|
1804 |
||
1805 |
int offset = __ offset(); |
|
1806 |
__ save_frame(0); |
|
2571 | 1807 |
__ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
1 | 1808 |
__ delayed()->restore(); |
1809 |
||
1810 |
assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); |
|
1811 |
||
1812 |
__ end_a_stub(); |
|
1813 |
return offset; |
|
1814 |
||
1815 |
} |
|
1816 |
||
1817 |
// Given a register encoding, produce a Integer Register object |
|
1818 |
static Register reg_to_register_object(int register_encoding) { |
|
1819 |
assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); |
|
1820 |
return as_Register(register_encoding); |
|
1821 |
} |
|
1822 |
||
1823 |
// Given a register encoding, produce a single-precision Float Register object |
|
1824 |
static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { |
|
1825 |
assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); |
|
1826 |
return as_SingleFloatRegister(register_encoding); |
|
1827 |
} |
|
1828 |
||
1829 |
// Given a register encoding, produce a double-precision Float Register object |
|
1830 |
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { |
|
1831 |
assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); |
|
1832 |
assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); |
|
1833 |
return as_DoubleFloatRegister(register_encoding); |
|
1834 |
} |
|
1835 |
||
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1836 |
const bool Matcher::match_rule_supported(int opcode) { |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1837 |
if (!has_match_rule(opcode)) |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1838 |
return false; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1839 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1840 |
switch (opcode) { |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1841 |
case Op_CountLeadingZerosI: |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1842 |
case Op_CountLeadingZerosL: |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1843 |
case Op_CountTrailingZerosI: |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1844 |
case Op_CountTrailingZerosL: |
12113
71f302d5c8ee
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
11445
diff
changeset
|
1845 |
case Op_PopCountI: |
71f302d5c8ee
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
11445
diff
changeset
|
1846 |
case Op_PopCountL: |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1847 |
if (!UsePopCountInstruction) |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1848 |
return false; |
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1849 |
case Op_CompareAndSwapL: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1850 |
#ifdef _LP64 |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1851 |
case Op_CompareAndSwapP: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1852 |
#endif |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1853 |
if (!VM_Version::supports_cx8()) |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
1854 |
return false; |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1855 |
break; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1856 |
} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1857 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1858 |
return true; // Per default match rules are supported. |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1859 |
} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
1860 |
|
1 | 1861 |
int Matcher::regnum_to_fpu_offset(int regnum) { |
1862 |
return regnum - 32; // The FP registers are in the second chunk |
|
1863 |
} |
|
1864 |
||
1865 |
#ifdef ASSERT |
|
1866 |
address last_rethrow = NULL; // debugging aid for Rethrow encoding |
|
1867 |
#endif |
|
1868 |
||
1869 |
// Vector width in bytes |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1870 |
const int Matcher::vector_width_in_bytes(BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1871 |
assert(MaxVectorSize == 8, ""); |
1 | 1872 |
return 8; |
1873 |
} |
|
1874 |
||
1875 |
// Vector ideal reg |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1876 |
const int Matcher::vector_ideal_reg(int size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1877 |
assert(MaxVectorSize == 8, ""); |
1 | 1878 |
return Op_RegD; |
1879 |
} |
|
1880 |
||
13930 | 1881 |
const int Matcher::vector_shift_count_ideal_reg(int size) { |
1882 |
fatal("vector shift is not supported"); |
|
1883 |
return Node::NotAMachineReg; |
|
1884 |
} |
|
1885 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1886 |
// Limits on vector size (number of elements) loaded into vector. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1887 |
const int Matcher::max_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1888 |
assert(is_java_primitive(bt), "only primitive type vectors"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1889 |
return vector_width_in_bytes(bt)/type2aelembytes(bt); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1890 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1891 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1892 |
const int Matcher::min_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1893 |
return max_vector_size(bt); // Same as max. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1894 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1895 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1896 |
// SPARC doesn't support misaligned vectors store/load. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1897 |
const bool Matcher::misaligned_vectors_ok() { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1898 |
return false; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1899 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
1900 |
|
22505 | 1901 |
// Current (2013) SPARC platforms need to read original key |
1902 |
// to construct decryption expanded key |
|
1903 |
const bool Matcher::pass_original_key_for_aes() { |
|
1904 |
return true; |
|
1905 |
} |
|
1906 |
||
1 | 1907 |
// USII supports fxtof through the whole range of number, USIII doesn't |
1908 |
const bool Matcher::convL2FSupported(void) { |
|
1909 |
return VM_Version::has_fast_fxtof(); |
|
1910 |
} |
|
1911 |
||
1912 |
// Is this branch offset short enough that a short branch can be used? |
|
1913 |
// |
|
1914 |
// NOTE: If the platform does not provide any short branch variants, then |
|
1915 |
// this method should return false for offset 0. |
|
10264 | 1916 |
bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1917 |
// The passed offset is relative to address of the branch. |
|
1918 |
// Don't need to adjust the offset. |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
1919 |
return UseCBCond && Assembler::is_simm12(offset); |
1 | 1920 |
} |
1921 |
||
1922 |
const bool Matcher::isSimpleConstant64(jlong value) { |
|
1923 |
// Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. |
|
1924 |
// Depends on optimizations in MacroAssembler::setx. |
|
1925 |
int hi = (int)(value >> 32); |
|
1926 |
int lo = (int)(value & ~0); |
|
1927 |
return (hi == 0) || (hi == -1) || (lo == 0); |
|
1928 |
} |
|
1929 |
||
1930 |
// No scaling for the parameter the ClearArray node. |
|
1931 |
const bool Matcher::init_array_count_is_in_bytes = true; |
|
1932 |
||
1933 |
// Threshold size for cleararray. |
|
1934 |
const int Matcher::init_array_short_size = 8 * BytesPerLong; |
|
1935 |
||
10971 | 1936 |
// No additional cost for CMOVL. |
1937 |
const int Matcher::long_cmove_cost() { return 0; } |
|
1938 |
||
1939 |
// CMOVF/CMOVD are expensive on T4 and on SPARC64. |
|
1940 |
const int Matcher::float_cmove_cost() { |
|
1941 |
return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; |
|
1942 |
} |
|
1943 |
||
22844
90f76a40ed8a
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
22838
diff
changeset
|
1944 |
// Does the CPU require late expand (see block.cpp for description of late expand)? |
90f76a40ed8a
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
22838
diff
changeset
|
1945 |
const bool Matcher::require_postalloc_expand = false; |
90f76a40ed8a
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
22838
diff
changeset
|
1946 |
|
1 | 1947 |
// Should the Matcher clone shifts on addressing modes, expecting them to |
1948 |
// be subsumed into complex addressing expressions or compute them into |
|
1949 |
// registers? True for Intel but false for most RISCs |
|
1950 |
const bool Matcher::clone_shift_expressions = false; |
|
1951 |
||
8868
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8324
diff
changeset
|
1952 |
// Do we need to mask the count passed to shift instructions or does |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8324
diff
changeset
|
1953 |
// the cpu only look at the lower 5/6 bits anyway? |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8324
diff
changeset
|
1954 |
const bool Matcher::need_masked_shift_count = false; |
1bae515b806b
7029017: Additional architecture support for c2 compiler
roland
parents:
8324
diff
changeset
|
1955 |
|
5698
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1956 |
bool Matcher::narrow_oop_use_complex_address() { |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1957 |
NOT_LP64(ShouldNotCallThis()); |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1958 |
assert(UseCompressedOops, "only for compressed oops code"); |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1959 |
return false; |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1960 |
} |
091095915ee6
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
5694
diff
changeset
|
1961 |
|
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
1962 |
bool Matcher::narrow_klass_use_complex_address() { |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
1963 |
NOT_LP64(ShouldNotCallThis()); |
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
19319
diff
changeset
|
1964 |
assert(UseCompressedClassPointers, "only for compressed klass code"); |
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
1965 |
return false; |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
1966 |
} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
1967 |
|
1 | 1968 |
// Is it better to copy float constants, or load them directly from memory? |
1969 |
// Intel can load a float constant from a direct address, requiring no |
|
1970 |
// extra registers. Most RISCs will have to materialize an address into a |
|
1971 |
// register first, so they would do better to copy the constant from stack. |
|
1972 |
const bool Matcher::rematerialize_float_constants = false; |
|
1973 |
||
1974 |
// If CPU can load and store mis-aligned doubles directly then no fixup is |
|
1975 |
// needed. Else we split the double into 2 integer pieces and move it |
|
1976 |
// piece-by-piece. Only happens when passing doubles into C code as the |
|
1977 |
// Java calling convention forces doubles to be aligned. |
|
1978 |
#ifdef _LP64 |
|
1979 |
const bool Matcher::misaligned_doubles_ok = true; |
|
1980 |
#else |
|
1981 |
const bool Matcher::misaligned_doubles_ok = false; |
|
1982 |
#endif |
|
1983 |
||
1984 |
// No-op on SPARC. |
|
1985 |
void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { |
|
1986 |
} |
|
1987 |
||
1988 |
// Advertise here if the CPU requires explicit rounding operations |
|
1989 |
// to implement the UseStrictFP mode. |
|
1990 |
const bool Matcher::strict_fp_requires_explicit_rounding = false; |
|
1991 |
||
26804
4b23f22faae6
8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents:
25933
diff
changeset
|
1992 |
// Are floats converted to double when stored to stack during deoptimization? |
5025
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4589
diff
changeset
|
1993 |
// Sparc does not handle callee-save floats. |
05adc9b8f96a
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
4589
diff
changeset
|
1994 |
bool Matcher::float_in_double() { return false; } |
1 | 1995 |
|
1996 |
// Do ints take an entire long register or just half? |
|
1997 |
// Note that we if-def off of _LP64. |
|
1998 |
// The relevant question is how the int is callee-saved. In _LP64 |
|
1999 |
// the whole long is written but de-opt'ing will have to extract |
|
2000 |
// the relevant 32 bits, in not-_LP64 only the low 32 bits is written. |
|
2001 |
#ifdef _LP64 |
|
2002 |
const bool Matcher::int_in_long = true; |
|
2003 |
#else |
|
2004 |
const bool Matcher::int_in_long = false; |
|
2005 |
#endif |
|
2006 |
||
2007 |
// Return whether or not this register is ever used as an argument. This |
|
2008 |
// function is used on startup to build the trampoline stubs in generateOptoStub. |
|
2009 |
// Registers not mentioned will be killed by the VM call in the trampoline, and |
|
2010 |
// arguments in those registers not be available to the callee. |
|
2011 |
bool Matcher::can_be_java_arg( int reg ) { |
|
2012 |
// Standard sparc 6 args in registers |
|
2013 |
if( reg == R_I0_num || |
|
2014 |
reg == R_I1_num || |
|
2015 |
reg == R_I2_num || |
|
2016 |
reg == R_I3_num || |
|
2017 |
reg == R_I4_num || |
|
2018 |
reg == R_I5_num ) return true; |
|
2019 |
#ifdef _LP64 |
|
2020 |
// 64-bit builds can pass 64-bit pointers and longs in |
|
2021 |
// the high I registers |
|
2022 |
if( reg == R_I0H_num || |
|
2023 |
reg == R_I1H_num || |
|
2024 |
reg == R_I2H_num || |
|
2025 |
reg == R_I3H_num || |
|
2026 |
reg == R_I4H_num || |
|
2027 |
reg == R_I5H_num ) return true; |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2028 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2029 |
if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2030 |
return true; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2031 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2032 |
|
1 | 2033 |
#else |
2034 |
// 32-bit builds with longs-in-one-entry pass longs in G1 & G4. |
|
2035 |
// Longs cannot be passed in O regs, because O regs become I regs |
|
2036 |
// after a 'save' and I regs get their high bits chopped off on |
|
2037 |
// interrupt. |
|
2038 |
if( reg == R_G1H_num || reg == R_G1_num ) return true; |
|
2039 |
if( reg == R_G4H_num || reg == R_G4_num ) return true; |
|
2040 |
#endif |
|
2041 |
// A few float args in registers |
|
2042 |
if( reg >= R_F0_num && reg <= R_F7_num ) return true; |
|
2043 |
||
2044 |
return false; |
|
2045 |
} |
|
2046 |
||
2047 |
bool Matcher::is_spillable_arg( int reg ) { |
|
2048 |
return can_be_java_arg(reg); |
|
2049 |
} |
|
2050 |
||
7115
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2051 |
bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2052 |
// Use hardware SDIVX instruction when it is |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2053 |
// faster than a code which use multiply. |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2054 |
return VM_Version::has_fast_idiv(); |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2055 |
} |
32300e243300
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
6418
diff
changeset
|
2056 |
|
1 | 2057 |
// Register for DIVI projection of divmodI |
2058 |
RegMask Matcher::divI_proj_mask() { |
|
2059 |
ShouldNotReachHere(); |
|
2060 |
return RegMask(); |
|
2061 |
} |
|
2062 |
||
2063 |
// Register for MODI projection of divmodI |
|
2064 |
RegMask Matcher::modI_proj_mask() { |
|
2065 |
ShouldNotReachHere(); |
|
2066 |
return RegMask(); |
|
2067 |
} |
|
2068 |
||
2069 |
// Register for DIVL projection of divmodL |
|
2070 |
RegMask Matcher::divL_proj_mask() { |
|
2071 |
ShouldNotReachHere(); |
|
2072 |
return RegMask(); |
|
2073 |
} |
|
2074 |
||
2075 |
// Register for MODL projection of divmodL |
|
2076 |
RegMask Matcher::modL_proj_mask() { |
|
2077 |
ShouldNotReachHere(); |
|
2078 |
return RegMask(); |
|
2079 |
} |
|
2080 |
||
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
4096
diff
changeset
|
2081 |
const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
11197
158eecd6b330
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
11190
diff
changeset
|
2082 |
return L7_REGP_mask(); |
4566
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
4096
diff
changeset
|
2083 |
} |
b363f6ef4068
6829187: compiler optimizations required for JSR 292
twisti
parents:
4096
diff
changeset
|
2084 |
|
1 | 2085 |
%} |
2086 |
||
2087 |
||
2088 |
// The intptr_t operand types, defined by textual substitution. |
|
2089 |
// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) |
|
2090 |
#ifdef _LP64 |
|
3177 | 2091 |
#define immX immL |
2092 |
#define immX13 immL13 |
|
2093 |
#define immX13m7 immL13m7 |
|
2094 |
#define iRegX iRegL |
|
2095 |
#define g1RegX g1RegL |
|
1 | 2096 |
#else |
3177 | 2097 |
#define immX immI |
2098 |
#define immX13 immI13 |
|
2099 |
#define immX13m7 immI13m7 |
|
2100 |
#define iRegX iRegI |
|
2101 |
#define g1RegX g1RegI |
|
1 | 2102 |
#endif |
2103 |
||
2104 |
//----------ENCODING BLOCK----------------------------------------------------- |
|
2105 |
// This block specifies the encoding classes used by the compiler to output |
|
2106 |
// byte streams. Encoding classes are parameterized macros used by |
|
2107 |
// Machine Instruction Nodes in order to generate the bit encoding of the |
|
2108 |
// instruction. Operands specify their base encoding interface with the |
|
2109 |
// interface keyword. There are currently supported four interfaces, |
|
2110 |
// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an |
|
2111 |
// operand to generate a function which returns its register number when |
|
2112 |
// queried. CONST_INTER causes an operand to generate a function which |
|
2113 |
// returns the value of the constant when queried. MEMORY_INTER causes an |
|
2114 |
// operand to generate four functions which return the Base Register, the |
|
2115 |
// Index Register, the Scale Value, and the Offset Value of the operand when |
|
2116 |
// queried. COND_INTER causes an operand to generate six functions which |
|
2117 |
// return the encoding code (ie - encoding bits for the instruction) |
|
2118 |
// associated with each basic boolean condition for a conditional instruction. |
|
2119 |
// |
|
2120 |
// Instructions specify two basic values for encoding. Again, a function |
|
2121 |
// is available to check if the constant displacement is an oop. They use the |
|
2122 |
// ins_encode keyword to specify their encoding classes (which must be |
|
2123 |
// a sequence of enc_class names, and their parameters, specified in |
|
2124 |
// the encoding block), and they use the |
|
2125 |
// opcode keyword to specify, in order, their primary, secondary, and |
|
2126 |
// tertiary opcode. Only the opcode sections which a particular instruction |
|
2127 |
// needs for encoding need to be specified. |
|
2128 |
encode %{ |
|
2129 |
enc_class enc_untested %{ |
|
2130 |
#ifdef ASSERT |
|
2131 |
MacroAssembler _masm(&cbuf); |
|
2132 |
__ untested("encoding"); |
|
2133 |
#endif |
|
2134 |
%} |
|
2135 |
||
2136 |
enc_class form3_mem_reg( memory mem, iRegI dst ) %{ |
|
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2137 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, |
1 | 2138 |
$mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
2139 |
%} |
|
2140 |
||
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
2141 |
enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2142 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
2143 |
$mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
2144 |
%} |
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
2145 |
|
1 | 2146 |
enc_class form3_mem_prefetch_read( memory mem ) %{ |
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2147 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
1 | 2148 |
$mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2149 |
%} |
|
2150 |
||
2151 |
enc_class form3_mem_prefetch_write( memory mem ) %{ |
|
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2152 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
1 | 2153 |
$mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2154 |
%} |
|
2155 |
||
2156 |
enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
2157 |
assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
2158 |
assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
1 | 2159 |
guarantee($mem$$index == R_G0_enc, "double index?"); |
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2160 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2161 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
1 | 2162 |
emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2163 |
emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); |
|
2164 |
%} |
|
2165 |
||
2166 |
enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
2167 |
assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
2168 |
assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
1 | 2169 |
guarantee($mem$$index == R_G0_enc, "double index?"); |
2170 |
// Load long with 2 instructions |
|
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2171 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2172 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
1 | 2173 |
%} |
2174 |
||
2175 |
//%%% form3_mem_plus_4_reg is a hack--get rid of it |
|
2176 |
enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ |
|
2177 |
guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); |
|
22228
f0a0d6be25c6
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
21523
diff
changeset
|
2178 |
emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
1 | 2179 |
%} |
2180 |
||
2181 |
enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ |
|
2182 |
// Encode a reg-reg copy. If it is useless, then empty encoding. |
|
2183 |
if( $rs2$$reg != $rd$$reg ) |
|
2184 |
emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); |
|
2185 |
%} |
|
2186 |
||
2187 |
// Target lo half of long |
|
2188 |
enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ |
|
2189 |
// Encode a reg-reg copy. If it is useless, then empty encoding. |
|
2190 |
if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) |
|
2191 |
emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); |
|
2192 |
%} |
|
2193 |
||
2194 |
// Source lo half of long |
|
2195 |
enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ |
|
2196 |
// Encode a reg-reg copy. If it is useless, then empty encoding. |
|
2197 |
if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) |
|
2198 |
emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); |
|
2199 |
%} |
|
2200 |
||
2201 |
// Target hi half of long |
|
2202 |
enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ |
|
2203 |
emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); |
|
2204 |
%} |
|
2205 |
||
2206 |
// Source lo half of long, and leave it sign extended. |
|
2207 |
enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ |
|
2208 |
// Sign extend low half |
|
2209 |
emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); |
|
2210 |
%} |
|
2211 |
||
2212 |
// Source hi half of long, and leave it sign extended. |
|
2213 |
enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ |
|
2214 |
// Shift high half to low half |
|
2215 |
emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); |
|
2216 |
%} |
|
2217 |
||
2218 |
// Source hi half of long |
|
2219 |
enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ |
|
2220 |
// Encode a reg-reg copy. If it is useless, then empty encoding. |
|
2221 |
if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) |
|
2222 |
emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); |
|
2223 |
%} |
|
2224 |
||
2225 |
enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ |
|
2226 |
emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); |
|
2227 |
%} |
|
2228 |
||
2229 |
enc_class enc_to_bool( iRegI src, iRegI dst ) %{ |
|
2230 |
emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); |
|
2231 |
emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); |
|
2232 |
%} |
|
2233 |
||
2234 |
enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ |
|
2235 |
emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); |
|
2236 |
// clear if nothing else is happening |
|
2237 |
emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); |
|
2238 |
// blt,a,pn done |
|
2239 |
emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); |
|
2240 |
// mov dst,-1 in delay slot |
|
2241 |
emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); |
|
2242 |
%} |
|
2243 |
||
2244 |
enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ |
|
2245 |
emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); |
|
2246 |
%} |
|
2247 |
||
2248 |
enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ |
|
2249 |
emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); |
|
2250 |
%} |
|
2251 |
||
2252 |
enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ |
|
2253 |
emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); |
|
2254 |
%} |
|
2255 |
||
2256 |
enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ |
|
2257 |
emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); |
|
2258 |
%} |
|
2259 |
||
2260 |
enc_class move_return_pc_to_o1() %{ |
|
2261 |
emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); |
|
2262 |
%} |
|
2263 |
||
2264 |
#ifdef _LP64 |
|
2265 |
/* %%% merge with enc_to_bool */ |
|
2266 |
enc_class enc_convP2B( iRegI dst, iRegP src ) %{ |
|
2267 |
MacroAssembler _masm(&cbuf); |
|
2268 |
||
2269 |
Register src_reg = reg_to_register_object($src$$reg); |
|
2270 |
Register dst_reg = reg_to_register_object($dst$$reg); |
|
2271 |
__ movr(Assembler::rc_nz, src_reg, 1, dst_reg); |
|
2272 |
%} |
|
2273 |
#endif |
|
2274 |
||
2275 |
enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ |
|
2276 |
// (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) |
|
2277 |
MacroAssembler _masm(&cbuf); |
|
2278 |
||
2279 |
Register p_reg = reg_to_register_object($p$$reg); |
|
2280 |
Register q_reg = reg_to_register_object($q$$reg); |
|
2281 |
Register y_reg = reg_to_register_object($y$$reg); |
|
2282 |
Register tmp_reg = reg_to_register_object($tmp$$reg); |
|
2283 |
||
2284 |
__ subcc( p_reg, q_reg, p_reg ); |
|
2285 |
__ add ( p_reg, y_reg, tmp_reg ); |
|
2286 |
__ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); |
|
2287 |
%} |
|
2288 |
||
2289 |
enc_class form_d2i_helper(regD src, regF dst) %{ |
|
2290 |
// fcmp %fcc0,$src,$src |
|
2291 |
emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); |
|
2292 |
// branch %fcc0 not-nan, predict taken |
|
2293 |
emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); |
|
2294 |
// fdtoi $src,$dst |
|
2295 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); |
|
2296 |
// fitos $dst,$dst (if nan) |
|
2297 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); |
|
2298 |
// clear $dst (if nan) |
|
2299 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); |
|
2300 |
// carry on here... |
|
2301 |
%} |
|
2302 |
||
2303 |
enc_class form_d2l_helper(regD src, regD dst) %{ |
|
2304 |
// fcmp %fcc0,$src,$src check for NAN |
|
2305 |
emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); |
|
2306 |
// branch %fcc0 not-nan, predict taken |
|
2307 |
emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); |
|
2308 |
// fdtox $src,$dst convert in delay slot |
|
2309 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); |
|
2310 |
// fxtod $dst,$dst (if nan) |
|
2311 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); |
|
2312 |
// clear $dst (if nan) |
|
2313 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); |
|
2314 |
// carry on here... |
|
2315 |
%} |
|
2316 |
||
2317 |
enc_class form_f2i_helper(regF src, regF dst) %{ |
|
2318 |
// fcmps %fcc0,$src,$src |
|
2319 |
emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); |
|
2320 |
// branch %fcc0 not-nan, predict taken |
|
2321 |
emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); |
|
2322 |
// fstoi $src,$dst |
|
2323 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); |
|
2324 |
// fitos $dst,$dst (if nan) |
|
2325 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); |
|
2326 |
// clear $dst (if nan) |
|
2327 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); |
|
2328 |
// carry on here... |
|
2329 |
%} |
|
2330 |
||
2331 |
enc_class form_f2l_helper(regF src, regD dst) %{ |
|
2332 |
// fcmps %fcc0,$src,$src |
|
2333 |
emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); |
|
2334 |
// branch %fcc0 not-nan, predict taken |
|
2335 |
emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); |
|
2336 |
// fstox $src,$dst |
|
2337 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); |
|
2338 |
// fxtod $dst,$dst (if nan) |
|
2339 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); |
|
2340 |
// clear $dst (if nan) |
|
2341 |
emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); |
|
2342 |
// carry on here... |
|
2343 |
%} |
|
2344 |
||
2345 |
enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} |
|
2346 |
enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} |
|
2347 |
enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} |
|
2348 |
enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} |
|
2349 |
||
2350 |
enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} |
|
2351 |
||
2352 |
enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} |
|
2353 |
enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} |
|
2354 |
||
2355 |
enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ |
|
2356 |
emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); |
|
2357 |
%} |
|
2358 |
||
2359 |
enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ |
|
2360 |
emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); |
|
2361 |
%} |
|
2362 |
||
2363 |
enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ |
|
2364 |
emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); |
|
2365 |
%} |
|
2366 |
||
2367 |
enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ |
|
2368 |
emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); |
|
2369 |
%} |
|
2370 |
||
2371 |
enc_class form3_convI2F(regF rs2, regF rd) %{ |
|
2372 |
emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); |
|
2373 |
%} |
|
2374 |
||
2375 |
// Encloding class for traceable jumps |
|
2376 |
enc_class form_jmpl(g3RegP dest) %{ |
|
2377 |
emit_jmpl(cbuf, $dest$$reg); |
|
2378 |
%} |
|
2379 |
||
2380 |
enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ |
|
2381 |
emit_jmpl_set_exception_pc(cbuf, $dest$$reg); |
|
2382 |
%} |
|
2383 |
||
2384 |
enc_class form2_nop() %{ |
|
2385 |
emit_nop(cbuf); |
|
2386 |
%} |
|
2387 |
||
2388 |
enc_class form2_illtrap() %{ |
|
2389 |
emit_illtrap(cbuf); |
|
2390 |
%} |
|
2391 |
||
2392 |
||
2393 |
// Compare longs and convert into -1, 0, 1. |
|
2394 |
enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ |
|
2395 |
// CMP $src1,$src2 |
|
2396 |
emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); |
|
2397 |
// blt,a,pn done |
|
2398 |
emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); |
|
2399 |
// mov dst,-1 in delay slot |
|
2400 |
emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); |
|
2401 |
// bgt,a,pn done |
|
2402 |
emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); |
|
2403 |
// mov dst,1 in delay slot |
|
2404 |
emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); |
|
2405 |
// CLR $dst |
|
2406 |
emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); |
|
2407 |
%} |
|
2408 |
||
2409 |
enc_class enc_PartialSubtypeCheck() %{ |
|
2410 |
MacroAssembler _masm(&cbuf); |
|
2411 |
__ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); |
|
2412 |
__ delayed()->nop(); |
|
2413 |
%} |
|
2414 |
||
10252 | 2415 |
enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
1 | 2416 |
MacroAssembler _masm(&cbuf); |
10252 | 2417 |
Label* L = $labl$$label; |
1 | 2418 |
Assembler::Predict predict_taken = |
10252 | 2419 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2420 |
||
2421 |
__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
1 | 2422 |
__ delayed()->nop(); |
2423 |
%} |
|
2424 |
||
10252 | 2425 |
enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
1 | 2426 |
MacroAssembler _masm(&cbuf); |
10252 | 2427 |
Label* L = $labl$$label; |
1 | 2428 |
Assembler::Predict predict_taken = |
10252 | 2429 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2430 |
||
2431 |
__ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); |
|
1 | 2432 |
__ delayed()->nop(); |
2433 |
%} |
|
2434 |
||
2435 |
enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ |
|
2436 |
int op = (Assembler::arith_op << 30) | |
|
2437 |
($dst$$reg << 25) | |
|
2438 |
(Assembler::movcc_op3 << 19) | |
|
2439 |
(1 << 18) | // cc2 bit for 'icc' |
|
2440 |
($cmp$$cmpcode << 14) | |
|
2441 |
(0 << 13) | // select register move |
|
2442 |
($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' |
|
2443 |
($src$$reg << 0); |
|
6418 | 2444 |
cbuf.insts()->emit_int32(op); |
1 | 2445 |
%} |
2446 |
||
2447 |
enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ |
|
2448 |
int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits |
|
2449 |
int op = (Assembler::arith_op << 30) | |
|
2450 |
($dst$$reg << 25) | |
|
2451 |
(Assembler::movcc_op3 << 19) | |
|
2452 |
(1 << 18) | // cc2 bit for 'icc' |
|
2453 |
($cmp$$cmpcode << 14) | |
|
2454 |
(1 << 13) | // select immediate move |
|
2455 |
($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' |
|
2456 |
(simm11 << 0); |
|
6418 | 2457 |
cbuf.insts()->emit_int32(op); |
1 | 2458 |
%} |
2459 |
||
2460 |
enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ |
|
2461 |
int op = (Assembler::arith_op << 30) | |
|
2462 |
($dst$$reg << 25) | |
|
2463 |
(Assembler::movcc_op3 << 19) | |
|
2464 |
(0 << 18) | // cc2 bit for 'fccX' |
|
2465 |
($cmp$$cmpcode << 14) | |
|
2466 |
(0 << 13) | // select register move |
|
2467 |
($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 |
|
2468 |
($src$$reg << 0); |
|
6418 | 2469 |
cbuf.insts()->emit_int32(op); |
1 | 2470 |
%} |
2471 |
||
2472 |
enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ |
|
2473 |
int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits |
|
2474 |
int op = (Assembler::arith_op << 30) | |
|
2475 |
($dst$$reg << 25) | |
|
2476 |
(Assembler::movcc_op3 << 19) | |
|
2477 |
(0 << 18) | // cc2 bit for 'fccX' |
|
2478 |
($cmp$$cmpcode << 14) | |
|
2479 |
(1 << 13) | // select immediate move |
|
2480 |
($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 |
|
2481 |
(simm11 << 0); |
|
6418 | 2482 |
cbuf.insts()->emit_int32(op); |
1 | 2483 |
%} |
2484 |
||
2485 |
enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ |
|
2486 |
int op = (Assembler::arith_op << 30) | |
|
2487 |
($dst$$reg << 25) | |
|
2488 |
(Assembler::fpop2_op3 << 19) | |
|
2489 |
(0 << 18) | |
|
2490 |
($cmp$$cmpcode << 14) | |
|
2491 |
(1 << 13) | // select register move |
|
2492 |
($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' |
|
2493 |
($primary << 5) | // select single, double or quad |
|
2494 |
($src$$reg << 0); |
|
6418 | 2495 |
cbuf.insts()->emit_int32(op); |
1 | 2496 |
%} |
2497 |
||
2498 |
enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ |
|
2499 |
int op = (Assembler::arith_op << 30) | |
|
2500 |
($dst$$reg << 25) | |
|
2501 |
(Assembler::fpop2_op3 << 19) | |
|
2502 |
(0 << 18) | |
|
2503 |
($cmp$$cmpcode << 14) | |
|
2504 |
($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' |
|
2505 |
($primary << 5) | // select single, double or quad |
|
2506 |
($src$$reg << 0); |
|
6418 | 2507 |
cbuf.insts()->emit_int32(op); |
1 | 2508 |
%} |
2509 |
||
2510 |
// Used by the MIN/MAX encodings. Same as a CMOV, but |
|
2511 |
// the condition comes from opcode-field instead of an argument. |
|
2512 |
enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ |
|
2513 |
int op = (Assembler::arith_op << 30) | |
|
2514 |
($dst$$reg << 25) | |
|
2515 |
(Assembler::movcc_op3 << 19) | |
|
2516 |
(1 << 18) | // cc2 bit for 'icc' |
|
2517 |
($primary << 14) | |
|
2518 |
(0 << 13) | // select register move |
|
2519 |
(0 << 11) | // cc1, cc0 bits for 'icc' |
|
2520 |
($src$$reg << 0); |
|
6418 | 2521 |
cbuf.insts()->emit_int32(op); |
1 | 2522 |
%} |
2523 |
||
2524 |
enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ |
|
2525 |
int op = (Assembler::arith_op << 30) | |
|
2526 |
($dst$$reg << 25) | |
|
2527 |
(Assembler::movcc_op3 << 19) | |
|
2528 |
(6 << 16) | // cc2 bit for 'xcc' |
|
2529 |
($primary << 14) | |
|
2530 |
(0 << 13) | // select register move |
|
2531 |
(0 << 11) | // cc1, cc0 bits for 'icc' |
|
2532 |
($src$$reg << 0); |
|
6418 | 2533 |
cbuf.insts()->emit_int32(op); |
1 | 2534 |
%} |
2535 |
||
2536 |
enc_class Set13( immI13 src, iRegI rd ) %{ |
|
2537 |
emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); |
|
2538 |
%} |
|
2539 |
||
2540 |
enc_class SetHi22( immI src, iRegI rd ) %{ |
|
2541 |
emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); |
|
2542 |
%} |
|
2543 |
||
2544 |
enc_class Set32( immI src, iRegI rd ) %{ |
|
2545 |
MacroAssembler _masm(&cbuf); |
|
2546 |
__ set($src$$constant, reg_to_register_object($rd$$reg)); |
|
2547 |
%} |
|
2548 |
||
2549 |
enc_class call_epilog %{ |
|
2550 |
if( VerifyStackAtCalls ) { |
|
2551 |
MacroAssembler _masm(&cbuf); |
|
24018
77b156916bab
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
24008
diff
changeset
|
2552 |
int framesize = ra_->C->frame_size_in_bytes(); |
1 | 2553 |
Register temp_reg = G3; |
2554 |
__ add(SP, framesize, temp_reg); |
|
2555 |
__ cmp(temp_reg, FP); |
|
2556 |
__ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); |
|
2557 |
} |
|
2558 |
%} |
|
2559 |
||
2560 |
// Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value |
|
2561 |
// to G1 so the register allocator will not have to deal with the misaligned register |
|
2562 |
// pair. |
|
2563 |
enc_class adjust_long_from_native_call %{ |
|
2564 |
#ifndef _LP64 |
|
2565 |
if (returns_long()) { |
|
2566 |
// sllx O0,32,O0 |
|
2567 |
emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); |
|
2568 |
// srl O1,0,O1 |
|
2569 |
emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); |
|
2570 |
// or O0,O1,G1 |
|
2571 |
emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); |
|
2572 |
} |
|
2573 |
#endif |
|
2574 |
%} |
|
2575 |
||
2576 |
enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime |
|
2577 |
// CALL directly to the runtime |
|
2578 |
// The user of this is responsible for ensuring that R_L7 is empty (killed). |
|
2579 |
emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, |
|
7892
ff4948f95c49
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
7704
diff
changeset
|
2580 |
/*preserve_g2=*/true); |
1 | 2581 |
%} |
2582 |
||
5690 | 2583 |
enc_class preserve_SP %{ |
2584 |
MacroAssembler _masm(&cbuf); |
|
2585 |
__ mov(SP, L7_mh_SP_save); |
|
2586 |
%} |
|
2587 |
||
2588 |
enc_class restore_SP %{ |
|
2589 |
MacroAssembler _masm(&cbuf); |
|
2590 |
__ mov(L7_mh_SP_save, SP); |
|
2591 |
%} |
|
2592 |
||
1 | 2593 |
enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2594 |
// CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
|
2595 |
// who we intended to call. |
|
17094
29c4955396d2
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
14833
diff
changeset
|
2596 |
if (!_method) { |
1 | 2597 |
emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
2598 |
} else if (_optimized_virtual) { |
|
2599 |
emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); |
|
2600 |
} else { |
|
2601 |
emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); |
|
2602 |
} |
|
17094
29c4955396d2
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
14833
diff
changeset
|
2603 |
if (_method) { // Emit stub for static call. |
29c4955396d2
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
14833
diff
changeset
|
2604 |
CompiledStaticCall::emit_to_interp_stub(cbuf); |
1 | 2605 |
} |
2606 |
%} |
|
2607 |
||
2608 |
enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL |
|
2609 |
MacroAssembler _masm(&cbuf); |
|
2610 |
__ set_inst_mark(); |
|
2611 |
int vtable_index = this->_vtable_index; |
|
2612 |
// MachCallDynamicJavaNode::ret_addr_offset uses this same test |
|
2613 |
if (vtable_index < 0) { |
|
2614 |
// must be invalid_vtable_index, not nonvirtual_vtable_index |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
2615 |
assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
1 | 2616 |
Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
2617 |
assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); |
|
2618 |
assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
2619 |
__ ic_call((address)$meth$$method); |
1 | 2620 |
} else { |
2621 |
assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
2622 |
// Just go thru the vtable |
|
2623 |
// get receiver klass (receiver already checked for non-null) |
|
2624 |
// If we end up going thru a c2i adapter interpreter expects method in G5 |
|
2625 |
int off = __ offset(); |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2626 |
__ load_klass(O0, G3_scratch); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2627 |
int klass_load_size; |
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
19319
diff
changeset
|
2628 |
if (UseCompressedClassPointers) { |
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
2629 |
assert(Universe::heap() != NULL, "java heap should be initialized"); |
19319
0ad35be0733a
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
18097
diff
changeset
|
2630 |
klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2631 |
} else { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2632 |
klass_load_size = 1*BytesPerInstWord; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2633 |
} |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
2634 |
int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
1 | 2635 |
int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
2636 |
if (Assembler::is_simm13(v_off)) { |
1 | 2637 |
__ ld_ptr(G3, v_off, G5_method); |
2638 |
} else { |
|
2639 |
// Generate 2 instructions |
|
2640 |
__ Assembler::sethi(v_off & ~0x3ff, G5_method); |
|
2641 |
__ or3(G5_method, v_off & 0x3ff, G5_method); |
|
2642 |
// ld_ptr, set_hi, set |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2643 |
assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
2644 |
"Unexpected instruction size(s)"); |
1 | 2645 |
__ ld_ptr(G3, G5_method, G5_method); |
2646 |
} |
|
2647 |
// NOTE: for vtable dispatches, the vtable entry will never be null. |
|
2648 |
// However it may very well end up in handle_wrong_method if the |
|
2649 |
// method is abstract for the particular class. |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
2650 |
__ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
1 | 2651 |
// jump to target (either compiled code or c2iadapter) |
2652 |
__ jmpl(G3_scratch, G0, O7); |
|
2653 |
__ delayed()->nop(); |
|
2654 |
} |
|
2655 |
%} |
|
2656 |
||
2657 |
enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL |
|
2658 |
MacroAssembler _masm(&cbuf); |
|
2659 |
||
2660 |
Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
|
2661 |
Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because |
|
2662 |
// we might be calling a C2I adapter which needs it. |
|
2663 |
||
2664 |
assert(temp_reg != G5_ic_reg, "conflicting registers"); |
|
2665 |
// Load nmethod |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
2666 |
__ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
1 | 2667 |
|
2668 |
// CALL to compiled java, indirect the contents of G3 |
|
2669 |
__ set_inst_mark(); |
|
2670 |
__ callr(temp_reg, G0); |
|
2671 |
__ delayed()->nop(); |
|
2672 |
%} |
|
2673 |
||
2674 |
enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ |
|
2675 |
MacroAssembler _masm(&cbuf); |
|
2676 |
Register Rdividend = reg_to_register_object($src1$$reg); |
|
2677 |
Register Rdivisor = reg_to_register_object($src2$$reg); |
|
2678 |
Register Rresult = reg_to_register_object($dst$$reg); |
|
2679 |
||
2680 |
__ sra(Rdivisor, 0, Rdivisor); |
|
2681 |
__ sra(Rdividend, 0, Rdividend); |
|
2682 |
__ sdivx(Rdividend, Rdivisor, Rresult); |
|
2683 |
%} |
|
2684 |
||
2685 |
enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ |
|
2686 |
MacroAssembler _masm(&cbuf); |
|
2687 |
||
2688 |
Register Rdividend = reg_to_register_object($src1$$reg); |
|
2689 |
int divisor = $imm$$constant; |
|
2690 |
Register Rresult = reg_to_register_object($dst$$reg); |
|
2691 |
||
2692 |
__ sra(Rdividend, 0, Rdividend); |
|
2693 |
__ sdivx(Rdividend, divisor, Rresult); |
|
2694 |
%} |
|
2695 |
||
2696 |
enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ |
|
2697 |
MacroAssembler _masm(&cbuf); |
|
2698 |
Register Rsrc1 = reg_to_register_object($src1$$reg); |
|
2699 |
Register Rsrc2 = reg_to_register_object($src2$$reg); |
|
2700 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2701 |
||
2702 |
__ sra( Rsrc1, 0, Rsrc1 ); |
|
2703 |
__ sra( Rsrc2, 0, Rsrc2 ); |
|
2704 |
__ mulx( Rsrc1, Rsrc2, Rdst ); |
|
2705 |
__ srlx( Rdst, 32, Rdst ); |
|
2706 |
%} |
|
2707 |
||
2708 |
enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ |
|
2709 |
MacroAssembler _masm(&cbuf); |
|
2710 |
Register Rdividend = reg_to_register_object($src1$$reg); |
|
2711 |
Register Rdivisor = reg_to_register_object($src2$$reg); |
|
2712 |
Register Rresult = reg_to_register_object($dst$$reg); |
|
2713 |
Register Rscratch = reg_to_register_object($scratch$$reg); |
|
2714 |
||
2715 |
assert(Rdividend != Rscratch, ""); |
|
2716 |
assert(Rdivisor != Rscratch, ""); |
|
2717 |
||
2718 |
__ sra(Rdividend, 0, Rdividend); |
|
2719 |
__ sra(Rdivisor, 0, Rdivisor); |
|
2720 |
__ sdivx(Rdividend, Rdivisor, Rscratch); |
|
2721 |
__ mulx(Rscratch, Rdivisor, Rscratch); |
|
2722 |
__ sub(Rdividend, Rscratch, Rresult); |
|
2723 |
%} |
|
2724 |
||
2725 |
enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ |
|
2726 |
MacroAssembler _masm(&cbuf); |
|
2727 |
||
2728 |
Register Rdividend = reg_to_register_object($src1$$reg); |
|
2729 |
int divisor = $imm$$constant; |
|
2730 |
Register Rresult = reg_to_register_object($dst$$reg); |
|
2731 |
Register Rscratch = reg_to_register_object($scratch$$reg); |
|
2732 |
||
2733 |
assert(Rdividend != Rscratch, ""); |
|
2734 |
||
2735 |
__ sra(Rdividend, 0, Rdividend); |
|
2736 |
__ sdivx(Rdividend, divisor, Rscratch); |
|
2737 |
__ mulx(Rscratch, divisor, Rscratch); |
|
2738 |
__ sub(Rdividend, Rscratch, Rresult); |
|
2739 |
%} |
|
2740 |
||
2741 |
enc_class fabss (sflt_reg dst, sflt_reg src) %{ |
|
2742 |
MacroAssembler _masm(&cbuf); |
|
2743 |
||
2744 |
FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); |
|
2745 |
FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); |
|
2746 |
||
2747 |
__ fabs(FloatRegisterImpl::S, Fsrc, Fdst); |
|
2748 |
%} |
|
2749 |
||
2750 |
enc_class fabsd (dflt_reg dst, dflt_reg src) %{ |
|
2751 |
MacroAssembler _masm(&cbuf); |
|
2752 |
||
2753 |
FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); |
|
2754 |
FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); |
|
2755 |
||
2756 |
__ fabs(FloatRegisterImpl::D, Fsrc, Fdst); |
|
2757 |
%} |
|
2758 |
||
2759 |
enc_class fnegd (dflt_reg dst, dflt_reg src) %{ |
|
2760 |
MacroAssembler _masm(&cbuf); |
|
2761 |
||
2762 |
FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); |
|
2763 |
FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); |
|
2764 |
||
2765 |
__ fneg(FloatRegisterImpl::D, Fsrc, Fdst); |
|
2766 |
%} |
|
2767 |
||
2768 |
enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ |
|
2769 |
MacroAssembler _masm(&cbuf); |
|
2770 |
||
2771 |
FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); |
|
2772 |
FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); |
|
2773 |
||
2774 |
__ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); |
|
2775 |
%} |
|
2776 |
||
2777 |
enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ |
|
2778 |
MacroAssembler _masm(&cbuf); |
|
2779 |
||
2780 |
FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); |
|
2781 |
FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); |
|
2782 |
||
2783 |
__ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); |
|
2784 |
%} |
|
2785 |
||
2786 |
enc_class fmovs (dflt_reg dst, dflt_reg src) %{ |
|
2787 |
MacroAssembler _masm(&cbuf); |
|
2788 |
||
2789 |
FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); |
|
2790 |
FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); |
|
2791 |
||
2792 |
__ fmov(FloatRegisterImpl::S, Fsrc, Fdst); |
|
2793 |
%} |
|
2794 |
||
2795 |
enc_class fmovd (dflt_reg dst, dflt_reg src) %{ |
|
2796 |
MacroAssembler _masm(&cbuf); |
|
2797 |
||
2798 |
FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); |
|
2799 |
FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); |
|
2800 |
||
2801 |
__ fmov(FloatRegisterImpl::D, Fsrc, Fdst); |
|
2802 |
%} |
|
2803 |
||
2804 |
enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ |
|
2805 |
MacroAssembler _masm(&cbuf); |
|
2806 |
||
2807 |
Register Roop = reg_to_register_object($oop$$reg); |
|
2808 |
Register Rbox = reg_to_register_object($box$$reg); |
|
2809 |
Register Rscratch = reg_to_register_object($scratch$$reg); |
|
2810 |
Register Rmark = reg_to_register_object($scratch2$$reg); |
|
2811 |
||
2812 |
assert(Roop != Rscratch, ""); |
|
2813 |
assert(Roop != Rmark, ""); |
|
2814 |
assert(Rbox != Rscratch, ""); |
|
2815 |
assert(Rbox != Rmark, ""); |
|
2816 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
2817 |
__ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
1 | 2818 |
%} |
2819 |
||
2820 |
enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ |
|
2821 |
MacroAssembler _masm(&cbuf); |
|
2822 |
||
2823 |
Register Roop = reg_to_register_object($oop$$reg); |
|
2824 |
Register Rbox = reg_to_register_object($box$$reg); |
|
2825 |
Register Rscratch = reg_to_register_object($scratch$$reg); |
|
2826 |
Register Rmark = reg_to_register_object($scratch2$$reg); |
|
2827 |
||
2828 |
assert(Roop != Rscratch, ""); |
|
2829 |
assert(Roop != Rmark, ""); |
|
2830 |
assert(Rbox != Rscratch, ""); |
|
2831 |
assert(Rbox != Rmark, ""); |
|
2832 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
2833 |
__ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
1 | 2834 |
%} |
2835 |
||
2836 |
enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ |
|
2837 |
MacroAssembler _masm(&cbuf); |
|
2838 |
Register Rmem = reg_to_register_object($mem$$reg); |
|
2839 |
Register Rold = reg_to_register_object($old$$reg); |
|
2840 |
Register Rnew = reg_to_register_object($new$$reg); |
|
2841 |
||
18097 | 2842 |
__ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
1 | 2843 |
__ cmp( Rold, Rnew ); |
2844 |
%} |
|
2845 |
||
2846 |
enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ |
|
2847 |
Register Rmem = reg_to_register_object($mem$$reg); |
|
2848 |
Register Rold = reg_to_register_object($old$$reg); |
|
2849 |
Register Rnew = reg_to_register_object($new$$reg); |
|
2850 |
||
2851 |
MacroAssembler _masm(&cbuf); |
|
2852 |
__ mov(Rnew, O7); |
|
2853 |
__ casx(Rmem, Rold, O7); |
|
2854 |
__ cmp( Rold, O7 ); |
|
2855 |
%} |
|
2856 |
||
2857 |
// raw int cas, used for compareAndSwap |
|
2858 |
enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ |
|
2859 |
Register Rmem = reg_to_register_object($mem$$reg); |
|
2860 |
Register Rold = reg_to_register_object($old$$reg); |
|
2861 |
Register Rnew = reg_to_register_object($new$$reg); |
|
2862 |
||
2863 |
MacroAssembler _masm(&cbuf); |
|
2864 |
__ mov(Rnew, O7); |
|
2865 |
__ cas(Rmem, Rold, O7); |
|
2866 |
__ cmp( Rold, O7 ); |
|
2867 |
%} |
|
2868 |
||
2869 |
enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ |
|
2870 |
Register Rres = reg_to_register_object($res$$reg); |
|
2871 |
||
2872 |
MacroAssembler _masm(&cbuf); |
|
2873 |
__ mov(1, Rres); |
|
2874 |
__ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); |
|
2875 |
%} |
|
2876 |
||
2877 |
enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ |
|
2878 |
Register Rres = reg_to_register_object($res$$reg); |
|
2879 |
||
2880 |
MacroAssembler _masm(&cbuf); |
|
2881 |
__ mov(1, Rres); |
|
2882 |
__ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); |
|
2883 |
%} |
|
2884 |
||
2885 |
enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ |
|
2886 |
MacroAssembler _masm(&cbuf); |
|
2887 |
Register Rdst = reg_to_register_object($dst$$reg); |
|
2888 |
FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) |
|
2889 |
: reg_to_DoubleFloatRegister_object($src1$$reg); |
|
2890 |
FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) |
|
2891 |
: reg_to_DoubleFloatRegister_object($src2$$reg); |
|
2892 |
||
2893 |
// Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) |
|
2894 |
__ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); |
|
2895 |
%} |
|
2896 |
||
2897 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2898 |
enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
1 | 2899 |
Label Ldone, Lloop; |
2900 |
MacroAssembler _masm(&cbuf); |
|
2901 |
||
2902 |
Register str1_reg = reg_to_register_object($str1$$reg); |
|
2903 |
Register str2_reg = reg_to_register_object($str2$$reg); |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2904 |
Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2905 |
Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
1 | 2906 |
Register result_reg = reg_to_register_object($result$$reg); |
2907 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2908 |
assert(result_reg != str1_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2909 |
result_reg != str2_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2910 |
result_reg != cnt1_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2911 |
result_reg != cnt2_reg , |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2912 |
"need different registers"); |
1 | 2913 |
|
2914 |
// Compute the minimum of the string lengths(str1_reg) and the |
|
2915 |
// difference of the string lengths (stack) |
|
2916 |
||
2917 |
// See if the lengths are different, and calculate min in str1_reg. |
|
2918 |
// Stash diff in O7 in case we need it for a tie-breaker. |
|
2919 |
Label Lskip; |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2920 |
__ subcc(cnt1_reg, cnt2_reg, O7); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2921 |
__ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
1 | 2922 |
__ br(Assembler::greater, true, Assembler::pt, Lskip); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2923 |
// cnt2 is shorter, so use its count: |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2924 |
__ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
1 | 2925 |
__ bind(Lskip); |
2926 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2927 |
// reallocate cnt1_reg, cnt2_reg, result_reg |
1 | 2928 |
// Note: limit_reg holds the string length pre-scaled by 2 |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2929 |
Register limit_reg = cnt1_reg; |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2930 |
Register chr2_reg = cnt2_reg; |
1 | 2931 |
Register chr1_reg = result_reg; |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2932 |
// str{12} are the base pointers |
1 | 2933 |
|
2934 |
// Is the minimum length zero? |
|
2935 |
__ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity |
|
2936 |
__ br(Assembler::equal, true, Assembler::pn, Ldone); |
|
2937 |
__ delayed()->mov(O7, result_reg); // result is difference in lengths |
|
2938 |
||
2939 |
// Load first characters |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2940 |
__ lduh(str1_reg, 0, chr1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2941 |
__ lduh(str2_reg, 0, chr2_reg); |
1 | 2942 |
|
2943 |
// Compare first characters |
|
2944 |
__ subcc(chr1_reg, chr2_reg, chr1_reg); |
|
2945 |
__ br(Assembler::notZero, false, Assembler::pt, Ldone); |
|
2946 |
assert(chr1_reg == result_reg, "result must be pre-placed"); |
|
2947 |
__ delayed()->nop(); |
|
2948 |
||
2949 |
{ |
|
2950 |
// Check after comparing first character to see if strings are equivalent |
|
2951 |
Label LSkip2; |
|
2952 |
// Check if the strings start at same location |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
2953 |
__ cmp(str1_reg, str2_reg); |
1 | 2954 |
__ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2955 |
__ delayed()->nop(); |
|
2956 |
||
2957 |
// Check if the length difference is zero (in O7) |
|
2958 |
__ cmp(G0, O7); |
|
2959 |
__ br(Assembler::equal, true, Assembler::pn, Ldone); |
|
2960 |
__ delayed()->mov(G0, result_reg); // result is zero |
|
2961 |
||
2962 |
// Strings might not be equal |
|
2963 |
__ bind(LSkip2); |
|
2964 |
} |
|
2965 |
||
21523
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
2966 |
// We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
2967 |
__ signx(limit_reg); |
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
2968 |
|
1 | 2969 |
__ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); |
2970 |
__ br(Assembler::equal, true, Assembler::pn, Ldone); |
|
2971 |
__ delayed()->mov(O7, result_reg); // result is difference in lengths |
|
2972 |
||
3905
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
2973 |
// Shift str1_reg and str2_reg to the end of the arrays, negate limit |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
2974 |
__ add(str1_reg, limit_reg, str1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
2975 |
__ add(str2_reg, limit_reg, str2_reg); |
1 | 2976 |
__ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2977 |
||
2978 |
// Compare the rest of the characters |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
2979 |
__ lduh(str1_reg, limit_reg, chr1_reg); |
1 | 2980 |
__ bind(Lloop); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
2981 |
// __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
2982 |
__ lduh(str2_reg, limit_reg, chr2_reg); |
1 | 2983 |
__ subcc(chr1_reg, chr2_reg, chr1_reg); |
2984 |
__ br(Assembler::notZero, false, Assembler::pt, Ldone); |
|
2985 |
assert(chr1_reg == result_reg, "result must be pre-placed"); |
|
2986 |
__ delayed()->inccc(limit_reg, sizeof(jchar)); |
|
2987 |
// annul LDUH if branch is not taken to prevent access past end of string |
|
2988 |
__ br(Assembler::notZero, true, Assembler::pt, Lloop); |
|
3905
7d725029ac85
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parents:
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diff
changeset
|
2989 |
__ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
1 | 2990 |
|
2991 |
// If strings are equal up to min length, return the length difference. |
|
2992 |
__ mov(O7, result_reg); |
|
2993 |
||
2994 |
// Otherwise, return the difference between the first mismatched chars. |
|
2995 |
__ bind(Ldone); |
|
2996 |
%} |
|
2997 |
||
3905
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diff
changeset
|
2998 |
enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
7d725029ac85
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parents:
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diff
changeset
|
2999 |
Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
2348 | 3000 |
MacroAssembler _masm(&cbuf); |
3001 |
||
3002 |
Register str1_reg = reg_to_register_object($str1$$reg); |
|
3003 |
Register str2_reg = reg_to_register_object($str2$$reg); |
|
3905
7d725029ac85
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diff
changeset
|
3004 |
Register cnt_reg = reg_to_register_object($cnt$$reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
3005 |
Register tmp1_reg = O7; |
2348 | 3006 |
Register result_reg = reg_to_register_object($result$$reg); |
3007 |
||
3905
7d725029ac85
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parents:
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diff
changeset
|
3008 |
assert(result_reg != str1_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
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diff
changeset
|
3009 |
result_reg != str2_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3010 |
result_reg != cnt_reg && |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3011 |
result_reg != tmp1_reg , |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3012 |
"need different registers"); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3013 |
|
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
3798
diff
changeset
|
3014 |
__ cmp(str1_reg, str2_reg); //same char[] ? |
2348 | 3015 |
__ brx(Assembler::equal, true, Assembler::pn, Ldone); |
3016 |
__ delayed()->add(G0, 1, result_reg); |
|
3017 |
||
10252 | 3018 |
__ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
3905
7d725029ac85
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parents:
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diff
changeset
|
3019 |
__ delayed()->add(G0, 1, result_reg); // count == 0 |
7d725029ac85
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parents:
3798
diff
changeset
|
3020 |
|
2348 | 3021 |
//rename registers |
3905
7d725029ac85
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parents:
3798
diff
changeset
|
3022 |
Register limit_reg = cnt_reg; |
2348 | 3023 |
Register chr1_reg = result_reg; |
3905
7d725029ac85
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kvn
parents:
3798
diff
changeset
|
3024 |
Register chr2_reg = tmp1_reg; |
2348 | 3025 |
|
21523
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
3026 |
// We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
3027 |
__ signx(limit_reg); |
49c80d56e5e3
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
21189
diff
changeset
|
3028 |
|
2348 | 3029 |
//check for alignment and position the pointers to the ends |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3030 |
__ or3(str1_reg, str2_reg, chr1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3031 |
__ andcc(chr1_reg, 0x3, chr1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3032 |
// notZero means at least one not 4-byte aligned. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3033 |
// We could optimize the case when both arrays are not aligned |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3034 |
// but it is not frequent case and it requires additional checks. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3035 |
__ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3036 |
__ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3037 |
|
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3038 |
// Compare char[] arrays aligned to 4 bytes. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3039 |
__ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3040 |
chr1_reg, chr2_reg, Ldone); |
10252 | 3041 |
__ ba(Ldone); |
2348 | 3042 |
__ delayed()->add(G0, 1, result_reg); |
3043 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3044 |
// char by char compare |
2348 | 3045 |
__ bind(Lchar); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3046 |
__ add(str1_reg, limit_reg, str1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3047 |
__ add(str2_reg, limit_reg, str2_reg); |
2348 | 3048 |
__ neg(limit_reg); //negate count |
3049 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3050 |
__ lduh(str1_reg, limit_reg, chr1_reg); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3051 |
// Lchar_loop |
2348 | 3052 |
__ bind(Lchar_loop); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3053 |
__ lduh(str2_reg, limit_reg, chr2_reg); |
2348 | 3054 |
__ cmp(chr1_reg, chr2_reg); |
3055 |
__ br(Assembler::notEqual, true, Assembler::pt, Ldone); |
|
3056 |
__ delayed()->mov(G0, result_reg); //not equal |
|
3057 |
__ inccc(limit_reg, sizeof(jchar)); |
|
3058 |
// annul LDUH if branch is not taken to prevent access past end of string |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3059 |
__ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3060 |
__ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
2348 | 3061 |
|
3062 |
__ add(G0, 1, result_reg); //equal |
|
3063 |
||
3064 |
__ bind(Ldone); |
|
3065 |
%} |
|
3066 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3067 |
enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
2348 | 3068 |
Label Lvector, Ldone, Lloop; |
3069 |
MacroAssembler _masm(&cbuf); |
|
3070 |
||
3071 |
Register ary1_reg = reg_to_register_object($ary1$$reg); |
|
3072 |
Register ary2_reg = reg_to_register_object($ary2$$reg); |
|
3073 |
Register tmp1_reg = reg_to_register_object($tmp1$$reg); |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3074 |
Register tmp2_reg = O7; |
2348 | 3075 |
Register result_reg = reg_to_register_object($result$$reg); |
3076 |
||
3077 |
int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
3078 |
int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
3079 |
||
3080 |
// return true if the same array |
|
3081 |
__ cmp(ary1_reg, ary2_reg); |
|
4019 | 3082 |
__ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2348 | 3083 |
__ delayed()->add(G0, 1, result_reg); // equal |
3084 |
||
3085 |
__ br_null(ary1_reg, true, Assembler::pn, Ldone); |
|
3086 |
__ delayed()->mov(G0, result_reg); // not equal |
|
3087 |
||
3088 |
__ br_null(ary2_reg, true, Assembler::pn, Ldone); |
|
3089 |
__ delayed()->mov(G0, result_reg); // not equal |
|
3090 |
||
3091 |
//load the lengths of arrays |
|
2571 | 3092 |
__ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3093 |
__ ld(Address(ary2_reg, length_offset), tmp2_reg); |
|
2348 | 3094 |
|
3095 |
// return false if the two arrays are not equal length |
|
3096 |
__ cmp(tmp1_reg, tmp2_reg); |
|
3097 |
__ br(Assembler::notEqual, true, Assembler::pn, Ldone); |
|
3098 |
__ delayed()->mov(G0, result_reg); // not equal |
|
3099 |
||
10252 | 3100 |
__ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
2348 | 3101 |
__ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3102 |
||
3103 |
// load array addresses |
|
3104 |
__ add(ary1_reg, base_offset, ary1_reg); |
|
3105 |
__ add(ary2_reg, base_offset, ary2_reg); |
|
3106 |
||
3107 |
// renaming registers |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3108 |
Register chr1_reg = result_reg; // for characters in ary1 |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3109 |
Register chr2_reg = tmp2_reg; // for characters in ary2 |
2348 | 3110 |
Register limit_reg = tmp1_reg; // length |
3111 |
||
3112 |
// set byte count |
|
3113 |
__ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3114 |
|
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3115 |
// Compare char[] arrays aligned to 4 bytes. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3116 |
__ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
3117 |
chr1_reg, chr2_reg, Ldone); |
2348 | 3118 |
__ add(G0, 1, result_reg); // equals |
3119 |
||
3120 |
__ bind(Ldone); |
|
3121 |
%} |
|
3122 |
||
1 | 3123 |
enc_class enc_rethrow() %{ |
6418 | 3124 |
cbuf.set_insts_mark(); |
1 | 3125 |
Register temp_reg = G3; |
2571 | 3126 |
AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
1 | 3127 |
assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3128 |
MacroAssembler _masm(&cbuf); |
|
3129 |
#ifdef ASSERT |
|
3130 |
__ save_frame(0); |
|
2571 | 3131 |
AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3132 |
__ sethi(last_rethrow_addrlit, L1); |
|
3133 |
Address addr(L1, last_rethrow_addrlit.low10()); |
|
18097 | 3134 |
__ rdpc(L2); |
1 | 3135 |
__ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
2571 | 3136 |
__ st_ptr(L2, addr); |
1 | 3137 |
__ restore(); |
3138 |
#endif |
|
2571 | 3139 |
__ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
1 | 3140 |
__ delayed()->nop(); |
3141 |
%} |
|
3142 |
||
3143 |
enc_class emit_mem_nop() %{ |
|
3144 |
// Generates the instruction LDUXA [o6,g0],#0x82,g0 |
|
6418 | 3145 |
cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
1 | 3146 |
%} |
3147 |
||
3148 |
enc_class emit_fadd_nop() %{ |
|
3149 |
// Generates the instruction FMOVS f31,f31 |
|
6418 | 3150 |
cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
1 | 3151 |
%} |
3152 |
||
3153 |
enc_class emit_br_nop() %{ |
|
3154 |
// Generates the instruction BPN,PN . |
|
6418 | 3155 |
cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
1 | 3156 |
%} |
3157 |
||
3158 |
enc_class enc_membar_acquire %{ |
|
3159 |
MacroAssembler _masm(&cbuf); |
|
3160 |
__ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); |
|
3161 |
%} |
|
3162 |
||
3163 |
enc_class enc_membar_release %{ |
|
3164 |
MacroAssembler _masm(&cbuf); |
|
3165 |
__ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); |
|
3166 |
%} |
|
3167 |
||
3168 |
enc_class enc_membar_volatile %{ |
|
3169 |
MacroAssembler _masm(&cbuf); |
|
3170 |
__ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); |
|
3171 |
%} |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3172 |
|
1 | 3173 |
%} |
3174 |
||
3175 |
//----------FRAME-------------------------------------------------------------- |
|
3176 |
// Definition of frame structure and management information. |
|
3177 |
// |
|
3178 |
// S T A C K L A Y O U T Allocators stack-slot number |
|
3179 |
// | (to get allocators register number |
|
3180 |
// G Owned by | | v add VMRegImpl::stack0) |
|
3181 |
// r CALLER | | |
|
3182 |
// o | +--------+ pad to even-align allocators stack-slot |
|
3183 |
// w V | pad0 | numbers; owned by CALLER |
|
3184 |
// t -----------+--------+----> Matcher::_in_arg_limit, unaligned |
|
3185 |
// h ^ | in | 5 |
|
3186 |
// | | args | 4 Holes in incoming args owned by SELF |
|
3187 |
// | | | | 3 |
|
3188 |
// | | +--------+ |
|
3189 |
// V | | old out| Empty on Intel, window on Sparc |
|
3190 |
// | old |preserve| Must be even aligned. |
|
3191 |
// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned |
|
3192 |
// | | in | 3 area for Intel ret address |
|
3193 |
// Owned by |preserve| Empty on Sparc. |
|
3194 |
// SELF +--------+ |
|
3195 |
// | | pad2 | 2 pad to align old SP |
|
3196 |
// | +--------+ 1 |
|
3197 |
// | | locks | 0 |
|
3198 |
// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned |
|
3199 |
// | | pad1 | 11 pad to align new SP |
|
3200 |
// | +--------+ |
|
3201 |
// | | | 10 |
|
3202 |
// | | spills | 9 spills |
|
3203 |
// V | | 8 (pad0 slot for callee) |
|
3204 |
// -----------+--------+----> Matcher::_out_arg_limit, unaligned |
|
3205 |
// ^ | out | 7 |
|
3206 |
// | | args | 6 Holes in outgoing args owned by CALLEE |
|
3207 |
// Owned by +--------+ |
|
3208 |
// CALLEE | new out| 6 Empty on Intel, window on Sparc |
|
3209 |
// | new |preserve| Must be even-aligned. |
|
3210 |
// | SP-+--------+----> Matcher::_new_SP, even aligned |
|
3211 |
// | | | |
|
3212 |
// |
|
3213 |
// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is |
|
3214 |
// known from SELF's arguments and the Java calling convention. |
|
3215 |
// Region 6-7 is determined per call site. |
|
3216 |
// Note 2: If the calling convention leaves holes in the incoming argument |
|
3217 |
// area, those holes are owned by SELF. Holes in the outgoing area |
|
3218 |
// are owned by the CALLEE. Holes should not be nessecary in the |
|
3219 |
// incoming area, as the Java calling convention is completely under |
|
3220 |
// the control of the AD file. Doubles can be sorted and packed to |
|
26804
4b23f22faae6
8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents:
25933
diff
changeset
|
3221 |
// avoid holes. Holes in the outgoing arguments may be necessary for |
1 | 3222 |
// varargs C calling conventions. |
3223 |
// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is |
|
3224 |
// even aligned with pad0 as needed. |
|
3225 |
// Region 6 is even aligned. Region 6-7 is NOT even aligned; |
|
3226 |
// region 6-11 is even aligned; it may be padded out more so that |
|
3227 |
// the region from SP to FP meets the minimum stack alignment. |
|
3228 |
||
3229 |
frame %{ |
|
3230 |
// What direction does stack grow in (assumed to be same for native & Java) |
|
3231 |
stack_direction(TOWARDS_LOW); |
|
3232 |
||
3233 |
// These two registers define part of the calling convention |
|
3234 |
// between compiled code and the interpreter. |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
3235 |
inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
1 | 3236 |
interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
3237 |
||
3238 |
// Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] |
|
3239 |
cisc_spilling_operand_name(indOffset); |
|
3240 |
||
3241 |
// Number of stack slots consumed by a Monitor enter |
|
3242 |
#ifdef _LP64 |
|
3243 |
sync_stack_slots(2); |
|
3244 |
#else |
|
3245 |
sync_stack_slots(1); |
|
3246 |
#endif |
|
3247 |
||
3248 |
// Compiled code's Frame Pointer |
|
3249 |
frame_pointer(R_SP); |
|
3250 |
||
3251 |
// Stack alignment requirement |
|
3252 |
stack_alignment(StackAlignmentInBytes); |
|
3253 |
// LP64: Alignment size in bytes (128-bit -> 16 bytes) |
|
3254 |
// !LP64: Alignment size in bytes (64-bit -> 8 bytes) |
|
3255 |
||
3256 |
// Number of stack slots between incoming argument block and the start of |
|
3257 |
// a new frame. The PROLOG must add this many slots to the stack. The |
|
3258 |
// EPILOG must remove this many slots. |
|
3259 |
in_preserve_stack_slots(0); |
|
3260 |
||
3261 |
// Number of outgoing stack slots killed above the out_preserve_stack_slots |
|
3262 |
// for calls to C. Supports the var-args backing area for register parms. |
|
3263 |
// ADLC doesn't support parsing expressions, so I folded the math by hand. |
|
3264 |
#ifdef _LP64 |
|
3265 |
// (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word |
|
3266 |
varargs_C_out_slots_killed(12); |
|
3267 |
#else |
|
3268 |
// (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word |
|
3269 |
varargs_C_out_slots_killed( 7); |
|
3270 |
#endif |
|
3271 |
||
3272 |
// The after-PROLOG location of the return address. Location of |
|
3273 |
// return address specifies a type (REG or STACK) and a number |
|
3274 |
// representing the register number (i.e. - use a register name) or |
|
3275 |
// stack slot. |
|
3276 |
return_addr(REG R_I7); // Ret Addr is in register I7 |
|
3277 |
||
3278 |
// Body of function which returns an OptoRegs array locating |
|
3279 |
// arguments either in registers or in stack slots for calling |
|
3280 |
// java |
|
3281 |
calling_convention %{ |
|
3282 |
(void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); |
|
3283 |
||
3284 |
%} |
|
3285 |
||
3286 |
// Body of function which returns an OptoRegs array locating |
|
26804
4b23f22faae6
8050022: linux-sparcv9: assert(SharedSkipVerify || obj->is_oop()) failed: sanity check
morris
parents:
25933
diff
changeset
|
3287 |
// arguments either in registers or in stack slots for calling |
1 | 3288 |
// C. |
3289 |
c_calling_convention %{ |
|
3290 |
// This is obviously always outgoing |
|
22832
03720a5b7595
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
19319
diff
changeset
|
3291 |
(void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
1 | 3292 |
%} |
3293 |
||
3294 |
// Location of native (C/C++) and interpreter return values. This is specified to |
|
3295 |
// be the same as Java. In the 32-bit VM, long values are actually returned from |
|
3296 |
// native calls in O0:O1 and returned to the interpreter in I0:I1. The copying |
|
3297 |
// to and from the register pairs is done by the appropriate call and epilog |
|
3298 |
// opcodes. This simplifies the register allocator. |
|
3299 |
c_return_value %{ |
|
3300 |
assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); |
|
3301 |
#ifdef _LP64 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3302 |
static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3303 |
static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3304 |
static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3305 |
static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
1 | 3306 |
#else // !_LP64 |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3307 |
static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3308 |
static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3309 |
static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3310 |
static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
1 | 3311 |
#endif |
3312 |
return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], |
|
3313 |
(is_outgoing?lo_out:lo_in)[ideal_reg] ); |
|
3314 |
%} |
|
3315 |
||
3316 |
// Location of compiled Java return values. Same as C |
|
3317 |
return_value %{ |
|
3318 |
assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); |
|
3319 |
#ifdef _LP64 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3320 |
static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3321 |
static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3322 |
static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3323 |
static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
1 | 3324 |
#else // !_LP64 |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3325 |
static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3326 |
static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3327 |
static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3328 |
static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
1 | 3329 |
#endif |
3330 |
return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], |
|
3331 |
(is_outgoing?lo_out:lo_in)[ideal_reg] ); |
|
3332 |
%} |
|
3333 |
||
3334 |
%} |
|
3335 |
||
3336 |
||
3337 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
3338 |
//----------Operand Attributes------------------------------------------------- |
|
3339 |
op_attrib op_cost(1); // Required cost attribute |
|
3340 |
||
3341 |
//----------Instruction Attributes--------------------------------------------- |
|
3342 |
ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute |
|
10255 | 3343 |
ins_attrib ins_size(32); // Required size attribute (in bits) |
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3344 |
|
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3345 |
// avoid_back_to_back attribute is an expression that must return |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3346 |
// one of the following values defined in MachNode: |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3347 |
// AVOID_NONE - instruction can be placed anywhere |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3348 |
// AVOID_BEFORE - instruction cannot be placed after an |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3349 |
// instruction with MachNode::AVOID_AFTER |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3350 |
// AVOID_AFTER - the next instruction cannot be the one |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3351 |
// with MachNode::AVOID_BEFORE |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3352 |
// AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3353 |
// the same time |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3354 |
ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); |
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
3355 |
|
10255 | 3356 |
ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3357 |
// non-matching short branch variant of some |
|
1 | 3358 |
// long branch? |
3359 |
||
3360 |
//----------OPERANDS----------------------------------------------------------- |
|
3361 |
// Operand definitions must precede instruction definitions for correct parsing |
|
3362 |
// in the ADLC because operands constitute user defined types which are used in |
|
3363 |
// instruction definitions. |
|
3364 |
||
3365 |
//----------Simple Operands---------------------------------------------------- |
|
3366 |
// Immediate Operands |
|
3367 |
// Integer Immediate: 32-bit |
|
3368 |
operand immI() %{ |
|
3369 |
match(ConI); |
|
3370 |
||
3371 |
op_cost(0); |
|
3372 |
// formats are generated automatically for constants and base registers |
|
3373 |
format %{ %} |
|
3374 |
interface(CONST_INTER); |
|
3375 |
%} |
|
3376 |
||
3177 | 3377 |
// Integer Immediate: 8-bit |
3378 |
operand immI8() %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
3379 |
predicate(Assembler::is_simm8(n->get_int())); |
3177 | 3380 |
match(ConI); |
3381 |
op_cost(0); |
|
3382 |
format %{ %} |
|
3383 |
interface(CONST_INTER); |
|
3384 |
%} |
|
3385 |
||
1 | 3386 |
// Integer Immediate: 13-bit |
3387 |
operand immI13() %{ |
|
3388 |
predicate(Assembler::is_simm13(n->get_int())); |
|
3389 |
match(ConI); |
|
3390 |
op_cost(0); |
|
3391 |
||
3392 |
format %{ %} |
|
3393 |
interface(CONST_INTER); |
|
3394 |
%} |
|
3395 |
||
2872 | 3396 |
// Integer Immediate: 13-bit minus 7 |
3397 |
operand immI13m7() %{ |
|
3398 |
predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); |
|
3399 |
match(ConI); |
|
3400 |
op_cost(0); |
|
3401 |
||
3402 |
format %{ %} |
|
3403 |
interface(CONST_INTER); |
|
3404 |
%} |
|
3405 |
||
3177 | 3406 |
// Integer Immediate: 16-bit |
3407 |
operand immI16() %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
3408 |
predicate(Assembler::is_simm16(n->get_int())); |
3177 | 3409 |
match(ConI); |
3410 |
op_cost(0); |
|
3411 |
format %{ %} |
|
3412 |
interface(CONST_INTER); |
|
3413 |
%} |
|
3414 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3415 |
// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3416 |
operand immU12() %{ |
1 | 3417 |
predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
3418 |
match(ConI); |
|
3419 |
op_cost(0); |
|
3420 |
||
3421 |
format %{ %} |
|
3422 |
interface(CONST_INTER); |
|
3423 |
%} |
|
3424 |
||
3425 |
// Integer Immediate: 6-bit |
|
3426 |
operand immU6() %{ |
|
3427 |
predicate(n->get_int() >= 0 && n->get_int() <= 63); |
|
3428 |
match(ConI); |
|
3429 |
op_cost(0); |
|
3430 |
format %{ %} |
|
3431 |
interface(CONST_INTER); |
|
3432 |
%} |
|
3433 |
||
3434 |
// Integer Immediate: 11-bit |
|
3435 |
operand immI11() %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
3436 |
predicate(Assembler::is_simm11(n->get_int())); |
1 | 3437 |
match(ConI); |
3438 |
op_cost(0); |
|
3439 |
format %{ %} |
|
3440 |
interface(CONST_INTER); |
|
3441 |
%} |
|
3442 |
||
10264 | 3443 |
// Integer Immediate: 5-bit |
3444 |
operand immI5() %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
3445 |
predicate(Assembler::is_simm5(n->get_int())); |
10264 | 3446 |
match(ConI); |
3447 |
op_cost(0); |
|
3448 |
format %{ %} |
|
3449 |
interface(CONST_INTER); |
|
3450 |
%} |
|
3451 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3452 |
// Int Immediate non-negative |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3453 |
operand immU31() |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3454 |
%{ |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3455 |
predicate(n->get_int() >= 0); |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3456 |
match(ConI); |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3457 |
|
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3458 |
op_cost(0); |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3459 |
format %{ %} |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3460 |
interface(CONST_INTER); |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3461 |
%} |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
3462 |
|
1 | 3463 |
// Integer Immediate: 0-bit |
3464 |
operand immI0() %{ |
|
3465 |
predicate(n->get_int() == 0); |
|
3466 |
match(ConI); |
|
3467 |
op_cost(0); |
|
3468 |
||
3469 |
format %{ %} |
|
3470 |
interface(CONST_INTER); |
|
3471 |
%} |
|
3472 |
||
3473 |
// Integer Immediate: the value 10 |
|
3474 |
operand immI10() %{ |
|
3475 |
predicate(n->get_int() == 10); |
|
3476 |
match(ConI); |
|
3477 |
op_cost(0); |
|
3478 |
||
3479 |
format %{ %} |
|
3480 |
interface(CONST_INTER); |
|
3481 |
%} |
|
3482 |
||
3483 |
// Integer Immediate: the values 0-31 |
|
3484 |
operand immU5() %{ |
|
3485 |
predicate(n->get_int() >= 0 && n->get_int() <= 31); |
|
3486 |
match(ConI); |
|
3487 |
op_cost(0); |
|
3488 |
||
3489 |
format %{ %} |
|
3490 |
interface(CONST_INTER); |
|
3491 |
%} |
|
3492 |
||
3493 |
// Integer Immediate: the values 1-31 |
|
3494 |
operand immI_1_31() %{ |
|
3495 |
predicate(n->get_int() >= 1 && n->get_int() <= 31); |
|
3496 |
match(ConI); |
|
3497 |
op_cost(0); |
|
3498 |
||
3499 |
format %{ %} |
|
3500 |
interface(CONST_INTER); |
|
3501 |
%} |
|
3502 |
||
3503 |
// Integer Immediate: the values 32-63 |
|
3504 |
operand immI_32_63() %{ |
|
3505 |
predicate(n->get_int() >= 32 && n->get_int() <= 63); |
|
3506 |
match(ConI); |
|
3507 |
op_cost(0); |
|
3508 |
||
3509 |
format %{ %} |
|
3510 |
interface(CONST_INTER); |
|
3511 |
%} |
|
3512 |
||
2872 | 3513 |
// Immediates for special shifts (sign extend) |
3514 |
||
3515 |
// Integer Immediate: the value 16 |
|
3516 |
operand immI_16() %{ |
|
3517 |
predicate(n->get_int() == 16); |
|
3518 |
match(ConI); |
|
3519 |
op_cost(0); |
|
3520 |
||
3521 |
format %{ %} |
|
3522 |
interface(CONST_INTER); |
|
3523 |
%} |
|
3524 |
||
3525 |
// Integer Immediate: the value 24 |
|
3526 |
operand immI_24() %{ |
|
3527 |
predicate(n->get_int() == 24); |
|
3528 |
match(ConI); |
|
3529 |
op_cost(0); |
|
3530 |
||
3531 |
format %{ %} |
|
3532 |
interface(CONST_INTER); |
|
3533 |
%} |
|
3534 |
||
1 | 3535 |
// Integer Immediate: the value 255 |
3536 |
operand immI_255() %{ |
|
3537 |
predicate( n->get_int() == 255 ); |
|
3538 |
match(ConI); |
|
3539 |
op_cost(0); |
|
3540 |
||
3541 |
format %{ %} |
|
3542 |
interface(CONST_INTER); |
|
3543 |
%} |
|
3544 |
||
2872 | 3545 |
// Integer Immediate: the value 65535 |
3546 |
operand immI_65535() %{ |
|
3547 |
predicate(n->get_int() == 65535); |
|
3548 |
match(ConI); |
|
3549 |
op_cost(0); |
|
3550 |
||
3551 |
format %{ %} |
|
3552 |
interface(CONST_INTER); |
|
3553 |
%} |
|
3554 |
||
1 | 3555 |
// Long Immediate: the value FF |
3556 |
operand immL_FF() %{ |
|
3557 |
predicate( n->get_long() == 0xFFL ); |
|
3558 |
match(ConL); |
|
3559 |
op_cost(0); |
|
3560 |
||
3561 |
format %{ %} |
|
3562 |
interface(CONST_INTER); |
|
3563 |
%} |
|
3564 |
||
3565 |
// Long Immediate: the value FFFF |
|
3566 |
operand immL_FFFF() %{ |
|
3567 |
predicate( n->get_long() == 0xFFFFL ); |
|
3568 |
match(ConL); |
|
3569 |
op_cost(0); |
|
3570 |
||
3571 |
format %{ %} |
|
3572 |
interface(CONST_INTER); |
|
3573 |
%} |
|
3574 |
||
3575 |
// Pointer Immediate: 32 or 64-bit |
|
3576 |
operand immP() %{ |
|
3577 |
match(ConP); |
|
3578 |
||
3579 |
op_cost(5); |
|
3580 |
// formats are generated automatically for constants and base registers |
|
3581 |
format %{ %} |
|
3582 |
interface(CONST_INTER); |
|
3583 |
%} |
|
3584 |
||
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3585 |
#ifdef _LP64 |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3586 |
// Pointer Immediate: 64-bit |
7433 | 3587 |
operand immP_set() %{ |
7704 | 3588 |
predicate(!VM_Version::is_niagara_plus()); |
7433 | 3589 |
match(ConP); |
3590 |
||
3591 |
op_cost(5); |
|
3592 |
// formats are generated automatically for constants and base registers |
|
3593 |
format %{ %} |
|
3594 |
interface(CONST_INTER); |
|
3595 |
%} |
|
3596 |
||
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3597 |
// Pointer Immediate: 64-bit |
7433 | 3598 |
// From Niagara2 processors on a load should be better than materializing. |
3599 |
operand immP_load() %{ |
|
7704 | 3600 |
predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
7433 | 3601 |
match(ConP); |
3602 |
||
3603 |
op_cost(5); |
|
3604 |
// formats are generated automatically for constants and base registers |
|
3605 |
format %{ %} |
|
3606 |
interface(CONST_INTER); |
|
3607 |
%} |
|
3608 |
||
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3609 |
// Pointer Immediate: 64-bit |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3610 |
operand immP_no_oop_cheap() %{ |
7704 | 3611 |
predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3612 |
match(ConP); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3613 |
|
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3614 |
op_cost(5); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3615 |
// formats are generated automatically for constants and base registers |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3616 |
format %{ %} |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3617 |
interface(CONST_INTER); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3618 |
%} |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3619 |
#endif |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
3620 |
|
1 | 3621 |
operand immP13() %{ |
3622 |
predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); |
|
3623 |
match(ConP); |
|
3624 |
op_cost(0); |
|
3625 |
||
3626 |
format %{ %} |
|
3627 |
interface(CONST_INTER); |
|
3628 |
%} |
|
3629 |
||
3630 |
operand immP0() %{ |
|
3631 |
predicate(n->get_ptr() == 0); |
|
3632 |
match(ConP); |
|
3633 |
op_cost(0); |
|
3634 |
||
3635 |
format %{ %} |
|
3636 |
interface(CONST_INTER); |
|
3637 |
%} |
|
3638 |
||
3639 |
operand immP_poll() %{ |
|
3640 |
predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); |
|
3641 |
match(ConP); |
|
3642 |
||
3643 |
// formats are generated automatically for constants and base registers |
|
3644 |
format %{ %} |
|
3645 |
interface(CONST_INTER); |
|
3646 |
%} |
|
3647 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3648 |
// Pointer Immediate |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3649 |
operand immN() |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3650 |
%{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3651 |
match(ConN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3652 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3653 |
op_cost(10); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3654 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3655 |
interface(CONST_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3656 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3657 |
|
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3658 |
operand immNKlass() |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3659 |
%{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3660 |
match(ConNKlass); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3661 |
|
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3662 |
op_cost(10); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3663 |
format %{ %} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3664 |
interface(CONST_INTER); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3665 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
3666 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3667 |
// NULL Pointer Immediate |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3668 |
operand immN0() |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3669 |
%{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3670 |
predicate(n->get_narrowcon() == 0); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3671 |
match(ConN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3672 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3673 |
op_cost(0); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3674 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3675 |
interface(CONST_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3676 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3677 |
|
1 | 3678 |
operand immL() %{ |
3679 |
match(ConL); |
|
3680 |
op_cost(40); |
|
3681 |
// formats are generated automatically for constants and base registers |
|
3682 |
format %{ %} |
|
3683 |
interface(CONST_INTER); |
|
3684 |
%} |
|
3685 |
||
3686 |
operand immL0() %{ |
|
3687 |
predicate(n->get_long() == 0L); |
|
3688 |
match(ConL); |
|
3689 |
op_cost(0); |
|
3690 |
// formats are generated automatically for constants and base registers |
|
3691 |
format %{ %} |
|
3692 |
interface(CONST_INTER); |
|
3693 |
%} |
|
3694 |
||
10264 | 3695 |
// Integer Immediate: 5-bit |
3696 |
operand immL5() %{ |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
3697 |
predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
10264 | 3698 |
match(ConL); |
3699 |
op_cost(0); |
|
3700 |
format %{ %} |
|
3701 |
interface(CONST_INTER); |
|
3702 |
%} |
|
3703 |
||
1 | 3704 |
// Long Immediate: 13-bit |
3705 |
operand immL13() %{ |
|
3706 |
predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); |
|
3707 |
match(ConL); |
|
3708 |
op_cost(0); |
|
3709 |
||
3710 |
format %{ %} |
|
3711 |
interface(CONST_INTER); |
|
3712 |
%} |
|
3713 |
||
2872 | 3714 |
// Long Immediate: 13-bit minus 7 |
3715 |
operand immL13m7() %{ |
|
3716 |
predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); |
|
3717 |
match(ConL); |
|
3718 |
op_cost(0); |
|
3719 |
||
3720 |
format %{ %} |
|
3721 |
interface(CONST_INTER); |
|
3722 |
%} |
|
3723 |
||
1 | 3724 |
// Long Immediate: low 32-bit mask |
3725 |
operand immL_32bits() %{ |
|
3726 |
predicate(n->get_long() == 0xFFFFFFFFL); |
|
3727 |
match(ConL); |
|
3728 |
op_cost(0); |
|
3729 |
||
3730 |
format %{ %} |
|
3731 |
interface(CONST_INTER); |
|
3732 |
%} |
|
3733 |
||
7433 | 3734 |
// Long Immediate: cheap (materialize in <= 3 instructions) |
3735 |
operand immL_cheap() %{ |
|
7704 | 3736 |
predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
7433 | 3737 |
match(ConL); |
3738 |
op_cost(0); |
|
3739 |
||
3740 |
format %{ %} |
|
3741 |
interface(CONST_INTER); |
|
3742 |
%} |
|
3743 |
||
3744 |
// Long Immediate: expensive (materialize in > 3 instructions) |
|
3745 |
operand immL_expensive() %{ |
|
7704 | 3746 |
predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
7433 | 3747 |
match(ConL); |
3748 |
op_cost(0); |
|
3749 |
||
3750 |
format %{ %} |
|
3751 |
interface(CONST_INTER); |
|
3752 |
%} |
|
3753 |
||
1 | 3754 |
// Double Immediate |
3755 |
operand immD() %{ |
|
3756 |
match(ConD); |
|
3757 |
||
3758 |
op_cost(40); |
|
3759 |
format %{ %} |
|
3760 |
interface(CONST_INTER); |
|
3761 |
%} |
|
3762 |
||
3763 |
operand immD0() %{ |
|
3764 |
#ifdef _LP64 |
|
3765 |
// on 64-bit architectures this comparision is faster |
|
3766 |
predicate(jlong_cast(n->getd()) == 0); |
|
3767 |
#else |
|
3768 |
predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); |
|
3769 |
#endif |
|
3770 |
match(ConD); |
|
3771 |
||
3772 |
op_cost(0); |
|
3773 |
format %{ %} |
|
3774 |
interface(CONST_INTER); |
|
3775 |
%} |
|
3776 |
||
3777 |
// Float Immediate |
|
3778 |
operand immF() %{ |
|
3779 |
match(ConF); |
|
3780 |
||
3781 |
op_cost(20); |
|
3782 |
format %{ %} |
|
3783 |
interface(CONST_INTER); |
|
3784 |
%} |
|
3785 |
||
3786 |
// Float Immediate: 0 |
|
3787 |
operand immF0() %{ |
|
3788 |
predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); |
|
3789 |
match(ConF); |
|
3790 |
||
3791 |
op_cost(0); |
|
3792 |
format %{ %} |
|
3793 |
interface(CONST_INTER); |
|
3794 |
%} |
|
3795 |
||
3796 |
// Integer Register Operands |
|
3797 |
// Integer Register |
|
3798 |
operand iRegI() %{ |
|
3799 |
constraint(ALLOC_IN_RC(int_reg)); |
|
3800 |
match(RegI); |
|
3801 |
||
3802 |
match(notemp_iRegI); |
|
3803 |
match(g1RegI); |
|
3804 |
match(o0RegI); |
|
3805 |
match(iRegIsafe); |
|
3806 |
||
3807 |
format %{ %} |
|
3808 |
interface(REG_INTER); |
|
3809 |
%} |
|
3810 |
||
3811 |
operand notemp_iRegI() %{ |
|
3812 |
constraint(ALLOC_IN_RC(notemp_int_reg)); |
|
3813 |
match(RegI); |
|
3814 |
||
3815 |
match(o0RegI); |
|
3816 |
||
3817 |
format %{ %} |
|
3818 |
interface(REG_INTER); |
|
3819 |
%} |
|
3820 |
||
3821 |
operand o0RegI() %{ |
|
3822 |
constraint(ALLOC_IN_RC(o0_regI)); |
|
3823 |
match(iRegI); |
|
3824 |
||
3825 |
format %{ %} |
|
3826 |
interface(REG_INTER); |
|
3827 |
%} |
|
3828 |
||
3829 |
// Pointer Register |
|
3830 |
operand iRegP() %{ |
|
3831 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
3832 |
match(RegP); |
|
3833 |
||
3834 |
match(lock_ptr_RegP); |
|
3835 |
match(g1RegP); |
|
3836 |
match(g2RegP); |
|
3837 |
match(g3RegP); |
|
3838 |
match(g4RegP); |
|
3839 |
match(i0RegP); |
|
3840 |
match(o0RegP); |
|
3841 |
match(o1RegP); |
|
3842 |
match(l7RegP); |
|
3843 |
||
3844 |
format %{ %} |
|
3845 |
interface(REG_INTER); |
|
3846 |
%} |
|
3847 |
||
3848 |
operand sp_ptr_RegP() %{ |
|
3849 |
constraint(ALLOC_IN_RC(sp_ptr_reg)); |
|
3850 |
match(RegP); |
|
3851 |
match(iRegP); |
|
3852 |
||
3853 |
format %{ %} |
|
3854 |
interface(REG_INTER); |
|
3855 |
%} |
|
3856 |
||
3857 |
operand lock_ptr_RegP() %{ |
|
3858 |
constraint(ALLOC_IN_RC(lock_ptr_reg)); |
|
3859 |
match(RegP); |
|
3860 |
match(i0RegP); |
|
3861 |
match(o0RegP); |
|
3862 |
match(o1RegP); |
|
3863 |
match(l7RegP); |
|
3864 |
||
3865 |
format %{ %} |
|
3866 |
interface(REG_INTER); |
|
3867 |
%} |
|
3868 |
||
3869 |
operand g1RegP() %{ |
|
3870 |
constraint(ALLOC_IN_RC(g1_regP)); |
|
3871 |
match(iRegP); |
|
3872 |
||
3873 |
format %{ %} |
|
3874 |
interface(REG_INTER); |
|
3875 |
%} |
|
3876 |
||
3877 |
operand g2RegP() %{ |
|
3878 |
constraint(ALLOC_IN_RC(g2_regP)); |
|
3879 |
match(iRegP); |
|
3880 |
||
3881 |
format %{ %} |
|
3882 |
interface(REG_INTER); |
|
3883 |
%} |
|
3884 |
||
3885 |
operand g3RegP() %{ |
|
3886 |
constraint(ALLOC_IN_RC(g3_regP)); |
|
3887 |
match(iRegP); |
|
3888 |
||
3889 |
format %{ %} |
|
3890 |
interface(REG_INTER); |
|
3891 |
%} |
|
3892 |
||
3893 |
operand g1RegI() %{ |
|
3894 |
constraint(ALLOC_IN_RC(g1_regI)); |
|
3895 |
match(iRegI); |
|
3896 |
||
3897 |
format %{ %} |
|
3898 |
interface(REG_INTER); |
|
3899 |
%} |
|
3900 |
||
3901 |
operand g3RegI() %{ |
|
3902 |
constraint(ALLOC_IN_RC(g3_regI)); |
|
3903 |
match(iRegI); |
|
3904 |
||
3905 |
format %{ %} |
|
3906 |
interface(REG_INTER); |
|
3907 |
%} |
|
3908 |
||
3909 |
operand g4RegI() %{ |
|
3910 |
constraint(ALLOC_IN_RC(g4_regI)); |
|
3911 |
match(iRegI); |
|
3912 |
||
3913 |
format %{ %} |
|
3914 |
interface(REG_INTER); |
|
3915 |
%} |
|
3916 |
||
3917 |
operand g4RegP() %{ |
|
3918 |
constraint(ALLOC_IN_RC(g4_regP)); |
|
3919 |
match(iRegP); |
|
3920 |
||
3921 |
format %{ %} |
|
3922 |
interface(REG_INTER); |
|
3923 |
%} |
|
3924 |
||
3925 |
operand i0RegP() %{ |
|
3926 |
constraint(ALLOC_IN_RC(i0_regP)); |
|
3927 |
match(iRegP); |
|
3928 |
||
3929 |
format %{ %} |
|
3930 |
interface(REG_INTER); |
|
3931 |
%} |
|
3932 |
||
3933 |
operand o0RegP() %{ |
|
3934 |
constraint(ALLOC_IN_RC(o0_regP)); |
|
3935 |
match(iRegP); |
|
3936 |
||
3937 |
format %{ %} |
|
3938 |
interface(REG_INTER); |
|
3939 |
%} |
|
3940 |
||
3941 |
operand o1RegP() %{ |
|
3942 |
constraint(ALLOC_IN_RC(o1_regP)); |
|
3943 |
match(iRegP); |
|
3944 |
||
3945 |
format %{ %} |
|
3946 |
interface(REG_INTER); |
|
3947 |
%} |
|
3948 |
||
3949 |
operand o2RegP() %{ |
|
3950 |
constraint(ALLOC_IN_RC(o2_regP)); |
|
3951 |
match(iRegP); |
|
3952 |
||
3953 |
format %{ %} |
|
3954 |
interface(REG_INTER); |
|
3955 |
%} |
|
3956 |
||
3957 |
operand o7RegP() %{ |
|
3958 |
constraint(ALLOC_IN_RC(o7_regP)); |
|
3959 |
match(iRegP); |
|
3960 |
||
3961 |
format %{ %} |
|
3962 |
interface(REG_INTER); |
|
3963 |
%} |
|
3964 |
||
3965 |
operand l7RegP() %{ |
|
3966 |
constraint(ALLOC_IN_RC(l7_regP)); |
|
3967 |
match(iRegP); |
|
3968 |
||
3969 |
format %{ %} |
|
3970 |
interface(REG_INTER); |
|
3971 |
%} |
|
3972 |
||
3973 |
operand o7RegI() %{ |
|
3974 |
constraint(ALLOC_IN_RC(o7_regI)); |
|
3975 |
match(iRegI); |
|
3976 |
||
3977 |
format %{ %} |
|
3978 |
interface(REG_INTER); |
|
3979 |
%} |
|
3980 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3981 |
operand iRegN() %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3982 |
constraint(ALLOC_IN_RC(int_reg)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3983 |
match(RegN); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3984 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3985 |
format %{ %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3986 |
interface(REG_INTER); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3987 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
3988 |
|
1 | 3989 |
// Long Register |
3990 |
operand iRegL() %{ |
|
3991 |
constraint(ALLOC_IN_RC(long_reg)); |
|
3992 |
match(RegL); |
|
3993 |
||
3994 |
format %{ %} |
|
3995 |
interface(REG_INTER); |
|
3996 |
%} |
|
3997 |
||
3998 |
operand o2RegL() %{ |
|
3999 |
constraint(ALLOC_IN_RC(o2_regL)); |
|
4000 |
match(iRegL); |
|
4001 |
||
4002 |
format %{ %} |
|
4003 |
interface(REG_INTER); |
|
4004 |
%} |
|
4005 |
||
4006 |
operand o7RegL() %{ |
|
4007 |
constraint(ALLOC_IN_RC(o7_regL)); |
|
4008 |
match(iRegL); |
|
4009 |
||
4010 |
format %{ %} |
|
4011 |
interface(REG_INTER); |
|
4012 |
%} |
|
4013 |
||
4014 |
operand g1RegL() %{ |
|
4015 |
constraint(ALLOC_IN_RC(g1_regL)); |
|
4016 |
match(iRegL); |
|
4017 |
||
4018 |
format %{ %} |
|
4019 |
interface(REG_INTER); |
|
4020 |
%} |
|
4021 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4022 |
operand g3RegL() %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4023 |
constraint(ALLOC_IN_RC(g3_regL)); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4024 |
match(iRegL); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4025 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4026 |
format %{ %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4027 |
interface(REG_INTER); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4028 |
%} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
4029 |
|
1 | 4030 |
// Int Register safe |
4031 |
// This is 64bit safe |
|
4032 |
operand iRegIsafe() %{ |
|
4033 |
constraint(ALLOC_IN_RC(long_reg)); |
|
4034 |
||
4035 |
match(iRegI); |
|
4036 |
||
4037 |
format %{ %} |
|
4038 |
interface(REG_INTER); |
|
4039 |
%} |
|
4040 |
||
4041 |
// Condition Code Flag Register |
|
4042 |
operand flagsReg() %{ |
|
4043 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4044 |
match(RegFlags); |
|
4045 |
||
4046 |
format %{ "ccr" %} // both ICC and XCC |
|
4047 |
interface(REG_INTER); |
|
4048 |
%} |
|
4049 |
||
4050 |
// Condition Code Register, unsigned comparisons. |
|
4051 |
operand flagsRegU() %{ |
|
4052 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4053 |
match(RegFlags); |
|
4054 |
||
4055 |
format %{ "icc_U" %} |
|
4056 |
interface(REG_INTER); |
|
4057 |
%} |
|
4058 |
||
4059 |
// Condition Code Register, pointer comparisons. |
|
4060 |
operand flagsRegP() %{ |
|
4061 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4062 |
match(RegFlags); |
|
4063 |
||
4064 |
#ifdef _LP64 |
|
4065 |
format %{ "xcc_P" %} |
|
4066 |
#else |
|
4067 |
format %{ "icc_P" %} |
|
4068 |
#endif |
|
4069 |
interface(REG_INTER); |
|
4070 |
%} |
|
4071 |
||
4072 |
// Condition Code Register, long comparisons. |
|
4073 |
operand flagsRegL() %{ |
|
4074 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4075 |
match(RegFlags); |
|
4076 |
||
4077 |
format %{ "xcc_L" %} |
|
4078 |
interface(REG_INTER); |
|
4079 |
%} |
|
4080 |
||
4081 |
// Condition Code Register, floating comparisons, unordered same as "less". |
|
4082 |
operand flagsRegF() %{ |
|
4083 |
constraint(ALLOC_IN_RC(float_flags)); |
|
4084 |
match(RegFlags); |
|
4085 |
match(flagsRegF0); |
|
4086 |
||
4087 |
format %{ %} |
|
4088 |
interface(REG_INTER); |
|
4089 |
%} |
|
4090 |
||
4091 |
operand flagsRegF0() %{ |
|
4092 |
constraint(ALLOC_IN_RC(float_flag0)); |
|
4093 |
match(RegFlags); |
|
4094 |
||
4095 |
format %{ %} |
|
4096 |
interface(REG_INTER); |
|
4097 |
%} |
|
4098 |
||
4099 |
||
4100 |
// Condition Code Flag Register used by long compare |
|
4101 |
operand flagsReg_long_LTGE() %{ |
|
4102 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4103 |
match(RegFlags); |
|
4104 |
format %{ "icc_LTGE" %} |
|
4105 |
interface(REG_INTER); |
|
4106 |
%} |
|
4107 |
operand flagsReg_long_EQNE() %{ |
|
4108 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4109 |
match(RegFlags); |
|
4110 |
format %{ "icc_EQNE" %} |
|
4111 |
interface(REG_INTER); |
|
4112 |
%} |
|
4113 |
operand flagsReg_long_LEGT() %{ |
|
4114 |
constraint(ALLOC_IN_RC(int_flags)); |
|
4115 |
match(RegFlags); |
|
4116 |
format %{ "icc_LEGT" %} |
|
4117 |
interface(REG_INTER); |
|
4118 |
%} |
|
4119 |
||
4120 |
||
4121 |
operand regD() %{ |
|
4122 |
constraint(ALLOC_IN_RC(dflt_reg)); |
|
4123 |
match(RegD); |
|
4124 |
||
2015
580165b3f277
6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents:
1500
diff
changeset
|
4125 |
match(regD_low); |
580165b3f277
6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents:
1500
diff
changeset
|
4126 |
|
1 | 4127 |
format %{ %} |
4128 |
interface(REG_INTER); |
|
4129 |
%} |
|
4130 |
||
4131 |
operand regF() %{ |
|
4132 |
constraint(ALLOC_IN_RC(sflt_reg)); |
|
4133 |
match(RegF); |
|
4134 |
||
4135 |
format %{ %} |
|
4136 |
interface(REG_INTER); |
|
4137 |
%} |
|
4138 |
||
4139 |
operand regD_low() %{ |
|
4140 |
constraint(ALLOC_IN_RC(dflt_low_reg)); |
|
2015
580165b3f277
6790182: matcher.cpp:1375: assert(false,"bad AD file")
kvn
parents:
1500
diff
changeset
|
4141 |
match(regD); |
1 | 4142 |
|
4143 |
format %{ %} |
|
4144 |
interface(REG_INTER); |
|
4145 |
%} |
|
4146 |
||
4147 |
// Special Registers |
|
4148 |
||
4149 |
// Method Register |
|
4150 |
operand inline_cache_regP(iRegP reg) %{ |
|
4151 |
constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 |
|
4152 |
match(reg); |
|
4153 |
format %{ %} |
|
4154 |
interface(REG_INTER); |
|
4155 |
%} |
|
4156 |
||
4157 |
operand interpreter_method_oop_regP(iRegP reg) %{ |
|
4158 |
constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 |
|
4159 |
match(reg); |
|
4160 |
format %{ %} |
|
4161 |
interface(REG_INTER); |
|
4162 |
%} |
|
4163 |
||
4164 |
||
4165 |
//----------Complex Operands--------------------------------------------------- |
|
4166 |
// Indirect Memory Reference |
|
4167 |
operand indirect(sp_ptr_RegP reg) %{ |
|
4168 |
constraint(ALLOC_IN_RC(sp_ptr_reg)); |
|
4169 |
match(reg); |
|
4170 |
||
4171 |
op_cost(100); |
|
4172 |
format %{ "[$reg]" %} |
|
4173 |
interface(MEMORY_INTER) %{ |
|
4174 |
base($reg); |
|
4175 |
index(0x0); |
|
4176 |
scale(0x0); |
|
4177 |
disp(0x0); |
|
4178 |
%} |
|
4179 |
%} |
|
4180 |
||
2872 | 4181 |
// Indirect with simm13 Offset |
1 | 4182 |
operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4183 |
constraint(ALLOC_IN_RC(sp_ptr_reg)); |
|
4184 |
match(AddP reg offset); |
|
4185 |
||
4186 |
op_cost(100); |
|
4187 |
format %{ "[$reg + $offset]" %} |
|
4188 |
interface(MEMORY_INTER) %{ |
|
4189 |
base($reg); |
|
4190 |
index(0x0); |
|
4191 |
scale(0x0); |
|
4192 |
disp($offset); |
|
4193 |
%} |
|
4194 |
%} |
|
4195 |
||
2872 | 4196 |
// Indirect with simm13 Offset minus 7 |
4197 |
operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ |
|
4198 |
constraint(ALLOC_IN_RC(sp_ptr_reg)); |
|
4199 |
match(AddP reg offset); |
|
4200 |
||
4201 |
op_cost(100); |
|
4202 |
format %{ "[$reg + $offset]" %} |
|
4203 |
interface(MEMORY_INTER) %{ |
|
4204 |
base($reg); |
|
4205 |
index(0x0); |
|
4206 |
scale(0x0); |
|
4207 |
disp($offset); |
|
4208 |
%} |
|
4209 |
%} |
|
4210 |
||
1 | 4211 |
// Note: Intel has a swapped version also, like this: |
4212 |
//operand indOffsetX(iRegI reg, immP offset) %{ |
|
4213 |
// constraint(ALLOC_IN_RC(int_reg)); |
|
4214 |
// match(AddP offset reg); |
|
4215 |
// |
|
4216 |
// op_cost(100); |
|
4217 |
// format %{ "[$reg + $offset]" %} |
|
4218 |
// interface(MEMORY_INTER) %{ |
|
4219 |
// base($reg); |
|
4220 |
// index(0x0); |
|
4221 |
// scale(0x0); |
|
4222 |
// disp($offset); |
|
4223 |
// %} |
|
4224 |
//%} |
|
4225 |
//// However, it doesn't make sense for SPARC, since |
|
4226 |
// we have no particularly good way to embed oops in |
|
4227 |
// single instructions. |
|
4228 |
||
4229 |
// Indirect with Register Index |
|
4230 |
operand indIndex(iRegP addr, iRegX index) %{ |
|
4231 |
constraint(ALLOC_IN_RC(ptr_reg)); |
|
4232 |
match(AddP addr index); |
|
4233 |
||
4234 |
op_cost(100); |
|
4235 |
format %{ "[$addr + $index]" %} |
|
4236 |
interface(MEMORY_INTER) %{ |
|
4237 |
base($addr); |
|
4238 |
index($index); |
|
4239 |
scale(0x0); |
|
4240 |
disp(0x0); |
|
4241 |
%} |
|
4242 |
%} |
|
4243 |
||
4244 |
//----------Special Memory Operands-------------------------------------------- |
|
4245 |
// Stack Slot Operand - This operand is used for loading and storing temporary |
|
4246 |
// values on the stack where a match requires a value to |
|
4247 |
// flow through memory. |
|
4248 |
operand stackSlotI(sRegI reg) %{ |
|
4249 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4250 |
op_cost(100); |
|
4251 |
//match(RegI); |
|
4252 |
format %{ "[$reg]" %} |
|
4253 |
interface(MEMORY_INTER) %{ |
|
4254 |
base(0xE); // R_SP |
|
4255 |
index(0x0); |
|
4256 |
scale(0x0); |
|
4257 |
disp($reg); // Stack Offset |
|
4258 |
%} |
|
4259 |
%} |
|
4260 |
||
4261 |
operand stackSlotP(sRegP reg) %{ |
|
4262 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4263 |
op_cost(100); |
|
4264 |
//match(RegP); |
|
4265 |
format %{ "[$reg]" %} |
|
4266 |
interface(MEMORY_INTER) %{ |
|
4267 |
base(0xE); // R_SP |
|
4268 |
index(0x0); |
|
4269 |
scale(0x0); |
|
4270 |
disp($reg); // Stack Offset |
|
4271 |
%} |
|
4272 |
%} |
|
4273 |
||
4274 |
operand stackSlotF(sRegF reg) %{ |
|
4275 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4276 |
op_cost(100); |
|
4277 |
//match(RegF); |
|
4278 |
format %{ "[$reg]" %} |
|
4279 |
interface(MEMORY_INTER) %{ |
|
4280 |
base(0xE); // R_SP |
|
4281 |
index(0x0); |
|
4282 |
scale(0x0); |
|
4283 |
disp($reg); // Stack Offset |
|
4284 |
%} |
|
4285 |
%} |
|
4286 |
operand stackSlotD(sRegD reg) %{ |
|
4287 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4288 |
op_cost(100); |
|
4289 |
//match(RegD); |
|
4290 |
format %{ "[$reg]" %} |
|
4291 |
interface(MEMORY_INTER) %{ |
|
4292 |
base(0xE); // R_SP |
|
4293 |
index(0x0); |
|
4294 |
scale(0x0); |
|
4295 |
disp($reg); // Stack Offset |
|
4296 |
%} |
|
4297 |
%} |
|
4298 |
operand stackSlotL(sRegL reg) %{ |
|
4299 |
constraint(ALLOC_IN_RC(stack_slots)); |
|
4300 |
op_cost(100); |
|
4301 |
//match(RegL); |
|
4302 |
format %{ "[$reg]" %} |
|
4303 |
interface(MEMORY_INTER) %{ |
|
4304 |
base(0xE); // R_SP |
|
4305 |
index(0x0); |
|
4306 |
scale(0x0); |
|
4307 |
disp($reg); // Stack Offset |
|
4308 |
%} |
|
4309 |
%} |
|
4310 |
||
4311 |
// Operands for expressing Control Flow |
|
4312 |
// NOTE: Label is a predefined operand which should not be redefined in |
|
4313 |
// the AD file. It is generically handled within the ADLC. |
|
4314 |
||
4315 |
//----------Conditional Branch Operands---------------------------------------- |
|
4316 |
// Comparison Op - This is the operation of the comparison, and is limited to |
|
4317 |
// the following set of codes: |
|
4318 |
// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) |
|
4319 |
// |
|
4320 |
// Other attributes of the comparison, such as unsignedness, are specified |
|
4321 |
// by the comparison instruction that sets a condition code flags register. |
|
4322 |
// That result is represented by a flags operand whose subtype is appropriate |
|
4323 |
// to the unsignedness (etc.) of the comparison. |
|
4324 |
// |
|
4325 |
// Later, the instruction which matches both the Comparison Op (a Bool) and |
|
4326 |
// the flags (produced by the Cmp) specifies the coding of the comparison op |
|
4327 |
// by matching a specific subtype of Bool operand below, such as cmpOpU. |
|
4328 |
||
4329 |
operand cmpOp() %{ |
|
4330 |
match(Bool); |
|
4331 |
||
4332 |
format %{ "" %} |
|
4333 |
interface(COND_INTER) %{ |
|
4334 |
equal(0x1); |
|
4335 |
not_equal(0x9); |
|
4336 |
less(0x3); |
|
4337 |
greater_equal(0xB); |
|
4338 |
less_equal(0x2); |
|
4339 |
greater(0xA); |
|
20289 | 4340 |
overflow(0x7); |
4341 |
no_overflow(0xF); |
|
1 | 4342 |
%} |
4343 |
%} |
|
4344 |
||
4345 |
// Comparison Op, unsigned |
|
4346 |
operand cmpOpU() %{ |
|
4347 |
match(Bool); |
|
20289 | 4348 |
predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4349 |
n->as_Bool()->_test._test != BoolTest::no_overflow); |
|
1 | 4350 |
|
4351 |
format %{ "u" %} |
|
4352 |
interface(COND_INTER) %{ |
|
4353 |
equal(0x1); |
|
4354 |
not_equal(0x9); |
|
4355 |
less(0x5); |
|
4356 |
greater_equal(0xD); |
|
4357 |
less_equal(0x4); |
|
4358 |
greater(0xC); |
|
20289 | 4359 |
overflow(0x7); |
4360 |
no_overflow(0xF); |
|
1 | 4361 |
%} |
4362 |
%} |
|
4363 |
||
4364 |
// Comparison Op, pointer (same as unsigned) |
|
4365 |
operand cmpOpP() %{ |
|
4366 |
match(Bool); |
|
20289 | 4367 |
predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4368 |
n->as_Bool()->_test._test != BoolTest::no_overflow); |
|
1 | 4369 |
|
4370 |
format %{ "p" %} |
|
4371 |
interface(COND_INTER) %{ |
|
4372 |
equal(0x1); |
|
4373 |
not_equal(0x9); |
|
4374 |
less(0x5); |
|
4375 |
greater_equal(0xD); |
|
4376 |
less_equal(0x4); |
|
4377 |
greater(0xC); |
|
20289 | 4378 |
overflow(0x7); |
4379 |
no_overflow(0xF); |
|
1 | 4380 |
%} |
4381 |
%} |
|
4382 |
||
4383 |
// Comparison Op, branch-register encoding |
|
4384 |
operand cmpOp_reg() %{ |
|
4385 |
match(Bool); |
|
20289 | 4386 |
predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4387 |
n->as_Bool()->_test._test != BoolTest::no_overflow); |
|
1 | 4388 |
|
4389 |
format %{ "" %} |
|
4390 |
interface(COND_INTER) %{ |
|
4391 |
equal (0x1); |
|
4392 |
not_equal (0x5); |
|
4393 |
less (0x3); |
|
4394 |
greater_equal(0x7); |
|
4395 |
less_equal (0x2); |
|
4396 |
greater (0x6); |
|
20289 | 4397 |
overflow(0x7); // not supported |
4398 |
no_overflow(0xF); // not supported |
|
1 | 4399 |
%} |
4400 |
%} |
|
4401 |
||
4402 |
// Comparison Code, floating, unordered same as less |
|
4403 |
operand cmpOpF() %{ |
|
4404 |
match(Bool); |
|
20289 | 4405 |
predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4406 |
n->as_Bool()->_test._test != BoolTest::no_overflow); |
|
1 | 4407 |
|
4408 |
format %{ "fl" %} |
|
4409 |
interface(COND_INTER) %{ |
|
4410 |
equal(0x9); |
|
4411 |
not_equal(0x1); |
|
4412 |
less(0x3); |
|
4413 |
greater_equal(0xB); |
|
4414 |
less_equal(0xE); |
|
4415 |
greater(0x6); |
|
20289 | 4416 |
|
4417 |
overflow(0x7); // not supported |
|
4418 |
no_overflow(0xF); // not supported |
|
1 | 4419 |
%} |
4420 |
%} |
|
4421 |
||
4422 |
// Used by long compare |
|
4423 |
operand cmpOp_commute() %{ |
|
4424 |
match(Bool); |
|
20289 | 4425 |
predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4426 |
n->as_Bool()->_test._test != BoolTest::no_overflow); |
|
1 | 4427 |
|
4428 |
format %{ "" %} |
|
4429 |
interface(COND_INTER) %{ |
|
4430 |
equal(0x1); |
|
4431 |
not_equal(0x9); |
|
4432 |
less(0xA); |
|
4433 |
greater_equal(0x2); |
|
4434 |
less_equal(0xB); |
|
4435 |
greater(0x3); |
|
20289 | 4436 |
overflow(0x7); |
4437 |
no_overflow(0xF); |
|
1 | 4438 |
%} |
4439 |
%} |
|
4440 |
||
4441 |
//----------OPERAND CLASSES---------------------------------------------------- |
|
4442 |
// Operand Classes are groups of operands that are used to simplify |
|
2131 | 4443 |
// instruction definitions by not requiring the AD writer to specify separate |
1 | 4444 |
// instructions for every form of operand when the instruction accepts |
4445 |
// multiple operand types with the same basic encoding and format. The classic |
|
4446 |
// case of this is memory operands. |
|
4447 |
opclass memory( indirect, indOffset13, indIndex ); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
4448 |
opclass indIndexMemory( indIndex ); |
1 | 4449 |
|
4450 |
//----------PIPELINE----------------------------------------------------------- |
|
4451 |
pipeline %{ |
|
4452 |
||
4453 |
//----------ATTRIBUTES--------------------------------------------------------- |
|
4454 |
attributes %{ |
|
4455 |
fixed_size_instructions; // Fixed size instructions |
|
4456 |
branch_has_delay_slot; // Branch has delay slot following |
|
4457 |
max_instructions_per_bundle = 4; // Up to 4 instructions per bundle |
|
4458 |
instruction_unit_size = 4; // An instruction is 4 bytes long |
|
4459 |
instruction_fetch_unit_size = 16; // The processor fetches one line |
|
4460 |
instruction_fetch_units = 1; // of 16 bytes |
|
4461 |
||
4462 |
// List of nop instructions |
|
4463 |
nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); |
|
4464 |
%} |
|
4465 |
||
4466 |
//----------RESOURCES---------------------------------------------------------- |
|
4467 |
// Resources are the functional units available to the machine |
|
4468 |
resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); |
|
4469 |
||
4470 |
//----------PIPELINE DESCRIPTION----------------------------------------------- |
|
4471 |
// Pipeline Description specifies the stages in the machine's pipeline |
|
4472 |
||
4473 |
pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); |
|
4474 |
||
4475 |
//----------PIPELINE CLASSES--------------------------------------------------- |
|
4476 |
// Pipeline Classes describe the stages in which input and output are |
|
4477 |
// referenced by the hardware pipeline. |
|
4478 |
||
4479 |
// Integer ALU reg-reg operation |
|
4480 |
pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
4481 |
single_instruction; |
|
4482 |
dst : E(write); |
|
4483 |
src1 : R(read); |
|
4484 |
src2 : R(read); |
|
4485 |
IALU : R; |
|
4486 |
%} |
|
4487 |
||
4488 |
// Integer ALU reg-reg long operation |
|
4489 |
pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ |
|
4490 |
instruction_count(2); |
|
4491 |
dst : E(write); |
|
4492 |
src1 : R(read); |
|
4493 |
src2 : R(read); |
|
4494 |
IALU : R; |
|
4495 |
IALU : R; |
|
4496 |
%} |
|
4497 |
||
4498 |
// Integer ALU reg-reg long dependent operation |
|
4499 |
pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ |
|
4500 |
instruction_count(1); multiple_bundles; |
|
4501 |
dst : E(write); |
|
4502 |
src1 : R(read); |
|
4503 |
src2 : R(read); |
|
4504 |
cr : E(write); |
|
4505 |
IALU : R(2); |
|
4506 |
%} |
|
4507 |
||
4508 |
// Integer ALU reg-imm operaion |
|
4509 |
pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ |
|
4510 |
single_instruction; |
|
4511 |
dst : E(write); |
|
4512 |
src1 : R(read); |
|
4513 |
IALU : R; |
|
4514 |
%} |
|
4515 |
||
4516 |
// Integer ALU reg-reg operation with condition code |
|
4517 |
pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ |
|
4518 |
single_instruction; |
|
4519 |
dst : E(write); |
|
4520 |
cr : E(write); |
|
4521 |
src1 : R(read); |
|
4522 |
src2 : R(read); |
|
4523 |
IALU : R; |
|
4524 |
%} |
|
4525 |
||
4526 |
// Integer ALU reg-imm operation with condition code |
|
4527 |
pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ |
|
4528 |
single_instruction; |
|
4529 |
dst : E(write); |
|
4530 |
cr : E(write); |
|
4531 |
src1 : R(read); |
|
4532 |
IALU : R; |
|
4533 |
%} |
|
4534 |
||
4535 |
// Integer ALU zero-reg operation |
|
4536 |
pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ |
|
4537 |
single_instruction; |
|
4538 |
dst : E(write); |
|
4539 |
src2 : R(read); |
|
4540 |
IALU : R; |
|
4541 |
%} |
|
4542 |
||
4543 |
// Integer ALU zero-reg operation with condition code only |
|
4544 |
pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ |
|
4545 |
single_instruction; |
|
4546 |
cr : E(write); |
|
4547 |
src : R(read); |
|
4548 |
IALU : R; |
|
4549 |
%} |
|
4550 |
||
4551 |
// Integer ALU reg-reg operation with condition code only |
|
4552 |
pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ |
|
4553 |
single_instruction; |
|
4554 |
cr : E(write); |
|
4555 |
src1 : R(read); |
|
4556 |
src2 : R(read); |
|
4557 |
IALU : R; |
|
4558 |
%} |
|
4559 |
||
4560 |
// Integer ALU reg-imm operation with condition code only |
|
4561 |
pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ |
|
4562 |
single_instruction; |
|
4563 |
cr : E(write); |
|
4564 |
src1 : R(read); |
|
4565 |
IALU : R; |
|
4566 |
%} |
|
4567 |
||
4568 |
// Integer ALU reg-reg-zero operation with condition code only |
|
4569 |
pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ |
|
4570 |
single_instruction; |
|
4571 |
cr : E(write); |
|
4572 |
src1 : R(read); |
|
4573 |
src2 : R(read); |
|
4574 |
IALU : R; |
|
4575 |
%} |
|
4576 |
||
4577 |
// Integer ALU reg-imm-zero operation with condition code only |
|
4578 |
pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ |
|
4579 |
single_instruction; |
|
4580 |
cr : E(write); |
|
4581 |
src1 : R(read); |
|
4582 |
IALU : R; |
|
4583 |
%} |
|
4584 |
||
4585 |
// Integer ALU reg-reg operation with condition code, src1 modified |
|
4586 |
pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ |
|
4587 |
single_instruction; |
|
4588 |
cr : E(write); |
|
4589 |
src1 : E(write); |
|
4590 |
src1 : R(read); |
|
4591 |
src2 : R(read); |
|
4592 |
IALU : R; |
|
4593 |
%} |
|
4594 |
||
4595 |
// Integer ALU reg-imm operation with condition code, src1 modified |
|
4596 |
pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ |
|
4597 |
single_instruction; |
|
4598 |
cr : E(write); |
|
4599 |
src1 : E(write); |
|
4600 |
src1 : R(read); |
|
4601 |
IALU : R; |
|
4602 |
%} |
|
4603 |
||
4604 |
pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ |
|
4605 |
multiple_bundles; |
|
4606 |
dst : E(write)+4; |
|
4607 |
cr : E(write); |
|
4608 |
src1 : R(read); |
|
4609 |
src2 : R(read); |
|
4610 |
IALU : R(3); |
|
4611 |
BR : R(2); |
|
4612 |
%} |
|
4613 |
||
4614 |
// Integer ALU operation |
|
4615 |
pipe_class ialu_none(iRegI dst) %{ |
|
4616 |
single_instruction; |
|
4617 |
dst : E(write); |
|
4618 |
IALU : R; |
|
4619 |
%} |
|
4620 |
||
4621 |
// Integer ALU reg operation |
|
4622 |
pipe_class ialu_reg(iRegI dst, iRegI src) %{ |
|
4623 |
single_instruction; may_have_no_code; |
|
4624 |
dst : E(write); |
|
4625 |
src : R(read); |
|
4626 |
IALU : R; |
|
4627 |
%} |
|
4628 |
||
4629 |
// Integer ALU reg conditional operation |
|
4630 |
// This instruction has a 1 cycle stall, and cannot execute |
|
4631 |
// in the same cycle as the instruction setting the condition |
|
4632 |
// code. We kludge this by pretending to read the condition code |
|
4633 |
// 1 cycle earlier, and by marking the functional units as busy |
|
4634 |
// for 2 cycles with the result available 1 cycle later than |
|
4635 |
// is really the case. |
|
4636 |
pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ |
|
4637 |
single_instruction; |
|
4638 |
op2_out : C(write); |
|
4639 |
op1 : R(read); |
|
4640 |
cr : R(read); // This is really E, with a 1 cycle stall |
|
4641 |
BR : R(2); |
|
4642 |
MS : R(2); |
|
4643 |
%} |
|
4644 |
||
4645 |
#ifdef _LP64 |
|
4646 |
pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ |
|
4647 |
instruction_count(1); multiple_bundles; |
|
4648 |
dst : C(write)+1; |
|
4649 |
src : R(read)+1; |
|
4650 |
IALU : R(1); |
|
4651 |
BR : E(2); |
|
4652 |
MS : E(2); |
|
4653 |
%} |
|
4654 |
#endif |
|
4655 |
||
4656 |
// Integer ALU reg operation |
|
4657 |
pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ |
|
4658 |
single_instruction; may_have_no_code; |
|
4659 |
dst : E(write); |
|
4660 |
src : R(read); |
|
4661 |
IALU : R; |
|
4662 |
%} |
|
4663 |
pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ |
|
4664 |
single_instruction; may_have_no_code; |
|
4665 |
dst : E(write); |
|
4666 |
src : R(read); |
|
4667 |
IALU : R; |
|
4668 |
%} |
|
4669 |
||
4670 |
// Two integer ALU reg operations |
|
4671 |
pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ |
|
4672 |
instruction_count(2); |
|
4673 |
dst : E(write); |
|
4674 |
src : R(read); |
|
4675 |
A0 : R; |
|
4676 |
A1 : R; |
|
4677 |
%} |
|
4678 |
||
4679 |
// Two integer ALU reg operations |
|
4680 |
pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ |
|
4681 |
instruction_count(2); may_have_no_code; |
|
4682 |
dst : E(write); |
|
4683 |
src : R(read); |
|
4684 |
A0 : R; |
|
4685 |
A1 : R; |
|
4686 |
%} |
|
4687 |
||
4688 |
// Integer ALU imm operation |
|
4689 |
pipe_class ialu_imm(iRegI dst, immI13 src) %{ |
|
4690 |
single_instruction; |
|
4691 |
dst : E(write); |
|
4692 |
IALU : R; |
|
4693 |
%} |
|
4694 |
||
4695 |
// Integer ALU reg-reg with carry operation |
|
4696 |
pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ |
|
4697 |
single_instruction; |
|
4698 |
dst : E(write); |
|
4699 |
src1 : R(read); |
|
4700 |
src2 : R(read); |
|
4701 |
IALU : R; |
|
4702 |
%} |
|
4703 |
||
4704 |
// Integer ALU cc operation |
|
4705 |
pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ |
|
4706 |
single_instruction; |
|
4707 |
dst : E(write); |
|
4708 |
cc : R(read); |
|
4709 |
IALU : R; |
|
4710 |
%} |
|
4711 |
||
4712 |
// Integer ALU cc / second IALU operation |
|
4713 |
pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ |
|
4714 |
instruction_count(1); multiple_bundles; |
|
4715 |
dst : E(write)+1; |
|
4716 |
src : R(read); |
|
4717 |
IALU : R; |
|
4718 |
%} |
|
4719 |
||
4720 |
// Integer ALU cc / second IALU operation |
|
4721 |
pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ |
|
4722 |
instruction_count(1); multiple_bundles; |
|
4723 |
dst : E(write)+1; |
|
4724 |
p : R(read); |
|
4725 |
q : R(read); |
|
4726 |
IALU : R; |
|
4727 |
%} |
|
4728 |
||
4729 |
// Integer ALU hi-lo-reg operation |
|
4730 |
pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ |
|
4731 |
instruction_count(1); multiple_bundles; |
|
4732 |
dst : E(write)+1; |
|
4733 |
IALU : R(2); |
|
4734 |
%} |
|
4735 |
||
4736 |
// Float ALU hi-lo-reg operation (with temp) |
|
4737 |
pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ |
|
4738 |
instruction_count(1); multiple_bundles; |
|
4739 |
dst : E(write)+1; |
|
4740 |
IALU : R(2); |
|
4741 |
%} |
|
4742 |
||
4743 |
// Long Constant |
|
4744 |
pipe_class loadConL( iRegL dst, immL src ) %{ |
|
4745 |
instruction_count(2); multiple_bundles; |
|
4746 |
dst : E(write)+1; |
|
4747 |
IALU : R(2); |
|
4748 |
IALU : R(2); |
|
4749 |
%} |
|
4750 |
||
4751 |
// Pointer Constant |
|
4752 |
pipe_class loadConP( iRegP dst, immP src ) %{ |
|
4753 |
instruction_count(0); multiple_bundles; |
|
4754 |
fixed_latency(6); |
|
4755 |
%} |
|
4756 |
||
4757 |
// Polling Address |
|
4758 |
pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ |
|
4759 |
#ifdef _LP64 |
|
4760 |
instruction_count(0); multiple_bundles; |
|
4761 |
fixed_latency(6); |
|
4762 |
#else |
|
4763 |
dst : E(write); |
|
4764 |
IALU : R; |
|
4765 |
#endif |
|
4766 |
%} |
|
4767 |
||
4768 |
// Long Constant small |
|
4769 |
pipe_class loadConLlo( iRegL dst, immL src ) %{ |
|
4770 |
instruction_count(2); |
|
4771 |
dst : E(write); |
|
4772 |
IALU : R; |
|
4773 |
IALU : R; |
|
4774 |
%} |
|
4775 |
||
4776 |
// [PHH] This is wrong for 64-bit. See LdImmF/D. |
|
4777 |
pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ |
|
4778 |
instruction_count(1); multiple_bundles; |
|
4779 |
src : R(read); |
|
4780 |
dst : M(write)+1; |
|
4781 |
IALU : R; |
|
4782 |
MS : E; |
|
4783 |
%} |
|
4784 |
||
4785 |
// Integer ALU nop operation |
|
4786 |
pipe_class ialu_nop() %{ |
|
4787 |
single_instruction; |
|
4788 |
IALU : R; |
|
4789 |
%} |
|
4790 |
||
4791 |
// Integer ALU nop operation |
|
4792 |
pipe_class ialu_nop_A0() %{ |
|
4793 |
single_instruction; |
|
4794 |
A0 : R; |
|
4795 |
%} |
|
4796 |
||
4797 |
// Integer ALU nop operation |
|
4798 |
pipe_class ialu_nop_A1() %{ |
|
4799 |
single_instruction; |
|
4800 |
A1 : R; |
|
4801 |
%} |
|
4802 |
||
4803 |
// Integer Multiply reg-reg operation |
|
4804 |
pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
4805 |
single_instruction; |
|
4806 |
dst : E(write); |
|
4807 |
src1 : R(read); |
|
4808 |
src2 : R(read); |
|
4809 |
MS : R(5); |
|
4810 |
%} |
|
4811 |
||
4812 |
// Integer Multiply reg-imm operation |
|
4813 |
pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ |
|
4814 |
single_instruction; |
|
4815 |
dst : E(write); |
|
4816 |
src1 : R(read); |
|
4817 |
MS : R(5); |
|
4818 |
%} |
|
4819 |
||
4820 |
pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
4821 |
single_instruction; |
|
4822 |
dst : E(write)+4; |
|
4823 |
src1 : R(read); |
|
4824 |
src2 : R(read); |
|
4825 |
MS : R(6); |
|
4826 |
%} |
|
4827 |
||
4828 |
pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ |
|
4829 |
single_instruction; |
|
4830 |
dst : E(write)+4; |
|
4831 |
src1 : R(read); |
|
4832 |
MS : R(6); |
|
4833 |
%} |
|
4834 |
||
4835 |
// Integer Divide reg-reg |
|
4836 |
pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ |
|
4837 |
instruction_count(1); multiple_bundles; |
|
4838 |
dst : E(write); |
|
4839 |
temp : E(write); |
|
4840 |
src1 : R(read); |
|
4841 |
src2 : R(read); |
|
4842 |
temp : R(read); |
|
4843 |
MS : R(38); |
|
4844 |
%} |
|
4845 |
||
4846 |
// Integer Divide reg-imm |
|
4847 |
pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ |
|
4848 |
instruction_count(1); multiple_bundles; |
|
4849 |
dst : E(write); |
|
4850 |
temp : E(write); |
|
4851 |
src1 : R(read); |
|
4852 |
temp : R(read); |
|
4853 |
MS : R(38); |
|
4854 |
%} |
|
4855 |
||
4856 |
// Long Divide |
|
4857 |
pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
4858 |
dst : E(write)+71; |
|
4859 |
src1 : R(read); |
|
4860 |
src2 : R(read)+1; |
|
4861 |
MS : R(70); |
|
4862 |
%} |
|
4863 |
||
4864 |
pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ |
|
4865 |
dst : E(write)+71; |
|
4866 |
src1 : R(read); |
|
4867 |
MS : R(70); |
|
4868 |
%} |
|
4869 |
||
4870 |
// Floating Point Add Float |
|
4871 |
pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
4872 |
single_instruction; |
|
4873 |
dst : X(write); |
|
4874 |
src1 : E(read); |
|
4875 |
src2 : E(read); |
|
4876 |
FA : R; |
|
4877 |
%} |
|
4878 |
||
4879 |
// Floating Point Add Double |
|
4880 |
pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
4881 |
single_instruction; |
|
4882 |
dst : X(write); |
|
4883 |
src1 : E(read); |
|
4884 |
src2 : E(read); |
|
4885 |
FA : R; |
|
4886 |
%} |
|
4887 |
||
4888 |
// Floating Point Conditional Move based on integer flags |
|
4889 |
pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ |
|
4890 |
single_instruction; |
|
4891 |
dst : X(write); |
|
4892 |
src : E(read); |
|
4893 |
cr : R(read); |
|
4894 |
FA : R(2); |
|
4895 |
BR : R(2); |
|
4896 |
%} |
|
4897 |
||
4898 |
// Floating Point Conditional Move based on integer flags |
|
4899 |
pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ |
|
4900 |
single_instruction; |
|
4901 |
dst : X(write); |
|
4902 |
src : E(read); |
|
4903 |
cr : R(read); |
|
4904 |
FA : R(2); |
|
4905 |
BR : R(2); |
|
4906 |
%} |
|
4907 |
||
4908 |
// Floating Point Multiply Float |
|
4909 |
pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
4910 |
single_instruction; |
|
4911 |
dst : X(write); |
|
4912 |
src1 : E(read); |
|
4913 |
src2 : E(read); |
|
4914 |
FM : R; |
|
4915 |
%} |
|
4916 |
||
4917 |
// Floating Point Multiply Double |
|
4918 |
pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
4919 |
single_instruction; |
|
4920 |
dst : X(write); |
|
4921 |
src1 : E(read); |
|
4922 |
src2 : E(read); |
|
4923 |
FM : R; |
|
4924 |
%} |
|
4925 |
||
4926 |
// Floating Point Divide Float |
|
4927 |
pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
4928 |
single_instruction; |
|
4929 |
dst : X(write); |
|
4930 |
src1 : E(read); |
|
4931 |
src2 : E(read); |
|
4932 |
FM : R; |
|
4933 |
FDIV : C(14); |
|
4934 |
%} |
|
4935 |
||
4936 |
// Floating Point Divide Double |
|
4937 |
pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
4938 |
single_instruction; |
|
4939 |
dst : X(write); |
|
4940 |
src1 : E(read); |
|
4941 |
src2 : E(read); |
|
4942 |
FM : R; |
|
4943 |
FDIV : C(17); |
|
4944 |
%} |
|
4945 |
||
4946 |
// Floating Point Move/Negate/Abs Float |
|
4947 |
pipe_class faddF_reg(regF dst, regF src) %{ |
|
4948 |
single_instruction; |
|
4949 |
dst : W(write); |
|
4950 |
src : E(read); |
|
4951 |
FA : R(1); |
|
4952 |
%} |
|
4953 |
||
4954 |
// Floating Point Move/Negate/Abs Double |
|
4955 |
pipe_class faddD_reg(regD dst, regD src) %{ |
|
4956 |
single_instruction; |
|
4957 |
dst : W(write); |
|
4958 |
src : E(read); |
|
4959 |
FA : R; |
|
4960 |
%} |
|
4961 |
||
4962 |
// Floating Point Convert F->D |
|
4963 |
pipe_class fcvtF2D(regD dst, regF src) %{ |
|
4964 |
single_instruction; |
|
4965 |
dst : X(write); |
|
4966 |
src : E(read); |
|
4967 |
FA : R; |
|
4968 |
%} |
|
4969 |
||
4970 |
// Floating Point Convert I->D |
|
4971 |
pipe_class fcvtI2D(regD dst, regF src) %{ |
|
4972 |
single_instruction; |
|
4973 |
dst : X(write); |
|
4974 |
src : E(read); |
|
4975 |
FA : R; |
|
4976 |
%} |
|
4977 |
||
4978 |
// Floating Point Convert LHi->D |
|
4979 |
pipe_class fcvtLHi2D(regD dst, regD src) %{ |
|
4980 |
single_instruction; |
|
4981 |
dst : X(write); |
|
4982 |
src : E(read); |
|
4983 |
FA : R; |
|
4984 |
%} |
|
4985 |
||
4986 |
// Floating Point Convert L->D |
|
4987 |
pipe_class fcvtL2D(regD dst, regF src) %{ |
|
4988 |
single_instruction; |
|
4989 |
dst : X(write); |
|
4990 |
src : E(read); |
|
4991 |
FA : R; |
|
4992 |
%} |
|
4993 |
||
4994 |
// Floating Point Convert L->F |
|
4995 |
pipe_class fcvtL2F(regD dst, regF src) %{ |
|
4996 |
single_instruction; |
|
4997 |
dst : X(write); |
|
4998 |
src : E(read); |
|
4999 |
FA : R; |
|
5000 |
%} |
|
5001 |
||
5002 |
// Floating Point Convert D->F |
|
5003 |
pipe_class fcvtD2F(regD dst, regF src) %{ |
|
5004 |
single_instruction; |
|
5005 |
dst : X(write); |
|
5006 |
src : E(read); |
|
5007 |
FA : R; |
|
5008 |
%} |
|
5009 |
||
5010 |
// Floating Point Convert I->L |
|
5011 |
pipe_class fcvtI2L(regD dst, regF src) %{ |
|
5012 |
single_instruction; |
|
5013 |
dst : X(write); |
|
5014 |
src : E(read); |
|
5015 |
FA : R; |
|
5016 |
%} |
|
5017 |
||
5018 |
// Floating Point Convert D->F |
|
5019 |
pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ |
|
5020 |
instruction_count(1); multiple_bundles; |
|
5021 |
dst : X(write)+6; |
|
5022 |
src : E(read); |
|
5023 |
FA : R; |
|
5024 |
%} |
|
5025 |
||
5026 |
// Floating Point Convert D->L |
|
5027 |
pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ |
|
5028 |
instruction_count(1); multiple_bundles; |
|
5029 |
dst : X(write)+6; |
|
5030 |
src : E(read); |
|
5031 |
FA : R; |
|
5032 |
%} |
|
5033 |
||
5034 |
// Floating Point Convert F->I |
|
5035 |
pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ |
|
5036 |
instruction_count(1); multiple_bundles; |
|
5037 |
dst : X(write)+6; |
|
5038 |
src : E(read); |
|
5039 |
FA : R; |
|
5040 |
%} |
|
5041 |
||
5042 |
// Floating Point Convert F->L |
|
5043 |
pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ |
|
5044 |
instruction_count(1); multiple_bundles; |
|
5045 |
dst : X(write)+6; |
|
5046 |
src : E(read); |
|
5047 |
FA : R; |
|
5048 |
%} |
|
5049 |
||
5050 |
// Floating Point Convert I->F |
|
5051 |
pipe_class fcvtI2F(regF dst, regF src) %{ |
|
5052 |
single_instruction; |
|
5053 |
dst : X(write); |
|
5054 |
src : E(read); |
|
5055 |
FA : R; |
|
5056 |
%} |
|
5057 |
||
5058 |
// Floating Point Compare |
|
5059 |
pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ |
|
5060 |
single_instruction; |
|
5061 |
cr : X(write); |
|
5062 |
src1 : E(read); |
|
5063 |
src2 : E(read); |
|
5064 |
FA : R; |
|
5065 |
%} |
|
5066 |
||
5067 |
// Floating Point Compare |
|
5068 |
pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ |
|
5069 |
single_instruction; |
|
5070 |
cr : X(write); |
|
5071 |
src1 : E(read); |
|
5072 |
src2 : E(read); |
|
5073 |
FA : R; |
|
5074 |
%} |
|
5075 |
||
5076 |
// Floating Add Nop |
|
5077 |
pipe_class fadd_nop() %{ |
|
5078 |
single_instruction; |
|
5079 |
FA : R; |
|
5080 |
%} |
|
5081 |
||
5082 |
// Integer Store to Memory |
|
5083 |
pipe_class istore_mem_reg(memory mem, iRegI src) %{ |
|
5084 |
single_instruction; |
|
5085 |
mem : R(read); |
|
5086 |
src : C(read); |
|
5087 |
MS : R; |
|
5088 |
%} |
|
5089 |
||
5090 |
// Integer Store to Memory |
|
5091 |
pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ |
|
5092 |
single_instruction; |
|
5093 |
mem : R(read); |
|
5094 |
src : C(read); |
|
5095 |
MS : R; |
|
5096 |
%} |
|
5097 |
||
5098 |
// Integer Store Zero to Memory |
|
5099 |
pipe_class istore_mem_zero(memory mem, immI0 src) %{ |
|
5100 |
single_instruction; |
|
5101 |
mem : R(read); |
|
5102 |
MS : R; |
|
5103 |
%} |
|
5104 |
||
5105 |
// Special Stack Slot Store |
|
5106 |
pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ |
|
5107 |
single_instruction; |
|
5108 |
stkSlot : R(read); |
|
5109 |
src : C(read); |
|
5110 |
MS : R; |
|
5111 |
%} |
|
5112 |
||
5113 |
// Special Stack Slot Store |
|
5114 |
pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ |
|
5115 |
instruction_count(2); multiple_bundles; |
|
5116 |
stkSlot : R(read); |
|
5117 |
src : C(read); |
|
5118 |
MS : R(2); |
|
5119 |
%} |
|
5120 |
||
5121 |
// Float Store |
|
5122 |
pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ |
|
5123 |
single_instruction; |
|
5124 |
mem : R(read); |
|
5125 |
src : C(read); |
|
5126 |
MS : R; |
|
5127 |
%} |
|
5128 |
||
5129 |
// Float Store |
|
5130 |
pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ |
|
5131 |
single_instruction; |
|
5132 |
mem : R(read); |
|
5133 |
MS : R; |
|
5134 |
%} |
|
5135 |
||
5136 |
// Double Store |
|
5137 |
pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ |
|
5138 |
instruction_count(1); |
|
5139 |
mem : R(read); |
|
5140 |
src : C(read); |
|
5141 |
MS : R; |
|
5142 |
%} |
|
5143 |
||
5144 |
// Double Store |
|
5145 |
pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ |
|
5146 |
single_instruction; |
|
5147 |
mem : R(read); |
|
5148 |
MS : R; |
|
5149 |
%} |
|
5150 |
||
5151 |
// Special Stack Slot Float Store |
|
5152 |
pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ |
|
5153 |
single_instruction; |
|
5154 |
stkSlot : R(read); |
|
5155 |
src : C(read); |
|
5156 |
MS : R; |
|
5157 |
%} |
|
5158 |
||
5159 |
// Special Stack Slot Double Store |
|
5160 |
pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ |
|
5161 |
single_instruction; |
|
5162 |
stkSlot : R(read); |
|
5163 |
src : C(read); |
|
5164 |
MS : R; |
|
5165 |
%} |
|
5166 |
||
5167 |
// Integer Load (when sign bit propagation not needed) |
|
5168 |
pipe_class iload_mem(iRegI dst, memory mem) %{ |
|
5169 |
single_instruction; |
|
5170 |
mem : R(read); |
|
5171 |
dst : C(write); |
|
5172 |
MS : R; |
|
5173 |
%} |
|
5174 |
||
5175 |
// Integer Load from stack operand |
|
5176 |
pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ |
|
5177 |
single_instruction; |
|
5178 |
mem : R(read); |
|
5179 |
dst : C(write); |
|
5180 |
MS : R; |
|
5181 |
%} |
|
5182 |
||
5183 |
// Integer Load (when sign bit propagation or masking is needed) |
|
5184 |
pipe_class iload_mask_mem(iRegI dst, memory mem) %{ |
|
5185 |
single_instruction; |
|
5186 |
mem : R(read); |
|
5187 |
dst : M(write); |
|
5188 |
MS : R; |
|
5189 |
%} |
|
5190 |
||
5191 |
// Float Load |
|
5192 |
pipe_class floadF_mem(regF dst, memory mem) %{ |
|
5193 |
single_instruction; |
|
5194 |
mem : R(read); |
|
5195 |
dst : M(write); |
|
5196 |
MS : R; |
|
5197 |
%} |
|
5198 |
||
5199 |
// Float Load |
|
5200 |
pipe_class floadD_mem(regD dst, memory mem) %{ |
|
5201 |
instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case |
|
5202 |
mem : R(read); |
|
5203 |
dst : M(write); |
|
5204 |
MS : R; |
|
5205 |
%} |
|
5206 |
||
5207 |
// Float Load |
|
5208 |
pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ |
|
5209 |
single_instruction; |
|
5210 |
stkSlot : R(read); |
|
5211 |
dst : M(write); |
|
5212 |
MS : R; |
|
5213 |
%} |
|
5214 |
||
5215 |
// Float Load |
|
5216 |
pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ |
|
5217 |
single_instruction; |
|
5218 |
stkSlot : R(read); |
|
5219 |
dst : M(write); |
|
5220 |
MS : R; |
|
5221 |
%} |
|
5222 |
||
5223 |
// Memory Nop |
|
5224 |
pipe_class mem_nop() %{ |
|
5225 |
single_instruction; |
|
5226 |
MS : R; |
|
5227 |
%} |
|
5228 |
||
5229 |
pipe_class sethi(iRegP dst, immI src) %{ |
|
5230 |
single_instruction; |
|
5231 |
dst : E(write); |
|
5232 |
IALU : R; |
|
5233 |
%} |
|
5234 |
||
5235 |
pipe_class loadPollP(iRegP poll) %{ |
|
5236 |
single_instruction; |
|
5237 |
poll : R(read); |
|
5238 |
MS : R; |
|
5239 |
%} |
|
5240 |
||
5241 |
pipe_class br(Universe br, label labl) %{ |
|
5242 |
single_instruction_with_delay_slot; |
|
5243 |
BR : R; |
|
5244 |
%} |
|
5245 |
||
5246 |
pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ |
|
5247 |
single_instruction_with_delay_slot; |
|
5248 |
cr : E(read); |
|
5249 |
BR : R; |
|
5250 |
%} |
|
5251 |
||
5252 |
pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ |
|
5253 |
single_instruction_with_delay_slot; |
|
5254 |
op1 : E(read); |
|
5255 |
BR : R; |
|
5256 |
MS : R; |
|
5257 |
%} |
|
5258 |
||
10264 | 5259 |
// Compare and branch |
5260 |
pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ |
|
5261 |
instruction_count(2); has_delay_slot; |
|
5262 |
cr : E(write); |
|
5263 |
src1 : R(read); |
|
5264 |
src2 : R(read); |
|
5265 |
IALU : R; |
|
5266 |
BR : R; |
|
5267 |
%} |
|
5268 |
||
5269 |
// Compare and branch |
|
5270 |
pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ |
|
5271 |
instruction_count(2); has_delay_slot; |
|
5272 |
cr : E(write); |
|
5273 |
src1 : R(read); |
|
5274 |
IALU : R; |
|
5275 |
BR : R; |
|
5276 |
%} |
|
5277 |
||
5278 |
// Compare and branch using cbcond |
|
5279 |
pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ |
|
5280 |
single_instruction; |
|
5281 |
src1 : E(read); |
|
5282 |
src2 : E(read); |
|
5283 |
IALU : R; |
|
5284 |
BR : R; |
|
5285 |
%} |
|
5286 |
||
5287 |
// Compare and branch using cbcond |
|
5288 |
pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ |
|
5289 |
single_instruction; |
|
5290 |
src1 : E(read); |
|
5291 |
IALU : R; |
|
5292 |
BR : R; |
|
5293 |
%} |
|
5294 |
||
1 | 5295 |
pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5296 |
single_instruction_with_delay_slot; |
|
5297 |
cr : E(read); |
|
5298 |
BR : R; |
|
5299 |
%} |
|
5300 |
||
5301 |
pipe_class br_nop() %{ |
|
5302 |
single_instruction; |
|
5303 |
BR : R; |
|
5304 |
%} |
|
5305 |
||
5306 |
pipe_class simple_call(method meth) %{ |
|
5307 |
instruction_count(2); multiple_bundles; force_serialization; |
|
5308 |
fixed_latency(100); |
|
5309 |
BR : R(1); |
|
5310 |
MS : R(1); |
|
5311 |
A0 : R(1); |
|
5312 |
%} |
|
5313 |
||
5314 |
pipe_class compiled_call(method meth) %{ |
|
5315 |
instruction_count(1); multiple_bundles; force_serialization; |
|
5316 |
fixed_latency(100); |
|
5317 |
MS : R(1); |
|
5318 |
%} |
|
5319 |
||
5320 |
pipe_class call(method meth) %{ |
|
5321 |
instruction_count(0); multiple_bundles; force_serialization; |
|
5322 |
fixed_latency(100); |
|
5323 |
%} |
|
5324 |
||
5325 |
pipe_class tail_call(Universe ignore, label labl) %{ |
|
5326 |
single_instruction; has_delay_slot; |
|
5327 |
fixed_latency(100); |
|
5328 |
BR : R(1); |
|
5329 |
MS : R(1); |
|
5330 |
%} |
|
5331 |
||
5332 |
pipe_class ret(Universe ignore) %{ |
|
5333 |
single_instruction; has_delay_slot; |
|
5334 |
BR : R(1); |
|
5335 |
MS : R(1); |
|
5336 |
%} |
|
5337 |
||
5338 |
pipe_class ret_poll(g3RegP poll) %{ |
|
5339 |
instruction_count(3); has_delay_slot; |
|
5340 |
poll : E(read); |
|
5341 |
MS : R; |
|
5342 |
%} |
|
5343 |
||
5344 |
// The real do-nothing guy |
|
5345 |
pipe_class empty( ) %{ |
|
5346 |
instruction_count(0); |
|
5347 |
%} |
|
5348 |
||
5349 |
pipe_class long_memory_op() %{ |
|
5350 |
instruction_count(0); multiple_bundles; force_serialization; |
|
5351 |
fixed_latency(25); |
|
5352 |
MS : R(1); |
|
5353 |
%} |
|
5354 |
||
5355 |
// Check-cast |
|
5356 |
pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ |
|
5357 |
array : R(read); |
|
5358 |
match : R(read); |
|
5359 |
IALU : R(2); |
|
5360 |
BR : R(2); |
|
5361 |
MS : R; |
|
5362 |
%} |
|
5363 |
||
5364 |
// Convert FPU flags into +1,0,-1 |
|
5365 |
pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ |
|
5366 |
src1 : E(read); |
|
5367 |
src2 : E(read); |
|
5368 |
dst : E(write); |
|
5369 |
FA : R; |
|
5370 |
MS : R(2); |
|
5371 |
BR : R(2); |
|
5372 |
%} |
|
5373 |
||
5374 |
// Compare for p < q, and conditionally add y |
|
5375 |
pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ |
|
5376 |
p : E(read); |
|
5377 |
q : E(read); |
|
5378 |
y : E(read); |
|
5379 |
IALU : R(3) |
|
5380 |
%} |
|
5381 |
||
5382 |
// Perform a compare, then move conditionally in a branch delay slot. |
|
5383 |
pipe_class min_max( iRegI src2, iRegI srcdst ) %{ |
|
5384 |
src2 : E(read); |
|
5385 |
srcdst : E(read); |
|
5386 |
IALU : R; |
|
5387 |
BR : R; |
|
5388 |
%} |
|
5389 |
||
5390 |
// Define the class for the Nop node |
|
5391 |
define %{ |
|
5392 |
MachNop = ialu_nop; |
|
5393 |
%} |
|
5394 |
||
5395 |
%} |
|
5396 |
||
5397 |
//----------INSTRUCTIONS------------------------------------------------------- |
|
5398 |
||
5399 |
//------------Special Stack Slot instructions - no match rules----------------- |
|
5400 |
instruct stkI_to_regF(regF dst, stackSlotI src) %{ |
|
5401 |
// No match rule to avoid chain rule match. |
|
5402 |
effect(DEF dst, USE src); |
|
5403 |
ins_cost(MEMORY_REF_COST); |
|
5404 |
size(4); |
|
5405 |
format %{ "LDF $src,$dst\t! stkI to regF" %} |
|
5406 |
opcode(Assembler::ldf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5407 |
ins_encode(simple_form3_mem_reg(src, dst)); |
1 | 5408 |
ins_pipe(floadF_stk); |
5409 |
%} |
|
5410 |
||
5411 |
instruct stkL_to_regD(regD dst, stackSlotL src) %{ |
|
5412 |
// No match rule to avoid chain rule match. |
|
5413 |
effect(DEF dst, USE src); |
|
5414 |
ins_cost(MEMORY_REF_COST); |
|
5415 |
size(4); |
|
5416 |
format %{ "LDDF $src,$dst\t! stkL to regD" %} |
|
5417 |
opcode(Assembler::lddf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5418 |
ins_encode(simple_form3_mem_reg(src, dst)); |
1 | 5419 |
ins_pipe(floadD_stk); |
5420 |
%} |
|
5421 |
||
5422 |
instruct regF_to_stkI(stackSlotI dst, regF src) %{ |
|
5423 |
// No match rule to avoid chain rule match. |
|
5424 |
effect(DEF dst, USE src); |
|
5425 |
ins_cost(MEMORY_REF_COST); |
|
5426 |
size(4); |
|
5427 |
format %{ "STF $src,$dst\t! regF to stkI" %} |
|
5428 |
opcode(Assembler::stf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5429 |
ins_encode(simple_form3_mem_reg(dst, src)); |
1 | 5430 |
ins_pipe(fstoreF_stk_reg); |
5431 |
%} |
|
5432 |
||
5433 |
instruct regD_to_stkL(stackSlotL dst, regD src) %{ |
|
5434 |
// No match rule to avoid chain rule match. |
|
5435 |
effect(DEF dst, USE src); |
|
5436 |
ins_cost(MEMORY_REF_COST); |
|
5437 |
size(4); |
|
5438 |
format %{ "STDF $src,$dst\t! regD to stkL" %} |
|
5439 |
opcode(Assembler::stdf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5440 |
ins_encode(simple_form3_mem_reg(dst, src)); |
1 | 5441 |
ins_pipe(fstoreD_stk_reg); |
5442 |
%} |
|
5443 |
||
5444 |
instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ |
|
5445 |
effect(DEF dst, USE src); |
|
5446 |
ins_cost(MEMORY_REF_COST*2); |
|
5447 |
size(8); |
|
5448 |
format %{ "STW $src,$dst.hi\t! long\n\t" |
|
5449 |
"STW R_G0,$dst.lo" %} |
|
5450 |
opcode(Assembler::stw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5451 |
ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
1 | 5452 |
ins_pipe(lstoreI_stk_reg); |
5453 |
%} |
|
5454 |
||
5455 |
instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ |
|
5456 |
// No match rule to avoid chain rule match. |
|
5457 |
effect(DEF dst, USE src); |
|
5458 |
ins_cost(MEMORY_REF_COST); |
|
5459 |
size(4); |
|
5460 |
format %{ "STX $src,$dst\t! regL to stkD" %} |
|
5461 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5462 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 5463 |
ins_pipe(istore_stk_reg); |
5464 |
%} |
|
5465 |
||
5466 |
//---------- Chain stack slots between similar types -------- |
|
5467 |
||
5468 |
// Load integer from stack slot |
|
5469 |
instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ |
|
5470 |
match(Set dst src); |
|
5471 |
ins_cost(MEMORY_REF_COST); |
|
5472 |
||
5473 |
size(4); |
|
5474 |
format %{ "LDUW $src,$dst\t!stk" %} |
|
5475 |
opcode(Assembler::lduw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5476 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 5477 |
ins_pipe(iload_mem); |
5478 |
%} |
|
5479 |
||
5480 |
// Store integer to stack slot |
|
5481 |
instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ |
|
5482 |
match(Set dst src); |
|
5483 |
ins_cost(MEMORY_REF_COST); |
|
5484 |
||
5485 |
size(4); |
|
5486 |
format %{ "STW $src,$dst\t!stk" %} |
|
5487 |
opcode(Assembler::stw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5488 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 5489 |
ins_pipe(istore_mem_reg); |
5490 |
%} |
|
5491 |
||
5492 |
// Load long from stack slot |
|
5493 |
instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ |
|
5494 |
match(Set dst src); |
|
5495 |
||
5496 |
ins_cost(MEMORY_REF_COST); |
|
5497 |
size(4); |
|
5498 |
format %{ "LDX $src,$dst\t! long" %} |
|
5499 |
opcode(Assembler::ldx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5500 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 5501 |
ins_pipe(iload_mem); |
5502 |
%} |
|
5503 |
||
5504 |
// Store long to stack slot |
|
5505 |
instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ |
|
5506 |
match(Set dst src); |
|
5507 |
||
5508 |
ins_cost(MEMORY_REF_COST); |
|
5509 |
size(4); |
|
5510 |
format %{ "STX $src,$dst\t! long" %} |
|
5511 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5512 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 5513 |
ins_pipe(istore_mem_reg); |
5514 |
%} |
|
5515 |
||
5516 |
#ifdef _LP64 |
|
5517 |
// Load pointer from stack slot, 64-bit encoding |
|
5518 |
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ |
|
5519 |
match(Set dst src); |
|
5520 |
ins_cost(MEMORY_REF_COST); |
|
5521 |
size(4); |
|
5522 |
format %{ "LDX $src,$dst\t!ptr" %} |
|
5523 |
opcode(Assembler::ldx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5524 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 5525 |
ins_pipe(iload_mem); |
5526 |
%} |
|
5527 |
||
5528 |
// Store pointer to stack slot |
|
5529 |
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ |
|
5530 |
match(Set dst src); |
|
5531 |
ins_cost(MEMORY_REF_COST); |
|
5532 |
size(4); |
|
5533 |
format %{ "STX $src,$dst\t!ptr" %} |
|
5534 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5535 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 5536 |
ins_pipe(istore_mem_reg); |
5537 |
%} |
|
5538 |
#else // _LP64 |
|
5539 |
// Load pointer from stack slot, 32-bit encoding |
|
5540 |
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ |
|
5541 |
match(Set dst src); |
|
5542 |
ins_cost(MEMORY_REF_COST); |
|
5543 |
format %{ "LDUW $src,$dst\t!ptr" %} |
|
5544 |
opcode(Assembler::lduw_op3, Assembler::ldst_op); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5545 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 5546 |
ins_pipe(iload_mem); |
5547 |
%} |
|
5548 |
||
5549 |
// Store pointer to stack slot |
|
5550 |
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ |
|
5551 |
match(Set dst src); |
|
5552 |
ins_cost(MEMORY_REF_COST); |
|
5553 |
format %{ "STW $src,$dst\t!ptr" %} |
|
5554 |
opcode(Assembler::stw_op3, Assembler::ldst_op); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5555 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 5556 |
ins_pipe(istore_mem_reg); |
5557 |
%} |
|
5558 |
#endif // _LP64 |
|
5559 |
||
5560 |
//------------Special Nop instructions for bundling - no match rules----------- |
|
5561 |
// Nop using the A0 functional unit |
|
5562 |
instruct Nop_A0() %{ |
|
5563 |
ins_cost(0); |
|
5564 |
||
5565 |
format %{ "NOP ! Alu Pipeline" %} |
|
5566 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
5567 |
ins_encode( form2_nop() ); |
|
5568 |
ins_pipe(ialu_nop_A0); |
|
5569 |
%} |
|
5570 |
||
5571 |
// Nop using the A1 functional unit |
|
5572 |
instruct Nop_A1( ) %{ |
|
5573 |
ins_cost(0); |
|
5574 |
||
5575 |
format %{ "NOP ! Alu Pipeline" %} |
|
5576 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
5577 |
ins_encode( form2_nop() ); |
|
5578 |
ins_pipe(ialu_nop_A1); |
|
5579 |
%} |
|
5580 |
||
5581 |
// Nop using the memory functional unit |
|
5582 |
instruct Nop_MS( ) %{ |
|
5583 |
ins_cost(0); |
|
5584 |
||
5585 |
format %{ "NOP ! Memory Pipeline" %} |
|
5586 |
ins_encode( emit_mem_nop ); |
|
5587 |
ins_pipe(mem_nop); |
|
5588 |
%} |
|
5589 |
||
5590 |
// Nop using the floating add functional unit |
|
5591 |
instruct Nop_FA( ) %{ |
|
5592 |
ins_cost(0); |
|
5593 |
||
5594 |
format %{ "NOP ! Floating Add Pipeline" %} |
|
5595 |
ins_encode( emit_fadd_nop ); |
|
5596 |
ins_pipe(fadd_nop); |
|
5597 |
%} |
|
5598 |
||
5599 |
// Nop using the branch functional unit |
|
5600 |
instruct Nop_BR( ) %{ |
|
5601 |
ins_cost(0); |
|
5602 |
||
5603 |
format %{ "NOP ! Branch Pipeline" %} |
|
5604 |
ins_encode( emit_br_nop ); |
|
5605 |
ins_pipe(br_nop); |
|
5606 |
%} |
|
5607 |
||
5608 |
//----------Load/Store/Move Instructions--------------------------------------- |
|
5609 |
//----------Load Instructions-------------------------------------------------- |
|
5610 |
// Load Byte (8bit signed) |
|
5611 |
instruct loadB(iRegI dst, memory mem) %{ |
|
5612 |
match(Set dst (LoadB mem)); |
|
5613 |
ins_cost(MEMORY_REF_COST); |
|
5614 |
||
5615 |
size(4); |
|
2150 | 5616 |
format %{ "LDSB $mem,$dst\t! byte" %} |
2571 | 5617 |
ins_encode %{ |
5618 |
__ ldsb($mem$$Address, $dst$$Register); |
|
5619 |
%} |
|
2150 | 5620 |
ins_pipe(iload_mask_mem); |
5621 |
%} |
|
5622 |
||
5623 |
// Load Byte (8bit signed) into a Long Register |
|
5624 |
instruct loadB2L(iRegL dst, memory mem) %{ |
|
5625 |
match(Set dst (ConvI2L (LoadB mem))); |
|
5626 |
ins_cost(MEMORY_REF_COST); |
|
5627 |
||
5628 |
size(4); |
|
5629 |
format %{ "LDSB $mem,$dst\t! byte -> long" %} |
|
2571 | 5630 |
ins_encode %{ |
5631 |
__ ldsb($mem$$Address, $dst$$Register); |
|
5632 |
%} |
|
1 | 5633 |
ins_pipe(iload_mask_mem); |
5634 |
%} |
|
5635 |
||
2150 | 5636 |
// Load Unsigned Byte (8bit UNsigned) into an int reg |
5637 |
instruct loadUB(iRegI dst, memory mem) %{ |
|
5638 |
match(Set dst (LoadUB mem)); |
|
1 | 5639 |
ins_cost(MEMORY_REF_COST); |
5640 |
||
5641 |
size(4); |
|
2150 | 5642 |
format %{ "LDUB $mem,$dst\t! ubyte" %} |
2571 | 5643 |
ins_encode %{ |
5644 |
__ ldub($mem$$Address, $dst$$Register); |
|
5645 |
%} |
|
3177 | 5646 |
ins_pipe(iload_mem); |
2150 | 5647 |
%} |
5648 |
||
5649 |
// Load Unsigned Byte (8bit UNsigned) into a Long Register |
|
5650 |
instruct loadUB2L(iRegL dst, memory mem) %{ |
|
5651 |
match(Set dst (ConvI2L (LoadUB mem))); |
|
5652 |
ins_cost(MEMORY_REF_COST); |
|
5653 |
||
5654 |
size(4); |
|
5655 |
format %{ "LDUB $mem,$dst\t! ubyte -> long" %} |
|
2571 | 5656 |
ins_encode %{ |
5657 |
__ ldub($mem$$Address, $dst$$Register); |
|
5658 |
%} |
|
3177 | 5659 |
ins_pipe(iload_mem); |
5660 |
%} |
|
5661 |
||
5662 |
// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register |
|
5663 |
instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ |
|
5664 |
match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); |
|
5665 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5666 |
||
5667 |
size(2*4); |
|
5668 |
format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" |
|
5669 |
"AND $dst,$mask,$dst" %} |
|
5670 |
ins_encode %{ |
|
5671 |
__ ldub($mem$$Address, $dst$$Register); |
|
5672 |
__ and3($dst$$Register, $mask$$constant, $dst$$Register); |
|
5673 |
%} |
|
5674 |
ins_pipe(iload_mem); |
|
1 | 5675 |
%} |
5676 |
||
2150 | 5677 |
// Load Short (16bit signed) |
5678 |
instruct loadS(iRegI dst, memory mem) %{ |
|
5679 |
match(Set dst (LoadS mem)); |
|
5680 |
ins_cost(MEMORY_REF_COST); |
|
5681 |
||
5682 |
size(4); |
|
5683 |
format %{ "LDSH $mem,$dst\t! short" %} |
|
2571 | 5684 |
ins_encode %{ |
5685 |
__ ldsh($mem$$Address, $dst$$Register); |
|
5686 |
%} |
|
2150 | 5687 |
ins_pipe(iload_mask_mem); |
5688 |
%} |
|
5689 |
||
2872 | 5690 |
// Load Short (16 bit signed) to Byte (8 bit signed) |
5691 |
instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ |
|
5692 |
match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
|
5693 |
ins_cost(MEMORY_REF_COST); |
|
5694 |
||
5695 |
size(4); |
|
5696 |
||
5697 |
format %{ "LDSB $mem+1,$dst\t! short -> byte" %} |
|
5698 |
ins_encode %{ |
|
5699 |
__ ldsb($mem$$Address, $dst$$Register, 1); |
|
5700 |
%} |
|
5701 |
ins_pipe(iload_mask_mem); |
|
5702 |
%} |
|
5703 |
||
2150 | 5704 |
// Load Short (16bit signed) into a Long Register |
5705 |
instruct loadS2L(iRegL dst, memory mem) %{ |
|
5706 |
match(Set dst (ConvI2L (LoadS mem))); |
|
1 | 5707 |
ins_cost(MEMORY_REF_COST); |
5708 |
||
5709 |
size(4); |
|
2150 | 5710 |
format %{ "LDSH $mem,$dst\t! short -> long" %} |
2571 | 5711 |
ins_encode %{ |
5712 |
__ ldsh($mem$$Address, $dst$$Register); |
|
5713 |
%} |
|
2150 | 5714 |
ins_pipe(iload_mask_mem); |
5715 |
%} |
|
5716 |
||
5717 |
// Load Unsigned Short/Char (16bit UNsigned) |
|
5718 |
instruct loadUS(iRegI dst, memory mem) %{ |
|
5719 |
match(Set dst (LoadUS mem)); |
|
5720 |
ins_cost(MEMORY_REF_COST); |
|
5721 |
||
5722 |
size(4); |
|
5723 |
format %{ "LDUH $mem,$dst\t! ushort/char" %} |
|
2571 | 5724 |
ins_encode %{ |
5725 |
__ lduh($mem$$Address, $dst$$Register); |
|
5726 |
%} |
|
3177 | 5727 |
ins_pipe(iload_mem); |
1 | 5728 |
%} |
5729 |
||
2872 | 5730 |
// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5731 |
instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ |
|
5732 |
match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
|
5733 |
ins_cost(MEMORY_REF_COST); |
|
5734 |
||
5735 |
size(4); |
|
5736 |
format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} |
|
5737 |
ins_encode %{ |
|
5738 |
__ ldsb($mem$$Address, $dst$$Register, 1); |
|
5739 |
%} |
|
5740 |
ins_pipe(iload_mask_mem); |
|
5741 |
%} |
|
5742 |
||
2022
28ce8115a91d
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
2015
diff
changeset
|
5743 |
// Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
2150 | 5744 |
instruct loadUS2L(iRegL dst, memory mem) %{ |
5745 |
match(Set dst (ConvI2L (LoadUS mem))); |
|
1 | 5746 |
ins_cost(MEMORY_REF_COST); |
5747 |
||
5748 |
size(4); |
|
2150 | 5749 |
format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
2571 | 5750 |
ins_encode %{ |
5751 |
__ lduh($mem$$Address, $dst$$Register); |
|
5752 |
%} |
|
3177 | 5753 |
ins_pipe(iload_mem); |
5754 |
%} |
|
5755 |
||
5756 |
// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register |
|
5757 |
instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ |
|
5758 |
match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
|
5759 |
ins_cost(MEMORY_REF_COST); |
|
5760 |
||
5761 |
size(4); |
|
5762 |
format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} |
|
5763 |
ins_encode %{ |
|
5764 |
__ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE |
|
5765 |
%} |
|
5766 |
ins_pipe(iload_mem); |
|
5767 |
%} |
|
5768 |
||
5769 |
// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register |
|
5770 |
instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ |
|
5771 |
match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
|
5772 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5773 |
||
5774 |
size(2*4); |
|
5775 |
format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" |
|
5776 |
"AND $dst,$mask,$dst" %} |
|
5777 |
ins_encode %{ |
|
5778 |
Register Rdst = $dst$$Register; |
|
5779 |
__ lduh($mem$$Address, Rdst); |
|
5780 |
__ and3(Rdst, $mask$$constant, Rdst); |
|
5781 |
%} |
|
5782 |
ins_pipe(iload_mem); |
|
5783 |
%} |
|
5784 |
||
5785 |
// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register |
|
5786 |
instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ |
|
5787 |
match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); |
|
5788 |
effect(TEMP dst, TEMP tmp); |
|
5789 |
ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
|
5790 |
||
5791 |
format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
|
5792 |
"SET $mask,$tmp\n\t" |
|
5793 |
"AND $dst,$tmp,$dst" %} |
|
5794 |
ins_encode %{ |
|
5795 |
Register Rdst = $dst$$Register; |
|
5796 |
Register Rtmp = $tmp$$Register; |
|
5797 |
__ lduh($mem$$Address, Rdst); |
|
5798 |
__ set($mask$$constant, Rtmp); |
|
5799 |
__ and3(Rdst, Rtmp, Rdst); |
|
5800 |
%} |
|
5801 |
ins_pipe(iload_mem); |
|
1 | 5802 |
%} |
5803 |
||
5804 |
// Load Integer |
|
5805 |
instruct loadI(iRegI dst, memory mem) %{ |
|
5806 |
match(Set dst (LoadI mem)); |
|
5807 |
ins_cost(MEMORY_REF_COST); |
|
2150 | 5808 |
|
5809 |
size(4); |
|
5810 |
format %{ "LDUW $mem,$dst\t! int" %} |
|
2571 | 5811 |
ins_encode %{ |
5812 |
__ lduw($mem$$Address, $dst$$Register); |
|
5813 |
%} |
|
2150 | 5814 |
ins_pipe(iload_mem); |
5815 |
%} |
|
5816 |
||
2872 | 5817 |
// Load Integer to Byte (8 bit signed) |
5818 |
instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ |
|
5819 |
match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
|
5820 |
ins_cost(MEMORY_REF_COST); |
|
5821 |
||
5822 |
size(4); |
|
5823 |
||
5824 |
format %{ "LDSB $mem+3,$dst\t! int -> byte" %} |
|
5825 |
ins_encode %{ |
|
5826 |
__ ldsb($mem$$Address, $dst$$Register, 3); |
|
5827 |
%} |
|
5828 |
ins_pipe(iload_mask_mem); |
|
5829 |
%} |
|
5830 |
||
5831 |
// Load Integer to Unsigned Byte (8 bit UNsigned) |
|
5832 |
instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ |
|
5833 |
match(Set dst (AndI (LoadI mem) mask)); |
|
5834 |
ins_cost(MEMORY_REF_COST); |
|
5835 |
||
5836 |
size(4); |
|
5837 |
||
5838 |
format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} |
|
5839 |
ins_encode %{ |
|
5840 |
__ ldub($mem$$Address, $dst$$Register, 3); |
|
5841 |
%} |
|
5842 |
ins_pipe(iload_mask_mem); |
|
5843 |
%} |
|
5844 |
||
5845 |
// Load Integer to Short (16 bit signed) |
|
5846 |
instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ |
|
5847 |
match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
|
5848 |
ins_cost(MEMORY_REF_COST); |
|
5849 |
||
5850 |
size(4); |
|
5851 |
||
5852 |
format %{ "LDSH $mem+2,$dst\t! int -> short" %} |
|
5853 |
ins_encode %{ |
|
5854 |
__ ldsh($mem$$Address, $dst$$Register, 2); |
|
5855 |
%} |
|
5856 |
ins_pipe(iload_mask_mem); |
|
5857 |
%} |
|
5858 |
||
5859 |
// Load Integer to Unsigned Short (16 bit UNsigned) |
|
5860 |
instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ |
|
5861 |
match(Set dst (AndI (LoadI mem) mask)); |
|
5862 |
ins_cost(MEMORY_REF_COST); |
|
5863 |
||
5864 |
size(4); |
|
5865 |
||
5866 |
format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} |
|
5867 |
ins_encode %{ |
|
5868 |
__ lduh($mem$$Address, $dst$$Register, 2); |
|
5869 |
%} |
|
5870 |
ins_pipe(iload_mask_mem); |
|
5871 |
%} |
|
5872 |
||
2150 | 5873 |
// Load Integer into a Long Register |
5874 |
instruct loadI2L(iRegL dst, memory mem) %{ |
|
5875 |
match(Set dst (ConvI2L (LoadI mem))); |
|
5876 |
ins_cost(MEMORY_REF_COST); |
|
5877 |
||
5878 |
size(4); |
|
5879 |
format %{ "LDSW $mem,$dst\t! int -> long" %} |
|
2571 | 5880 |
ins_encode %{ |
5881 |
__ ldsw($mem$$Address, $dst$$Register); |
|
5882 |
%} |
|
3177 | 5883 |
ins_pipe(iload_mask_mem); |
5884 |
%} |
|
5885 |
||
5886 |
// Load Integer with mask 0xFF into a Long Register |
|
5887 |
instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ |
|
5888 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
|
5889 |
ins_cost(MEMORY_REF_COST); |
|
5890 |
||
5891 |
size(4); |
|
5892 |
format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} |
|
5893 |
ins_encode %{ |
|
5894 |
__ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE |
|
5895 |
%} |
|
5896 |
ins_pipe(iload_mem); |
|
5897 |
%} |
|
5898 |
||
5899 |
// Load Integer with mask 0xFFFF into a Long Register |
|
5900 |
instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ |
|
5901 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
|
5902 |
ins_cost(MEMORY_REF_COST); |
|
5903 |
||
5904 |
size(4); |
|
5905 |
format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} |
|
5906 |
ins_encode %{ |
|
5907 |
__ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE |
|
5908 |
%} |
|
5909 |
ins_pipe(iload_mem); |
|
5910 |
%} |
|
5911 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5912 |
// Load Integer with a 12-bit mask into a Long Register |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5913 |
instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ |
3177 | 5914 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5915 |
ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5916 |
||
5917 |
size(2*4); |
|
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5918 |
format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" |
3177 | 5919 |
"AND $dst,$mask,$dst" %} |
5920 |
ins_encode %{ |
|
5921 |
Register Rdst = $dst$$Register; |
|
5922 |
__ lduw($mem$$Address, Rdst); |
|
5923 |
__ and3(Rdst, $mask$$constant, Rdst); |
|
5924 |
%} |
|
5925 |
ins_pipe(iload_mem); |
|
5926 |
%} |
|
5927 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5928 |
// Load Integer with a 31-bit mask into a Long Register |
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5929 |
instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ |
3177 | 5930 |
match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5931 |
effect(TEMP dst, TEMP tmp); |
|
5932 |
ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); |
|
5933 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
5934 |
format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" |
3177 | 5935 |
"SET $mask,$tmp\n\t" |
5936 |
"AND $dst,$tmp,$dst" %} |
|
5937 |
ins_encode %{ |
|
5938 |
Register Rdst = $dst$$Register; |
|
5939 |
Register Rtmp = $tmp$$Register; |
|
5940 |
__ lduw($mem$$Address, Rdst); |
|
5941 |
__ set($mask$$constant, Rtmp); |
|
5942 |
__ and3(Rdst, Rtmp, Rdst); |
|
5943 |
%} |
|
2150 | 5944 |
ins_pipe(iload_mem); |
5945 |
%} |
|
5946 |
||
5947 |
// Load Unsigned Integer into a Long Register |
|
13970 | 5948 |
instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
5949 |
match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); |
|
2150 | 5950 |
ins_cost(MEMORY_REF_COST); |
5951 |
||
5952 |
size(4); |
|
5953 |
format %{ "LDUW $mem,$dst\t! uint -> long" %} |
|
2571 | 5954 |
ins_encode %{ |
5955 |
__ lduw($mem$$Address, $dst$$Register); |
|
5956 |
%} |
|
1 | 5957 |
ins_pipe(iload_mem); |
5958 |
%} |
|
5959 |
||
5960 |
// Load Long - aligned |
|
5961 |
instruct loadL(iRegL dst, memory mem ) %{ |
|
5962 |
match(Set dst (LoadL mem)); |
|
5963 |
ins_cost(MEMORY_REF_COST); |
|
2150 | 5964 |
|
1 | 5965 |
size(4); |
5966 |
format %{ "LDX $mem,$dst\t! long" %} |
|
2571 | 5967 |
ins_encode %{ |
5968 |
__ ldx($mem$$Address, $dst$$Register); |
|
5969 |
%} |
|
1 | 5970 |
ins_pipe(iload_mem); |
5971 |
%} |
|
5972 |
||
5973 |
// Load Long - UNaligned |
|
5974 |
instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ |
|
5975 |
match(Set dst (LoadL_unaligned mem)); |
|
5976 |
effect(KILL tmp); |
|
5977 |
ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); |
|
5978 |
size(16); |
|
5979 |
format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" |
|
5980 |
"\tLDUW $mem ,$dst\n" |
|
5981 |
"\tSLLX #32, $dst, $dst\n" |
|
5982 |
"\tOR $dst, R_O7, $dst" %} |
|
5983 |
opcode(Assembler::lduw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5984 |
ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
1 | 5985 |
ins_pipe(iload_mem); |
5986 |
%} |
|
5987 |
||
5988 |
// Load Range |
|
5989 |
instruct loadRange(iRegI dst, memory mem) %{ |
|
5990 |
match(Set dst (LoadRange mem)); |
|
5991 |
ins_cost(MEMORY_REF_COST); |
|
5992 |
||
5993 |
size(4); |
|
5994 |
format %{ "LDUW $mem,$dst\t! range" %} |
|
5995 |
opcode(Assembler::lduw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
5996 |
ins_encode(simple_form3_mem_reg( mem, dst ) ); |
1 | 5997 |
ins_pipe(iload_mem); |
5998 |
%} |
|
5999 |
||
6000 |
// Load Integer into %f register (for fitos/fitod) |
|
6001 |
instruct loadI_freg(regF dst, memory mem) %{ |
|
6002 |
match(Set dst (LoadI mem)); |
|
6003 |
ins_cost(MEMORY_REF_COST); |
|
6004 |
size(4); |
|
6005 |
||
6006 |
format %{ "LDF $mem,$dst\t! for fitos/fitod" %} |
|
6007 |
opcode(Assembler::ldf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6008 |
ins_encode(simple_form3_mem_reg( mem, dst ) ); |
1 | 6009 |
ins_pipe(floadF_mem); |
6010 |
%} |
|
6011 |
||
6012 |
// Load Pointer |
|
6013 |
instruct loadP(iRegP dst, memory mem) %{ |
|
6014 |
match(Set dst (LoadP mem)); |
|
6015 |
ins_cost(MEMORY_REF_COST); |
|
6016 |
size(4); |
|
6017 |
||
6018 |
#ifndef _LP64 |
|
6019 |
format %{ "LDUW $mem,$dst\t! ptr" %} |
|
2571 | 6020 |
ins_encode %{ |
6021 |
__ lduw($mem$$Address, $dst$$Register); |
|
6022 |
%} |
|
1 | 6023 |
#else |
6024 |
format %{ "LDX $mem,$dst\t! ptr" %} |
|
2571 | 6025 |
ins_encode %{ |
6026 |
__ ldx($mem$$Address, $dst$$Register); |
|
6027 |
%} |
|
1 | 6028 |
#endif |
6029 |
ins_pipe(iload_mem); |
|
6030 |
%} |
|
6031 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6032 |
// Load Compressed Pointer |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6033 |
instruct loadN(iRegN dst, memory mem) %{ |
2571 | 6034 |
match(Set dst (LoadN mem)); |
6035 |
ins_cost(MEMORY_REF_COST); |
|
6036 |
size(4); |
|
6037 |
||
6038 |
format %{ "LDUW $mem,$dst\t! compressed ptr" %} |
|
6039 |
ins_encode %{ |
|
6040 |
__ lduw($mem$$Address, $dst$$Register); |
|
6041 |
%} |
|
6042 |
ins_pipe(iload_mem); |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6043 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6044 |
|
1 | 6045 |
// Load Klass Pointer |
6046 |
instruct loadKlass(iRegP dst, memory mem) %{ |
|
6047 |
match(Set dst (LoadKlass mem)); |
|
6048 |
ins_cost(MEMORY_REF_COST); |
|
6049 |
size(4); |
|
6050 |
||
6051 |
#ifndef _LP64 |
|
6052 |
format %{ "LDUW $mem,$dst\t! klass ptr" %} |
|
2571 | 6053 |
ins_encode %{ |
6054 |
__ lduw($mem$$Address, $dst$$Register); |
|
6055 |
%} |
|
1 | 6056 |
#else |
6057 |
format %{ "LDX $mem,$dst\t! klass ptr" %} |
|
2571 | 6058 |
ins_encode %{ |
6059 |
__ ldx($mem$$Address, $dst$$Register); |
|
6060 |
%} |
|
1 | 6061 |
#endif |
6062 |
ins_pipe(iload_mem); |
|
6063 |
%} |
|
6064 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6065 |
// Load narrow Klass Pointer |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6066 |
instruct loadNKlass(iRegN dst, memory mem) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6067 |
match(Set dst (LoadNKlass mem)); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6068 |
ins_cost(MEMORY_REF_COST); |
591
04d2e26e6d69
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
590
diff
changeset
|
6069 |
size(4); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6070 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6071 |
format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6072 |
ins_encode %{ |
2571 | 6073 |
__ lduw($mem$$Address, $dst$$Register); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6074 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6075 |
ins_pipe(iload_mem); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6076 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6077 |
|
1 | 6078 |
// Load Double |
6079 |
instruct loadD(regD dst, memory mem) %{ |
|
6080 |
match(Set dst (LoadD mem)); |
|
6081 |
ins_cost(MEMORY_REF_COST); |
|
6082 |
||
6083 |
size(4); |
|
6084 |
format %{ "LDDF $mem,$dst" %} |
|
6085 |
opcode(Assembler::lddf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6086 |
ins_encode(simple_form3_mem_reg( mem, dst ) ); |
1 | 6087 |
ins_pipe(floadD_mem); |
6088 |
%} |
|
6089 |
||
6090 |
// Load Double - UNaligned |
|
6091 |
instruct loadD_unaligned(regD_low dst, memory mem ) %{ |
|
6092 |
match(Set dst (LoadD_unaligned mem)); |
|
6093 |
ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); |
|
6094 |
size(8); |
|
6095 |
format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" |
|
6096 |
"\tLDF $mem+4,$dst.lo\t!" %} |
|
6097 |
opcode(Assembler::ldf_op3); |
|
6098 |
ins_encode( form3_mem_reg_double_unaligned( mem, dst )); |
|
6099 |
ins_pipe(iload_mem); |
|
6100 |
%} |
|
6101 |
||
6102 |
// Load Float |
|
6103 |
instruct loadF(regF dst, memory mem) %{ |
|
6104 |
match(Set dst (LoadF mem)); |
|
6105 |
ins_cost(MEMORY_REF_COST); |
|
6106 |
||
6107 |
size(4); |
|
6108 |
format %{ "LDF $mem,$dst" %} |
|
6109 |
opcode(Assembler::ldf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6110 |
ins_encode(simple_form3_mem_reg( mem, dst ) ); |
1 | 6111 |
ins_pipe(floadF_mem); |
6112 |
%} |
|
6113 |
||
6114 |
// Load Constant |
|
6115 |
instruct loadConI( iRegI dst, immI src ) %{ |
|
6116 |
match(Set dst src); |
|
6117 |
ins_cost(DEFAULT_COST * 3/2); |
|
6118 |
format %{ "SET $src,$dst" %} |
|
6119 |
ins_encode( Set32(src, dst) ); |
|
6120 |
ins_pipe(ialu_hi_lo_reg); |
|
6121 |
%} |
|
6122 |
||
6123 |
instruct loadConI13( iRegI dst, immI13 src ) %{ |
|
6124 |
match(Set dst src); |
|
6125 |
||
6126 |
size(4); |
|
6127 |
format %{ "MOV $src,$dst" %} |
|
6128 |
ins_encode( Set13( src, dst ) ); |
|
6129 |
ins_pipe(ialu_imm); |
|
6130 |
%} |
|
6131 |
||
7433 | 6132 |
#ifndef _LP64 |
6133 |
instruct loadConP(iRegP dst, immP con) %{ |
|
6134 |
match(Set dst con); |
|
6135 |
ins_cost(DEFAULT_COST * 3/2); |
|
6136 |
format %{ "SET $con,$dst\t!ptr" %} |
|
6137 |
ins_encode %{ |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6138 |
relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
7433 | 6139 |
intptr_t val = $con$$constant; |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6140 |
if (constant_reloc == relocInfo::oop_type) { |
7433 | 6141 |
__ set_oop_constant((jobject) val, $dst$$Register); |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6142 |
} else if (constant_reloc == relocInfo::metadata_type) { |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6143 |
__ set_metadata_constant((Metadata*)val, $dst$$Register); |
7433 | 6144 |
} else { // non-oop pointers, e.g. card mark base, heap top |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6145 |
assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6146 |
__ set(val, $dst$$Register); |
7433 | 6147 |
} |
6148 |
%} |
|
6149 |
ins_pipe(loadConP); |
|
6150 |
%} |
|
6151 |
#else |
|
6152 |
instruct loadConP_set(iRegP dst, immP_set con) %{ |
|
6153 |
match(Set dst con); |
|
1 | 6154 |
ins_cost(DEFAULT_COST * 3/2); |
7433 | 6155 |
format %{ "SET $con,$dst\t! ptr" %} |
6156 |
ins_encode %{ |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6157 |
relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
7433 | 6158 |
intptr_t val = $con$$constant; |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6159 |
if (constant_reloc == relocInfo::oop_type) { |
7433 | 6160 |
__ set_oop_constant((jobject) val, $dst$$Register); |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6161 |
} else if (constant_reloc == relocInfo::metadata_type) { |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6162 |
__ set_metadata_constant((Metadata*)val, $dst$$Register); |
7433 | 6163 |
} else { // non-oop pointers, e.g. card mark base, heap top |
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6164 |
assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13104
diff
changeset
|
6165 |
__ set(val, $dst$$Register); |
7433 | 6166 |
} |
6167 |
%} |
|
1 | 6168 |
ins_pipe(loadConP); |
7433 | 6169 |
%} |
6170 |
||
6171 |
instruct loadConP_load(iRegP dst, immP_load con) %{ |
|
6172 |
match(Set dst con); |
|
6173 |
ins_cost(MEMORY_REF_COST); |
|
6174 |
format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} |
|
6175 |
ins_encode %{ |
|
7700
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6176 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6177 |
__ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6178 |
%} |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6179 |
ins_pipe(loadConP); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6180 |
%} |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6181 |
|
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6182 |
instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6183 |
match(Set dst con); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6184 |
ins_cost(DEFAULT_COST * 3/2); |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6185 |
format %{ "SET $con,$dst\t! non-oop ptr" %} |
3252c02e23b8
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
7437
diff
changeset
|
6186 |
ins_encode %{ |
25933
ea319da89b55
8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents:
25741
diff
changeset
|
6187 |
if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { |
ea319da89b55
8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents:
25741
diff
changeset
|
6188 |
__ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); |
ea319da89b55
8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents:
25741
diff
changeset
|
6189 |
} else { |
ea319da89b55
8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents:
25741
diff
changeset
|
6190 |
__ set($con$$constant, $dst$$Register); |
ea319da89b55
8029443: 'assert(klass->is_loader_alive(_is_alive)) failed: must be alive' during VM_CollectForMetadataAllocation
thartmann
parents:
25741
diff
changeset
|
6191 |
} |
7433 | 6192 |
%} |
6193 |
ins_pipe(loadConP); |
|
6194 |
%} |
|
6195 |
#endif // _LP64 |
|
1 | 6196 |
|
6197 |
instruct loadConP0(iRegP dst, immP0 src) %{ |
|
6198 |
match(Set dst src); |
|
6199 |
||
6200 |
size(4); |
|
6201 |
format %{ "CLR $dst\t!ptr" %} |
|
7433 | 6202 |
ins_encode %{ |
6203 |
__ clr($dst$$Register); |
|
6204 |
%} |
|
1 | 6205 |
ins_pipe(ialu_imm); |
6206 |
%} |
|
6207 |
||
6208 |
instruct loadConP_poll(iRegP dst, immP_poll src) %{ |
|
6209 |
match(Set dst src); |
|
6210 |
ins_cost(DEFAULT_COST); |
|
6211 |
format %{ "SET $src,$dst\t!ptr" %} |
|
6212 |
ins_encode %{ |
|
2571 | 6213 |
AddressLiteral polling_page(os::get_polling_page()); |
6214 |
__ sethi(polling_page, reg_to_register_object($dst$$reg)); |
|
1 | 6215 |
%} |
6216 |
ins_pipe(loadConP_poll); |
|
6217 |
%} |
|
6218 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6219 |
instruct loadConN0(iRegN dst, immN0 src) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6220 |
match(Set dst src); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6221 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6222 |
size(4); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6223 |
format %{ "CLR $dst\t! compressed NULL ptr" %} |
7433 | 6224 |
ins_encode %{ |
6225 |
__ clr($dst$$Register); |
|
6226 |
%} |
|
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6227 |
ins_pipe(ialu_imm); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6228 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6229 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6230 |
instruct loadConN(iRegN dst, immN src) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6231 |
match(Set dst src); |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6232 |
ins_cost(DEFAULT_COST * 3/2); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6233 |
format %{ "SET $src,$dst\t! compressed ptr" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6234 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6235 |
Register dst = $dst$$Register; |
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6236 |
__ set_narrow_oop((jobject)$src$$constant, dst); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6237 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6238 |
ins_pipe(ialu_hi_lo_reg); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6239 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6240 |
|
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6241 |
instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6242 |
match(Set dst src); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6243 |
ins_cost(DEFAULT_COST * 3/2); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6244 |
format %{ "SET $src,$dst\t! compressed klass ptr" %} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6245 |
ins_encode %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6246 |
Register dst = $dst$$Register; |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6247 |
__ set_narrow_klass((Klass*)$src$$constant, dst); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6248 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6249 |
ins_pipe(ialu_hi_lo_reg); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6250 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6251 |
|
7433 | 6252 |
// Materialize long value (predicated by immL_cheap). |
6253 |
instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ |
|
6254 |
match(Set dst con); |
|
1 | 6255 |
effect(KILL tmp); |
7433 | 6256 |
ins_cost(DEFAULT_COST * 3); |
6257 |
format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} |
|
6258 |
ins_encode %{ |
|
6259 |
__ set64($con$$constant, $dst$$Register, $tmp$$Register); |
|
6260 |
%} |
|
6261 |
ins_pipe(loadConL); |
|
6262 |
%} |
|
6263 |
||
6264 |
// Load long value from constant table (predicated by immL_expensive). |
|
6265 |
instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ |
|
6266 |
match(Set dst con); |
|
6267 |
ins_cost(MEMORY_REF_COST); |
|
6268 |
format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} |
|
6269 |
ins_encode %{ |
|
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6270 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6271 |
__ ldx($constanttablebase, con_offset, $dst$$Register); |
7433 | 6272 |
%} |
1 | 6273 |
ins_pipe(loadConL); |
6274 |
%} |
|
6275 |
||
6276 |
instruct loadConL0( iRegL dst, immL0 src ) %{ |
|
6277 |
match(Set dst src); |
|
6278 |
ins_cost(DEFAULT_COST); |
|
6279 |
size(4); |
|
6280 |
format %{ "CLR $dst\t! long" %} |
|
6281 |
ins_encode( Set13( src, dst ) ); |
|
6282 |
ins_pipe(ialu_imm); |
|
6283 |
%} |
|
6284 |
||
6285 |
instruct loadConL13( iRegL dst, immL13 src ) %{ |
|
6286 |
match(Set dst src); |
|
6287 |
ins_cost(DEFAULT_COST * 2); |
|
6288 |
||
6289 |
size(4); |
|
6290 |
format %{ "MOV $src,$dst\t! long" %} |
|
6291 |
ins_encode( Set13( src, dst ) ); |
|
6292 |
ins_pipe(ialu_imm); |
|
6293 |
%} |
|
6294 |
||
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6295 |
instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
7433 | 6296 |
match(Set dst con); |
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6297 |
effect(KILL tmp); |
7433 | 6298 |
format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
2571 | 6299 |
ins_encode %{ |
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6300 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6301 |
__ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
2571 | 6302 |
%} |
1 | 6303 |
ins_pipe(loadConFD); |
6304 |
%} |
|
6305 |
||
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6306 |
instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
7433 | 6307 |
match(Set dst con); |
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6308 |
effect(KILL tmp); |
7433 | 6309 |
format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
2571 | 6310 |
ins_encode %{ |
2576
a3babdbbca51
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
2571
diff
changeset
|
6311 |
// XXX This is a quick fix for 6833573. |
7433 | 6312 |
//__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6313 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
6314 |
__ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
2571 | 6315 |
%} |
1 | 6316 |
ins_pipe(loadConFD); |
6317 |
%} |
|
6318 |
||
6319 |
// Prefetch instructions. |
|
6320 |
// Must be safe to execute with invalid address (cannot fault). |
|
6321 |
||
6322 |
instruct prefetchr( memory mem ) %{ |
|
6323 |
match( PrefetchRead mem ); |
|
6324 |
ins_cost(MEMORY_REF_COST); |
|
10267 | 6325 |
size(4); |
1 | 6326 |
|
6327 |
format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} |
|
6328 |
opcode(Assembler::prefetch_op3); |
|
6329 |
ins_encode( form3_mem_prefetch_read( mem ) ); |
|
6330 |
ins_pipe(iload_mem); |
|
6331 |
%} |
|
6332 |
||
6333 |
instruct prefetchw( memory mem ) %{ |
|
6334 |
match( PrefetchWrite mem ); |
|
6335 |
ins_cost(MEMORY_REF_COST); |
|
10267 | 6336 |
size(4); |
1 | 6337 |
|
6338 |
format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} |
|
6339 |
opcode(Assembler::prefetch_op3); |
|
6340 |
ins_encode( form3_mem_prefetch_write( mem ) ); |
|
6341 |
ins_pipe(iload_mem); |
|
6342 |
%} |
|
6343 |
||
10267 | 6344 |
// Prefetch instructions for allocation. |
6345 |
||
6346 |
instruct prefetchAlloc( memory mem ) %{ |
|
6347 |
predicate(AllocatePrefetchInstr == 0); |
|
6348 |
match( PrefetchAllocation mem ); |
|
6349 |
ins_cost(MEMORY_REF_COST); |
|
6350 |
size(4); |
|
6351 |
||
6352 |
format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} |
|
6353 |
opcode(Assembler::prefetch_op3); |
|
6354 |
ins_encode( form3_mem_prefetch_write( mem ) ); |
|
6355 |
ins_pipe(iload_mem); |
|
6356 |
%} |
|
6357 |
||
6358 |
// Use BIS instruction to prefetch for allocation. |
|
6359 |
// Could fault, need space at the end of TLAB. |
|
6360 |
instruct prefetchAlloc_bis( iRegP dst ) %{ |
|
6361 |
predicate(AllocatePrefetchInstr == 1); |
|
6362 |
match( PrefetchAllocation dst ); |
|
6363 |
ins_cost(MEMORY_REF_COST); |
|
6364 |
size(4); |
|
6365 |
||
6366 |
format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} |
|
6367 |
ins_encode %{ |
|
6368 |
__ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); |
|
5251
f86f7a86d761
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
5025
diff
changeset
|
6369 |
%} |
f86f7a86d761
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
5025
diff
changeset
|
6370 |
ins_pipe(istore_mem_reg); |
f86f7a86d761
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
5025
diff
changeset
|
6371 |
%} |
1 | 6372 |
|
10267 | 6373 |
// Next code is used for finding next cache line address to prefetch. |
6374 |
#ifndef _LP64 |
|
6375 |
instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ |
|
6376 |
match(Set dst (CastX2P (AndI (CastP2X src) mask))); |
|
6377 |
ins_cost(DEFAULT_COST); |
|
6378 |
size(4); |
|
6379 |
||
6380 |
format %{ "AND $src,$mask,$dst\t! next cache line address" %} |
|
6381 |
ins_encode %{ |
|
6382 |
__ and3($src$$Register, $mask$$constant, $dst$$Register); |
|
6383 |
%} |
|
6384 |
ins_pipe(ialu_reg_imm); |
|
6385 |
%} |
|
6386 |
#else |
|
6387 |
instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ |
|
6388 |
match(Set dst (CastX2P (AndL (CastP2X src) mask))); |
|
6389 |
ins_cost(DEFAULT_COST); |
|
6390 |
size(4); |
|
6391 |
||
6392 |
format %{ "AND $src,$mask,$dst\t! next cache line address" %} |
|
6393 |
ins_encode %{ |
|
6394 |
__ and3($src$$Register, $mask$$constant, $dst$$Register); |
|
6395 |
%} |
|
6396 |
ins_pipe(ialu_reg_imm); |
|
6397 |
%} |
|
6398 |
#endif |
|
6399 |
||
1 | 6400 |
//----------Store Instructions------------------------------------------------- |
6401 |
// Store Byte |
|
6402 |
instruct storeB(memory mem, iRegI src) %{ |
|
6403 |
match(Set mem (StoreB mem src)); |
|
6404 |
ins_cost(MEMORY_REF_COST); |
|
6405 |
||
6406 |
size(4); |
|
6407 |
format %{ "STB $src,$mem\t! byte" %} |
|
6408 |
opcode(Assembler::stb_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6409 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6410 |
ins_pipe(istore_mem_reg); |
6411 |
%} |
|
6412 |
||
6413 |
instruct storeB0(memory mem, immI0 src) %{ |
|
6414 |
match(Set mem (StoreB mem src)); |
|
6415 |
ins_cost(MEMORY_REF_COST); |
|
6416 |
||
6417 |
size(4); |
|
6418 |
format %{ "STB $src,$mem\t! byte" %} |
|
6419 |
opcode(Assembler::stb_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6420 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6421 |
ins_pipe(istore_mem_zero); |
6422 |
%} |
|
6423 |
||
6424 |
instruct storeCM0(memory mem, immI0 src) %{ |
|
6425 |
match(Set mem (StoreCM mem src)); |
|
6426 |
ins_cost(MEMORY_REF_COST); |
|
6427 |
||
6428 |
size(4); |
|
6429 |
format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} |
|
6430 |
opcode(Assembler::stb_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6431 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6432 |
ins_pipe(istore_mem_zero); |
6433 |
%} |
|
6434 |
||
6435 |
// Store Char/Short |
|
6436 |
instruct storeC(memory mem, iRegI src) %{ |
|
6437 |
match(Set mem (StoreC mem src)); |
|
6438 |
ins_cost(MEMORY_REF_COST); |
|
6439 |
||
6440 |
size(4); |
|
6441 |
format %{ "STH $src,$mem\t! short" %} |
|
6442 |
opcode(Assembler::sth_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6443 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6444 |
ins_pipe(istore_mem_reg); |
6445 |
%} |
|
6446 |
||
6447 |
instruct storeC0(memory mem, immI0 src) %{ |
|
6448 |
match(Set mem (StoreC mem src)); |
|
6449 |
ins_cost(MEMORY_REF_COST); |
|
6450 |
||
6451 |
size(4); |
|
6452 |
format %{ "STH $src,$mem\t! short" %} |
|
6453 |
opcode(Assembler::sth_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6454 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6455 |
ins_pipe(istore_mem_zero); |
6456 |
%} |
|
6457 |
||
6458 |
// Store Integer |
|
6459 |
instruct storeI(memory mem, iRegI src) %{ |
|
6460 |
match(Set mem (StoreI mem src)); |
|
6461 |
ins_cost(MEMORY_REF_COST); |
|
6462 |
||
6463 |
size(4); |
|
6464 |
format %{ "STW $src,$mem" %} |
|
6465 |
opcode(Assembler::stw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6466 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6467 |
ins_pipe(istore_mem_reg); |
6468 |
%} |
|
6469 |
||
6470 |
// Store Long |
|
6471 |
instruct storeL(memory mem, iRegL src) %{ |
|
6472 |
match(Set mem (StoreL mem src)); |
|
6473 |
ins_cost(MEMORY_REF_COST); |
|
6474 |
size(4); |
|
6475 |
format %{ "STX $src,$mem\t! long" %} |
|
6476 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6477 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6478 |
ins_pipe(istore_mem_reg); |
6479 |
%} |
|
6480 |
||
6481 |
instruct storeI0(memory mem, immI0 src) %{ |
|
6482 |
match(Set mem (StoreI mem src)); |
|
6483 |
ins_cost(MEMORY_REF_COST); |
|
6484 |
||
6485 |
size(4); |
|
6486 |
format %{ "STW $src,$mem" %} |
|
6487 |
opcode(Assembler::stw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6488 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6489 |
ins_pipe(istore_mem_zero); |
6490 |
%} |
|
6491 |
||
6492 |
instruct storeL0(memory mem, immL0 src) %{ |
|
6493 |
match(Set mem (StoreL mem src)); |
|
6494 |
ins_cost(MEMORY_REF_COST); |
|
6495 |
||
6496 |
size(4); |
|
6497 |
format %{ "STX $src,$mem" %} |
|
6498 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6499 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6500 |
ins_pipe(istore_mem_zero); |
6501 |
%} |
|
6502 |
||
6503 |
// Store Integer from float register (used after fstoi) |
|
6504 |
instruct storeI_Freg(memory mem, regF src) %{ |
|
6505 |
match(Set mem (StoreI mem src)); |
|
6506 |
ins_cost(MEMORY_REF_COST); |
|
6507 |
||
6508 |
size(4); |
|
6509 |
format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} |
|
6510 |
opcode(Assembler::stf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6511 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6512 |
ins_pipe(fstoreF_mem_reg); |
6513 |
%} |
|
6514 |
||
6515 |
// Store Pointer |
|
6516 |
instruct storeP(memory dst, sp_ptr_RegP src) %{ |
|
6517 |
match(Set dst (StoreP dst src)); |
|
6518 |
ins_cost(MEMORY_REF_COST); |
|
6519 |
size(4); |
|
6520 |
||
6521 |
#ifndef _LP64 |
|
6522 |
format %{ "STW $src,$dst\t! ptr" %} |
|
6523 |
opcode(Assembler::stw_op3, 0, REGP_OP); |
|
6524 |
#else |
|
6525 |
format %{ "STX $src,$dst\t! ptr" %} |
|
6526 |
opcode(Assembler::stx_op3, 0, REGP_OP); |
|
6527 |
#endif |
|
6528 |
ins_encode( form3_mem_reg( dst, src ) ); |
|
6529 |
ins_pipe(istore_mem_spORreg); |
|
6530 |
%} |
|
6531 |
||
6532 |
instruct storeP0(memory dst, immP0 src) %{ |
|
6533 |
match(Set dst (StoreP dst src)); |
|
6534 |
ins_cost(MEMORY_REF_COST); |
|
6535 |
size(4); |
|
6536 |
||
6537 |
#ifndef _LP64 |
|
6538 |
format %{ "STW $src,$dst\t! ptr" %} |
|
6539 |
opcode(Assembler::stw_op3, 0, REGP_OP); |
|
6540 |
#else |
|
6541 |
format %{ "STX $src,$dst\t! ptr" %} |
|
6542 |
opcode(Assembler::stx_op3, 0, REGP_OP); |
|
6543 |
#endif |
|
6544 |
ins_encode( form3_mem_reg( dst, R_G0 ) ); |
|
6545 |
ins_pipe(istore_mem_zero); |
|
6546 |
%} |
|
6547 |
||
360
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
6548 |
// Store Compressed Pointer |
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
6549 |
instruct storeN(memory dst, iRegN src) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6550 |
match(Set dst (StoreN dst src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6551 |
ins_cost(MEMORY_REF_COST); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6552 |
size(4); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6553 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6554 |
format %{ "STW $src,$dst\t! compressed ptr" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6555 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6556 |
Register base = as_Register($dst$$base); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6557 |
Register index = as_Register($dst$$index); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6558 |
Register src = $src$$Register; |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6559 |
if (index != G0) { |
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
6560 |
__ stw(src, base, index); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6561 |
} else { |
21d113ecbf6a
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coleenp
parents:
254
diff
changeset
|
6562 |
__ stw(src, base, $dst$$disp); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6563 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6564 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6565 |
ins_pipe(istore_mem_spORreg); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6566 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6567 |
|
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6568 |
instruct storeNKlass(memory dst, iRegN src) %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6569 |
match(Set dst (StoreNKlass dst src)); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6570 |
ins_cost(MEMORY_REF_COST); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6571 |
size(4); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6572 |
|
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6573 |
format %{ "STW $src,$dst\t! compressed klass ptr" %} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6574 |
ins_encode %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6575 |
Register base = as_Register($dst$$base); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6576 |
Register index = as_Register($dst$$index); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6577 |
Register src = $src$$Register; |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6578 |
if (index != G0) { |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6579 |
__ stw(src, base, index); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6580 |
} else { |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6581 |
__ stw(src, base, $dst$$disp); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6582 |
} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6583 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6584 |
ins_pipe(istore_mem_spORreg); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6585 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6586 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6587 |
instruct storeN0(memory dst, immN0 src) %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6588 |
match(Set dst (StoreN dst src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6589 |
ins_cost(MEMORY_REF_COST); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6590 |
size(4); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6591 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6592 |
format %{ "STW $src,$dst\t! compressed ptr" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6593 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6594 |
Register base = as_Register($dst$$base); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6595 |
Register index = as_Register($dst$$index); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6596 |
if (index != G0) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6597 |
__ stw(0, base, index); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6598 |
} else { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6599 |
__ stw(0, base, $dst$$disp); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6600 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6601 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6602 |
ins_pipe(istore_mem_zero); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6603 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6604 |
|
1 | 6605 |
// Store Double |
6606 |
instruct storeD( memory mem, regD src) %{ |
|
6607 |
match(Set mem (StoreD mem src)); |
|
6608 |
ins_cost(MEMORY_REF_COST); |
|
6609 |
||
6610 |
size(4); |
|
6611 |
format %{ "STDF $src,$mem" %} |
|
6612 |
opcode(Assembler::stdf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6613 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6614 |
ins_pipe(fstoreD_mem_reg); |
6615 |
%} |
|
6616 |
||
6617 |
instruct storeD0( memory mem, immD0 src) %{ |
|
6618 |
match(Set mem (StoreD mem src)); |
|
6619 |
ins_cost(MEMORY_REF_COST); |
|
6620 |
||
6621 |
size(4); |
|
6622 |
format %{ "STX $src,$mem" %} |
|
6623 |
opcode(Assembler::stx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6624 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6625 |
ins_pipe(fstoreD_mem_zero); |
6626 |
%} |
|
6627 |
||
6628 |
// Store Float |
|
6629 |
instruct storeF( memory mem, regF src) %{ |
|
6630 |
match(Set mem (StoreF mem src)); |
|
6631 |
ins_cost(MEMORY_REF_COST); |
|
6632 |
||
6633 |
size(4); |
|
6634 |
format %{ "STF $src,$mem" %} |
|
6635 |
opcode(Assembler::stf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6636 |
ins_encode(simple_form3_mem_reg( mem, src ) ); |
1 | 6637 |
ins_pipe(fstoreF_mem_reg); |
6638 |
%} |
|
6639 |
||
6640 |
instruct storeF0( memory mem, immF0 src) %{ |
|
6641 |
match(Set mem (StoreF mem src)); |
|
6642 |
ins_cost(MEMORY_REF_COST); |
|
6643 |
||
6644 |
size(4); |
|
6645 |
format %{ "STW $src,$mem\t! storeF0" %} |
|
6646 |
opcode(Assembler::stw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6647 |
ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
1 | 6648 |
ins_pipe(fstoreF_mem_zero); |
6649 |
%} |
|
6650 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6651 |
// Convert oop pointer into compressed form |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6652 |
instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
767
64fb1fd7186d
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
608
diff
changeset
|
6653 |
predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6654 |
match(Set dst (EncodeP src)); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6655 |
format %{ "encode_heap_oop $src, $dst" %} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6656 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6657 |
__ encode_heap_oop($src$$Register, $dst$$Register); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6658 |
%} |
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
6659 |
ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6660 |
ins_pipe(ialu_reg); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6661 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6662 |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6663 |
instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
767
64fb1fd7186d
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
608
diff
changeset
|
6664 |
predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6665 |
match(Set dst (EncodeP src)); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6666 |
format %{ "encode_heap_oop_not_null $src, $dst" %} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6667 |
ins_encode %{ |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6668 |
__ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6669 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6670 |
ins_pipe(ialu_reg); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6671 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6672 |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6673 |
instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
608
fe8c5fbbc54e
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
607
diff
changeset
|
6674 |
predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
fe8c5fbbc54e
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
607
diff
changeset
|
6675 |
n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6676 |
match(Set dst (DecodeN src)); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6677 |
format %{ "decode_heap_oop $src, $dst" %} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6678 |
ins_encode %{ |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6679 |
__ decode_heap_oop($src$$Register, $dst$$Register); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6680 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6681 |
ins_pipe(ialu_reg); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6682 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6683 |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6684 |
instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
608
fe8c5fbbc54e
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
607
diff
changeset
|
6685 |
predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
fe8c5fbbc54e
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
607
diff
changeset
|
6686 |
n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6687 |
match(Set dst (DecodeN src)); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6688 |
format %{ "decode_heap_oop_not_null $src, $dst" %} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6689 |
ins_encode %{ |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6690 |
__ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6691 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6692 |
ins_pipe(ialu_reg); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6693 |
%} |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
6694 |
|
13969
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6695 |
instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6696 |
match(Set dst (EncodePKlass src)); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6697 |
format %{ "encode_klass_not_null $src, $dst" %} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6698 |
ins_encode %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6699 |
__ encode_klass_not_null($src$$Register, $dst$$Register); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6700 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6701 |
ins_pipe(ialu_reg); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6702 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6703 |
|
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6704 |
instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6705 |
match(Set dst (DecodeNKlass src)); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6706 |
format %{ "decode_klass_not_null $src, $dst" %} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6707 |
ins_encode %{ |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6708 |
__ decode_klass_not_null($src$$Register, $dst$$Register); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6709 |
%} |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6710 |
ins_pipe(ialu_reg); |
d2a189b83b87
7054512: Compress class pointers after perm gen removal
roland
parents:
13930
diff
changeset
|
6711 |
%} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
6712 |
|
1 | 6713 |
//----------MemBar Instructions----------------------------------------------- |
6714 |
// Memory barrier flavors |
|
6715 |
||
6716 |
instruct membar_acquire() %{ |
|
6717 |
match(MemBarAcquire); |
|
22855
d637fd28a6c3
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
22851
diff
changeset
|
6718 |
match(LoadFence); |
1 | 6719 |
ins_cost(4*MEMORY_REF_COST); |
6720 |
||
6721 |
size(0); |
|
6722 |
format %{ "MEMBAR-acquire" %} |
|
6723 |
ins_encode( enc_membar_acquire ); |
|
6724 |
ins_pipe(long_memory_op); |
|
6725 |
%} |
|
6726 |
||
6727 |
instruct membar_acquire_lock() %{ |
|
10262
c5f62d314bee
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
10255
diff
changeset
|
6728 |
match(MemBarAcquireLock); |
1 | 6729 |
ins_cost(0); |
6730 |
||
6731 |
size(0); |
|
6732 |
format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} |
|
6733 |
ins_encode( ); |
|
6734 |
ins_pipe(empty); |
|
6735 |
%} |
|
6736 |
||
6737 |
instruct membar_release() %{ |
|
6738 |
match(MemBarRelease); |
|
22855
d637fd28a6c3
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
22851
diff
changeset
|
6739 |
match(StoreFence); |
1 | 6740 |
ins_cost(4*MEMORY_REF_COST); |
6741 |
||
6742 |
size(0); |
|
6743 |
format %{ "MEMBAR-release" %} |
|
6744 |
ins_encode( enc_membar_release ); |
|
6745 |
ins_pipe(long_memory_op); |
|
6746 |
%} |
|
6747 |
||
6748 |
instruct membar_release_lock() %{ |
|
10262
c5f62d314bee
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
10255
diff
changeset
|
6749 |
match(MemBarReleaseLock); |
1 | 6750 |
ins_cost(0); |
6751 |
||
6752 |
size(0); |
|
6753 |
format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} |
|
6754 |
ins_encode( ); |
|
6755 |
ins_pipe(empty); |
|
6756 |
%} |
|
6757 |
||
6758 |
instruct membar_volatile() %{ |
|
6759 |
match(MemBarVolatile); |
|
6760 |
ins_cost(4*MEMORY_REF_COST); |
|
6761 |
||
6762 |
size(4); |
|
6763 |
format %{ "MEMBAR-volatile" %} |
|
6764 |
ins_encode( enc_membar_volatile ); |
|
6765 |
ins_pipe(long_memory_op); |
|
6766 |
%} |
|
6767 |
||
6768 |
instruct unnecessary_membar_volatile() %{ |
|
6769 |
match(MemBarVolatile); |
|
6770 |
predicate(Matcher::post_store_load_barrier(n)); |
|
6771 |
ins_cost(0); |
|
6772 |
||
6773 |
size(0); |
|
6774 |
format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} |
|
6775 |
ins_encode( ); |
|
6776 |
ins_pipe(empty); |
|
6777 |
%} |
|
6778 |
||
11431
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6779 |
instruct membar_storestore() %{ |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6780 |
match(MemBarStoreStore); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6781 |
ins_cost(0); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6782 |
|
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6783 |
size(0); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6784 |
format %{ "!MEMBAR-storestore (empty encoding)" %} |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6785 |
ins_encode( ); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6786 |
ins_pipe(empty); |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6787 |
%} |
5ca3a19e559a
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
11197
diff
changeset
|
6788 |
|
1 | 6789 |
//----------Register Move Instructions----------------------------------------- |
6790 |
instruct roundDouble_nop(regD dst) %{ |
|
6791 |
match(Set dst (RoundDouble dst)); |
|
6792 |
ins_cost(0); |
|
6793 |
// SPARC results are already "rounded" (i.e., normal-format IEEE) |
|
6794 |
ins_encode( ); |
|
6795 |
ins_pipe(empty); |
|
6796 |
%} |
|
6797 |
||
6798 |
||
6799 |
instruct roundFloat_nop(regF dst) %{ |
|
6800 |
match(Set dst (RoundFloat dst)); |
|
6801 |
ins_cost(0); |
|
6802 |
// SPARC results are already "rounded" (i.e., normal-format IEEE) |
|
6803 |
ins_encode( ); |
|
6804 |
ins_pipe(empty); |
|
6805 |
%} |
|
6806 |
||
6807 |
||
6808 |
// Cast Index to Pointer for unsafe natives |
|
6809 |
instruct castX2P(iRegX src, iRegP dst) %{ |
|
6810 |
match(Set dst (CastX2P src)); |
|
6811 |
||
6812 |
format %{ "MOV $src,$dst\t! IntX->Ptr" %} |
|
6813 |
ins_encode( form3_g0_rs2_rd_move( src, dst ) ); |
|
6814 |
ins_pipe(ialu_reg); |
|
6815 |
%} |
|
6816 |
||
6817 |
// Cast Pointer to Index for unsafe natives |
|
6818 |
instruct castP2X(iRegP src, iRegX dst) %{ |
|
6819 |
match(Set dst (CastP2X src)); |
|
6820 |
||
6821 |
format %{ "MOV $src,$dst\t! Ptr->IntX" %} |
|
6822 |
ins_encode( form3_g0_rs2_rd_move( src, dst ) ); |
|
6823 |
ins_pipe(ialu_reg); |
|
6824 |
%} |
|
6825 |
||
6826 |
instruct stfSSD(stackSlotD stkSlot, regD src) %{ |
|
6827 |
// %%%% TO DO: Tell the coalescer that this kind of node is a copy! |
|
6828 |
match(Set stkSlot src); // chain rule |
|
6829 |
ins_cost(MEMORY_REF_COST); |
|
6830 |
format %{ "STDF $src,$stkSlot\t!stk" %} |
|
6831 |
opcode(Assembler::stdf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6832 |
ins_encode(simple_form3_mem_reg(stkSlot, src)); |
1 | 6833 |
ins_pipe(fstoreD_stk_reg); |
6834 |
%} |
|
6835 |
||
6836 |
instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ |
|
6837 |
// %%%% TO DO: Tell the coalescer that this kind of node is a copy! |
|
6838 |
match(Set dst stkSlot); // chain rule |
|
6839 |
ins_cost(MEMORY_REF_COST); |
|
6840 |
format %{ "LDDF $stkSlot,$dst\t!stk" %} |
|
6841 |
opcode(Assembler::lddf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6842 |
ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
1 | 6843 |
ins_pipe(floadD_stk); |
6844 |
%} |
|
6845 |
||
6846 |
instruct stfSSF(stackSlotF stkSlot, regF src) %{ |
|
6847 |
// %%%% TO DO: Tell the coalescer that this kind of node is a copy! |
|
6848 |
match(Set stkSlot src); // chain rule |
|
6849 |
ins_cost(MEMORY_REF_COST); |
|
6850 |
format %{ "STF $src,$stkSlot\t!stk" %} |
|
6851 |
opcode(Assembler::stf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
6852 |
ins_encode(simple_form3_mem_reg(stkSlot, src)); |
1 | 6853 |
ins_pipe(fstoreF_stk_reg); |
6854 |
%} |
|
6855 |
||
6856 |
//----------Conditional Move--------------------------------------------------- |
|
6857 |
// Conditional move |
|
6858 |
instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ |
|
6859 |
match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); |
|
6860 |
ins_cost(150); |
|
6861 |
format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
6862 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
6863 |
ins_pipe(ialu_reg); |
|
6864 |
%} |
|
6865 |
||
6866 |
instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ |
|
6867 |
match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); |
|
6868 |
ins_cost(140); |
|
6869 |
format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
6870 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
6871 |
ins_pipe(ialu_imm); |
|
6872 |
%} |
|
6873 |
||
6874 |
instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ |
|
6875 |
match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
|
6876 |
ins_cost(150); |
|
6877 |
size(4); |
|
6878 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
|
6879 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
6880 |
ins_pipe(ialu_reg); |
|
6881 |
%} |
|
6882 |
||
6883 |
instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ |
|
6884 |
match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
|
6885 |
ins_cost(140); |
|
6886 |
size(4); |
|
6887 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
|
6888 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
6889 |
ins_pipe(ialu_imm); |
|
6890 |
%} |
|
6891 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6892 |
instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
1 | 6893 |
match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6894 |
ins_cost(150); |
|
6895 |
size(4); |
|
6896 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
|
6897 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
6898 |
ins_pipe(ialu_reg); |
|
6899 |
%} |
|
6900 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6901 |
instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
1 | 6902 |
match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6903 |
ins_cost(140); |
|
6904 |
size(4); |
|
6905 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
|
6906 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
6907 |
ins_pipe(ialu_imm); |
|
6908 |
%} |
|
6909 |
||
6910 |
instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ |
|
6911 |
match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); |
|
6912 |
ins_cost(150); |
|
6913 |
size(4); |
|
6914 |
format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
6915 |
ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
6916 |
ins_pipe(ialu_reg); |
|
6917 |
%} |
|
6918 |
||
6919 |
instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ |
|
6920 |
match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); |
|
6921 |
ins_cost(140); |
|
6922 |
size(4); |
|
6923 |
format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
6924 |
ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); |
|
6925 |
ins_pipe(ialu_imm); |
|
6926 |
%} |
|
6927 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6928 |
// Conditional move for RegN. Only cmov(reg,reg). |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6929 |
instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6930 |
match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6931 |
ins_cost(150); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6932 |
format %{ "MOV$cmp $pcc,$src,$dst" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6933 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6934 |
ins_pipe(ialu_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6935 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6936 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6937 |
// This instruction also works with CmpN so we don't need cmovNN_reg. |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6938 |
instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6939 |
match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6940 |
ins_cost(150); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6941 |
size(4); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6942 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6943 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6944 |
ins_pipe(ialu_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6945 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6946 |
|
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6947 |
// This instruction also works with CmpN so we don't need cmovNN_reg. |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6948 |
instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6949 |
match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6950 |
ins_cost(150); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6951 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6952 |
format %{ "MOV$cmp $icc,$src,$dst" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6953 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6954 |
ins_pipe(ialu_reg); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6955 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6956 |
|
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6957 |
instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6958 |
match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6959 |
ins_cost(150); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6960 |
size(4); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6961 |
format %{ "MOV$cmp $fcc,$src,$dst" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6962 |
ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6963 |
ins_pipe(ialu_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6964 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6965 |
|
1 | 6966 |
// Conditional move |
6967 |
instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ |
|
6968 |
match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); |
|
6969 |
ins_cost(150); |
|
6970 |
format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
|
6971 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
6972 |
ins_pipe(ialu_reg); |
|
6973 |
%} |
|
6974 |
||
6975 |
instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ |
|
6976 |
match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); |
|
6977 |
ins_cost(140); |
|
6978 |
format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} |
|
6979 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
6980 |
ins_pipe(ialu_imm); |
|
6981 |
%} |
|
6982 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
6983 |
// This instruction also works with CmpN so we don't need cmovPN_reg. |
1 | 6984 |
instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6985 |
match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
6986 |
ins_cost(150); |
|
6987 |
||
6988 |
size(4); |
|
6989 |
format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
6990 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
6991 |
ins_pipe(ialu_reg); |
|
6992 |
%} |
|
6993 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6994 |
instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6995 |
match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6996 |
ins_cost(150); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6997 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6998 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
6999 |
format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7000 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7001 |
ins_pipe(ialu_reg); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7002 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7003 |
|
1 | 7004 |
instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
7005 |
match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
7006 |
ins_cost(140); |
|
7007 |
||
7008 |
size(4); |
|
7009 |
format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
7010 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
7011 |
ins_pipe(ialu_imm); |
|
7012 |
%} |
|
7013 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7014 |
instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7015 |
match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7016 |
ins_cost(140); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7017 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7018 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7019 |
format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7020 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7021 |
ins_pipe(ialu_imm); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7022 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7023 |
|
1 | 7024 |
instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
7025 |
match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); |
|
7026 |
ins_cost(150); |
|
7027 |
size(4); |
|
7028 |
format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
7029 |
ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
7030 |
ins_pipe(ialu_imm); |
|
7031 |
%} |
|
7032 |
||
7033 |
instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ |
|
7034 |
match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); |
|
7035 |
ins_cost(140); |
|
7036 |
size(4); |
|
7037 |
format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
7038 |
ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); |
|
7039 |
ins_pipe(ialu_imm); |
|
7040 |
%} |
|
7041 |
||
7042 |
// Conditional move |
|
7043 |
instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ |
|
7044 |
match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); |
|
7045 |
ins_cost(150); |
|
7046 |
opcode(0x101); |
|
7047 |
format %{ "FMOVD$cmp $pcc,$src,$dst" %} |
|
7048 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
7049 |
ins_pipe(int_conditional_float_move); |
|
7050 |
%} |
|
7051 |
||
7052 |
instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ |
|
7053 |
match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
7054 |
ins_cost(150); |
|
7055 |
||
7056 |
size(4); |
|
7057 |
format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
7058 |
opcode(0x101); |
|
7059 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
7060 |
ins_pipe(int_conditional_float_move); |
|
7061 |
%} |
|
7062 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7063 |
instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7064 |
match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7065 |
ins_cost(150); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7066 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7067 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7068 |
format %{ "FMOVS$cmp $icc,$src,$dst" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7069 |
opcode(0x101); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7070 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7071 |
ins_pipe(int_conditional_float_move); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7072 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7073 |
|
1 | 7074 |
// Conditional move, |
7075 |
instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ |
|
7076 |
match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); |
|
7077 |
ins_cost(150); |
|
7078 |
size(4); |
|
7079 |
format %{ "FMOVF$cmp $fcc,$src,$dst" %} |
|
7080 |
opcode(0x1); |
|
7081 |
ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); |
|
7082 |
ins_pipe(int_conditional_double_move); |
|
7083 |
%} |
|
7084 |
||
7085 |
// Conditional move |
|
7086 |
instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ |
|
7087 |
match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); |
|
7088 |
ins_cost(150); |
|
7089 |
size(4); |
|
7090 |
opcode(0x102); |
|
7091 |
format %{ "FMOVD$cmp $pcc,$src,$dst" %} |
|
7092 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
7093 |
ins_pipe(int_conditional_double_move); |
|
7094 |
%} |
|
7095 |
||
7096 |
instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ |
|
7097 |
match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
7098 |
ins_cost(150); |
|
7099 |
||
7100 |
size(4); |
|
7101 |
format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
7102 |
opcode(0x102); |
|
7103 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
7104 |
ins_pipe(int_conditional_double_move); |
|
7105 |
%} |
|
7106 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7107 |
instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7108 |
match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7109 |
ins_cost(150); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7110 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7111 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7112 |
format %{ "FMOVD$cmp $icc,$src,$dst" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7113 |
opcode(0x102); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7114 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7115 |
ins_pipe(int_conditional_double_move); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7116 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7117 |
|
1 | 7118 |
// Conditional move, |
7119 |
instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ |
|
7120 |
match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); |
|
7121 |
ins_cost(150); |
|
7122 |
size(4); |
|
7123 |
format %{ "FMOVD$cmp $fcc,$src,$dst" %} |
|
7124 |
opcode(0x2); |
|
7125 |
ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); |
|
7126 |
ins_pipe(int_conditional_double_move); |
|
7127 |
%} |
|
7128 |
||
7129 |
// Conditional move |
|
7130 |
instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ |
|
7131 |
match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); |
|
7132 |
ins_cost(150); |
|
7133 |
format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} |
|
7134 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
7135 |
ins_pipe(ialu_reg); |
|
7136 |
%} |
|
7137 |
||
7138 |
instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ |
|
7139 |
match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); |
|
7140 |
ins_cost(140); |
|
7141 |
format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} |
|
7142 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
7143 |
ins_pipe(ialu_imm); |
|
7144 |
%} |
|
7145 |
||
7146 |
instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ |
|
7147 |
match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
7148 |
ins_cost(150); |
|
7149 |
||
7150 |
size(4); |
|
7151 |
format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
7152 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
7153 |
ins_pipe(ialu_reg); |
|
7154 |
%} |
|
7155 |
||
7156 |
||
4589
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7157 |
instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7158 |
match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7159 |
ins_cost(150); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7160 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7161 |
size(4); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7162 |
format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7163 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7164 |
ins_pipe(ialu_reg); |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7165 |
%} |
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7166 |
|
2621c7da5a88
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
4566
diff
changeset
|
7167 |
|
1 | 7168 |
instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7169 |
match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); |
|
7170 |
ins_cost(150); |
|
7171 |
||
7172 |
size(4); |
|
7173 |
format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} |
|
7174 |
ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
7175 |
ins_pipe(ialu_reg); |
|
7176 |
%} |
|
7177 |
||
7178 |
||
7179 |
||
7180 |
//----------OS and Locking Instructions---------------------------------------- |
|
7181 |
||
7182 |
// This name is KNOWN by the ADLC and cannot be changed. |
|
7183 |
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type |
|
7184 |
// for this guy. |
|
7185 |
instruct tlsLoadP(g2RegP dst) %{ |
|
7186 |
match(Set dst (ThreadLocal)); |
|
7187 |
||
7188 |
size(0); |
|
7189 |
ins_cost(0); |
|
7190 |
format %{ "# TLS is in G2" %} |
|
7191 |
ins_encode( /*empty encoding*/ ); |
|
7192 |
ins_pipe(ialu_none); |
|
7193 |
%} |
|
7194 |
||
7195 |
instruct checkCastPP( iRegP dst ) %{ |
|
7196 |
match(Set dst (CheckCastPP dst)); |
|
7197 |
||
7198 |
size(0); |
|
7199 |
format %{ "# checkcastPP of $dst" %} |
|
7200 |
ins_encode( /*empty encoding*/ ); |
|
7201 |
ins_pipe(empty); |
|
7202 |
%} |
|
7203 |
||
7204 |
||
7205 |
instruct castPP( iRegP dst ) %{ |
|
7206 |
match(Set dst (CastPP dst)); |
|
7207 |
format %{ "# castPP of $dst" %} |
|
7208 |
ins_encode( /*empty encoding*/ ); |
|
7209 |
ins_pipe(empty); |
|
7210 |
%} |
|
7211 |
||
7212 |
instruct castII( iRegI dst ) %{ |
|
7213 |
match(Set dst (CastII dst)); |
|
7214 |
format %{ "# castII of $dst" %} |
|
7215 |
ins_encode( /*empty encoding*/ ); |
|
7216 |
ins_cost(0); |
|
7217 |
ins_pipe(empty); |
|
7218 |
%} |
|
7219 |
||
7220 |
//----------Arithmetic Instructions-------------------------------------------- |
|
7221 |
// Addition Instructions |
|
7222 |
// Register Addition |
|
7223 |
instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7224 |
match(Set dst (AddI src1 src2)); |
|
7225 |
||
7226 |
size(4); |
|
7227 |
format %{ "ADD $src1,$src2,$dst" %} |
|
7228 |
ins_encode %{ |
|
7229 |
__ add($src1$$Register, $src2$$Register, $dst$$Register); |
|
7230 |
%} |
|
7231 |
ins_pipe(ialu_reg_reg); |
|
7232 |
%} |
|
7233 |
||
7234 |
// Immediate Addition |
|
7235 |
instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
7236 |
match(Set dst (AddI src1 src2)); |
|
7237 |
||
7238 |
size(4); |
|
7239 |
format %{ "ADD $src1,$src2,$dst" %} |
|
7240 |
opcode(Assembler::add_op3, Assembler::arith_op); |
|
7241 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7242 |
ins_pipe(ialu_reg_imm); |
|
7243 |
%} |
|
7244 |
||
7245 |
// Pointer Register Addition |
|
7246 |
instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ |
|
7247 |
match(Set dst (AddP src1 src2)); |
|
7248 |
||
7249 |
size(4); |
|
7250 |
format %{ "ADD $src1,$src2,$dst" %} |
|
7251 |
opcode(Assembler::add_op3, Assembler::arith_op); |
|
7252 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7253 |
ins_pipe(ialu_reg_reg); |
|
7254 |
%} |
|
7255 |
||
7256 |
// Pointer Immediate Addition |
|
7257 |
instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ |
|
7258 |
match(Set dst (AddP src1 src2)); |
|
7259 |
||
7260 |
size(4); |
|
7261 |
format %{ "ADD $src1,$src2,$dst" %} |
|
7262 |
opcode(Assembler::add_op3, Assembler::arith_op); |
|
7263 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7264 |
ins_pipe(ialu_reg_imm); |
|
7265 |
%} |
|
7266 |
||
7267 |
// Long Addition |
|
7268 |
instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7269 |
match(Set dst (AddL src1 src2)); |
|
7270 |
||
7271 |
size(4); |
|
7272 |
format %{ "ADD $src1,$src2,$dst\t! long" %} |
|
7273 |
opcode(Assembler::add_op3, Assembler::arith_op); |
|
7274 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7275 |
ins_pipe(ialu_reg_reg); |
|
7276 |
%} |
|
7277 |
||
7278 |
instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ |
|
7279 |
match(Set dst (AddL src1 con)); |
|
7280 |
||
7281 |
size(4); |
|
7282 |
format %{ "ADD $src1,$con,$dst" %} |
|
7283 |
opcode(Assembler::add_op3, Assembler::arith_op); |
|
7284 |
ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); |
|
7285 |
ins_pipe(ialu_reg_imm); |
|
7286 |
%} |
|
7287 |
||
7288 |
//----------Conditional_store-------------------------------------------------- |
|
7289 |
// Conditional-store of the updated heap-top. |
|
7290 |
// Used during allocation of the shared heap. |
|
7291 |
// Sets flags (EQ) on success. Implemented with a CASA on Sparc. |
|
7292 |
||
7293 |
// LoadP-locked. Same as a regular pointer load when used with a compare-swap |
|
7294 |
instruct loadPLocked(iRegP dst, memory mem) %{ |
|
7295 |
match(Set dst (LoadPLocked mem)); |
|
7296 |
ins_cost(MEMORY_REF_COST); |
|
7297 |
||
7298 |
#ifndef _LP64 |
|
7299 |
size(4); |
|
7300 |
format %{ "LDUW $mem,$dst\t! ptr" %} |
|
7301 |
opcode(Assembler::lduw_op3, 0, REGP_OP); |
|
7302 |
#else |
|
7303 |
format %{ "LDX $mem,$dst\t! ptr" %} |
|
7304 |
opcode(Assembler::ldx_op3, 0, REGP_OP); |
|
7305 |
#endif |
|
7306 |
ins_encode( form3_mem_reg( mem, dst ) ); |
|
7307 |
ins_pipe(iload_mem); |
|
7308 |
%} |
|
7309 |
||
7310 |
instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ |
|
7311 |
match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); |
|
7312 |
effect( KILL newval ); |
|
7313 |
format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" |
|
7314 |
"CMP R_G3,$oldval\t\t! See if we made progress" %} |
|
7315 |
ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); |
|
7316 |
ins_pipe( long_memory_op ); |
|
7317 |
%} |
|
7318 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7319 |
// Conditional-store of an int value. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7320 |
instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7321 |
match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7322 |
effect( KILL newval ); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7323 |
format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7324 |
"CMP $oldval,$newval\t\t! See if we made progress" %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7325 |
ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
1 | 7326 |
ins_pipe( long_memory_op ); |
7327 |
%} |
|
7328 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7329 |
// Conditional-store of a long value. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7330 |
instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7331 |
match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7332 |
effect( KILL newval ); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7333 |
format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7334 |
"CMP $oldval,$newval\t\t! See if we made progress" %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
7335 |
ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
1 | 7336 |
ins_pipe( long_memory_op ); |
7337 |
%} |
|
7338 |
||
7339 |
// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
|
7340 |
||
7341 |
instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7342 |
predicate(VM_Version::supports_cx8()); |
1 | 7343 |
match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7344 |
effect( USE mem_ptr, KILL ccr, KILL tmp1); |
|
7345 |
format %{ |
|
7346 |
"MOV $newval,O7\n\t" |
|
7347 |
"CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
|
7348 |
"CMP $oldval,O7\t\t! See if we made progress\n\t" |
|
7349 |
"MOV 1,$res\n\t" |
|
7350 |
"MOVne xcc,R_G0,$res" |
|
7351 |
%} |
|
7352 |
ins_encode( enc_casx(mem_ptr, oldval, newval), |
|
7353 |
enc_lflags_ne_to_boolean(res) ); |
|
7354 |
ins_pipe( long_memory_op ); |
|
7355 |
%} |
|
7356 |
||
7357 |
||
7358 |
instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
7359 |
match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
|
7360 |
effect( USE mem_ptr, KILL ccr, KILL tmp1); |
|
7361 |
format %{ |
|
7362 |
"MOV $newval,O7\n\t" |
|
7363 |
"CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
|
7364 |
"CMP $oldval,O7\t\t! See if we made progress\n\t" |
|
7365 |
"MOV 1,$res\n\t" |
|
7366 |
"MOVne icc,R_G0,$res" |
|
7367 |
%} |
|
7368 |
ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
7369 |
enc_iflags_ne_to_boolean(res) ); |
|
7370 |
ins_pipe( long_memory_op ); |
|
7371 |
%} |
|
7372 |
||
7373 |
instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7374 |
#ifdef _LP64 |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7375 |
predicate(VM_Version::supports_cx8()); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7376 |
#endif |
1 | 7377 |
match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7378 |
effect( USE mem_ptr, KILL ccr, KILL tmp1); |
|
7379 |
format %{ |
|
7380 |
"MOV $newval,O7\n\t" |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7381 |
"CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
1 | 7382 |
"CMP $oldval,O7\t\t! See if we made progress\n\t" |
7383 |
"MOV 1,$res\n\t" |
|
7384 |
"MOVne xcc,R_G0,$res" |
|
7385 |
%} |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7386 |
#ifdef _LP64 |
1 | 7387 |
ins_encode( enc_casx(mem_ptr, oldval, newval), |
7388 |
enc_lflags_ne_to_boolean(res) ); |
|
7389 |
#else |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7390 |
ins_encode( enc_casi(mem_ptr, oldval, newval), |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7391 |
enc_iflags_ne_to_boolean(res) ); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7392 |
#endif |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7393 |
ins_pipe( long_memory_op ); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7394 |
%} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7395 |
|
607
3edc58bab61e
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
591
diff
changeset
|
7396 |
instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
7397 |
match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
607
3edc58bab61e
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
591
diff
changeset
|
7398 |
effect( USE mem_ptr, KILL ccr, KILL tmp1); |
1 | 7399 |
format %{ |
7400 |
"MOV $newval,O7\n\t" |
|
7401 |
"CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
|
7402 |
"CMP $oldval,O7\t\t! See if we made progress\n\t" |
|
7403 |
"MOV 1,$res\n\t" |
|
7404 |
"MOVne icc,R_G0,$res" |
|
7405 |
%} |
|
607
3edc58bab61e
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
591
diff
changeset
|
7406 |
ins_encode( enc_casi(mem_ptr, oldval, newval), |
3edc58bab61e
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
591
diff
changeset
|
7407 |
enc_iflags_ne_to_boolean(res) ); |
1 | 7408 |
ins_pipe( long_memory_op ); |
7409 |
%} |
|
7410 |
||
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7411 |
instruct xchgI( memory mem, iRegI newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7412 |
match(Set newval (GetAndSetI mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7413 |
format %{ "SWAP [$mem],$newval" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7414 |
size(4); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7415 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7416 |
__ swap($mem$$Address, $newval$$Register); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7417 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7418 |
ins_pipe( long_memory_op ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7419 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7420 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7421 |
#ifndef _LP64 |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7422 |
instruct xchgP( memory mem, iRegP newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7423 |
match(Set newval (GetAndSetP mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7424 |
format %{ "SWAP [$mem],$newval" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7425 |
size(4); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7426 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7427 |
__ swap($mem$$Address, $newval$$Register); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7428 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7429 |
ins_pipe( long_memory_op ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7430 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7431 |
#endif |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7432 |
|
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7433 |
instruct xchgN( memory mem, iRegN newval) %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7434 |
match(Set newval (GetAndSetN mem newval)); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7435 |
format %{ "SWAP [$mem],$newval" %} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7436 |
size(4); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7437 |
ins_encode %{ |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7438 |
__ swap($mem$$Address, $newval$$Register); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7439 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7440 |
ins_pipe( long_memory_op ); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7441 |
%} |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13728
diff
changeset
|
7442 |
|
1 | 7443 |
//--------------------- |
7444 |
// Subtraction Instructions |
|
7445 |
// Register Subtraction |
|
7446 |
instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7447 |
match(Set dst (SubI src1 src2)); |
|
7448 |
||
7449 |
size(4); |
|
7450 |
format %{ "SUB $src1,$src2,$dst" %} |
|
7451 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7452 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7453 |
ins_pipe(ialu_reg_reg); |
|
7454 |
%} |
|
7455 |
||
7456 |
// Immediate Subtraction |
|
7457 |
instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
7458 |
match(Set dst (SubI src1 src2)); |
|
7459 |
||
7460 |
size(4); |
|
7461 |
format %{ "SUB $src1,$src2,$dst" %} |
|
7462 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7463 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7464 |
ins_pipe(ialu_reg_imm); |
|
7465 |
%} |
|
7466 |
||
7467 |
instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ |
|
7468 |
match(Set dst (SubI zero src2)); |
|
7469 |
||
7470 |
size(4); |
|
7471 |
format %{ "NEG $src2,$dst" %} |
|
7472 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7473 |
ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); |
|
7474 |
ins_pipe(ialu_zero_reg); |
|
7475 |
%} |
|
7476 |
||
7477 |
// Long subtraction |
|
7478 |
instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7479 |
match(Set dst (SubL src1 src2)); |
|
7480 |
||
7481 |
size(4); |
|
7482 |
format %{ "SUB $src1,$src2,$dst\t! long" %} |
|
7483 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7484 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7485 |
ins_pipe(ialu_reg_reg); |
|
7486 |
%} |
|
7487 |
||
7488 |
// Immediate Subtraction |
|
7489 |
instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ |
|
7490 |
match(Set dst (SubL src1 con)); |
|
7491 |
||
7492 |
size(4); |
|
7493 |
format %{ "SUB $src1,$con,$dst\t! long" %} |
|
7494 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7495 |
ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); |
|
7496 |
ins_pipe(ialu_reg_imm); |
|
7497 |
%} |
|
7498 |
||
7499 |
// Long negation |
|
7500 |
instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ |
|
7501 |
match(Set dst (SubL zero src2)); |
|
7502 |
||
7503 |
size(4); |
|
7504 |
format %{ "NEG $src2,$dst\t! long" %} |
|
7505 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7506 |
ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); |
|
7507 |
ins_pipe(ialu_zero_reg); |
|
7508 |
%} |
|
7509 |
||
7510 |
// Multiplication Instructions |
|
7511 |
// Integer Multiplication |
|
7512 |
// Register Multiplication |
|
7513 |
instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7514 |
match(Set dst (MulI src1 src2)); |
|
7515 |
||
7516 |
size(4); |
|
7517 |
format %{ "MULX $src1,$src2,$dst" %} |
|
7518 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7519 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7520 |
ins_pipe(imul_reg_reg); |
|
7521 |
%} |
|
7522 |
||
7523 |
// Immediate Multiplication |
|
7524 |
instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
7525 |
match(Set dst (MulI src1 src2)); |
|
7526 |
||
7527 |
size(4); |
|
7528 |
format %{ "MULX $src1,$src2,$dst" %} |
|
7529 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7530 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7531 |
ins_pipe(imul_reg_imm); |
|
7532 |
%} |
|
7533 |
||
7534 |
instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7535 |
match(Set dst (MulL src1 src2)); |
|
7536 |
ins_cost(DEFAULT_COST * 5); |
|
7537 |
size(4); |
|
7538 |
format %{ "MULX $src1,$src2,$dst\t! long" %} |
|
7539 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7540 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7541 |
ins_pipe(mulL_reg_reg); |
|
7542 |
%} |
|
7543 |
||
7544 |
// Immediate Multiplication |
|
7545 |
instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ |
|
7546 |
match(Set dst (MulL src1 src2)); |
|
7547 |
ins_cost(DEFAULT_COST * 5); |
|
7548 |
size(4); |
|
7549 |
format %{ "MULX $src1,$src2,$dst" %} |
|
7550 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7551 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7552 |
ins_pipe(mulL_reg_imm); |
|
7553 |
%} |
|
7554 |
||
7555 |
// Integer Division |
|
7556 |
// Register Division |
|
7557 |
instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ |
|
7558 |
match(Set dst (DivI src1 src2)); |
|
7559 |
ins_cost((2+71)*DEFAULT_COST); |
|
7560 |
||
7561 |
format %{ "SRA $src2,0,$src2\n\t" |
|
7562 |
"SRA $src1,0,$src1\n\t" |
|
7563 |
"SDIVX $src1,$src2,$dst" %} |
|
7564 |
ins_encode( idiv_reg( src1, src2, dst ) ); |
|
7565 |
ins_pipe(sdiv_reg_reg); |
|
7566 |
%} |
|
7567 |
||
7568 |
// Immediate Division |
|
7569 |
instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ |
|
7570 |
match(Set dst (DivI src1 src2)); |
|
7571 |
ins_cost((2+71)*DEFAULT_COST); |
|
7572 |
||
7573 |
format %{ "SRA $src1,0,$src1\n\t" |
|
7574 |
"SDIVX $src1,$src2,$dst" %} |
|
7575 |
ins_encode( idiv_imm( src1, src2, dst ) ); |
|
7576 |
ins_pipe(sdiv_reg_imm); |
|
7577 |
%} |
|
7578 |
||
7579 |
//----------Div-By-10-Expansion------------------------------------------------ |
|
7580 |
// Extract hi bits of a 32x32->64 bit multiply. |
|
7581 |
// Expand rule only, not matched |
|
7582 |
instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ |
|
7583 |
effect( DEF dst, USE src1, USE src2 ); |
|
7584 |
format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" |
|
7585 |
"SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} |
|
7586 |
ins_encode( enc_mul_hi(dst,src1,src2)); |
|
7587 |
ins_pipe(sdiv_reg_reg); |
|
7588 |
%} |
|
7589 |
||
2131 | 7590 |
// Magic constant, reciprocal of 10 |
1 | 7591 |
instruct loadConI_x66666667(iRegIsafe dst) %{ |
7592 |
effect( DEF dst ); |
|
7593 |
||
7594 |
size(8); |
|
7595 |
format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} |
|
7596 |
ins_encode( Set32(0x66666667, dst) ); |
|
7597 |
ins_pipe(ialu_hi_lo_reg); |
|
7598 |
%} |
|
7599 |
||
2131 | 7600 |
// Register Shift Right Arithmetic Long by 32-63 |
1 | 7601 |
instruct sra_31( iRegI dst, iRegI src ) %{ |
7602 |
effect( DEF dst, USE src ); |
|
7603 |
format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} |
|
7604 |
ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); |
|
7605 |
ins_pipe(ialu_reg_reg); |
|
7606 |
%} |
|
7607 |
||
7608 |
// Arithmetic Shift Right by 8-bit immediate |
|
7609 |
instruct sra_reg_2( iRegI dst, iRegI src ) %{ |
|
7610 |
effect( DEF dst, USE src ); |
|
7611 |
format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} |
|
7612 |
opcode(Assembler::sra_op3, Assembler::arith_op); |
|
7613 |
ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); |
|
7614 |
ins_pipe(ialu_reg_imm); |
|
7615 |
%} |
|
7616 |
||
7617 |
// Integer DIV with 10 |
|
7618 |
instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ |
|
7619 |
match(Set dst (DivI src div)); |
|
7620 |
ins_cost((6+6)*DEFAULT_COST); |
|
7621 |
expand %{ |
|
7622 |
iRegIsafe tmp1; // Killed temps; |
|
7623 |
iRegIsafe tmp2; // Killed temps; |
|
7624 |
iRegI tmp3; // Killed temps; |
|
7625 |
iRegI tmp4; // Killed temps; |
|
7626 |
loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 |
|
7627 |
mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 |
|
7628 |
sra_31( tmp3, src ); // SRA src,31 -> tmp3 |
|
7629 |
sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 |
|
7630 |
subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst |
|
7631 |
%} |
|
7632 |
%} |
|
7633 |
||
7634 |
// Register Long Division |
|
7635 |
instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7636 |
match(Set dst (DivL src1 src2)); |
|
7637 |
ins_cost(DEFAULT_COST*71); |
|
7638 |
size(4); |
|
7639 |
format %{ "SDIVX $src1,$src2,$dst\t! long" %} |
|
7640 |
opcode(Assembler::sdivx_op3, Assembler::arith_op); |
|
7641 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7642 |
ins_pipe(divL_reg_reg); |
|
7643 |
%} |
|
7644 |
||
7645 |
// Register Long Division |
|
7646 |
instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ |
|
7647 |
match(Set dst (DivL src1 src2)); |
|
7648 |
ins_cost(DEFAULT_COST*71); |
|
7649 |
size(4); |
|
7650 |
format %{ "SDIVX $src1,$src2,$dst\t! long" %} |
|
7651 |
opcode(Assembler::sdivx_op3, Assembler::arith_op); |
|
7652 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7653 |
ins_pipe(divL_reg_imm); |
|
7654 |
%} |
|
7655 |
||
7656 |
// Integer Remainder |
|
7657 |
// Register Remainder |
|
7658 |
instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ |
|
7659 |
match(Set dst (ModI src1 src2)); |
|
7660 |
effect( KILL ccr, KILL temp); |
|
7661 |
||
7662 |
format %{ "SREM $src1,$src2,$dst" %} |
|
7663 |
ins_encode( irem_reg(src1, src2, dst, temp) ); |
|
7664 |
ins_pipe(sdiv_reg_reg); |
|
7665 |
%} |
|
7666 |
||
7667 |
// Immediate Remainder |
|
7668 |
instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ |
|
7669 |
match(Set dst (ModI src1 src2)); |
|
7670 |
effect( KILL ccr, KILL temp); |
|
7671 |
||
7672 |
format %{ "SREM $src1,$src2,$dst" %} |
|
7673 |
ins_encode( irem_imm(src1, src2, dst, temp) ); |
|
7674 |
ins_pipe(sdiv_reg_imm); |
|
7675 |
%} |
|
7676 |
||
7677 |
// Register Long Remainder |
|
7678 |
instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7679 |
effect(DEF dst, USE src1, USE src2); |
|
7680 |
size(4); |
|
7681 |
format %{ "SDIVX $src1,$src2,$dst\t! long" %} |
|
7682 |
opcode(Assembler::sdivx_op3, Assembler::arith_op); |
|
7683 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7684 |
ins_pipe(divL_reg_reg); |
|
7685 |
%} |
|
7686 |
||
7687 |
// Register Long Division |
|
7688 |
instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ |
|
7689 |
effect(DEF dst, USE src1, USE src2); |
|
7690 |
size(4); |
|
7691 |
format %{ "SDIVX $src1,$src2,$dst\t! long" %} |
|
7692 |
opcode(Assembler::sdivx_op3, Assembler::arith_op); |
|
7693 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7694 |
ins_pipe(divL_reg_imm); |
|
7695 |
%} |
|
7696 |
||
7697 |
instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7698 |
effect(DEF dst, USE src1, USE src2); |
|
7699 |
size(4); |
|
7700 |
format %{ "MULX $src1,$src2,$dst\t! long" %} |
|
7701 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7702 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7703 |
ins_pipe(mulL_reg_reg); |
|
7704 |
%} |
|
7705 |
||
7706 |
// Immediate Multiplication |
|
7707 |
instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ |
|
7708 |
effect(DEF dst, USE src1, USE src2); |
|
7709 |
size(4); |
|
7710 |
format %{ "MULX $src1,$src2,$dst" %} |
|
7711 |
opcode(Assembler::mulx_op3, Assembler::arith_op); |
|
7712 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
7713 |
ins_pipe(mulL_reg_imm); |
|
7714 |
%} |
|
7715 |
||
7716 |
instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7717 |
effect(DEF dst, USE src1, USE src2); |
|
7718 |
size(4); |
|
7719 |
format %{ "SUB $src1,$src2,$dst\t! long" %} |
|
7720 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7721 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7722 |
ins_pipe(ialu_reg_reg); |
|
7723 |
%} |
|
7724 |
||
7725 |
instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7726 |
effect(DEF dst, USE src1, USE src2); |
|
7727 |
size(4); |
|
7728 |
format %{ "SUB $src1,$src2,$dst\t! long" %} |
|
7729 |
opcode(Assembler::sub_op3, Assembler::arith_op); |
|
7730 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7731 |
ins_pipe(ialu_reg_reg); |
|
7732 |
%} |
|
7733 |
||
7734 |
// Register Long Remainder |
|
7735 |
instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
7736 |
match(Set dst (ModL src1 src2)); |
|
7737 |
ins_cost(DEFAULT_COST*(71 + 6 + 1)); |
|
7738 |
expand %{ |
|
7739 |
iRegL tmp1; |
|
7740 |
iRegL tmp2; |
|
7741 |
divL_reg_reg_1(tmp1, src1, src2); |
|
7742 |
mulL_reg_reg_1(tmp2, tmp1, src2); |
|
7743 |
subL_reg_reg_1(dst, src1, tmp2); |
|
7744 |
%} |
|
7745 |
%} |
|
7746 |
||
7747 |
// Register Long Remainder |
|
7748 |
instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ |
|
7749 |
match(Set dst (ModL src1 src2)); |
|
7750 |
ins_cost(DEFAULT_COST*(71 + 6 + 1)); |
|
7751 |
expand %{ |
|
7752 |
iRegL tmp1; |
|
7753 |
iRegL tmp2; |
|
7754 |
divL_reg_imm13_1(tmp1, src1, src2); |
|
7755 |
mulL_reg_imm13_1(tmp2, tmp1, src2); |
|
7756 |
subL_reg_reg_2 (dst, src1, tmp2); |
|
7757 |
%} |
|
7758 |
%} |
|
7759 |
||
7760 |
// Integer Shift Instructions |
|
7761 |
// Register Shift Left |
|
7762 |
instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7763 |
match(Set dst (LShiftI src1 src2)); |
|
7764 |
||
7765 |
size(4); |
|
7766 |
format %{ "SLL $src1,$src2,$dst" %} |
|
7767 |
opcode(Assembler::sll_op3, Assembler::arith_op); |
|
7768 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7769 |
ins_pipe(ialu_reg_reg); |
|
7770 |
%} |
|
7771 |
||
7772 |
// Register Shift Left Immediate |
|
7773 |
instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ |
|
7774 |
match(Set dst (LShiftI src1 src2)); |
|
7775 |
||
7776 |
size(4); |
|
7777 |
format %{ "SLL $src1,$src2,$dst" %} |
|
7778 |
opcode(Assembler::sll_op3, Assembler::arith_op); |
|
7779 |
ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); |
|
7780 |
ins_pipe(ialu_reg_imm); |
|
7781 |
%} |
|
7782 |
||
7783 |
// Register Shift Left |
|
7784 |
instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ |
|
7785 |
match(Set dst (LShiftL src1 src2)); |
|
7786 |
||
7787 |
size(4); |
|
7788 |
format %{ "SLLX $src1,$src2,$dst" %} |
|
7789 |
opcode(Assembler::sllx_op3, Assembler::arith_op); |
|
7790 |
ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); |
|
7791 |
ins_pipe(ialu_reg_reg); |
|
7792 |
%} |
|
7793 |
||
7794 |
// Register Shift Left Immediate |
|
7795 |
instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ |
|
7796 |
match(Set dst (LShiftL src1 src2)); |
|
7797 |
||
7798 |
size(4); |
|
7799 |
format %{ "SLLX $src1,$src2,$dst" %} |
|
7800 |
opcode(Assembler::sllx_op3, Assembler::arith_op); |
|
7801 |
ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); |
|
7802 |
ins_pipe(ialu_reg_imm); |
|
7803 |
%} |
|
7804 |
||
7805 |
// Register Arithmetic Shift Right |
|
7806 |
instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7807 |
match(Set dst (RShiftI src1 src2)); |
|
7808 |
size(4); |
|
7809 |
format %{ "SRA $src1,$src2,$dst" %} |
|
7810 |
opcode(Assembler::sra_op3, Assembler::arith_op); |
|
7811 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7812 |
ins_pipe(ialu_reg_reg); |
|
7813 |
%} |
|
7814 |
||
7815 |
// Register Arithmetic Shift Right Immediate |
|
7816 |
instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ |
|
7817 |
match(Set dst (RShiftI src1 src2)); |
|
7818 |
||
7819 |
size(4); |
|
7820 |
format %{ "SRA $src1,$src2,$dst" %} |
|
7821 |
opcode(Assembler::sra_op3, Assembler::arith_op); |
|
7822 |
ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); |
|
7823 |
ins_pipe(ialu_reg_imm); |
|
7824 |
%} |
|
7825 |
||
7826 |
// Register Shift Right Arithmatic Long |
|
7827 |
instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ |
|
7828 |
match(Set dst (RShiftL src1 src2)); |
|
7829 |
||
7830 |
size(4); |
|
7831 |
format %{ "SRAX $src1,$src2,$dst" %} |
|
7832 |
opcode(Assembler::srax_op3, Assembler::arith_op); |
|
7833 |
ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); |
|
7834 |
ins_pipe(ialu_reg_reg); |
|
7835 |
%} |
|
7836 |
||
7837 |
// Register Shift Left Immediate |
|
7838 |
instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ |
|
7839 |
match(Set dst (RShiftL src1 src2)); |
|
7840 |
||
7841 |
size(4); |
|
7842 |
format %{ "SRAX $src1,$src2,$dst" %} |
|
7843 |
opcode(Assembler::srax_op3, Assembler::arith_op); |
|
7844 |
ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); |
|
7845 |
ins_pipe(ialu_reg_imm); |
|
7846 |
%} |
|
7847 |
||
7848 |
// Register Shift Right |
|
7849 |
instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
7850 |
match(Set dst (URShiftI src1 src2)); |
|
7851 |
||
7852 |
size(4); |
|
7853 |
format %{ "SRL $src1,$src2,$dst" %} |
|
7854 |
opcode(Assembler::srl_op3, Assembler::arith_op); |
|
7855 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
7856 |
ins_pipe(ialu_reg_reg); |
|
7857 |
%} |
|
7858 |
||
7859 |
// Register Shift Right Immediate |
|
7860 |
instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ |
|
7861 |
match(Set dst (URShiftI src1 src2)); |
|
7862 |
||
7863 |
size(4); |
|
7864 |
format %{ "SRL $src1,$src2,$dst" %} |
|
7865 |
opcode(Assembler::srl_op3, Assembler::arith_op); |
|
7866 |
ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); |
|
7867 |
ins_pipe(ialu_reg_imm); |
|
7868 |
%} |
|
7869 |
||
7870 |
// Register Shift Right |
|
7871 |
instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ |
|
7872 |
match(Set dst (URShiftL src1 src2)); |
|
7873 |
||
7874 |
size(4); |
|
7875 |
format %{ "SRLX $src1,$src2,$dst" %} |
|
7876 |
opcode(Assembler::srlx_op3, Assembler::arith_op); |
|
7877 |
ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); |
|
7878 |
ins_pipe(ialu_reg_reg); |
|
7879 |
%} |
|
7880 |
||
7881 |
// Register Shift Right Immediate |
|
7882 |
instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ |
|
7883 |
match(Set dst (URShiftL src1 src2)); |
|
7884 |
||
7885 |
size(4); |
|
7886 |
format %{ "SRLX $src1,$src2,$dst" %} |
|
7887 |
opcode(Assembler::srlx_op3, Assembler::arith_op); |
|
7888 |
ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); |
|
7889 |
ins_pipe(ialu_reg_imm); |
|
7890 |
%} |
|
7891 |
||
7892 |
// Register Shift Right Immediate with a CastP2X |
|
7893 |
#ifdef _LP64 |
|
7894 |
instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ |
|
7895 |
match(Set dst (URShiftL (CastP2X src1) src2)); |
|
7896 |
size(4); |
|
7897 |
format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} |
|
7898 |
opcode(Assembler::srlx_op3, Assembler::arith_op); |
|
7899 |
ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); |
|
7900 |
ins_pipe(ialu_reg_imm); |
|
7901 |
%} |
|
7902 |
#else |
|
7903 |
instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ |
|
7904 |
match(Set dst (URShiftI (CastP2X src1) src2)); |
|
7905 |
size(4); |
|
7906 |
format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} |
|
7907 |
opcode(Assembler::srl_op3, Assembler::arith_op); |
|
7908 |
ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); |
|
7909 |
ins_pipe(ialu_reg_imm); |
|
7910 |
%} |
|
7911 |
#endif |
|
7912 |
||
7913 |
||
7914 |
//----------Floating Point Arithmetic Instructions----------------------------- |
|
7915 |
||
7916 |
// Add float single precision |
|
7917 |
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
7918 |
match(Set dst (AddF src1 src2)); |
|
7919 |
||
7920 |
size(4); |
|
7921 |
format %{ "FADDS $src1,$src2,$dst" %} |
|
7922 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); |
|
7923 |
ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); |
|
7924 |
ins_pipe(faddF_reg_reg); |
|
7925 |
%} |
|
7926 |
||
7927 |
// Add float double precision |
|
7928 |
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
7929 |
match(Set dst (AddD src1 src2)); |
|
7930 |
||
7931 |
size(4); |
|
7932 |
format %{ "FADDD $src1,$src2,$dst" %} |
|
7933 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); |
|
7934 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
7935 |
ins_pipe(faddD_reg_reg); |
|
7936 |
%} |
|
7937 |
||
7938 |
// Sub float single precision |
|
7939 |
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
7940 |
match(Set dst (SubF src1 src2)); |
|
7941 |
||
7942 |
size(4); |
|
7943 |
format %{ "FSUBS $src1,$src2,$dst" %} |
|
7944 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); |
|
7945 |
ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); |
|
7946 |
ins_pipe(faddF_reg_reg); |
|
7947 |
%} |
|
7948 |
||
7949 |
// Sub float double precision |
|
7950 |
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
7951 |
match(Set dst (SubD src1 src2)); |
|
7952 |
||
7953 |
size(4); |
|
7954 |
format %{ "FSUBD $src1,$src2,$dst" %} |
|
7955 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); |
|
7956 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
7957 |
ins_pipe(faddD_reg_reg); |
|
7958 |
%} |
|
7959 |
||
7960 |
// Mul float single precision |
|
7961 |
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
7962 |
match(Set dst (MulF src1 src2)); |
|
7963 |
||
7964 |
size(4); |
|
7965 |
format %{ "FMULS $src1,$src2,$dst" %} |
|
7966 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); |
|
7967 |
ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); |
|
7968 |
ins_pipe(fmulF_reg_reg); |
|
7969 |
%} |
|
7970 |
||
7971 |
// Mul float double precision |
|
7972 |
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
7973 |
match(Set dst (MulD src1 src2)); |
|
7974 |
||
7975 |
size(4); |
|
7976 |
format %{ "FMULD $src1,$src2,$dst" %} |
|
7977 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); |
|
7978 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
7979 |
ins_pipe(fmulD_reg_reg); |
|
7980 |
%} |
|
7981 |
||
7982 |
// Div float single precision |
|
7983 |
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
7984 |
match(Set dst (DivF src1 src2)); |
|
7985 |
||
7986 |
size(4); |
|
7987 |
format %{ "FDIVS $src1,$src2,$dst" %} |
|
7988 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); |
|
7989 |
ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); |
|
7990 |
ins_pipe(fdivF_reg_reg); |
|
7991 |
%} |
|
7992 |
||
7993 |
// Div float double precision |
|
7994 |
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
7995 |
match(Set dst (DivD src1 src2)); |
|
7996 |
||
7997 |
size(4); |
|
7998 |
format %{ "FDIVD $src1,$src2,$dst" %} |
|
7999 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); |
|
8000 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
8001 |
ins_pipe(fdivD_reg_reg); |
|
8002 |
%} |
|
8003 |
||
8004 |
// Absolute float double precision |
|
8005 |
instruct absD_reg(regD dst, regD src) %{ |
|
8006 |
match(Set dst (AbsD src)); |
|
8007 |
||
8008 |
format %{ "FABSd $src,$dst" %} |
|
8009 |
ins_encode(fabsd(dst, src)); |
|
8010 |
ins_pipe(faddD_reg); |
|
8011 |
%} |
|
8012 |
||
8013 |
// Absolute float single precision |
|
8014 |
instruct absF_reg(regF dst, regF src) %{ |
|
8015 |
match(Set dst (AbsF src)); |
|
8016 |
||
8017 |
format %{ "FABSs $src,$dst" %} |
|
8018 |
ins_encode(fabss(dst, src)); |
|
8019 |
ins_pipe(faddF_reg); |
|
8020 |
%} |
|
8021 |
||
8022 |
instruct negF_reg(regF dst, regF src) %{ |
|
8023 |
match(Set dst (NegF src)); |
|
8024 |
||
8025 |
size(4); |
|
8026 |
format %{ "FNEGs $src,$dst" %} |
|
8027 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); |
|
8028 |
ins_encode(form3_opf_rs2F_rdF(src, dst)); |
|
8029 |
ins_pipe(faddF_reg); |
|
8030 |
%} |
|
8031 |
||
8032 |
instruct negD_reg(regD dst, regD src) %{ |
|
8033 |
match(Set dst (NegD src)); |
|
8034 |
||
8035 |
format %{ "FNEGd $src,$dst" %} |
|
8036 |
ins_encode(fnegd(dst, src)); |
|
8037 |
ins_pipe(faddD_reg); |
|
8038 |
%} |
|
8039 |
||
8040 |
// Sqrt float double precision |
|
8041 |
instruct sqrtF_reg_reg(regF dst, regF src) %{ |
|
8042 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
8043 |
||
8044 |
size(4); |
|
8045 |
format %{ "FSQRTS $src,$dst" %} |
|
8046 |
ins_encode(fsqrts(dst, src)); |
|
8047 |
ins_pipe(fdivF_reg_reg); |
|
8048 |
%} |
|
8049 |
||
8050 |
// Sqrt float double precision |
|
8051 |
instruct sqrtD_reg_reg(regD dst, regD src) %{ |
|
8052 |
match(Set dst (SqrtD src)); |
|
8053 |
||
8054 |
size(4); |
|
8055 |
format %{ "FSQRTD $src,$dst" %} |
|
8056 |
ins_encode(fsqrtd(dst, src)); |
|
8057 |
ins_pipe(fdivD_reg_reg); |
|
8058 |
%} |
|
8059 |
||
8060 |
//----------Logical Instructions----------------------------------------------- |
|
8061 |
// And Instructions |
|
8062 |
// Register And |
|
8063 |
instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
8064 |
match(Set dst (AndI src1 src2)); |
|
8065 |
||
8066 |
size(4); |
|
8067 |
format %{ "AND $src1,$src2,$dst" %} |
|
8068 |
opcode(Assembler::and_op3, Assembler::arith_op); |
|
8069 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8070 |
ins_pipe(ialu_reg_reg); |
|
8071 |
%} |
|
8072 |
||
8073 |
// Immediate And |
|
8074 |
instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
8075 |
match(Set dst (AndI src1 src2)); |
|
8076 |
||
8077 |
size(4); |
|
8078 |
format %{ "AND $src1,$src2,$dst" %} |
|
8079 |
opcode(Assembler::and_op3, Assembler::arith_op); |
|
8080 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
8081 |
ins_pipe(ialu_reg_imm); |
|
8082 |
%} |
|
8083 |
||
8084 |
// Register And Long |
|
8085 |
instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
8086 |
match(Set dst (AndL src1 src2)); |
|
8087 |
||
8088 |
ins_cost(DEFAULT_COST); |
|
8089 |
size(4); |
|
8090 |
format %{ "AND $src1,$src2,$dst\t! long" %} |
|
8091 |
opcode(Assembler::and_op3, Assembler::arith_op); |
|
8092 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8093 |
ins_pipe(ialu_reg_reg); |
|
8094 |
%} |
|
8095 |
||
8096 |
instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ |
|
8097 |
match(Set dst (AndL src1 con)); |
|
8098 |
||
8099 |
ins_cost(DEFAULT_COST); |
|
8100 |
size(4); |
|
8101 |
format %{ "AND $src1,$con,$dst\t! long" %} |
|
8102 |
opcode(Assembler::and_op3, Assembler::arith_op); |
|
8103 |
ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); |
|
8104 |
ins_pipe(ialu_reg_imm); |
|
8105 |
%} |
|
8106 |
||
8107 |
// Or Instructions |
|
8108 |
// Register Or |
|
8109 |
instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
8110 |
match(Set dst (OrI src1 src2)); |
|
8111 |
||
8112 |
size(4); |
|
8113 |
format %{ "OR $src1,$src2,$dst" %} |
|
8114 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
8115 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8116 |
ins_pipe(ialu_reg_reg); |
|
8117 |
%} |
|
8118 |
||
8119 |
// Immediate Or |
|
8120 |
instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
8121 |
match(Set dst (OrI src1 src2)); |
|
8122 |
||
8123 |
size(4); |
|
8124 |
format %{ "OR $src1,$src2,$dst" %} |
|
8125 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
8126 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
8127 |
ins_pipe(ialu_reg_imm); |
|
8128 |
%} |
|
8129 |
||
8130 |
// Register Or Long |
|
8131 |
instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
8132 |
match(Set dst (OrL src1 src2)); |
|
8133 |
||
8134 |
ins_cost(DEFAULT_COST); |
|
8135 |
size(4); |
|
8136 |
format %{ "OR $src1,$src2,$dst\t! long" %} |
|
8137 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
8138 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8139 |
ins_pipe(ialu_reg_reg); |
|
8140 |
%} |
|
8141 |
||
8142 |
instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ |
|
8143 |
match(Set dst (OrL src1 con)); |
|
8144 |
ins_cost(DEFAULT_COST*2); |
|
8145 |
||
8146 |
ins_cost(DEFAULT_COST); |
|
8147 |
size(4); |
|
8148 |
format %{ "OR $src1,$con,$dst\t! long" %} |
|
8149 |
opcode(Assembler::or_op3, Assembler::arith_op); |
|
8150 |
ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); |
|
8151 |
ins_pipe(ialu_reg_imm); |
|
8152 |
%} |
|
8153 |
||
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8154 |
#ifndef _LP64 |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8155 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8156 |
// Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8157 |
instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8158 |
match(Set dst (OrI src1 (CastP2X src2))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8159 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8160 |
size(4); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8161 |
format %{ "OR $src1,$src2,$dst" %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8162 |
opcode(Assembler::or_op3, Assembler::arith_op); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8163 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8164 |
ins_pipe(ialu_reg_reg); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8165 |
%} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8166 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8167 |
#else |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8168 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8169 |
instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8170 |
match(Set dst (OrL src1 (CastP2X src2))); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8171 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8172 |
ins_cost(DEFAULT_COST); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8173 |
size(4); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8174 |
format %{ "OR $src1,$src2,$dst\t! long" %} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8175 |
opcode(Assembler::or_op3, Assembler::arith_op); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8176 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8177 |
ins_pipe(ialu_reg_reg); |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8178 |
%} |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8179 |
|
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8180 |
#endif |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1495
diff
changeset
|
8181 |
|
1 | 8182 |
// Xor Instructions |
8183 |
// Register Xor |
|
8184 |
instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ |
|
8185 |
match(Set dst (XorI src1 src2)); |
|
8186 |
||
8187 |
size(4); |
|
8188 |
format %{ "XOR $src1,$src2,$dst" %} |
|
8189 |
opcode(Assembler::xor_op3, Assembler::arith_op); |
|
8190 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8191 |
ins_pipe(ialu_reg_reg); |
|
8192 |
%} |
|
8193 |
||
8194 |
// Immediate Xor |
|
8195 |
instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ |
|
8196 |
match(Set dst (XorI src1 src2)); |
|
8197 |
||
8198 |
size(4); |
|
8199 |
format %{ "XOR $src1,$src2,$dst" %} |
|
8200 |
opcode(Assembler::xor_op3, Assembler::arith_op); |
|
8201 |
ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); |
|
8202 |
ins_pipe(ialu_reg_imm); |
|
8203 |
%} |
|
8204 |
||
8205 |
// Register Xor Long |
|
8206 |
instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ |
|
8207 |
match(Set dst (XorL src1 src2)); |
|
8208 |
||
8209 |
ins_cost(DEFAULT_COST); |
|
8210 |
size(4); |
|
8211 |
format %{ "XOR $src1,$src2,$dst\t! long" %} |
|
8212 |
opcode(Assembler::xor_op3, Assembler::arith_op); |
|
8213 |
ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
8214 |
ins_pipe(ialu_reg_reg); |
|
8215 |
%} |
|
8216 |
||
8217 |
instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ |
|
8218 |
match(Set dst (XorL src1 con)); |
|
8219 |
||
8220 |
ins_cost(DEFAULT_COST); |
|
8221 |
size(4); |
|
8222 |
format %{ "XOR $src1,$con,$dst\t! long" %} |
|
8223 |
opcode(Assembler::xor_op3, Assembler::arith_op); |
|
8224 |
ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); |
|
8225 |
ins_pipe(ialu_reg_imm); |
|
8226 |
%} |
|
8227 |
||
8228 |
//----------Convert to Boolean------------------------------------------------- |
|
8229 |
// Nice hack for 32-bit tests but doesn't work for |
|
8230 |
// 64-bit pointers. |
|
8231 |
instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ |
|
8232 |
match(Set dst (Conv2B src)); |
|
8233 |
effect( KILL ccr ); |
|
8234 |
ins_cost(DEFAULT_COST*2); |
|
8235 |
format %{ "CMP R_G0,$src\n\t" |
|
8236 |
"ADDX R_G0,0,$dst" %} |
|
8237 |
ins_encode( enc_to_bool( src, dst ) ); |
|
8238 |
ins_pipe(ialu_reg_ialu); |
|
8239 |
%} |
|
8240 |
||
8241 |
#ifndef _LP64 |
|
8242 |
instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ |
|
8243 |
match(Set dst (Conv2B src)); |
|
8244 |
effect( KILL ccr ); |
|
8245 |
ins_cost(DEFAULT_COST*2); |
|
8246 |
format %{ "CMP R_G0,$src\n\t" |
|
8247 |
"ADDX R_G0,0,$dst" %} |
|
8248 |
ins_encode( enc_to_bool( src, dst ) ); |
|
8249 |
ins_pipe(ialu_reg_ialu); |
|
8250 |
%} |
|
8251 |
#else |
|
8252 |
instruct convP2B( iRegI dst, iRegP src ) %{ |
|
8253 |
match(Set dst (Conv2B src)); |
|
8254 |
ins_cost(DEFAULT_COST*2); |
|
8255 |
format %{ "MOV $src,$dst\n\t" |
|
8256 |
"MOVRNZ $src,1,$dst" %} |
|
8257 |
ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); |
|
8258 |
ins_pipe(ialu_clr_and_mover); |
|
8259 |
%} |
|
8260 |
#endif |
|
8261 |
||
8324
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8262 |
instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8263 |
match(Set dst (CmpLTMask src zero)); |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8264 |
effect(KILL ccr); |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8265 |
size(4); |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8266 |
format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8267 |
ins_encode %{ |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8268 |
__ sra($src$$Register, 31, $dst$$Register); |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8269 |
%} |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8270 |
ins_pipe(ialu_reg_imm); |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8271 |
%} |
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8272 |
|
1 | 8273 |
instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
8274 |
match(Set dst (CmpLTMask p q)); |
|
8275 |
effect( KILL ccr ); |
|
8276 |
ins_cost(DEFAULT_COST*4); |
|
8277 |
format %{ "CMP $p,$q\n\t" |
|
8278 |
"MOV #0,$dst\n\t" |
|
8279 |
"BLT,a .+8\n\t" |
|
8280 |
"MOV #-1,$dst" %} |
|
8281 |
ins_encode( enc_ltmask(p,q,dst) ); |
|
8282 |
ins_pipe(ialu_reg_reg_ialu); |
|
8283 |
%} |
|
8284 |
||
8285 |
instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ |
|
8286 |
match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
|
8287 |
effect(KILL ccr, TEMP tmp); |
|
8288 |
ins_cost(DEFAULT_COST*3); |
|
8289 |
||
8290 |
format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" |
|
8291 |
"ADD $p,$y,$tmp\t! g3=p-q+y\n\t" |
|
8324
a9933c6c5a95
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
7892
diff
changeset
|
8292 |
"MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
17008 | 8293 |
ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
8294 |
ins_pipe(cadd_cmpltmask); |
|
8295 |
%} |
|
8296 |
||
8297 |
instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ |
|
8298 |
match(Set p (AndI (CmpLTMask p q) y)); |
|
8299 |
effect(KILL ccr); |
|
8300 |
ins_cost(DEFAULT_COST*3); |
|
8301 |
||
8302 |
format %{ "CMP $p,$q\n\t" |
|
8303 |
"MOV $y,$p\n\t" |
|
8304 |
"MOVge G0,$p" %} |
|
8305 |
ins_encode %{ |
|
8306 |
__ cmp($p$$Register, $q$$Register); |
|
8307 |
__ mov($y$$Register, $p$$Register); |
|
8308 |
__ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); |
|
8309 |
%} |
|
8310 |
ins_pipe(ialu_reg_reg_ialu); |
|
8311 |
%} |
|
10027 | 8312 |
|
8313 |
//----------------------------------------------------------------- |
|
8314 |
// Direct raw moves between float and general registers using VIS3. |
|
8315 |
||
8316 |
// ins_pipe(faddF_reg); |
|
8317 |
instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ |
|
8318 |
predicate(UseVIS >= 3); |
|
8319 |
match(Set dst (MoveF2I src)); |
|
8320 |
||
8321 |
format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} |
|
8322 |
ins_encode %{ |
|
8323 |
__ movstouw($src$$FloatRegister, $dst$$Register); |
|
8324 |
%} |
|
8325 |
ins_pipe(ialu_reg_reg); |
|
8326 |
%} |
|
8327 |
||
8328 |
instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ |
|
8329 |
predicate(UseVIS >= 3); |
|
8330 |
match(Set dst (MoveI2F src)); |
|
8331 |
||
8332 |
format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} |
|
8333 |
ins_encode %{ |
|
8334 |
__ movwtos($src$$Register, $dst$$FloatRegister); |
|
8335 |
%} |
|
1 | 8336 |
ins_pipe(ialu_reg_reg); |
8337 |
%} |
|
8338 |
||
10027 | 8339 |
instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
8340 |
predicate(UseVIS >= 3); |
|
8341 |
match(Set dst (MoveD2L src)); |
|
8342 |
||
8343 |
format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} |
|
8344 |
ins_encode %{ |
|
8345 |
__ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); |
|
8346 |
%} |
|
1 | 8347 |
ins_pipe(ialu_reg_reg); |
8348 |
%} |
|
8349 |
||
10027 | 8350 |
instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
8351 |
predicate(UseVIS >= 3); |
|
8352 |
match(Set dst (MoveL2D src)); |
|
8353 |
||
8354 |
format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} |
|
8355 |
ins_encode %{ |
|
8356 |
__ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); |
|
8357 |
%} |
|
1 | 8358 |
ins_pipe(ialu_reg_reg); |
8359 |
%} |
|
8360 |
||
10027 | 8361 |
|
8362 |
// Raw moves between float and general registers using stack. |
|
8363 |
||
1 | 8364 |
instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
8365 |
match(Set dst (MoveF2I src)); |
|
8366 |
effect(DEF dst, USE src); |
|
8367 |
ins_cost(MEMORY_REF_COST); |
|
8368 |
||
8369 |
size(4); |
|
8370 |
format %{ "LDUW $src,$dst\t! MoveF2I" %} |
|
8371 |
opcode(Assembler::lduw_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8372 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 8373 |
ins_pipe(iload_mem); |
8374 |
%} |
|
8375 |
||
8376 |
instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ |
|
8377 |
match(Set dst (MoveI2F src)); |
|
8378 |
effect(DEF dst, USE src); |
|
8379 |
ins_cost(MEMORY_REF_COST); |
|
8380 |
||
8381 |
size(4); |
|
8382 |
format %{ "LDF $src,$dst\t! MoveI2F" %} |
|
8383 |
opcode(Assembler::ldf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8384 |
ins_encode(simple_form3_mem_reg(src, dst)); |
1 | 8385 |
ins_pipe(floadF_stk); |
8386 |
%} |
|
8387 |
||
8388 |
instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ |
|
8389 |
match(Set dst (MoveD2L src)); |
|
8390 |
effect(DEF dst, USE src); |
|
8391 |
ins_cost(MEMORY_REF_COST); |
|
8392 |
||
8393 |
size(4); |
|
8394 |
format %{ "LDX $src,$dst\t! MoveD2L" %} |
|
8395 |
opcode(Assembler::ldx_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8396 |
ins_encode(simple_form3_mem_reg( src, dst ) ); |
1 | 8397 |
ins_pipe(iload_mem); |
8398 |
%} |
|
8399 |
||
8400 |
instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ |
|
8401 |
match(Set dst (MoveL2D src)); |
|
8402 |
effect(DEF dst, USE src); |
|
8403 |
ins_cost(MEMORY_REF_COST); |
|
8404 |
||
8405 |
size(4); |
|
8406 |
format %{ "LDDF $src,$dst\t! MoveL2D" %} |
|
8407 |
opcode(Assembler::lddf_op3); |
|
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8408 |
ins_encode(simple_form3_mem_reg(src, dst)); |
1 | 8409 |
ins_pipe(floadD_stk); |
8410 |
%} |
|
8411 |
||
8412 |
instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ |
|
8413 |
match(Set dst (MoveF2I src)); |
|
8414 |
effect(DEF dst, USE src); |
|
8415 |
ins_cost(MEMORY_REF_COST); |
|
8416 |
||
8417 |
size(4); |
|
10027 | 8418 |
format %{ "STF $src,$dst\t! MoveF2I" %} |
1 | 8419 |
opcode(Assembler::stf_op3); |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8420 |
ins_encode(simple_form3_mem_reg(dst, src)); |
1 | 8421 |
ins_pipe(fstoreF_stk_reg); |
8422 |
%} |
|
8423 |
||
8424 |
instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ |
|
8425 |
match(Set dst (MoveI2F src)); |
|
8426 |
effect(DEF dst, USE src); |
|
8427 |
ins_cost(MEMORY_REF_COST); |
|
8428 |
||
8429 |
size(4); |
|
10027 | 8430 |
format %{ "STW $src,$dst\t! MoveI2F" %} |
1 | 8431 |
opcode(Assembler::stw_op3); |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8432 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 8433 |
ins_pipe(istore_mem_reg); |
8434 |
%} |
|
8435 |
||
8436 |
instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ |
|
8437 |
match(Set dst (MoveD2L src)); |
|
8438 |
effect(DEF dst, USE src); |
|
8439 |
ins_cost(MEMORY_REF_COST); |
|
8440 |
||
8441 |
size(4); |
|
10027 | 8442 |
format %{ "STDF $src,$dst\t! MoveD2L" %} |
1 | 8443 |
opcode(Assembler::stdf_op3); |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8444 |
ins_encode(simple_form3_mem_reg(dst, src)); |
1 | 8445 |
ins_pipe(fstoreD_stk_reg); |
8446 |
%} |
|
8447 |
||
8448 |
instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ |
|
8449 |
match(Set dst (MoveL2D src)); |
|
8450 |
effect(DEF dst, USE src); |
|
8451 |
ins_cost(MEMORY_REF_COST); |
|
8452 |
||
8453 |
size(4); |
|
10027 | 8454 |
format %{ "STX $src,$dst\t! MoveL2D" %} |
1 | 8455 |
opcode(Assembler::stx_op3); |
1495
128fe18951ed
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
781
diff
changeset
|
8456 |
ins_encode(simple_form3_mem_reg( dst, src ) ); |
1 | 8457 |
ins_pipe(istore_mem_reg); |
8458 |
%} |
|
8459 |
||
8460 |
||
10027 | 8461 |
//----------Arithmetic Conversion Instructions--------------------------------- |
8462 |
// The conversions operations are all Alpha sorted. Please keep it that way! |
|
8463 |
||
8464 |
instruct convD2F_reg(regF dst, regD src) %{ |
|
8465 |
match(Set dst (ConvD2F src)); |
|
8466 |
size(4); |
|
8467 |
format %{ "FDTOS $src,$dst" %} |
|
8468 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); |
|
8469 |
ins_encode(form3_opf_rs2D_rdF(src, dst)); |
|
8470 |
ins_pipe(fcvtD2F); |
|
8471 |
%} |
|
8472 |
||
8473 |
||
8474 |
// Convert a double to an int in a float register. |
|
8475 |
// If the double is a NAN, stuff a zero in instead. |
|
8476 |
instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ |
|
8477 |
effect(DEF dst, USE src, KILL fcc0); |
|
8478 |
format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" |
|
8479 |
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" |
|
8480 |
"FDTOI $src,$dst\t! convert in delay slot\n\t" |
|
8481 |
"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" |
|
8482 |
"FSUBs $dst,$dst,$dst\t! cleared only if nan\n" |
|
8483 |
"skip:" %} |
|
8484 |
ins_encode(form_d2i_helper(src,dst)); |
|
8485 |
ins_pipe(fcvtD2I); |
|
8486 |
%} |
|
8487 |
||
8488 |
instruct convD2I_stk(stackSlotI dst, regD src) %{ |
|
8489 |
match(Set dst (ConvD2I src)); |
|
8490 |
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); |
|
8491 |
expand %{ |
|
8492 |
regF tmp; |
|
8493 |
convD2I_helper(tmp, src); |
|
8494 |
regF_to_stkI(dst, tmp); |
|
8495 |
%} |
|
8496 |
%} |
|
8497 |
||
8498 |
instruct convD2I_reg(iRegI dst, regD src) %{ |
|
8499 |
predicate(UseVIS >= 3); |
|
8500 |
match(Set dst (ConvD2I src)); |
|
8501 |
ins_cost(DEFAULT_COST*2 + BRANCH_COST); |
|
8502 |
expand %{ |
|
8503 |
regF tmp; |
|
8504 |
convD2I_helper(tmp, src); |
|
8505 |
MoveF2I_reg_reg(dst, tmp); |
|
8506 |
%} |
|
8507 |
%} |
|
8508 |
||
8509 |
||
8510 |
// Convert a double to a long in a double register. |
|
8511 |
// If the double is a NAN, stuff a zero in instead. |
|
8512 |
instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ |
|
8513 |
effect(DEF dst, USE src, KILL fcc0); |
|
8514 |
format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" |
|
8515 |
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" |
|
8516 |
"FDTOX $src,$dst\t! convert in delay slot\n\t" |
|
8517 |
"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" |
|
8518 |
"FSUBd $dst,$dst,$dst\t! cleared only if nan\n" |
|
8519 |
"skip:" %} |
|
8520 |
ins_encode(form_d2l_helper(src,dst)); |
|
8521 |
ins_pipe(fcvtD2L); |
|
8522 |
%} |
|
8523 |
||
8524 |
instruct convD2L_stk(stackSlotL dst, regD src) %{ |
|
8525 |
match(Set dst (ConvD2L src)); |
|
8526 |
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); |
|
8527 |
expand %{ |
|
8528 |
regD tmp; |
|
8529 |
convD2L_helper(tmp, src); |
|
8530 |
regD_to_stkL(dst, tmp); |
|
8531 |
%} |
|
8532 |
%} |
|
8533 |
||
8534 |
instruct convD2L_reg(iRegL dst, regD src) %{ |
|
8535 |
predicate(UseVIS >= 3); |
|
8536 |
match(Set dst (ConvD2L src)); |
|
8537 |
ins_cost(DEFAULT_COST*2 + BRANCH_COST); |
|
8538 |
expand %{ |
|
8539 |
regD tmp; |
|
8540 |
convD2L_helper(tmp, src); |
|
8541 |
MoveD2L_reg_reg(dst, tmp); |
|
8542 |
%} |
|
8543 |
%} |
|
8544 |
||
8545 |
||
8546 |
instruct convF2D_reg(regD dst, regF src) %{ |
|
8547 |
match(Set dst (ConvF2D src)); |
|
8548 |
format %{ "FSTOD $src,$dst" %} |
|
8549 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); |
|
8550 |
ins_encode(form3_opf_rs2F_rdD(src, dst)); |
|
8551 |
ins_pipe(fcvtF2D); |
|
8552 |
%} |
|
8553 |
||
8554 |
||
8555 |
// Convert a float to an int in a float register. |
|
8556 |
// If the float is a NAN, stuff a zero in instead. |
|
8557 |
instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ |
|
8558 |
effect(DEF dst, USE src, KILL fcc0); |
|
8559 |
format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" |
|
8560 |
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" |
|
8561 |
"FSTOI $src,$dst\t! convert in delay slot\n\t" |
|
8562 |
"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" |
|
8563 |
"FSUBs $dst,$dst,$dst\t! cleared only if nan\n" |
|
8564 |
"skip:" %} |
|
8565 |
ins_encode(form_f2i_helper(src,dst)); |
|
8566 |
ins_pipe(fcvtF2I); |
|
8567 |
%} |
|
8568 |
||
8569 |
instruct convF2I_stk(stackSlotI dst, regF src) %{ |
|
8570 |
match(Set dst (ConvF2I src)); |
|
8571 |
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); |
|
8572 |
expand %{ |
|
8573 |
regF tmp; |
|
8574 |
convF2I_helper(tmp, src); |
|
8575 |
regF_to_stkI(dst, tmp); |
|
8576 |
%} |
|
8577 |
%} |
|
8578 |
||
8579 |
instruct convF2I_reg(iRegI dst, regF src) %{ |
|
8580 |
predicate(UseVIS >= 3); |
|
8581 |
match(Set dst (ConvF2I src)); |
|
8582 |
ins_cost(DEFAULT_COST*2 + BRANCH_COST); |
|
8583 |
expand %{ |
|
8584 |
regF tmp; |
|
8585 |
convF2I_helper(tmp, src); |
|
8586 |
MoveF2I_reg_reg(dst, tmp); |
|
8587 |
%} |
|
8588 |
%} |
|
8589 |
||
8590 |
||
8591 |
// Convert a float to a long in a float register. |
|
8592 |
// If the float is a NAN, stuff a zero in instead. |
|
8593 |
instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ |
|
8594 |
effect(DEF dst, USE src, KILL fcc0); |
|
8595 |
format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" |
|
8596 |
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" |
|
8597 |
"FSTOX $src,$dst\t! convert in delay slot\n\t" |
|
8598 |
"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" |
|
8599 |
"FSUBd $dst,$dst,$dst\t! cleared only if nan\n" |
|
8600 |
"skip:" %} |
|
8601 |
ins_encode(form_f2l_helper(src,dst)); |
|
8602 |
ins_pipe(fcvtF2L); |
|
8603 |
%} |
|
8604 |
||
8605 |
instruct convF2L_stk(stackSlotL dst, regF src) %{ |
|
8606 |
match(Set dst (ConvF2L src)); |
|
8607 |
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); |
|
8608 |
expand %{ |
|
8609 |
regD tmp; |
|
8610 |
convF2L_helper(tmp, src); |
|
8611 |
regD_to_stkL(dst, tmp); |
|
8612 |
%} |
|
8613 |
%} |
|
8614 |
||
8615 |
instruct convF2L_reg(iRegL dst, regF src) %{ |
|
8616 |
predicate(UseVIS >= 3); |
|
8617 |
match(Set dst (ConvF2L src)); |
|
8618 |
ins_cost(DEFAULT_COST*2 + BRANCH_COST); |
|
8619 |
expand %{ |
|
8620 |
regD tmp; |
|
8621 |
convF2L_helper(tmp, src); |
|
8622 |
MoveD2L_reg_reg(dst, tmp); |
|
8623 |
%} |
|
8624 |
%} |
|
8625 |
||
8626 |
||
8627 |
instruct convI2D_helper(regD dst, regF tmp) %{ |
|
8628 |
effect(USE tmp, DEF dst); |
|
8629 |
format %{ "FITOD $tmp,$dst" %} |
|
8630 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); |
|
8631 |
ins_encode(form3_opf_rs2F_rdD(tmp, dst)); |
|
8632 |
ins_pipe(fcvtI2D); |
|
8633 |
%} |
|
8634 |
||
8635 |
instruct convI2D_stk(stackSlotI src, regD dst) %{ |
|
8636 |
match(Set dst (ConvI2D src)); |
|
8637 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
8638 |
expand %{ |
|
8639 |
regF tmp; |
|
8640 |
stkI_to_regF(tmp, src); |
|
8641 |
convI2D_helper(dst, tmp); |
|
8642 |
%} |
|
8643 |
%} |
|
8644 |
||
8645 |
instruct convI2D_reg(regD_low dst, iRegI src) %{ |
|
8646 |
predicate(UseVIS >= 3); |
|
8647 |
match(Set dst (ConvI2D src)); |
|
8648 |
expand %{ |
|
8649 |
regF tmp; |
|
8650 |
MoveI2F_reg_reg(tmp, src); |
|
8651 |
convI2D_helper(dst, tmp); |
|
8652 |
%} |
|
8653 |
%} |
|
8654 |
||
8655 |
instruct convI2D_mem(regD_low dst, memory mem) %{ |
|
8656 |
match(Set dst (ConvI2D (LoadI mem))); |
|
8657 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
8658 |
size(8); |
|
8659 |
format %{ "LDF $mem,$dst\n\t" |
|
8660 |
"FITOD $dst,$dst" %} |
|
8661 |
opcode(Assembler::ldf_op3, Assembler::fitod_opf); |
|
8662 |
ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
|
8663 |
ins_pipe(floadF_mem); |
|
8664 |
%} |
|
8665 |
||
8666 |
||
8667 |
instruct convI2F_helper(regF dst, regF tmp) %{ |
|
8668 |
effect(DEF dst, USE tmp); |
|
8669 |
format %{ "FITOS $tmp,$dst" %} |
|
8670 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); |
|
8671 |
ins_encode(form3_opf_rs2F_rdF(tmp, dst)); |
|
8672 |
ins_pipe(fcvtI2F); |
|
8673 |
%} |
|
8674 |
||
8675 |
instruct convI2F_stk(regF dst, stackSlotI src) %{ |
|
8676 |
match(Set dst (ConvI2F src)); |
|
8677 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
8678 |
expand %{ |
|
8679 |
regF tmp; |
|
8680 |
stkI_to_regF(tmp,src); |
|
8681 |
convI2F_helper(dst, tmp); |
|
8682 |
%} |
|
8683 |
%} |
|
8684 |
||
8685 |
instruct convI2F_reg(regF dst, iRegI src) %{ |
|
8686 |
predicate(UseVIS >= 3); |
|
8687 |
match(Set dst (ConvI2F src)); |
|
8688 |
ins_cost(DEFAULT_COST); |
|
8689 |
expand %{ |
|
8690 |
regF tmp; |
|
8691 |
MoveI2F_reg_reg(tmp, src); |
|
8692 |
convI2F_helper(dst, tmp); |
|
8693 |
%} |
|
8694 |
%} |
|
8695 |
||
8696 |
instruct convI2F_mem( regF dst, memory mem ) %{ |
|
8697 |
match(Set dst (ConvI2F (LoadI mem))); |
|
8698 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
8699 |
size(8); |
|
8700 |
format %{ "LDF $mem,$dst\n\t" |
|
8701 |
"FITOS $dst,$dst" %} |
|
8702 |
opcode(Assembler::ldf_op3, Assembler::fitos_opf); |
|
8703 |
ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
|
8704 |
ins_pipe(floadF_mem); |
|
8705 |
%} |
|
8706 |
||
8707 |
||
8708 |
instruct convI2L_reg(iRegL dst, iRegI src) %{ |
|
8709 |
match(Set dst (ConvI2L src)); |
|
8710 |
size(4); |
|
8711 |
format %{ "SRA $src,0,$dst\t! int->long" %} |
|
8712 |
opcode(Assembler::sra_op3, Assembler::arith_op); |
|
8713 |
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); |
|
8714 |
ins_pipe(ialu_reg_reg); |
|
8715 |
%} |
|
8716 |
||
8717 |
// Zero-extend convert int to long |
|
8718 |
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ |
|
8719 |
match(Set dst (AndL (ConvI2L src) mask) ); |
|
8720 |
size(4); |
|
8721 |
format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} |
|
8722 |
opcode(Assembler::srl_op3, Assembler::arith_op); |
|
8723 |
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); |
|
8724 |
ins_pipe(ialu_reg_reg); |
|
8725 |
%} |
|
8726 |
||
8727 |
// Zero-extend long |
|
8728 |
instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ |
|
8729 |
match(Set dst (AndL src mask) ); |
|
8730 |
size(4); |
|
8731 |
format %{ "SRL $src,0,$dst\t! zero-extend long" %} |
|
8732 |
opcode(Assembler::srl_op3, Assembler::arith_op); |
|
8733 |
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); |
|
8734 |
ins_pipe(ialu_reg_reg); |
|
8735 |
%} |
|
8736 |
||
8737 |
||
1 | 8738 |
//----------- |
8739 |
// Long to Double conversion using V8 opcodes. |
|
8740 |
// Still useful because cheetah traps and becomes |
|
8741 |
// amazingly slow for some common numbers. |
|
8742 |
||
8743 |
// Magic constant, 0x43300000 |
|
8744 |
instruct loadConI_x43300000(iRegI dst) %{ |
|
8745 |
effect(DEF dst); |
|
8746 |
size(4); |
|
8747 |
format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} |
|
8748 |
ins_encode(SetHi22(0x43300000, dst)); |
|
8749 |
ins_pipe(ialu_none); |
|
8750 |
%} |
|
8751 |
||
8752 |
// Magic constant, 0x41f00000 |
|
8753 |
instruct loadConI_x41f00000(iRegI dst) %{ |
|
8754 |
effect(DEF dst); |
|
8755 |
size(4); |
|
8756 |
format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} |
|
8757 |
ins_encode(SetHi22(0x41f00000, dst)); |
|
8758 |
ins_pipe(ialu_none); |
|
8759 |
%} |
|
8760 |
||
8761 |
// Construct a double from two float halves |
|
8762 |
instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ |
|
8763 |
effect(DEF dst, USE src1, USE src2); |
|
8764 |
size(8); |
|
8765 |
format %{ "FMOVS $src1.hi,$dst.hi\n\t" |
|
8766 |
"FMOVS $src2.lo,$dst.lo" %} |
|
8767 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); |
|
8768 |
ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); |
|
8769 |
ins_pipe(faddD_reg_reg); |
|
8770 |
%} |
|
8771 |
||
8772 |
// Convert integer in high half of a double register (in the lower half of |
|
8773 |
// the double register file) to double |
|
8774 |
instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ |
|
8775 |
effect(DEF dst, USE src); |
|
8776 |
size(4); |
|
8777 |
format %{ "FITOD $src,$dst" %} |
|
8778 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); |
|
8779 |
ins_encode(form3_opf_rs2D_rdD(src, dst)); |
|
8780 |
ins_pipe(fcvtLHi2D); |
|
8781 |
%} |
|
8782 |
||
8783 |
// Add float double precision |
|
8784 |
instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ |
|
8785 |
effect(DEF dst, USE src1, USE src2); |
|
8786 |
size(4); |
|
8787 |
format %{ "FADDD $src1,$src2,$dst" %} |
|
8788 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); |
|
8789 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
8790 |
ins_pipe(faddD_reg_reg); |
|
8791 |
%} |
|
8792 |
||
8793 |
// Sub float double precision |
|
8794 |
instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ |
|
8795 |
effect(DEF dst, USE src1, USE src2); |
|
8796 |
size(4); |
|
8797 |
format %{ "FSUBD $src1,$src2,$dst" %} |
|
8798 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); |
|
8799 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
8800 |
ins_pipe(faddD_reg_reg); |
|
8801 |
%} |
|
8802 |
||
8803 |
// Mul float double precision |
|
8804 |
instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ |
|
8805 |
effect(DEF dst, USE src1, USE src2); |
|
8806 |
size(4); |
|
8807 |
format %{ "FMULD $src1,$src2,$dst" %} |
|
8808 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); |
|
8809 |
ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); |
|
8810 |
ins_pipe(fmulD_reg_reg); |
|
8811 |
%} |
|
8812 |
||
8813 |
instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ |
|
8814 |
match(Set dst (ConvL2D src)); |
|
8815 |
ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); |
|
8816 |
||
8817 |
expand %{ |
|
8818 |
regD_low tmpsrc; |
|
8819 |
iRegI ix43300000; |
|
8820 |
iRegI ix41f00000; |
|
8821 |
stackSlotL lx43300000; |
|
8822 |
stackSlotL lx41f00000; |
|
8823 |
regD_low dx43300000; |
|
8824 |
regD dx41f00000; |
|
8825 |
regD tmp1; |
|
8826 |
regD_low tmp2; |
|
8827 |
regD tmp3; |
|
8828 |
regD tmp4; |
|
8829 |
||
8830 |
stkL_to_regD(tmpsrc, src); |
|
8831 |
||
8832 |
loadConI_x43300000(ix43300000); |
|
8833 |
loadConI_x41f00000(ix41f00000); |
|
8834 |
regI_to_stkLHi(lx43300000, ix43300000); |
|
8835 |
regI_to_stkLHi(lx41f00000, ix41f00000); |
|
8836 |
stkL_to_regD(dx43300000, lx43300000); |
|
8837 |
stkL_to_regD(dx41f00000, lx41f00000); |
|
8838 |
||
8839 |
convI2D_regDHi_regD(tmp1, tmpsrc); |
|
8840 |
regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); |
|
8841 |
subD_regD_regD(tmp3, tmp2, dx43300000); |
|
8842 |
mulD_regD_regD(tmp4, tmp1, dx41f00000); |
|
8843 |
addD_regD_regD(dst, tmp3, tmp4); |
|
8844 |
%} |
|
8845 |
%} |
|
8846 |
||
8847 |
// Long to Double conversion using fast fxtof |
|
8848 |
instruct convL2D_helper(regD dst, regD tmp) %{ |
|
8849 |
effect(DEF dst, USE tmp); |
|
8850 |
size(4); |
|
8851 |
format %{ "FXTOD $tmp,$dst" %} |
|
8852 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); |
|
8853 |
ins_encode(form3_opf_rs2D_rdD(tmp, dst)); |
|
8854 |
ins_pipe(fcvtL2D); |
|
8855 |
%} |
|
8856 |
||
10027 | 8857 |
instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
1 | 8858 |
predicate(VM_Version::has_fast_fxtof()); |
8859 |
match(Set dst (ConvL2D src)); |
|
8860 |
ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); |
|
8861 |
expand %{ |
|
8862 |
regD tmp; |
|
8863 |
stkL_to_regD(tmp, src); |
|
8864 |
convL2D_helper(dst, tmp); |
|
8865 |
%} |
|
8866 |
%} |
|
8867 |
||
10027 | 8868 |
instruct convL2D_reg(regD dst, iRegL src) %{ |
8869 |
predicate(UseVIS >= 3); |
|
8870 |
match(Set dst (ConvL2D src)); |
|
8871 |
expand %{ |
|
8872 |
regD tmp; |
|
8873 |
MoveL2D_reg_reg(tmp, src); |
|
8874 |
convL2D_helper(dst, tmp); |
|
8875 |
%} |
|
8876 |
%} |
|
1 | 8877 |
|
8878 |
// Long to Float conversion using fast fxtof |
|
8879 |
instruct convL2F_helper(regF dst, regD tmp) %{ |
|
8880 |
effect(DEF dst, USE tmp); |
|
8881 |
size(4); |
|
8882 |
format %{ "FXTOS $tmp,$dst" %} |
|
8883 |
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); |
|
8884 |
ins_encode(form3_opf_rs2D_rdF(tmp, dst)); |
|
8885 |
ins_pipe(fcvtL2F); |
|
8886 |
%} |
|
8887 |
||
10027 | 8888 |
instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
1 | 8889 |
match(Set dst (ConvL2F src)); |
8890 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
8891 |
expand %{ |
|
8892 |
regD tmp; |
|
8893 |
stkL_to_regD(tmp, src); |
|
8894 |
convL2F_helper(dst, tmp); |
|
8895 |
%} |
|
8896 |
%} |
|
10027 | 8897 |
|
8898 |
instruct convL2F_reg(regF dst, iRegL src) %{ |
|
8899 |
predicate(UseVIS >= 3); |
|
8900 |
match(Set dst (ConvL2F src)); |
|
8901 |
ins_cost(DEFAULT_COST); |
|
8902 |
expand %{ |
|
8903 |
regD tmp; |
|
8904 |
MoveL2D_reg_reg(tmp, src); |
|
8905 |
convL2F_helper(dst, tmp); |
|
8906 |
%} |
|
8907 |
%} |
|
8908 |
||
1 | 8909 |
//----------- |
8910 |
||
8911 |
instruct convL2I_reg(iRegI dst, iRegL src) %{ |
|
8912 |
match(Set dst (ConvL2I src)); |
|
8913 |
#ifndef _LP64 |
|
8914 |
format %{ "MOV $src.lo,$dst\t! long->int" %} |
|
8915 |
ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); |
|
8916 |
ins_pipe(ialu_move_reg_I_to_L); |
|
8917 |
#else |
|
8918 |
size(4); |
|
8919 |
format %{ "SRA $src,R_G0,$dst\t! long->int" %} |
|
8920 |
ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); |
|
8921 |
ins_pipe(ialu_reg); |
|
8922 |
#endif |
|
8923 |
%} |
|
8924 |
||
8925 |
// Register Shift Right Immediate |
|
8926 |
instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ |
|
8927 |
match(Set dst (ConvL2I (RShiftL src cnt))); |
|
8928 |
||
8929 |
size(4); |
|
8930 |
format %{ "SRAX $src,$cnt,$dst" %} |
|
8931 |
opcode(Assembler::srax_op3, Assembler::arith_op); |
|
8932 |
ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); |
|
8933 |
ins_pipe(ialu_reg_imm); |
|
8934 |
%} |
|
8935 |
||
8936 |
//----------Control Flow Instructions------------------------------------------ |
|
8937 |
// Compare Instructions |
|
8938 |
// Compare Integers |
|
8939 |
instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ |
|
8940 |
match(Set icc (CmpI op1 op2)); |
|
8941 |
effect( DEF icc, USE op1, USE op2 ); |
|
8942 |
||
8943 |
size(4); |
|
8944 |
format %{ "CMP $op1,$op2" %} |
|
8945 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8946 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
8947 |
ins_pipe(ialu_cconly_reg_reg); |
|
8948 |
%} |
|
8949 |
||
8950 |
instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ |
|
8951 |
match(Set icc (CmpU op1 op2)); |
|
8952 |
||
8953 |
size(4); |
|
8954 |
format %{ "CMP $op1,$op2\t! unsigned" %} |
|
8955 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8956 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
8957 |
ins_pipe(ialu_cconly_reg_reg); |
|
8958 |
%} |
|
8959 |
||
8960 |
instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ |
|
8961 |
match(Set icc (CmpI op1 op2)); |
|
8962 |
effect( DEF icc, USE op1 ); |
|
8963 |
||
8964 |
size(4); |
|
8965 |
format %{ "CMP $op1,$op2" %} |
|
8966 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8967 |
ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
8968 |
ins_pipe(ialu_cconly_reg_imm); |
|
8969 |
%} |
|
8970 |
||
8971 |
instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ |
|
8972 |
match(Set icc (CmpI (AndI op1 op2) zero)); |
|
8973 |
||
8974 |
size(4); |
|
8975 |
format %{ "BTST $op2,$op1" %} |
|
8976 |
opcode(Assembler::andcc_op3, Assembler::arith_op); |
|
8977 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
8978 |
ins_pipe(ialu_cconly_reg_reg_zero); |
|
8979 |
%} |
|
8980 |
||
8981 |
instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ |
|
8982 |
match(Set icc (CmpI (AndI op1 op2) zero)); |
|
8983 |
||
8984 |
size(4); |
|
8985 |
format %{ "BTST $op2,$op1" %} |
|
8986 |
opcode(Assembler::andcc_op3, Assembler::arith_op); |
|
8987 |
ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
8988 |
ins_pipe(ialu_cconly_reg_imm_zero); |
|
8989 |
%} |
|
8990 |
||
8991 |
instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ |
|
8992 |
match(Set xcc (CmpL op1 op2)); |
|
8993 |
effect( DEF xcc, USE op1, USE op2 ); |
|
8994 |
||
8995 |
size(4); |
|
8996 |
format %{ "CMP $op1,$op2\t\t! long" %} |
|
8997 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
8998 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
8999 |
ins_pipe(ialu_cconly_reg_reg); |
|
9000 |
%} |
|
9001 |
||
9002 |
instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ |
|
9003 |
match(Set xcc (CmpL op1 con)); |
|
9004 |
effect( DEF xcc, USE op1, USE con ); |
|
9005 |
||
9006 |
size(4); |
|
9007 |
format %{ "CMP $op1,$con\t\t! long" %} |
|
9008 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
9009 |
ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); |
|
9010 |
ins_pipe(ialu_cconly_reg_reg); |
|
9011 |
%} |
|
9012 |
||
9013 |
instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ |
|
9014 |
match(Set xcc (CmpL (AndL op1 op2) zero)); |
|
9015 |
effect( DEF xcc, USE op1, USE op2 ); |
|
9016 |
||
9017 |
size(4); |
|
9018 |
format %{ "BTST $op1,$op2\t\t! long" %} |
|
9019 |
opcode(Assembler::andcc_op3, Assembler::arith_op); |
|
9020 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
9021 |
ins_pipe(ialu_cconly_reg_reg); |
|
9022 |
%} |
|
9023 |
||
9024 |
// useful for checking the alignment of a pointer: |
|
9025 |
instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ |
|
9026 |
match(Set xcc (CmpL (AndL op1 con) zero)); |
|
9027 |
effect( DEF xcc, USE op1, USE con ); |
|
9028 |
||
9029 |
size(4); |
|
9030 |
format %{ "BTST $op1,$con\t\t! long" %} |
|
9031 |
opcode(Assembler::andcc_op3, Assembler::arith_op); |
|
9032 |
ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); |
|
9033 |
ins_pipe(ialu_cconly_reg_reg); |
|
9034 |
%} |
|
9035 |
||
22513
dc47bc8ecb75
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
22512
diff
changeset
|
9036 |
instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ |
1 | 9037 |
match(Set icc (CmpU op1 op2)); |
9038 |
||
9039 |
size(4); |
|
9040 |
format %{ "CMP $op1,$op2\t! unsigned" %} |
|
9041 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
9042 |
ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
9043 |
ins_pipe(ialu_cconly_reg_imm); |
|
9044 |
%} |
|
9045 |
||
9046 |
// Compare Pointers |
|
9047 |
instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ |
|
9048 |
match(Set pcc (CmpP op1 op2)); |
|
9049 |
||
9050 |
size(4); |
|
9051 |
format %{ "CMP $op1,$op2\t! ptr" %} |
|
9052 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
9053 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
9054 |
ins_pipe(ialu_cconly_reg_reg); |
|
9055 |
%} |
|
9056 |
||
9057 |
instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ |
|
9058 |
match(Set pcc (CmpP op1 op2)); |
|
9059 |
||
9060 |
size(4); |
|
9061 |
format %{ "CMP $op1,$op2\t! ptr" %} |
|
9062 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
9063 |
ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
9064 |
ins_pipe(ialu_cconly_reg_imm); |
|
9065 |
%} |
|
9066 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9067 |
// Compare Narrow oops |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9068 |
instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9069 |
match(Set icc (CmpN op1 op2)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9070 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9071 |
size(4); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9072 |
format %{ "CMP $op1,$op2\t! compressed ptr" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9073 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9074 |
ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9075 |
ins_pipe(ialu_cconly_reg_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9076 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9077 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9078 |
instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9079 |
match(Set icc (CmpN op1 op2)); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9080 |
|
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9081 |
size(4); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9082 |
format %{ "CMP $op1,$op2\t! compressed ptr" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9083 |
opcode(Assembler::subcc_op3, Assembler::arith_op); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9084 |
ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9085 |
ins_pipe(ialu_cconly_reg_imm); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9086 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9087 |
|
1 | 9088 |
//----------Max and Min-------------------------------------------------------- |
9089 |
// Min Instructions |
|
9090 |
// Conditional move for min |
|
9091 |
instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ |
|
9092 |
effect( USE_DEF op2, USE op1, USE icc ); |
|
9093 |
||
9094 |
size(4); |
|
9095 |
format %{ "MOVlt icc,$op1,$op2\t! min" %} |
|
9096 |
opcode(Assembler::less); |
|
9097 |
ins_encode( enc_cmov_reg_minmax(op2,op1) ); |
|
9098 |
ins_pipe(ialu_reg_flags); |
|
9099 |
%} |
|
9100 |
||
9101 |
// Min Register with Register. |
|
9102 |
instruct minI_eReg(iRegI op1, iRegI op2) %{ |
|
9103 |
match(Set op2 (MinI op1 op2)); |
|
9104 |
ins_cost(DEFAULT_COST*2); |
|
9105 |
expand %{ |
|
9106 |
flagsReg icc; |
|
9107 |
compI_iReg(icc,op1,op2); |
|
9108 |
cmovI_reg_lt(op2,op1,icc); |
|
9109 |
%} |
|
9110 |
%} |
|
9111 |
||
9112 |
// Max Instructions |
|
9113 |
// Conditional move for max |
|
9114 |
instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ |
|
9115 |
effect( USE_DEF op2, USE op1, USE icc ); |
|
9116 |
format %{ "MOVgt icc,$op1,$op2\t! max" %} |
|
9117 |
opcode(Assembler::greater); |
|
9118 |
ins_encode( enc_cmov_reg_minmax(op2,op1) ); |
|
9119 |
ins_pipe(ialu_reg_flags); |
|
9120 |
%} |
|
9121 |
||
9122 |
// Max Register with Register |
|
9123 |
instruct maxI_eReg(iRegI op1, iRegI op2) %{ |
|
9124 |
match(Set op2 (MaxI op1 op2)); |
|
9125 |
ins_cost(DEFAULT_COST*2); |
|
9126 |
expand %{ |
|
9127 |
flagsReg icc; |
|
9128 |
compI_iReg(icc,op1,op2); |
|
9129 |
cmovI_reg_gt(op2,op1,icc); |
|
9130 |
%} |
|
9131 |
%} |
|
9132 |
||
9133 |
||
9134 |
//----------Float Compares---------------------------------------------------- |
|
9135 |
// Compare floating, generate condition code |
|
9136 |
instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ |
|
9137 |
match(Set fcc (CmpF src1 src2)); |
|
9138 |
||
9139 |
size(4); |
|
9140 |
format %{ "FCMPs $fcc,$src1,$src2" %} |
|
9141 |
opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); |
|
9142 |
ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); |
|
9143 |
ins_pipe(faddF_fcc_reg_reg_zero); |
|
9144 |
%} |
|
9145 |
||
9146 |
instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ |
|
9147 |
match(Set fcc (CmpD src1 src2)); |
|
9148 |
||
9149 |
size(4); |
|
9150 |
format %{ "FCMPd $fcc,$src1,$src2" %} |
|
9151 |
opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); |
|
9152 |
ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); |
|
9153 |
ins_pipe(faddD_fcc_reg_reg_zero); |
|
9154 |
%} |
|
9155 |
||
9156 |
||
9157 |
// Compare floating, generate -1,0,1 |
|
9158 |
instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ |
|
9159 |
match(Set dst (CmpF3 src1 src2)); |
|
9160 |
effect(KILL fcc0); |
|
9161 |
ins_cost(DEFAULT_COST*3+BRANCH_COST*3); |
|
9162 |
format %{ "fcmpl $dst,$src1,$src2" %} |
|
9163 |
// Primary = float |
|
9164 |
opcode( true ); |
|
9165 |
ins_encode( floating_cmp( dst, src1, src2 ) ); |
|
9166 |
ins_pipe( floating_cmp ); |
|
9167 |
%} |
|
9168 |
||
9169 |
instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ |
|
9170 |
match(Set dst (CmpD3 src1 src2)); |
|
9171 |
effect(KILL fcc0); |
|
9172 |
ins_cost(DEFAULT_COST*3+BRANCH_COST*3); |
|
9173 |
format %{ "dcmpl $dst,$src1,$src2" %} |
|
9174 |
// Primary = double (not float) |
|
9175 |
opcode( false ); |
|
9176 |
ins_encode( floating_cmp( dst, src1, src2 ) ); |
|
9177 |
ins_pipe( floating_cmp ); |
|
9178 |
%} |
|
9179 |
||
9180 |
//----------Branches--------------------------------------------------------- |
|
9181 |
// Jump |
|
9182 |
// (compare 'operand indIndex' and 'instruct addP_reg_reg' above) |
|
9183 |
instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ |
|
9184 |
match(Jump switch_val); |
|
11444
8a2619fd3fca
7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM
kvn
parents:
11431
diff
changeset
|
9185 |
effect(TEMP table); |
1 | 9186 |
|
9187 |
ins_cost(350); |
|
9188 |
||
7433 | 9189 |
format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9190 |
"LD [O7 + $switch_val], O7\n\t" |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9191 |
"JUMP O7" %} |
7433 | 9192 |
ins_encode %{ |
9193 |
// Calculate table address into a register. |
|
9194 |
Register table_reg; |
|
9195 |
Register label_reg = O7; |
|
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9196 |
// If we are calculating the size of this instruction don't trust |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9197 |
// zero offsets because they might change when |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9198 |
// MachConstantBaseNode decides to optimize the constant table |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9199 |
// base. |
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10971
diff
changeset
|
9200 |
if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
7433 | 9201 |
table_reg = $constanttablebase; |
9202 |
} else { |
|
9203 |
table_reg = O7; |
|
7437
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
9204 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
270cb0bf17af
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
7433
diff
changeset
|
9205 |
__ add($constanttablebase, con_offset, table_reg); |
7433 | 9206 |
} |
9207 |
||
9208 |
// Jump to base address + switch value |
|
9209 |
__ ld_ptr(table_reg, $switch_val$$Register, label_reg); |
|
9210 |
__ jmp(label_reg, G0); |
|
9211 |
__ delayed()->nop(); |
|
9212 |
%} |
|
1 | 9213 |
ins_pipe(ialu_reg_reg); |
9214 |
%} |
|
9215 |
||
9216 |
// Direct Branch. Use V8 version with longer range. |
|
9217 |
instruct branch(label labl) %{ |
|
9218 |
match(Goto); |
|
9219 |
effect(USE labl); |
|
9220 |
||
9221 |
size(8); |
|
9222 |
ins_cost(BRANCH_COST); |
|
9223 |
format %{ "BA $labl" %} |
|
10252 | 9224 |
ins_encode %{ |
9225 |
Label* L = $labl$$label; |
|
9226 |
__ ba(*L); |
|
9227 |
__ delayed()->nop(); |
|
9228 |
%} |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9229 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9230 |
ins_pipe(br); |
9231 |
%} |
|
9232 |
||
10264 | 9233 |
// Direct Branch, short with no delay slot |
9234 |
instruct branch_short(label labl) %{ |
|
9235 |
match(Goto); |
|
9236 |
predicate(UseCBCond); |
|
9237 |
effect(USE labl); |
|
9238 |
||
9239 |
size(4); |
|
9240 |
ins_cost(BRANCH_COST); |
|
9241 |
format %{ "BA $labl\t! short branch" %} |
|
22832
03720a5b7595
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
19319
diff
changeset
|
9242 |
ins_encode %{ |
10264 | 9243 |
Label* L = $labl$$label; |
9244 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9245 |
__ ba_short(*L); |
|
9246 |
%} |
|
9247 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9248 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9249 |
ins_pipe(cbcond_reg_imm); |
9250 |
%} |
|
9251 |
||
1 | 9252 |
// Conditional Direct Branch |
9253 |
instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ |
|
9254 |
match(If cmp icc); |
|
9255 |
effect(USE labl); |
|
9256 |
||
9257 |
size(8); |
|
9258 |
ins_cost(BRANCH_COST); |
|
9259 |
format %{ "BP$cmp $icc,$labl" %} |
|
9260 |
// Prim = bits 24-22, Secnd = bits 31-30 |
|
9261 |
ins_encode( enc_bp( labl, cmp, icc ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9262 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9263 |
ins_pipe(br_cc); |
9264 |
%} |
|
9265 |
||
9266 |
instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ |
|
9267 |
match(If cmp icc); |
|
9268 |
effect(USE labl); |
|
9269 |
||
10264 | 9270 |
ins_cost(BRANCH_COST); |
1 | 9271 |
format %{ "BP$cmp $icc,$labl" %} |
9272 |
// Prim = bits 24-22, Secnd = bits 31-30 |
|
9273 |
ins_encode( enc_bp( labl, cmp, icc ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9274 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9275 |
ins_pipe(br_cc); |
9276 |
%} |
|
9277 |
||
9278 |
instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ |
|
9279 |
match(If cmp pcc); |
|
9280 |
effect(USE labl); |
|
9281 |
||
9282 |
size(8); |
|
9283 |
ins_cost(BRANCH_COST); |
|
9284 |
format %{ "BP$cmp $pcc,$labl" %} |
|
10252 | 9285 |
ins_encode %{ |
9286 |
Label* L = $labl$$label; |
|
9287 |
Assembler::Predict predict_taken = |
|
9288 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9289 |
||
9290 |
__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); |
|
9291 |
__ delayed()->nop(); |
|
9292 |
%} |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9293 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9294 |
ins_pipe(br_cc); |
9295 |
%} |
|
9296 |
||
9297 |
instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ |
|
9298 |
match(If cmp fcc); |
|
9299 |
effect(USE labl); |
|
9300 |
||
9301 |
size(8); |
|
9302 |
ins_cost(BRANCH_COST); |
|
9303 |
format %{ "FBP$cmp $fcc,$labl" %} |
|
10252 | 9304 |
ins_encode %{ |
9305 |
Label* L = $labl$$label; |
|
9306 |
Assembler::Predict predict_taken = |
|
9307 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9308 |
||
9309 |
__ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); |
|
9310 |
__ delayed()->nop(); |
|
9311 |
%} |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9312 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9313 |
ins_pipe(br_fcc); |
9314 |
%} |
|
9315 |
||
9316 |
instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ |
|
9317 |
match(CountedLoopEnd cmp icc); |
|
9318 |
effect(USE labl); |
|
9319 |
||
9320 |
size(8); |
|
9321 |
ins_cost(BRANCH_COST); |
|
9322 |
format %{ "BP$cmp $icc,$labl\t! Loop end" %} |
|
9323 |
// Prim = bits 24-22, Secnd = bits 31-30 |
|
9324 |
ins_encode( enc_bp( labl, cmp, icc ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9325 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9326 |
ins_pipe(br_cc); |
9327 |
%} |
|
9328 |
||
9329 |
instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ |
|
9330 |
match(CountedLoopEnd cmp icc); |
|
9331 |
effect(USE labl); |
|
9332 |
||
9333 |
size(8); |
|
9334 |
ins_cost(BRANCH_COST); |
|
9335 |
format %{ "BP$cmp $icc,$labl\t! Loop end" %} |
|
9336 |
// Prim = bits 24-22, Secnd = bits 31-30 |
|
9337 |
ins_encode( enc_bp( labl, cmp, icc ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9338 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9339 |
ins_pipe(br_cc); |
9340 |
%} |
|
9341 |
||
10264 | 9342 |
// Compare and branch instructions |
9343 |
instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ |
|
9344 |
match(If cmp (CmpI op1 op2)); |
|
9345 |
effect(USE labl, KILL icc); |
|
9346 |
||
9347 |
size(12); |
|
9348 |
ins_cost(BRANCH_COST); |
|
9349 |
format %{ "CMP $op1,$op2\t! int\n\t" |
|
9350 |
"BP$cmp $labl" %} |
|
9351 |
ins_encode %{ |
|
9352 |
Label* L = $labl$$label; |
|
9353 |
Assembler::Predict predict_taken = |
|
9354 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9355 |
__ cmp($op1$$Register, $op2$$Register); |
|
9356 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9357 |
__ delayed()->nop(); |
|
9358 |
%} |
|
9359 |
ins_pipe(cmp_br_reg_reg); |
|
9360 |
%} |
|
9361 |
||
9362 |
instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ |
|
9363 |
match(If cmp (CmpI op1 op2)); |
|
9364 |
effect(USE labl, KILL icc); |
|
9365 |
||
9366 |
size(12); |
|
9367 |
ins_cost(BRANCH_COST); |
|
9368 |
format %{ "CMP $op1,$op2\t! int\n\t" |
|
9369 |
"BP$cmp $labl" %} |
|
9370 |
ins_encode %{ |
|
9371 |
Label* L = $labl$$label; |
|
9372 |
Assembler::Predict predict_taken = |
|
9373 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9374 |
__ cmp($op1$$Register, $op2$$constant); |
|
9375 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9376 |
__ delayed()->nop(); |
|
9377 |
%} |
|
9378 |
ins_pipe(cmp_br_reg_imm); |
|
9379 |
%} |
|
9380 |
||
9381 |
instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ |
|
9382 |
match(If cmp (CmpU op1 op2)); |
|
9383 |
effect(USE labl, KILL icc); |
|
9384 |
||
9385 |
size(12); |
|
9386 |
ins_cost(BRANCH_COST); |
|
9387 |
format %{ "CMP $op1,$op2\t! unsigned\n\t" |
|
9388 |
"BP$cmp $labl" %} |
|
9389 |
ins_encode %{ |
|
9390 |
Label* L = $labl$$label; |
|
9391 |
Assembler::Predict predict_taken = |
|
9392 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9393 |
__ cmp($op1$$Register, $op2$$Register); |
|
9394 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9395 |
__ delayed()->nop(); |
|
9396 |
%} |
|
9397 |
ins_pipe(cmp_br_reg_reg); |
|
9398 |
%} |
|
9399 |
||
9400 |
instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ |
|
9401 |
match(If cmp (CmpU op1 op2)); |
|
9402 |
effect(USE labl, KILL icc); |
|
9403 |
||
9404 |
size(12); |
|
9405 |
ins_cost(BRANCH_COST); |
|
9406 |
format %{ "CMP $op1,$op2\t! unsigned\n\t" |
|
9407 |
"BP$cmp $labl" %} |
|
9408 |
ins_encode %{ |
|
9409 |
Label* L = $labl$$label; |
|
9410 |
Assembler::Predict predict_taken = |
|
9411 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9412 |
__ cmp($op1$$Register, $op2$$constant); |
|
9413 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9414 |
__ delayed()->nop(); |
|
9415 |
%} |
|
9416 |
ins_pipe(cmp_br_reg_imm); |
|
9417 |
%} |
|
9418 |
||
9419 |
instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ |
|
9420 |
match(If cmp (CmpL op1 op2)); |
|
9421 |
effect(USE labl, KILL xcc); |
|
9422 |
||
9423 |
size(12); |
|
9424 |
ins_cost(BRANCH_COST); |
|
9425 |
format %{ "CMP $op1,$op2\t! long\n\t" |
|
9426 |
"BP$cmp $labl" %} |
|
9427 |
ins_encode %{ |
|
9428 |
Label* L = $labl$$label; |
|
9429 |
Assembler::Predict predict_taken = |
|
9430 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9431 |
__ cmp($op1$$Register, $op2$$Register); |
|
9432 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); |
|
9433 |
__ delayed()->nop(); |
|
9434 |
%} |
|
9435 |
ins_pipe(cmp_br_reg_reg); |
|
9436 |
%} |
|
9437 |
||
9438 |
instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ |
|
9439 |
match(If cmp (CmpL op1 op2)); |
|
9440 |
effect(USE labl, KILL xcc); |
|
9441 |
||
9442 |
size(12); |
|
9443 |
ins_cost(BRANCH_COST); |
|
9444 |
format %{ "CMP $op1,$op2\t! long\n\t" |
|
9445 |
"BP$cmp $labl" %} |
|
9446 |
ins_encode %{ |
|
9447 |
Label* L = $labl$$label; |
|
9448 |
Assembler::Predict predict_taken = |
|
9449 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9450 |
__ cmp($op1$$Register, $op2$$constant); |
|
9451 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); |
|
9452 |
__ delayed()->nop(); |
|
9453 |
%} |
|
9454 |
ins_pipe(cmp_br_reg_imm); |
|
9455 |
%} |
|
9456 |
||
9457 |
// Compare Pointers and branch |
|
9458 |
instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ |
|
9459 |
match(If cmp (CmpP op1 op2)); |
|
9460 |
effect(USE labl, KILL pcc); |
|
9461 |
||
9462 |
size(12); |
|
9463 |
ins_cost(BRANCH_COST); |
|
9464 |
format %{ "CMP $op1,$op2\t! ptr\n\t" |
|
9465 |
"B$cmp $labl" %} |
|
9466 |
ins_encode %{ |
|
9467 |
Label* L = $labl$$label; |
|
9468 |
Assembler::Predict predict_taken = |
|
9469 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9470 |
__ cmp($op1$$Register, $op2$$Register); |
|
9471 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); |
|
9472 |
__ delayed()->nop(); |
|
9473 |
%} |
|
9474 |
ins_pipe(cmp_br_reg_reg); |
|
9475 |
%} |
|
9476 |
||
9477 |
instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ |
|
9478 |
match(If cmp (CmpP op1 null)); |
|
9479 |
effect(USE labl, KILL pcc); |
|
9480 |
||
9481 |
size(12); |
|
9482 |
ins_cost(BRANCH_COST); |
|
9483 |
format %{ "CMP $op1,0\t! ptr\n\t" |
|
9484 |
"B$cmp $labl" %} |
|
9485 |
ins_encode %{ |
|
9486 |
Label* L = $labl$$label; |
|
9487 |
Assembler::Predict predict_taken = |
|
9488 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9489 |
__ cmp($op1$$Register, G0); |
|
9490 |
// bpr() is not used here since it has shorter distance. |
|
9491 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); |
|
9492 |
__ delayed()->nop(); |
|
9493 |
%} |
|
9494 |
ins_pipe(cmp_br_reg_reg); |
|
9495 |
%} |
|
9496 |
||
9497 |
instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ |
|
9498 |
match(If cmp (CmpN op1 op2)); |
|
9499 |
effect(USE labl, KILL icc); |
|
9500 |
||
9501 |
size(12); |
|
9502 |
ins_cost(BRANCH_COST); |
|
9503 |
format %{ "CMP $op1,$op2\t! compressed ptr\n\t" |
|
9504 |
"BP$cmp $labl" %} |
|
9505 |
ins_encode %{ |
|
9506 |
Label* L = $labl$$label; |
|
9507 |
Assembler::Predict predict_taken = |
|
9508 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9509 |
__ cmp($op1$$Register, $op2$$Register); |
|
9510 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9511 |
__ delayed()->nop(); |
|
9512 |
%} |
|
9513 |
ins_pipe(cmp_br_reg_reg); |
|
9514 |
%} |
|
9515 |
||
9516 |
instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ |
|
9517 |
match(If cmp (CmpN op1 null)); |
|
9518 |
effect(USE labl, KILL icc); |
|
9519 |
||
9520 |
size(12); |
|
9521 |
ins_cost(BRANCH_COST); |
|
9522 |
format %{ "CMP $op1,0\t! compressed ptr\n\t" |
|
9523 |
"BP$cmp $labl" %} |
|
9524 |
ins_encode %{ |
|
9525 |
Label* L = $labl$$label; |
|
9526 |
Assembler::Predict predict_taken = |
|
9527 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9528 |
__ cmp($op1$$Register, G0); |
|
9529 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9530 |
__ delayed()->nop(); |
|
9531 |
%} |
|
9532 |
ins_pipe(cmp_br_reg_reg); |
|
9533 |
%} |
|
9534 |
||
9535 |
// Loop back branch |
|
9536 |
instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ |
|
9537 |
match(CountedLoopEnd cmp (CmpI op1 op2)); |
|
9538 |
effect(USE labl, KILL icc); |
|
9539 |
||
9540 |
size(12); |
|
9541 |
ins_cost(BRANCH_COST); |
|
9542 |
format %{ "CMP $op1,$op2\t! int\n\t" |
|
9543 |
"BP$cmp $labl\t! Loop end" %} |
|
9544 |
ins_encode %{ |
|
9545 |
Label* L = $labl$$label; |
|
9546 |
Assembler::Predict predict_taken = |
|
9547 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9548 |
__ cmp($op1$$Register, $op2$$Register); |
|
9549 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9550 |
__ delayed()->nop(); |
|
9551 |
%} |
|
9552 |
ins_pipe(cmp_br_reg_reg); |
|
9553 |
%} |
|
9554 |
||
9555 |
instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ |
|
9556 |
match(CountedLoopEnd cmp (CmpI op1 op2)); |
|
9557 |
effect(USE labl, KILL icc); |
|
9558 |
||
9559 |
size(12); |
|
9560 |
ins_cost(BRANCH_COST); |
|
9561 |
format %{ "CMP $op1,$op2\t! int\n\t" |
|
9562 |
"BP$cmp $labl\t! Loop end" %} |
|
9563 |
ins_encode %{ |
|
9564 |
Label* L = $labl$$label; |
|
9565 |
Assembler::Predict predict_taken = |
|
9566 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9567 |
__ cmp($op1$$Register, $op2$$constant); |
|
9568 |
__ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); |
|
9569 |
__ delayed()->nop(); |
|
9570 |
%} |
|
9571 |
ins_pipe(cmp_br_reg_imm); |
|
9572 |
%} |
|
9573 |
||
9574 |
// Short compare and branch instructions |
|
9575 |
instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ |
|
9576 |
match(If cmp (CmpI op1 op2)); |
|
9577 |
predicate(UseCBCond); |
|
9578 |
effect(USE labl, KILL icc); |
|
9579 |
||
9580 |
size(4); |
|
9581 |
ins_cost(BRANCH_COST); |
|
9582 |
format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} |
|
9583 |
ins_encode %{ |
|
9584 |
Label* L = $labl$$label; |
|
9585 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9586 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); |
|
9587 |
%} |
|
9588 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9589 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9590 |
ins_pipe(cbcond_reg_reg); |
9591 |
%} |
|
9592 |
||
9593 |
instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ |
|
9594 |
match(If cmp (CmpI op1 op2)); |
|
9595 |
predicate(UseCBCond); |
|
9596 |
effect(USE labl, KILL icc); |
|
9597 |
||
9598 |
size(4); |
|
9599 |
ins_cost(BRANCH_COST); |
|
9600 |
format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} |
|
9601 |
ins_encode %{ |
|
9602 |
Label* L = $labl$$label; |
|
9603 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9604 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); |
|
9605 |
%} |
|
9606 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9607 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9608 |
ins_pipe(cbcond_reg_imm); |
9609 |
%} |
|
9610 |
||
9611 |
instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ |
|
9612 |
match(If cmp (CmpU op1 op2)); |
|
9613 |
predicate(UseCBCond); |
|
9614 |
effect(USE labl, KILL icc); |
|
9615 |
||
9616 |
size(4); |
|
9617 |
ins_cost(BRANCH_COST); |
|
9618 |
format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} |
|
9619 |
ins_encode %{ |
|
9620 |
Label* L = $labl$$label; |
|
9621 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9622 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); |
|
9623 |
%} |
|
9624 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9625 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9626 |
ins_pipe(cbcond_reg_reg); |
9627 |
%} |
|
9628 |
||
9629 |
instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ |
|
9630 |
match(If cmp (CmpU op1 op2)); |
|
9631 |
predicate(UseCBCond); |
|
9632 |
effect(USE labl, KILL icc); |
|
9633 |
||
9634 |
size(4); |
|
9635 |
ins_cost(BRANCH_COST); |
|
9636 |
format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} |
|
9637 |
ins_encode %{ |
|
9638 |
Label* L = $labl$$label; |
|
9639 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9640 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); |
|
9641 |
%} |
|
9642 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9643 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9644 |
ins_pipe(cbcond_reg_imm); |
9645 |
%} |
|
9646 |
||
9647 |
instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ |
|
9648 |
match(If cmp (CmpL op1 op2)); |
|
9649 |
predicate(UseCBCond); |
|
9650 |
effect(USE labl, KILL xcc); |
|
9651 |
||
9652 |
size(4); |
|
9653 |
ins_cost(BRANCH_COST); |
|
9654 |
format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} |
|
9655 |
ins_encode %{ |
|
9656 |
Label* L = $labl$$label; |
|
9657 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9658 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); |
|
9659 |
%} |
|
9660 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9661 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9662 |
ins_pipe(cbcond_reg_reg); |
9663 |
%} |
|
9664 |
||
9665 |
instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ |
|
9666 |
match(If cmp (CmpL op1 op2)); |
|
9667 |
predicate(UseCBCond); |
|
9668 |
effect(USE labl, KILL xcc); |
|
9669 |
||
9670 |
size(4); |
|
9671 |
ins_cost(BRANCH_COST); |
|
9672 |
format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} |
|
9673 |
ins_encode %{ |
|
9674 |
Label* L = $labl$$label; |
|
9675 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9676 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); |
|
9677 |
%} |
|
9678 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9679 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9680 |
ins_pipe(cbcond_reg_imm); |
9681 |
%} |
|
9682 |
||
9683 |
// Compare Pointers and branch |
|
9684 |
instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ |
|
9685 |
match(If cmp (CmpP op1 op2)); |
|
9686 |
predicate(UseCBCond); |
|
9687 |
effect(USE labl, KILL pcc); |
|
9688 |
||
9689 |
size(4); |
|
9690 |
ins_cost(BRANCH_COST); |
|
9691 |
#ifdef _LP64 |
|
9692 |
format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} |
|
9693 |
#else |
|
9694 |
format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} |
|
9695 |
#endif |
|
9696 |
ins_encode %{ |
|
9697 |
Label* L = $labl$$label; |
|
9698 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9699 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); |
|
9700 |
%} |
|
9701 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9702 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9703 |
ins_pipe(cbcond_reg_reg); |
9704 |
%} |
|
9705 |
||
9706 |
instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ |
|
9707 |
match(If cmp (CmpP op1 null)); |
|
9708 |
predicate(UseCBCond); |
|
9709 |
effect(USE labl, KILL pcc); |
|
9710 |
||
9711 |
size(4); |
|
9712 |
ins_cost(BRANCH_COST); |
|
9713 |
#ifdef _LP64 |
|
9714 |
format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} |
|
9715 |
#else |
|
9716 |
format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} |
|
9717 |
#endif |
|
9718 |
ins_encode %{ |
|
9719 |
Label* L = $labl$$label; |
|
9720 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9721 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); |
|
9722 |
%} |
|
9723 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9724 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9725 |
ins_pipe(cbcond_reg_reg); |
9726 |
%} |
|
9727 |
||
9728 |
instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ |
|
9729 |
match(If cmp (CmpN op1 op2)); |
|
9730 |
predicate(UseCBCond); |
|
9731 |
effect(USE labl, KILL icc); |
|
9732 |
||
9733 |
size(4); |
|
9734 |
ins_cost(BRANCH_COST); |
|
25741
aa6844e3ab10
8051550: Printing of 'cmpN_reg_branch_short' instruction shows wrong 'op2' register
thartmann
parents:
24932
diff
changeset
|
9735 |
format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} |
10264 | 9736 |
ins_encode %{ |
9737 |
Label* L = $labl$$label; |
|
9738 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9739 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); |
|
9740 |
%} |
|
9741 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9742 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9743 |
ins_pipe(cbcond_reg_reg); |
9744 |
%} |
|
9745 |
||
9746 |
instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ |
|
9747 |
match(If cmp (CmpN op1 null)); |
|
9748 |
predicate(UseCBCond); |
|
9749 |
effect(USE labl, KILL icc); |
|
9750 |
||
9751 |
size(4); |
|
9752 |
ins_cost(BRANCH_COST); |
|
9753 |
format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} |
|
9754 |
ins_encode %{ |
|
9755 |
Label* L = $labl$$label; |
|
9756 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9757 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); |
|
9758 |
%} |
|
9759 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9760 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9761 |
ins_pipe(cbcond_reg_reg); |
9762 |
%} |
|
9763 |
||
9764 |
// Loop back branch |
|
9765 |
instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ |
|
9766 |
match(CountedLoopEnd cmp (CmpI op1 op2)); |
|
9767 |
predicate(UseCBCond); |
|
9768 |
effect(USE labl, KILL icc); |
|
9769 |
||
9770 |
size(4); |
|
9771 |
ins_cost(BRANCH_COST); |
|
9772 |
format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} |
|
9773 |
ins_encode %{ |
|
9774 |
Label* L = $labl$$label; |
|
9775 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9776 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); |
|
9777 |
%} |
|
9778 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9779 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9780 |
ins_pipe(cbcond_reg_reg); |
9781 |
%} |
|
9782 |
||
9783 |
instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ |
|
9784 |
match(CountedLoopEnd cmp (CmpI op1 op2)); |
|
9785 |
predicate(UseCBCond); |
|
9786 |
effect(USE labl, KILL icc); |
|
9787 |
||
9788 |
size(4); |
|
9789 |
ins_cost(BRANCH_COST); |
|
9790 |
format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} |
|
9791 |
ins_encode %{ |
|
9792 |
Label* L = $labl$$label; |
|
9793 |
assert(__ use_cbcond(*L), "back to back cbcond"); |
|
9794 |
__ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); |
|
9795 |
%} |
|
9796 |
ins_short_branch(1); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9797 |
ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
10264 | 9798 |
ins_pipe(cbcond_reg_imm); |
9799 |
%} |
|
9800 |
||
9801 |
// Branch-on-register tests all 64 bits. We assume that values |
|
9802 |
// in 64-bit registers always remains zero or sign extended |
|
9803 |
// unless our code munges the high bits. Interrupts can chop |
|
9804 |
// the high order bits to zero or sign at any time. |
|
9805 |
instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ |
|
9806 |
match(If cmp (CmpI op1 zero)); |
|
9807 |
predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); |
|
9808 |
effect(USE labl); |
|
9809 |
||
9810 |
size(8); |
|
9811 |
ins_cost(BRANCH_COST); |
|
9812 |
format %{ "BR$cmp $op1,$labl" %} |
|
9813 |
ins_encode( enc_bpr( labl, cmp, op1 ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9814 |
ins_avoid_back_to_back(AVOID_BEFORE); |
10264 | 9815 |
ins_pipe(br_reg); |
9816 |
%} |
|
9817 |
||
9818 |
instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ |
|
9819 |
match(If cmp (CmpP op1 null)); |
|
9820 |
predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); |
|
9821 |
effect(USE labl); |
|
9822 |
||
9823 |
size(8); |
|
9824 |
ins_cost(BRANCH_COST); |
|
9825 |
format %{ "BR$cmp $op1,$labl" %} |
|
9826 |
ins_encode( enc_bpr( labl, cmp, op1 ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9827 |
ins_avoid_back_to_back(AVOID_BEFORE); |
10264 | 9828 |
ins_pipe(br_reg); |
9829 |
%} |
|
9830 |
||
9831 |
instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ |
|
9832 |
match(If cmp (CmpL op1 zero)); |
|
9833 |
predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); |
|
9834 |
effect(USE labl); |
|
9835 |
||
9836 |
size(8); |
|
9837 |
ins_cost(BRANCH_COST); |
|
9838 |
format %{ "BR$cmp $op1,$labl" %} |
|
9839 |
ins_encode( enc_bpr( labl, cmp, op1 ) ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9840 |
ins_avoid_back_to_back(AVOID_BEFORE); |
10264 | 9841 |
ins_pipe(br_reg); |
9842 |
%} |
|
9843 |
||
9844 |
||
1 | 9845 |
// ============================================================================ |
9846 |
// Long Compare |
|
9847 |
// |
|
9848 |
// Currently we hold longs in 2 registers. Comparing such values efficiently |
|
9849 |
// is tricky. The flavor of compare used depends on whether we are testing |
|
9850 |
// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. |
|
9851 |
// The GE test is the negated LT test. The LE test can be had by commuting |
|
9852 |
// the operands (yielding a GE test) and then negating; negate again for the |
|
9853 |
// GT test. The EQ test is done by ORcc'ing the high and low halves, and the |
|
9854 |
// NE test is negated from that. |
|
9855 |
||
9856 |
// Due to a shortcoming in the ADLC, it mixes up expressions like: |
|
9857 |
// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the |
|
9858 |
// difference between 'Y' and '0L'. The tree-matches for the CmpI sections |
|
9859 |
// are collapsed internally in the ADLC's dfa-gen code. The match for |
|
9860 |
// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the |
|
9861 |
// foo match ends up with the wrong leaf. One fix is to not match both |
|
9862 |
// reg-reg and reg-zero forms of long-compare. This is unfortunate because |
|
9863 |
// both forms beat the trinary form of long-compare and both are very useful |
|
9864 |
// on Intel which has so few registers. |
|
9865 |
||
9866 |
instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ |
|
9867 |
match(If cmp xcc); |
|
9868 |
effect(USE labl); |
|
9869 |
||
9870 |
size(8); |
|
9871 |
ins_cost(BRANCH_COST); |
|
9872 |
format %{ "BP$cmp $xcc,$labl" %} |
|
10252 | 9873 |
ins_encode %{ |
9874 |
Label* L = $labl$$label; |
|
9875 |
Assembler::Predict predict_taken = |
|
9876 |
cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
|
9877 |
||
9878 |
__ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); |
|
9879 |
__ delayed()->nop(); |
|
9880 |
%} |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
9881 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 9882 |
ins_pipe(br_cc); |
9883 |
%} |
|
9884 |
||
9885 |
// Manifest a CmpL3 result in an integer register. Very painful. |
|
9886 |
// This is the test to avoid. |
|
9887 |
instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ |
|
9888 |
match(Set dst (CmpL3 src1 src2) ); |
|
9889 |
effect( KILL ccr ); |
|
9890 |
ins_cost(6*DEFAULT_COST); |
|
9891 |
size(24); |
|
9892 |
format %{ "CMP $src1,$src2\t\t! long\n" |
|
9893 |
"\tBLT,a,pn done\n" |
|
9894 |
"\tMOV -1,$dst\t! delay slot\n" |
|
9895 |
"\tBGT,a,pn done\n" |
|
9896 |
"\tMOV 1,$dst\t! delay slot\n" |
|
9897 |
"\tCLR $dst\n" |
|
9898 |
"done:" %} |
|
9899 |
ins_encode( cmpl_flag(src1,src2,dst) ); |
|
9900 |
ins_pipe(cmpL_reg); |
|
9901 |
%} |
|
9902 |
||
9903 |
// Conditional move |
|
9904 |
instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ |
|
9905 |
match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); |
|
9906 |
ins_cost(150); |
|
9907 |
format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} |
|
9908 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
9909 |
ins_pipe(ialu_reg); |
|
9910 |
%} |
|
9911 |
||
9912 |
instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ |
|
9913 |
match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); |
|
9914 |
ins_cost(140); |
|
9915 |
format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} |
|
9916 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); |
|
9917 |
ins_pipe(ialu_imm); |
|
9918 |
%} |
|
9919 |
||
9920 |
instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ |
|
9921 |
match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); |
|
9922 |
ins_cost(150); |
|
9923 |
format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
9924 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
9925 |
ins_pipe(ialu_reg); |
|
9926 |
%} |
|
9927 |
||
9928 |
instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ |
|
9929 |
match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); |
|
9930 |
ins_cost(140); |
|
9931 |
format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
9932 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); |
|
9933 |
ins_pipe(ialu_imm); |
|
9934 |
%} |
|
9935 |
||
590
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9936 |
instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9937 |
match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9938 |
ins_cost(150); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9939 |
format %{ "MOV$cmp $xcc,$src,$dst" %} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9940 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9941 |
ins_pipe(ialu_reg); |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9942 |
%} |
2954744d7bba
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
589
diff
changeset
|
9943 |
|
1 | 9944 |
instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9945 |
match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); |
|
9946 |
ins_cost(150); |
|
9947 |
format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
9948 |
ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
9949 |
ins_pipe(ialu_reg); |
|
9950 |
%} |
|
9951 |
||
9952 |
instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ |
|
9953 |
match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); |
|
9954 |
ins_cost(140); |
|
9955 |
format %{ "MOV$cmp $xcc,$src,$dst" %} |
|
9956 |
ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); |
|
9957 |
ins_pipe(ialu_imm); |
|
9958 |
%} |
|
9959 |
||
9960 |
instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ |
|
9961 |
match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); |
|
9962 |
ins_cost(150); |
|
9963 |
opcode(0x101); |
|
9964 |
format %{ "FMOVS$cmp $xcc,$src,$dst" %} |
|
9965 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
9966 |
ins_pipe(int_conditional_float_move); |
|
9967 |
%} |
|
9968 |
||
9969 |
instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ |
|
9970 |
match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); |
|
9971 |
ins_cost(150); |
|
9972 |
opcode(0x102); |
|
9973 |
format %{ "FMOVD$cmp $xcc,$src,$dst" %} |
|
9974 |
ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); |
|
9975 |
ins_pipe(int_conditional_float_move); |
|
9976 |
%} |
|
9977 |
||
9978 |
// ============================================================================ |
|
9979 |
// Safepoint Instruction |
|
9980 |
instruct safePoint_poll(iRegP poll) %{ |
|
9981 |
match(SafePoint poll); |
|
9982 |
effect(USE poll); |
|
9983 |
||
9984 |
size(4); |
|
9985 |
#ifdef _LP64 |
|
9986 |
format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} |
|
9987 |
#else |
|
9988 |
format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} |
|
9989 |
#endif |
|
9990 |
ins_encode %{ |
|
9991 |
__ relocate(relocInfo::poll_type); |
|
9992 |
__ ld_ptr($poll$$Register, 0, G0); |
|
9993 |
%} |
|
9994 |
ins_pipe(loadPollP); |
|
9995 |
%} |
|
9996 |
||
9997 |
// ============================================================================ |
|
9998 |
// Call Instructions |
|
9999 |
// Call Java Static Instruction |
|
10000 |
instruct CallStaticJavaDirect( method meth ) %{ |
|
10001 |
match(CallStaticJava); |
|
5690 | 10002 |
predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
1 | 10003 |
effect(USE meth); |
10004 |
||
10005 |
size(8); |
|
10006 |
ins_cost(CALL_COST); |
|
10007 |
format %{ "CALL,static ; NOP ==> " %} |
|
10008 |
ins_encode( Java_Static_Call( meth ), call_epilog ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10009 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10010 |
ins_pipe(simple_call); |
10011 |
%} |
|
10012 |
||
5690 | 10013 |
// Call Java Static Instruction (method handle version) |
10014 |
instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ |
|
10015 |
match(CallStaticJava); |
|
10016 |
predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
10017 |
effect(USE meth, KILL l7_mh_SP_save); |
|
10018 |
||
10269
8a1ab847ebea
7079769: JSR 292: incorrect size() for CallStaticJavaHandle on sparc
twisti
parents:
10267
diff
changeset
|
10019 |
size(16); |
5690 | 10020 |
ins_cost(CALL_COST); |
10021 |
format %{ "CALL,static/MethodHandle" %} |
|
10022 |
ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); |
|
10023 |
ins_pipe(simple_call); |
|
10024 |
%} |
|
10025 |
||
1 | 10026 |
// Call Java Dynamic Instruction |
10027 |
instruct CallDynamicJavaDirect( method meth ) %{ |
|
10028 |
match(CallDynamicJava); |
|
10029 |
effect(USE meth); |
|
10030 |
||
10031 |
ins_cost(CALL_COST); |
|
10032 |
format %{ "SET (empty),R_G5\n\t" |
|
10033 |
"CALL,dynamic ; NOP ==> " %} |
|
10034 |
ins_encode( Java_Dynamic_Call( meth ), call_epilog ); |
|
10035 |
ins_pipe(call); |
|
10036 |
%} |
|
10037 |
||
10038 |
// Call Runtime Instruction |
|
10039 |
instruct CallRuntimeDirect(method meth, l7RegP l7) %{ |
|
10040 |
match(CallRuntime); |
|
10041 |
effect(USE meth, KILL l7); |
|
10042 |
ins_cost(CALL_COST); |
|
10043 |
format %{ "CALL,runtime" %} |
|
10044 |
ins_encode( Java_To_Runtime( meth ), |
|
10045 |
call_epilog, adjust_long_from_native_call ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10046 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10047 |
ins_pipe(simple_call); |
10048 |
%} |
|
10049 |
||
10050 |
// Call runtime without safepoint - same as CallRuntime |
|
10051 |
instruct CallLeafDirect(method meth, l7RegP l7) %{ |
|
10052 |
match(CallLeaf); |
|
10053 |
effect(USE meth, KILL l7); |
|
10054 |
ins_cost(CALL_COST); |
|
10055 |
format %{ "CALL,runtime leaf" %} |
|
10056 |
ins_encode( Java_To_Runtime( meth ), |
|
10057 |
call_epilog, |
|
10058 |
adjust_long_from_native_call ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10059 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10060 |
ins_pipe(simple_call); |
10061 |
%} |
|
10062 |
||
10063 |
// Call runtime without safepoint - same as CallLeaf |
|
10064 |
instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ |
|
10065 |
match(CallLeafNoFP); |
|
10066 |
effect(USE meth, KILL l7); |
|
10067 |
ins_cost(CALL_COST); |
|
10068 |
format %{ "CALL,runtime leaf nofp" %} |
|
10069 |
ins_encode( Java_To_Runtime( meth ), |
|
10070 |
call_epilog, |
|
10071 |
adjust_long_from_native_call ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10072 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10073 |
ins_pipe(simple_call); |
10074 |
%} |
|
10075 |
||
10076 |
// Tail Call; Jump from runtime stub to Java code. |
|
10077 |
// Also known as an 'interprocedural jump'. |
|
10078 |
// Target of jump will eventually return to caller. |
|
10079 |
// TailJump below removes the return address. |
|
10080 |
instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ |
|
10081 |
match(TailCall jump_target method_oop ); |
|
10082 |
||
10083 |
ins_cost(CALL_COST); |
|
10084 |
format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} |
|
10085 |
ins_encode(form_jmpl(jump_target)); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10086 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10087 |
ins_pipe(tail_call); |
10088 |
%} |
|
10089 |
||
10090 |
||
10091 |
// Return Instruction |
|
10092 |
instruct Ret() %{ |
|
10093 |
match(Return); |
|
10094 |
||
10095 |
// The epilogue node did the ret already. |
|
10096 |
size(0); |
|
10097 |
format %{ "! return" %} |
|
10098 |
ins_encode(); |
|
10099 |
ins_pipe(empty); |
|
10100 |
%} |
|
10101 |
||
10102 |
||
10103 |
// Tail Jump; remove the return address; jump to target. |
|
10104 |
// TailCall above leaves the return address around. |
|
10105 |
// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). |
|
10106 |
// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a |
|
10107 |
// "restore" before this instruction (in Epilogue), we need to materialize it |
|
10108 |
// in %i0. |
|
10109 |
instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ |
|
10110 |
match( TailJump jump_target ex_oop ); |
|
10111 |
ins_cost(CALL_COST); |
|
10112 |
format %{ "! discard R_O7\n\t" |
|
10113 |
"Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} |
|
10114 |
ins_encode(form_jmpl_set_exception_pc(jump_target)); |
|
10115 |
// opcode(Assembler::jmpl_op3, Assembler::arith_op); |
|
10116 |
// The hack duplicates the exception oop into G3, so that CreateEx can use it there. |
|
10117 |
// ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10118 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10119 |
ins_pipe(tail_call); |
10120 |
%} |
|
10121 |
||
10122 |
// Create exception oop: created by stack-crawling runtime code. |
|
10123 |
// Created exception is now available to this handler, and is setup |
|
10124 |
// just prior to jumping to this handler. No code emitted. |
|
10125 |
instruct CreateException( o0RegP ex_oop ) |
|
10126 |
%{ |
|
10127 |
match(Set ex_oop (CreateEx)); |
|
10128 |
ins_cost(0); |
|
10129 |
||
10130 |
size(0); |
|
10131 |
// use the following format syntax |
|
10132 |
format %{ "! exception oop is in R_O0; no code emitted" %} |
|
10133 |
ins_encode(); |
|
10134 |
ins_pipe(empty); |
|
10135 |
%} |
|
10136 |
||
10137 |
||
10138 |
// Rethrow exception: |
|
10139 |
// The exception oop will come in the first argument position. |
|
10140 |
// Then JUMP (not call) to the rethrow stub code. |
|
10141 |
instruct RethrowException() |
|
10142 |
%{ |
|
10143 |
match(Rethrow); |
|
10144 |
ins_cost(CALL_COST); |
|
10145 |
||
10146 |
// use the following format syntax |
|
10147 |
format %{ "Jmp rethrow_stub" %} |
|
10148 |
ins_encode(enc_rethrow); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10149 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10150 |
ins_pipe(tail_call); |
10151 |
%} |
|
10152 |
||
10153 |
||
10154 |
// Die now |
|
10155 |
instruct ShouldNotReachHere( ) |
|
10156 |
%{ |
|
10157 |
match(Halt); |
|
10158 |
ins_cost(CALL_COST); |
|
10159 |
||
10160 |
size(4); |
|
10161 |
// Use the following format syntax |
|
10162 |
format %{ "ILLTRAP ; ShouldNotReachHere" %} |
|
10163 |
ins_encode( form2_illtrap() ); |
|
10164 |
ins_pipe(tail_call); |
|
10165 |
%} |
|
10166 |
||
10167 |
// ============================================================================ |
|
10168 |
// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass |
|
10169 |
// array for an instance of the superklass. Set a hidden internal cache on a |
|
10170 |
// hit (cache is checked with exposed code in gen_subtype_check()). Return |
|
10171 |
// not zero for a miss or zero for a hit. The encoding ALSO sets flags. |
|
10172 |
instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ |
|
10173 |
match(Set index (PartialSubtypeCheck sub super)); |
|
10174 |
effect( KILL pcc, KILL o7 ); |
|
10175 |
ins_cost(DEFAULT_COST*10); |
|
10176 |
format %{ "CALL PartialSubtypeCheck\n\tNOP" %} |
|
10177 |
ins_encode( enc_PartialSubtypeCheck() ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10178 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10179 |
ins_pipe(partial_subtype_check_pipe); |
10180 |
%} |
|
10181 |
||
10182 |
instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ |
|
10183 |
match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); |
|
10184 |
effect( KILL idx, KILL o7 ); |
|
10185 |
ins_cost(DEFAULT_COST*10); |
|
10186 |
format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} |
|
10187 |
ins_encode( enc_PartialSubtypeCheck() ); |
|
24008
da7059252295
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
23498
diff
changeset
|
10188 |
ins_avoid_back_to_back(AVOID_BEFORE); |
1 | 10189 |
ins_pipe(partial_subtype_check_pipe); |
10190 |
%} |
|
10191 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
254
diff
changeset
|
10192 |
|
1 | 10193 |
// ============================================================================ |
10194 |
// inlined locking and unlocking |
|
10195 |
||
11445 | 10196 |
instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
1 | 10197 |
match(Set pcc (FastLock object box)); |
10198 |
||
11445 | 10199 |
effect(TEMP scratch2, USE_KILL box, KILL scratch); |
1 | 10200 |
ins_cost(100); |
10201 |
||
11445 | 10202 |
format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
1 | 10203 |
ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
10204 |
ins_pipe(long_memory_op); |
|
10205 |
%} |
|
10206 |
||
10207 |
||
11445 | 10208 |
instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
1 | 10209 |
match(Set pcc (FastUnlock object box)); |
11445 | 10210 |
effect(TEMP scratch2, USE_KILL box, KILL scratch); |
1 | 10211 |
ins_cost(100); |
10212 |
||
11445 | 10213 |
format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
1 | 10214 |
ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
10215 |
ins_pipe(long_memory_op); |
|
10216 |
%} |
|
10217 |
||
10501 | 10218 |
// The encodings are generic. |
1 | 10219 |
instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
10501 | 10220 |
predicate(!use_block_zeroing(n->in(2)) ); |
1 | 10221 |
match(Set dummy (ClearArray cnt base)); |
10222 |
effect(TEMP temp, KILL ccr); |
|
10223 |
ins_cost(300); |
|
10224 |
format %{ "MOV $cnt,$temp\n" |
|
10225 |
"loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" |
|
10226 |
" BRge loop\t\t! Clearing loop\n" |
|
10227 |
" STX G0,[$base+$temp]\t! delay slot" %} |
|
10501 | 10228 |
|
10229 |
ins_encode %{ |
|
10230 |
// Compiler ensures base is doubleword aligned and cnt is count of doublewords |
|
10231 |
Register nof_bytes_arg = $cnt$$Register; |
|
10232 |
Register nof_bytes_tmp = $temp$$Register; |
|
10233 |
Register base_pointer_arg = $base$$Register; |
|
10234 |
||
10235 |
Label loop; |
|
10236 |
__ mov(nof_bytes_arg, nof_bytes_tmp); |
|
10237 |
||
10238 |
// Loop and clear, walking backwards through the array. |
|
10239 |
// nof_bytes_tmp (if >0) is always the number of bytes to zero |
|
10240 |
__ bind(loop); |
|
10241 |
__ deccc(nof_bytes_tmp, 8); |
|
10242 |
__ br(Assembler::greaterEqual, true, Assembler::pt, loop); |
|
10243 |
__ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); |
|
10244 |
// %%%% this mini-loop must not cross a cache boundary! |
|
10245 |
%} |
|
10246 |
ins_pipe(long_memory_op); |
|
10247 |
%} |
|
10248 |
||
10249 |
instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ |
|
10250 |
predicate(use_block_zeroing(n->in(2))); |
|
10251 |
match(Set dummy (ClearArray cnt base)); |
|
10252 |
effect(USE_KILL cnt, USE_KILL base, KILL ccr); |
|
10253 |
ins_cost(300); |
|
10254 |
format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} |
|
10255 |
||
10256 |
ins_encode %{ |
|
10257 |
||
10258 |
assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); |
|
10259 |
Register to = $base$$Register; |
|
10260 |
Register count = $cnt$$Register; |
|
10261 |
||
10262 |
Label Ldone; |
|
10263 |
__ nop(); // Separate short branches |
|
10264 |
// Use BIS for zeroing (temp is not used). |
|
10265 |
__ bis_zeroing(to, count, G0, Ldone); |
|
10266 |
__ bind(Ldone); |
|
10267 |
||
10268 |
%} |
|
10269 |
ins_pipe(long_memory_op); |
|
10270 |
%} |
|
10271 |
||
10272 |
instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ |
|
10273 |
predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); |
|
10274 |
match(Set dummy (ClearArray cnt base)); |
|
10275 |
effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); |
|
10276 |
ins_cost(300); |
|
10277 |
format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} |
|
10278 |
||
10279 |
ins_encode %{ |
|
10280 |
||
10281 |
assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); |
|
10282 |
Register to = $base$$Register; |
|
10283 |
Register count = $cnt$$Register; |
|
10284 |
Register temp = $tmp$$Register; |
|
10285 |
||
10286 |
Label Ldone; |
|
10287 |
__ nop(); // Separate short branches |
|
10288 |
// Use BIS for zeroing |
|
10289 |
__ bis_zeroing(to, count, temp, Ldone); |
|
10290 |
__ bind(Ldone); |
|
10291 |
||
10292 |
%} |
|
1 | 10293 |
ins_pipe(long_memory_op); |
10294 |
%} |
|
10295 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10296 |
instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10297 |
o7RegI tmp, flagsReg ccr) %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10298 |
match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10299 |
effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
1 | 10300 |
ins_cost(300); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10301 |
format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10302 |
ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
1 | 10303 |
ins_pipe(long_memory_op); |
10304 |
%} |
|
10305 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10306 |
instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10307 |
o7RegI tmp, flagsReg ccr) %{ |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10308 |
match(Set result (StrEquals (Binary str1 str2) cnt)); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10309 |
effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
2348 | 10310 |
ins_cost(300); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10311 |
format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10312 |
ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
2348 | 10313 |
ins_pipe(long_memory_op); |
10314 |
%} |
|
10315 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10316 |
instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10317 |
o7RegI tmp2, flagsReg ccr) %{ |
2348 | 10318 |
match(Set result (AryEq ary1 ary2)); |
10319 |
effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); |
|
10320 |
ins_cost(300); |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10321 |
format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
3798
diff
changeset
|
10322 |
ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
2348 | 10323 |
ins_pipe(long_memory_op); |
10324 |
%} |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10325 |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10326 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10327 |
//---------- Zeros Count Instructions ------------------------------------------ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10328 |
|
14833
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10329 |
instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10330 |
predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10331 |
match(Set dst (CountLeadingZerosI src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10332 |
effect(TEMP dst, TEMP tmp, KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10333 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10334 |
// x |= (x >> 1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10335 |
// x |= (x >> 2); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10336 |
// x |= (x >> 4); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10337 |
// x |= (x >> 8); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10338 |
// x |= (x >> 16); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10339 |
// return (WORDBITS - popc(x)); |
4096
5d08743da209
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
4019
diff
changeset
|
10340 |
format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
5d08743da209
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
4019
diff
changeset
|
10341 |
"SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
5d08743da209
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
4019
diff
changeset
|
10342 |
"OR $dst,$tmp,$dst\n\t" |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10343 |
"SRL $dst,2,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10344 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10345 |
"SRL $dst,4,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10346 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10347 |
"SRL $dst,8,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10348 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10349 |
"SRL $dst,16,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10350 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10351 |
"POPC $dst,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10352 |
"MOV 32,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10353 |
"SUB $tmp,$dst,$dst" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10354 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10355 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10356 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10357 |
Register Rtmp = $tmp$$Register; |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10358 |
__ srl(Rsrc, 1, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10359 |
__ srl(Rsrc, 0, Rdst); |
4096
5d08743da209
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
4019
diff
changeset
|
10360 |
__ or3(Rdst, Rtmp, Rdst); |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10361 |
__ srl(Rdst, 2, Rtmp); |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10362 |
__ or3(Rdst, Rtmp, Rdst); |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10363 |
__ srl(Rdst, 4, Rtmp); |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10364 |
__ or3(Rdst, Rtmp, Rdst); |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10365 |
__ srl(Rdst, 8, Rtmp); |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10366 |
__ or3(Rdst, Rtmp, Rdst); |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10367 |
__ srl(Rdst, 16, Rtmp); |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10368 |
__ or3(Rdst, Rtmp, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10369 |
__ popc(Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10370 |
__ mov(BitsPerInt, Rtmp); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10371 |
__ sub(Rtmp, Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10372 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10373 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10374 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10375 |
|
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10376 |
instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10377 |
predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10378 |
match(Set dst (CountLeadingZerosL src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10379 |
effect(TEMP dst, TEMP tmp, KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10380 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10381 |
// x |= (x >> 1); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10382 |
// x |= (x >> 2); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10383 |
// x |= (x >> 4); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10384 |
// x |= (x >> 8); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10385 |
// x |= (x >> 16); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10386 |
// x |= (x >> 32); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10387 |
// return (WORDBITS - popc(x)); |
4096
5d08743da209
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
4019
diff
changeset
|
10388 |
format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10389 |
"OR $src,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10390 |
"SRLX $dst,2,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10391 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10392 |
"SRLX $dst,4,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10393 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10394 |
"SRLX $dst,8,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10395 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10396 |
"SRLX $dst,16,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10397 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10398 |
"SRLX $dst,32,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10399 |
"OR $dst,$tmp,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10400 |
"POPC $dst,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10401 |
"MOV 64,$tmp\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10402 |
"SUB $tmp,$dst,$dst" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10403 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10404 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10405 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10406 |
Register Rtmp = $tmp$$Register; |
7116
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10407 |
__ srlx(Rsrc, 1, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10408 |
__ or3( Rsrc, Rtmp, Rdst); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10409 |
__ srlx(Rdst, 2, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10410 |
__ or3( Rdst, Rtmp, Rdst); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10411 |
__ srlx(Rdst, 4, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10412 |
__ or3( Rdst, Rtmp, Rdst); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10413 |
__ srlx(Rdst, 8, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10414 |
__ or3( Rdst, Rtmp, Rdst); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10415 |
__ srlx(Rdst, 16, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10416 |
__ or3( Rdst, Rtmp, Rdst); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10417 |
__ srlx(Rdst, 32, Rtmp); |
e24b7743e3d4
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
7115
diff
changeset
|
10418 |
__ or3( Rdst, Rtmp, Rdst); |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10419 |
__ popc(Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10420 |
__ mov(BitsPerLong, Rtmp); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10421 |
__ sub(Rtmp, Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10422 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10423 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10424 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10425 |
|
14833
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10426 |
instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10427 |
predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10428 |
match(Set dst (CountTrailingZerosI src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10429 |
effect(TEMP dst, KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10430 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10431 |
// return popc(~x & (x - 1)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10432 |
format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10433 |
"ANDN $dst,$src,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10434 |
"SRL $dst,R_G0,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10435 |
"POPC $dst,$dst" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10436 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10437 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10438 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10439 |
__ sub(Rsrc, 1, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10440 |
__ andn(Rdst, Rsrc, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10441 |
__ srl(Rdst, G0, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10442 |
__ popc(Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10443 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10444 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10445 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10446 |
|
10736
1a11ec86574e
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
10507
diff
changeset
|
10447 |
instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10448 |
predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10449 |
match(Set dst (CountTrailingZerosL src)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10450 |
effect(TEMP dst, KILL cr); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10451 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10452 |
// return popc(~x & (x - 1)); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10453 |
format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10454 |
"ANDN $dst,$src,$dst\n\t" |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10455 |
"POPC $dst,$dst" %} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10456 |
ins_encode %{ |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10457 |
Register Rdst = $dst$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10458 |
Register Rsrc = $src$$Register; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10459 |
__ sub(Rsrc, 1, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10460 |
__ andn(Rdst, Rsrc, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10461 |
__ popc(Rdst, Rdst); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10462 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10463 |
ins_pipe(ialu_reg); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10464 |
%} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10465 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2576
diff
changeset
|
10466 |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10467 |
//---------- Population Count Instructions ------------------------------------- |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10468 |
|
14833
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10469 |
instruct popCountI(iRegIsafe dst, iRegI src) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10470 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10471 |
match(Set dst (PopCountI src)); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10472 |
|
14833
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10473 |
format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10474 |
"POPC $dst, $dst" %} |
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10475 |
ins_encode %{ |
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10476 |
__ srl($src$$Register, G0, $dst$$Register); |
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10477 |
__ popc($dst$$Register, $dst$$Register); |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10478 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10479 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10480 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10481 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10482 |
// Note: Long.bitCount(long) returns an int. |
14833
3c5e36997f11
8005033: clear high word for integer pop count on SPARC
twisti
parents:
13970
diff
changeset
|
10483 |
instruct popCountL(iRegIsafe dst, iRegL src) %{ |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10484 |
predicate(UsePopCountInstruction); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10485 |
match(Set dst (PopCountL src)); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10486 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10487 |
format %{ "POPC $src, $dst" %} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10488 |
ins_encode %{ |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10489 |
__ popc($src$$Register, $dst$$Register); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10490 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10491 |
ins_pipe(ialu_reg); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10492 |
%} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10493 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
10494 |
|
1 | 10495 |
// ============================================================================ |
10496 |
//------------Bytes reverse-------------------------------------------------- |
|
10497 |
||
10498 |
instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ |
|
10499 |
match(Set dst (ReverseBytesI src)); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10500 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10501 |
// Op cost is artificially doubled to make sure that load or store |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10502 |
// instructions are preferred over this one which requires a spill |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10503 |
// onto a stack slot. |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10504 |
ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10505 |
format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10506 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10507 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10508 |
__ set($src$$disp + STACK_BIAS, O7); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10509 |
__ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10510 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10511 |
ins_pipe( iload_mem ); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10512 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10513 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10514 |
instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10515 |
match(Set dst (ReverseBytesL src)); |
1 | 10516 |
|
10517 |
// Op cost is artificially doubled to make sure that load or store |
|
10518 |
// instructions are preferred over this one which requires a spill |
|
10519 |
// onto a stack slot. |
|
10520 |
ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10521 |
format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10522 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10523 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10524 |
__ set($src$$disp + STACK_BIAS, O7); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10525 |
__ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10526 |
%} |
1 | 10527 |
ins_pipe( iload_mem ); |
10528 |
%} |
|
10529 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10530 |
instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10531 |
match(Set dst (ReverseBytesUS src)); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10532 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10533 |
// Op cost is artificially doubled to make sure that load or store |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10534 |
// instructions are preferred over this one which requires a spill |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10535 |
// onto a stack slot. |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10536 |
ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10537 |
format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10538 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10539 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10540 |
// the value was spilled as an int so bias the load |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10541 |
__ set($src$$disp + STACK_BIAS + 2, O7); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10542 |
__ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10543 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10544 |
ins_pipe( iload_mem ); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10545 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10546 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10547 |
instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10548 |
match(Set dst (ReverseBytesS src)); |
1 | 10549 |
|
10550 |
// Op cost is artificially doubled to make sure that load or store |
|
10551 |
// instructions are preferred over this one which requires a spill |
|
10552 |
// onto a stack slot. |
|
10553 |
ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10554 |
format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10555 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10556 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10557 |
// the value was spilled as an int so bias the load |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10558 |
__ set($src$$disp + STACK_BIAS + 2, O7); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10559 |
__ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10560 |
%} |
1 | 10561 |
ins_pipe( iload_mem ); |
10562 |
%} |
|
10563 |
||
10564 |
// Load Integer reversed byte order |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10565 |
instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
1 | 10566 |
match(Set dst (ReverseBytesI (LoadI src))); |
10567 |
||
10568 |
ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10569 |
size(4); |
1 | 10570 |
format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
10571 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10572 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10573 |
__ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10574 |
%} |
1 | 10575 |
ins_pipe(iload_mem); |
10576 |
%} |
|
10577 |
||
10578 |
// Load Long - aligned and reversed |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10579 |
instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
1 | 10580 |
match(Set dst (ReverseBytesL (LoadL src))); |
10581 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10582 |
ins_cost(MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10583 |
size(4); |
1 | 10584 |
format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
10585 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10586 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10587 |
__ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10588 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10589 |
ins_pipe(iload_mem); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10590 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10591 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10592 |
// Load unsigned short / char reversed byte order |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10593 |
instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10594 |
match(Set dst (ReverseBytesUS (LoadUS src))); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10595 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10596 |
ins_cost(MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10597 |
size(4); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10598 |
format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10599 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10600 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10601 |
__ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10602 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10603 |
ins_pipe(iload_mem); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10604 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10605 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10606 |
// Load short reversed byte order |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10607 |
instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10608 |
match(Set dst (ReverseBytesS (LoadS src))); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10609 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10610 |
ins_cost(MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10611 |
size(4); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10612 |
format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10613 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10614 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10615 |
__ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10616 |
%} |
1 | 10617 |
ins_pipe(iload_mem); |
10618 |
%} |
|
10619 |
||
10620 |
// Store Integer reversed byte order |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10621 |
instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
1 | 10622 |
match(Set dst (StoreI dst (ReverseBytesI src))); |
10623 |
||
10624 |
ins_cost(MEMORY_REF_COST); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10625 |
size(4); |
1 | 10626 |
format %{ "STWA $src, $dst\t!asi=primary_little" %} |
10627 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10628 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10629 |
__ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10630 |
%} |
1 | 10631 |
ins_pipe(istore_mem_reg); |
10632 |
%} |
|
10633 |
||
10634 |
// Store Long reversed byte order |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10635 |
instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
1 | 10636 |
match(Set dst (StoreL dst (ReverseBytesL src))); |
10637 |
||
10638 |
ins_cost(MEMORY_REF_COST); |
|
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10639 |
size(4); |
1 | 10640 |
format %{ "STXA $src, $dst\t!asi=primary_little" %} |
10641 |
||
5352
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10642 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10643 |
__ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10644 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10645 |
ins_pipe(istore_mem_reg); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10646 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10647 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10648 |
// Store unsighed short/char reversed byte order |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10649 |
instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10650 |
match(Set dst (StoreC dst (ReverseBytesUS src))); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10651 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10652 |
ins_cost(MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10653 |
size(4); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10654 |
format %{ "STHA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10655 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10656 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10657 |
__ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10658 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10659 |
ins_pipe(istore_mem_reg); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10660 |
%} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10661 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10662 |
// Store short reversed byte order |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10663 |
instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10664 |
match(Set dst (StoreC dst (ReverseBytesS src))); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10665 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10666 |
ins_cost(MEMORY_REF_COST); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10667 |
size(4); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10668 |
format %{ "STHA $src, $dst\t!asi=primary_little" %} |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10669 |
|
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10670 |
ins_encode %{ |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10671 |
__ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
cee8f7acb7bc
6946040: add intrinsic for short and char reverseBytes
never
parents:
5251
diff
changeset
|
10672 |
%} |
1 | 10673 |
ins_pipe(istore_mem_reg); |
10674 |
%} |
|
10675 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10676 |
// ====================VECTOR INSTRUCTIONS===================================== |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10677 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10678 |
// Load Aligned Packed values into a Double Register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10679 |
instruct loadV8(regD dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10680 |
predicate(n->as_LoadVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10681 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10682 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10683 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10684 |
format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10685 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10686 |
__ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10687 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10688 |
ins_pipe(floadD_mem); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10689 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10690 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10691 |
// Store Vector in Double register to memory |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10692 |
instruct storeV8(memory mem, regD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10693 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10694 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10695 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10696 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10697 |
format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10698 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10699 |
__ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10700 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10701 |
ins_pipe(fstoreD_mem_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10702 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10703 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10704 |
// Store Zero into vector in memory |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10705 |
instruct storeV8B_zero(memory mem, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10706 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10707 |
match(Set mem (StoreVector mem (ReplicateB zero))); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10708 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10709 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10710 |
format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10711 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10712 |
__ stx(G0, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10713 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10714 |
ins_pipe(fstoreD_mem_zero); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10715 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10716 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10717 |
instruct storeV4S_zero(memory mem, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10718 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10719 |
match(Set mem (StoreVector mem (ReplicateS zero))); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10720 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10721 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10722 |
format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10723 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10724 |
__ stx(G0, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10725 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10726 |
ins_pipe(fstoreD_mem_zero); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10727 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10728 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10729 |
instruct storeV2I_zero(memory mem, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10730 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10731 |
match(Set mem (StoreVector mem (ReplicateI zero))); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10732 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10733 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10734 |
format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10735 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10736 |
__ stx(G0, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10737 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10738 |
ins_pipe(fstoreD_mem_zero); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10739 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10740 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10741 |
instruct storeV2F_zero(memory mem, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10742 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10743 |
match(Set mem (StoreVector mem (ReplicateF zero))); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10744 |
ins_cost(MEMORY_REF_COST); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10745 |
size(4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10746 |
format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10747 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10748 |
__ stx(G0, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10749 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10750 |
ins_pipe(fstoreD_mem_zero); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10751 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10752 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10753 |
// Replicate scalar to packed byte values into Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10754 |
instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10755 |
predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10756 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10757 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10758 |
format %{ "SLLX $src,56,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10759 |
"SRLX $tmp, 8,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10760 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10761 |
"SRLX $tmp,16,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10762 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10763 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10764 |
"OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10765 |
"MOVXTOD $tmp,$dst\t! MoveL2D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10766 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10767 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10768 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10769 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10770 |
__ sllx(Rsrc, 56, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10771 |
__ srlx(Rtmp, 8, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10772 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10773 |
__ srlx(Rtmp, 16, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10774 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10775 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10776 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10777 |
__ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10778 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10779 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10780 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10781 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10782 |
// Replicate scalar to packed byte values into Double stack |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10783 |
instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10784 |
predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10785 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10786 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10787 |
format %{ "SLLX $src,56,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10788 |
"SRLX $tmp, 8,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10789 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10790 |
"SRLX $tmp,16,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10791 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10792 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10793 |
"OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10794 |
"STX $tmp,$dst\t! regL to stkD" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10795 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10796 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10797 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10798 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10799 |
__ sllx(Rsrc, 56, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10800 |
__ srlx(Rtmp, 8, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10801 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10802 |
__ srlx(Rtmp, 16, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10803 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10804 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10805 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10806 |
__ set ($dst$$disp + STACK_BIAS, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10807 |
__ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10808 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10809 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10810 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10811 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10812 |
// Replicate scalar constant to packed byte values in Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10813 |
instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10814 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10815 |
match(Set dst (ReplicateB con)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10816 |
effect(KILL tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10817 |
format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10818 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10819 |
// XXX This is a quick fix for 6833573. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10820 |
//__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10821 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10822 |
__ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10823 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10824 |
ins_pipe(loadConFD); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10825 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10826 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10827 |
// Replicate scalar to packed char/short values into Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10828 |
instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10829 |
predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10830 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10831 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10832 |
format %{ "SLLX $src,48,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10833 |
"SRLX $tmp,16,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10834 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10835 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10836 |
"OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10837 |
"MOVXTOD $tmp,$dst\t! MoveL2D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10838 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10839 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10840 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10841 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10842 |
__ sllx(Rsrc, 48, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10843 |
__ srlx(Rtmp, 16, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10844 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10845 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10846 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10847 |
__ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10848 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10849 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10850 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10851 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10852 |
// Replicate scalar to packed char/short values into Double stack |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10853 |
instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10854 |
predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10855 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10856 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10857 |
format %{ "SLLX $src,48,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10858 |
"SRLX $tmp,16,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10859 |
"OR $tmp,$tmp2,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10860 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10861 |
"OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10862 |
"STX $tmp,$dst\t! regL to stkD" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10863 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10864 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10865 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10866 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10867 |
__ sllx(Rsrc, 48, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10868 |
__ srlx(Rtmp, 16, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10869 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10870 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10871 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10872 |
__ set ($dst$$disp + STACK_BIAS, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10873 |
__ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10874 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10875 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10876 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10877 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10878 |
// Replicate scalar constant to packed char/short values in Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10879 |
instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10880 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10881 |
match(Set dst (ReplicateS con)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10882 |
effect(KILL tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10883 |
format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10884 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10885 |
// XXX This is a quick fix for 6833573. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10886 |
//__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10887 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10888 |
__ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10889 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10890 |
ins_pipe(loadConFD); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10891 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10892 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10893 |
// Replicate scalar to packed int values into Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10894 |
instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10895 |
predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10896 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10897 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10898 |
format %{ "SLLX $src,32,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10899 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10900 |
"OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10901 |
"MOVXTOD $tmp,$dst\t! MoveL2D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10902 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10903 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10904 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10905 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10906 |
__ sllx(Rsrc, 32, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10907 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10908 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10909 |
__ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10910 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10911 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10912 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10913 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10914 |
// Replicate scalar to packed int values into Double stack |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10915 |
instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10916 |
predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10917 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10918 |
effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10919 |
format %{ "SLLX $src,32,$tmp\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10920 |
"SRLX $tmp,32,$tmp2\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10921 |
"OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10922 |
"STX $tmp,$dst\t! regL to stkD" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10923 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10924 |
Register Rsrc = $src$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10925 |
Register Rtmp = $tmp$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10926 |
Register Rtmp2 = $tmp2$$Register; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10927 |
__ sllx(Rsrc, 32, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10928 |
__ srlx(Rtmp, 32, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10929 |
__ or3 (Rtmp, Rtmp2, Rtmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10930 |
__ set ($dst$$disp + STACK_BIAS, Rtmp2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10931 |
__ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10932 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10933 |
ins_pipe(ialu_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10934 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10935 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10936 |
// Replicate scalar zero constant to packed int values in Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10937 |
instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10938 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10939 |
match(Set dst (ReplicateI con)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10940 |
effect(KILL tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10941 |
format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10942 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10943 |
// XXX This is a quick fix for 6833573. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10944 |
//__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10945 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10946 |
__ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10947 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10948 |
ins_pipe(loadConFD); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10949 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10950 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10951 |
// Replicate scalar to packed float values into Double stack |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10952 |
instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10953 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10954 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10955 |
ins_cost(MEMORY_REF_COST*2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10956 |
format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10957 |
"STF $src,$dst.lo" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10958 |
opcode(Assembler::stf_op3); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10959 |
ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10960 |
ins_pipe(fstoreF_stk_reg); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10961 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10962 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10963 |
// Replicate scalar zero constant to packed float values in Double register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10964 |
instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10965 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10966 |
match(Set dst (ReplicateF con)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10967 |
effect(KILL tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10968 |
format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10969 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10970 |
// XXX This is a quick fix for 6833573. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10971 |
//__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10972 |
RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10973 |
__ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10974 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10975 |
ins_pipe(loadConFD); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10976 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12957
diff
changeset
|
10977 |
|
1 | 10978 |
//----------PEEPHOLE RULES----------------------------------------------------- |
10979 |
// These must follow all instruction definitions as they use the names |
|
10980 |
// defined in the instructions definitions. |
|
10981 |
// |
|
2131 | 10982 |
// peepmatch ( root_instr_name [preceding_instruction]* ); |
1 | 10983 |
// |
10984 |
// peepconstraint %{ |
|
10985 |
// (instruction_number.operand_name relational_op instruction_number.operand_name |
|
10986 |
// [, ...] ); |
|
10987 |
// // instruction numbers are zero-based using left to right order in peepmatch |
|
10988 |
// |
|
10989 |
// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); |
|
10990 |
// // provide an instruction_number.operand_name for each operand that appears |
|
10991 |
// // in the replacement instruction's match rule |
|
10992 |
// |
|
10993 |
// ---------VM FLAGS--------------------------------------------------------- |
|
10994 |
// |
|
10995 |
// All peephole optimizations can be turned off using -XX:-OptoPeephole |
|
10996 |
// |
|
10997 |
// Each peephole rule is given an identifying number starting with zero and |
|
10998 |
// increasing by one in the order seen by the parser. An individual peephole |
|
10999 |
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# |
|
11000 |
// on the command-line. |
|
11001 |
// |
|
11002 |
// ---------CURRENT LIMITATIONS---------------------------------------------- |
|
11003 |
// |
|
11004 |
// Only match adjacent instructions in same basic block |
|
11005 |
// Only equality constraints |
|
11006 |
// Only constraints between operands, not (0.dest_reg == EAX_enc) |
|
11007 |
// Only one replacement instruction |
|
11008 |
// |
|
11009 |
// ---------EXAMPLE---------------------------------------------------------- |
|
11010 |
// |
|
11011 |
// // pertinent parts of existing instructions in architecture description |
|
11012 |
// instruct movI(eRegI dst, eRegI src) %{ |
|
11013 |
// match(Set dst (CopyI src)); |
|
11014 |
// %} |
|
11015 |
// |
|
11016 |
// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ |
|
11017 |
// match(Set dst (AddI dst src)); |
|
11018 |
// effect(KILL cr); |
|
11019 |
// %} |
|
11020 |
// |
|
11021 |
// // Change (inc mov) to lea |
|
11022 |
// peephole %{ |
|
11023 |
// // increment preceeded by register-register move |
|
11024 |
// peepmatch ( incI_eReg movI ); |
|
11025 |
// // require that the destination register of the increment |
|
11026 |
// // match the destination register of the move |
|
11027 |
// peepconstraint ( 0.dst == 1.dst ); |
|
11028 |
// // construct a replacement instruction that sets |
|
11029 |
// // the destination to ( move's source register + one ) |
|
11030 |
// peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); |
|
11031 |
// %} |
|
11032 |
// |
|
11033 |
||
11034 |
// // Change load of spilled value to only a spill |
|
11035 |
// instruct storeI(memory mem, eRegI src) %{ |
|
11036 |
// match(Set mem (StoreI mem src)); |
|
11037 |
// %} |
|
11038 |
// |
|
11039 |
// instruct loadI(eRegI dst, memory mem) %{ |
|
11040 |
// match(Set dst (LoadI mem)); |
|
11041 |
// %} |
|
11042 |
// |
|
11043 |
// peephole %{ |
|
11044 |
// peepmatch ( loadI storeI ); |
|
11045 |
// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); |
|
11046 |
// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); |
|
11047 |
// %} |
|
11048 |
||
11049 |
//----------SMARTSPILL RULES--------------------------------------------------- |
|
11050 |
// These must follow all instruction definitions as they use the names |
|
11051 |
// defined in the instructions definitions. |
|
11052 |
// |
|
11053 |
// SPARC will probably not have any of these rules due to RISC instruction set. |
|
11054 |
||
11055 |
//----------PIPELINE----------------------------------------------------------- |
|
11056 |
// Rules which define the behavior of the target architectures pipeline. |