8172881: AArch64: assertion failure: the int pressure is incorrect
Summary: Change the dst register type of get_and_setI/L/N/P from any register to non-special register.
Reviewed-by: aph
Contributed-by: yang.zhang@linaro.org
--- a/hotspot/src/cpu/aarch64/vm/aarch64.ad Thu Jan 26 08:35:17 2017 +0100
+++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad Sun Jan 22 16:33:54 2017 +0800
@@ -9994,7 +9994,7 @@
// END This section of the file is automatically generated. Do not edit --------------
// ---------------------------------------------------------------------
-instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
+instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
match(Set prev (GetAndSetI mem newv));
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
ins_encode %{
@@ -10003,7 +10003,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
+instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
match(Set prev (GetAndSetL mem newv));
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
ins_encode %{
@@ -10012,7 +10012,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setN(indirect mem, iRegNNoSp newv, iRegI prev) %{
+instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
match(Set prev (GetAndSetN mem newv));
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
ins_encode %{
@@ -10021,7 +10021,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setP(indirect mem, iRegPNoSp newv, iRegP prev) %{
+instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
match(Set prev (GetAndSetP mem newv));
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
ins_encode %{