8138952: C1: Distinguish between PPC32 and PPC64
Reviewed-by: twisti, goetz, vlivanov
--- a/hotspot/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
+ * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -105,4 +105,7 @@
void invalidate_registers(bool inv_r0, bool inv_r19, bool inv_r2, bool inv_r3, bool inv_r4, bool inv_r5) PRODUCT_RETURN;
+ // This platform only uses signal-based null checks. The Label is not needed.
+ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
+
#endif // CPU_AARCH64_VM_C1_MACROASSEMBLER_AARCH64_HPP
--- a/hotspot/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -88,4 +88,7 @@
void invalidate_registers(bool iregisters, bool lregisters, bool oregisters,
Register preserve1 = noreg, Register preserve2 = noreg);
+ // This platform only uses signal-based null checks. The Label is not needed.
+ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
+
#endif // CPU_SPARC_VM_C1_MACROASSEMBLER_SPARC_HPP
--- a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -117,4 +117,7 @@
void invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) PRODUCT_RETURN;
+ // This platform only uses signal-based null checks. The Label is not needed.
+ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); }
+
#endif // CPU_X86_VM_C1_MACROASSEMBLER_X86_HPP
--- a/hotspot/src/share/vm/c1/c1_Compilation.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_Compilation.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -192,7 +192,7 @@
const char* bailout_msg() const { return _bailout_msg; }
static int desired_max_code_buffer_size() {
-#ifndef PPC
+#ifndef PPC32
return (int) NMethodSizeLimit; // default 256K or 512K
#else
// conditional branches on PPC are restricted to 16 bit signed
--- a/hotspot/src/share/vm/c1/c1_LIR.cpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_LIR.cpp Mon Nov 23 11:06:14 2015 +0100
@@ -55,7 +55,7 @@
#endif // X86
-#if defined(SPARC) || defined(PPC)
+#if defined(SPARC) || defined(PPC32)
FloatRegister LIR_OprDesc::as_float_reg() const {
return FrameMap::nr2floatreg(fpu_regnr());
@@ -67,7 +67,7 @@
#endif
-#if defined(ARM) || defined (AARCH64)
+#if defined(ARM) || defined(AARCH64) || defined(PPC64)
FloatRegister LIR_OprDesc::as_float_reg() const {
return as_FloatRegister(fpu_regnr());
@@ -207,17 +207,17 @@
size_field() == double_size, "must match");
break;
case T_FLOAT:
- // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
+ // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register)
- PPC_ONLY(|| kindfield == cpu_register) ) &&
+ PPC32_ONLY(|| kindfield == cpu_register) ) &&
size_field() == single_size, "must match");
break;
case T_DOUBLE:
- // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
+ // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register)
- PPC_ONLY(|| kindfield == cpu_register) ) &&
+ PPC32_ONLY(|| kindfield == cpu_register) ) &&
size_field() == double_size, "must match");
break;
case T_BOOLEAN:
@@ -558,7 +558,7 @@
assert(opConvert->_info == NULL, "must be");
if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
if (opConvert->_result->is_valid()) do_output(opConvert->_result);
-#ifdef PPC
+#ifdef PPC32
if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
#endif
@@ -1953,7 +1953,7 @@
print_bytecode(out, bytecode());
in_opr()->print(out); out->print(" ");
result_opr()->print(out); out->print(" ");
-#ifdef PPC
+#ifdef PPC32
if(tmp1()->is_valid()) {
tmp1()->print(out); out->print(" ");
tmp2()->print(out); out->print(" ");
--- a/hotspot/src/share/vm/c1/c1_LIR.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_LIR.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -648,12 +648,14 @@
LIR_OprDesc::double_size |
LIR_OprDesc::is_xmm_mask); }
#endif // X86
-#ifdef PPC
+#if defined(PPC)
static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
(reg << LIR_OprDesc::reg2_shift) |
LIR_OprDesc::double_type |
LIR_OprDesc::fpu_register |
LIR_OprDesc::double_size); }
+#endif
+#ifdef PPC32
static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
LIR_OprDesc::float_type |
LIR_OprDesc::cpu_register |
@@ -663,7 +665,7 @@
LIR_OprDesc::double_type |
LIR_OprDesc::cpu_register |
LIR_OprDesc::double_size); }
-#endif // PPC
+#endif // PPC32
static LIR_Opr virtual_register(int index, BasicType type) {
LIR_Opr res;
@@ -1475,7 +1477,7 @@
private:
Bytecodes::Code _bytecode;
ConversionStub* _stub;
-#ifdef PPC
+#ifdef PPC32
LIR_Opr _tmp1;
LIR_Opr _tmp2;
#endif
@@ -1484,13 +1486,13 @@
LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
: LIR_Op1(lir_convert, opr, result)
, _stub(stub)
-#ifdef PPC
+#ifdef PPC32
, _tmp1(LIR_OprDesc::illegalOpr())
, _tmp2(LIR_OprDesc::illegalOpr())
#endif
, _bytecode(code) {}
-#ifdef PPC
+#ifdef PPC32
LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
,LIR_Opr tmp1, LIR_Opr tmp2)
: LIR_Op1(lir_convert, opr, result)
@@ -1502,7 +1504,7 @@
Bytecodes::Code bytecode() const { return _bytecode; }
ConversionStub* stub() const { return _stub; }
-#ifdef PPC
+#ifdef PPC32
LIR_Opr tmp1() const { return _tmp1; }
LIR_Opr tmp2() const { return _tmp2; }
#endif
@@ -2142,7 +2144,7 @@
void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); }
-#ifdef PPC
+#ifdef PPC32
void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
#endif
void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
--- a/hotspot/src/share/vm/c1/c1_LIRAssembler.cpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_LIRAssembler.cpp Mon Nov 23 11:06:14 2015 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -413,13 +413,14 @@
}
-void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
- add_debug_info_for_null_check(code_offset(), cinfo);
+ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
+ return add_debug_info_for_null_check(code_offset(), cinfo);
}
-void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
+ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
append_code_stub(stub);
+ return stub;
}
void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
@@ -557,10 +558,10 @@
case lir_null_check:
if (GenerateCompilerNullChecks) {
- add_debug_info_for_null_check_here(op->info());
+ ImplicitNullCheckStub* stub = add_debug_info_for_null_check_here(op->info());
if (op->in_opr()->is_single_cpu()) {
- _masm->null_check(op->in_opr()->as_register());
+ _masm->null_check(op->in_opr()->as_register(), stub->entry());
} else {
Unimplemented();
}
--- a/hotspot/src/share/vm/c1/c1_LIRAssembler.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_LIRAssembler.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -99,8 +99,8 @@
void add_debug_info_for_branch(CodeEmitInfo* info);
void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
void add_debug_info_for_div0_here(CodeEmitInfo* info);
- void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
- void add_debug_info_for_null_check_here(CodeEmitInfo* info);
+ ImplicitNullCheckStub* add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
+ ImplicitNullCheckStub* add_debug_info_for_null_check_here(CodeEmitInfo* info);
void set_24bit_FPU();
void reset_FPU();
--- a/hotspot/src/share/vm/c1/c1_LinearScan.cpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_LinearScan.cpp Mon Nov 23 11:06:14 2015 +0100
@@ -2087,7 +2087,7 @@
#ifdef _LP64
return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
#else
-#if defined(SPARC) || defined(PPC)
+#if defined(SPARC) || defined(PPC32)
return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
#else
return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
@@ -2728,7 +2728,7 @@
#ifdef ARM32
assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
#endif
-#ifdef PPC
+#ifdef PPC32
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
#endif
--- a/hotspot/src/share/vm/c1/c1_Runtime1.cpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/c1/c1_Runtime1.cpp Mon Nov 23 11:06:14 2015 +0100
@@ -210,7 +210,7 @@
case fpu2long_stub_id:
case unwind_exception_id:
case counter_overflow_id:
-#if defined(SPARC) || defined(PPC)
+#if defined(SPARC) || defined(PPC32)
case handle_exception_nofpu_id: // Unused on sparc
#endif
break;
@@ -1097,7 +1097,7 @@
ShouldNotReachHere();
}
-#if defined(SPARC) || defined(PPC)
+#if defined(SPARC) || defined(PPC32)
if (load_klass_or_mirror_patch_id ||
stub_id == Runtime1::load_appendix_patching_id) {
// Update the location in the nmethod with the proper
@@ -1195,7 +1195,7 @@
relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2,
relocInfo::none, rtype);
#endif
-#ifdef PPC
+#ifdef PPC32
{ address instr_pc2 = instr_pc + NativeMovConstReg::lo_offset;
RelocIterator iter2(nm, instr_pc2, instr_pc2 + 1);
relocInfo::change_reloc_info_for_address(&iter2, (address) instr_pc2,
--- a/hotspot/src/share/vm/runtime/sharedRuntime.cpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/runtime/sharedRuntime.cpp Mon Nov 23 11:06:14 2015 +0100
@@ -386,7 +386,7 @@
#endif
-#if defined(__SOFTFP__) || defined(PPC32)
+#if defined(__SOFTFP__) || defined(PPC)
double SharedRuntime::dsqrt(double f) {
return sqrt(f);
}
--- a/hotspot/src/share/vm/runtime/sharedRuntime.hpp Tue Nov 24 10:30:23 2015 +0100
+++ b/hotspot/src/share/vm/runtime/sharedRuntime.hpp Mon Nov 23 11:06:14 2015 +0100
@@ -141,7 +141,7 @@
static double dabs(double f);
#endif
-#if defined(__SOFTFP__) || defined(PPC32)
+#if defined(__SOFTFP__) || defined(PPC)
static double dsqrt(double f);
#endif