--- a/src/hotspot/cpu/ppc/ppc.ad	Thu Oct 05 10:55:34 2017 +0200
+++ b/src/hotspot/cpu/ppc/ppc.ad	Thu Oct 05 12:56:42 2017 +0200
@@ -452,17 +452,6 @@
 );
 
 alloc_class chunk3 (
-  // special registers
-  // These registers are not allocated, but used for nodes generated by postalloc expand.
-  SR_XER,
-  SR_LR,
-  SR_CTR,
-  SR_VRSAVE,
-  SR_SPEFSCR,
-  SR_PPR
-);
-
-alloc_class chunk4 (
   VSR0,
   VSR1,
   VSR2,
@@ -529,6 +518,17 @@
   VSR63
 );
 
+alloc_class chunk4 (
+  // special registers
+  // These registers are not allocated, but used for nodes generated by postalloc expand.
+  SR_XER,
+  SR_LR,
+  SR_CTR,
+  SR_VRSAVE,
+  SR_SPEFSCR,
+  SR_PPR
+);
+
 //-------Architecture Description Register Classes-----------------------
 
 // Several register classes are automatically defined based upon
@@ -1675,7 +1675,7 @@
   if (reg < 64+64) return rc_float;
 
   // Between float regs & stack are the flags regs.
-  assert(OptoReg::is_stack(reg), "blow up if spilling flags");
+  assert(OptoReg::is_stack(reg) || reg < 64+64+64, "blow up if spilling flags");
 
   return rc_stack;
 }
@@ -2221,7 +2221,7 @@
 
 // Vector width in bytes.
 const int Matcher::vector_width_in_bytes(BasicType bt) {
-  if (VM_Version::has_vsx()) {
+  if (SuperwordUseVSX) {
     assert(MaxVectorSize == 16, "");
     return 16;
   } else {
@@ -2232,7 +2232,7 @@
 
 // Vector ideal reg.
 const uint Matcher::vector_ideal_reg(int size) {
-  if (VM_Version::has_vsx()) {
+  if (SuperwordUseVSX) {
     assert(MaxVectorSize == 16 && size == 16, "");
     return Op_VecX;
   } else {
@@ -2258,10 +2258,7 @@
 
 // PPC doesn't support misaligned vectors store/load.
 const bool Matcher::misaligned_vectors_ok() {
-  if (VM_Version::has_vsx())
-    return !AlignVector; // can be changed by flag
-  else
-    return false;
+  return !AlignVector; // can be changed by flag
 }
 
 // PPC AES support not yet implemented