src/hotspot/cpu/ppc/ppc.ad
changeset 47594 fd0db78ac8d4
parent 47584 b02ea7eb7d93
child 48332 651a95f30dfb
equal deleted inserted replaced
47593:2d56326b98f0 47594:fd0db78ac8d4
   450   CCR6,
   450   CCR6,
   451   CCR7
   451   CCR7
   452 );
   452 );
   453 
   453 
   454 alloc_class chunk3 (
   454 alloc_class chunk3 (
   455   // special registers
       
   456   // These registers are not allocated, but used for nodes generated by postalloc expand.
       
   457   SR_XER,
       
   458   SR_LR,
       
   459   SR_CTR,
       
   460   SR_VRSAVE,
       
   461   SR_SPEFSCR,
       
   462   SR_PPR
       
   463 );
       
   464 
       
   465 alloc_class chunk4 (
       
   466   VSR0,
   455   VSR0,
   467   VSR1,
   456   VSR1,
   468   VSR2,
   457   VSR2,
   469   VSR3,
   458   VSR3,
   470   VSR4,
   459   VSR4,
   527   VSR61,
   516   VSR61,
   528   VSR62,
   517   VSR62,
   529   VSR63
   518   VSR63
   530 );
   519 );
   531 
   520 
       
   521 alloc_class chunk4 (
       
   522   // special registers
       
   523   // These registers are not allocated, but used for nodes generated by postalloc expand.
       
   524   SR_XER,
       
   525   SR_LR,
       
   526   SR_CTR,
       
   527   SR_VRSAVE,
       
   528   SR_SPEFSCR,
       
   529   SR_PPR
       
   530 );
       
   531 
   532 //-------Architecture Description Register Classes-----------------------
   532 //-------Architecture Description Register Classes-----------------------
   533 
   533 
   534 // Several register classes are automatically defined based upon
   534 // Several register classes are automatically defined based upon
   535 // information in this architecture description.
   535 // information in this architecture description.
   536 
   536 
  1673 
  1673 
  1674   // We have 64 floating-point register halves, starting at index 64.
  1674   // We have 64 floating-point register halves, starting at index 64.
  1675   if (reg < 64+64) return rc_float;
  1675   if (reg < 64+64) return rc_float;
  1676 
  1676 
  1677   // Between float regs & stack are the flags regs.
  1677   // Between float regs & stack are the flags regs.
  1678   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
  1678   assert(OptoReg::is_stack(reg) || reg < 64+64+64, "blow up if spilling flags");
  1679 
  1679 
  1680   return rc_stack;
  1680   return rc_stack;
  1681 }
  1681 }
  1682 
  1682 
  1683 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
  1683 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
  2219   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
  2219   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
  2220 }
  2220 }
  2221 
  2221 
  2222 // Vector width in bytes.
  2222 // Vector width in bytes.
  2223 const int Matcher::vector_width_in_bytes(BasicType bt) {
  2223 const int Matcher::vector_width_in_bytes(BasicType bt) {
  2224   if (VM_Version::has_vsx()) {
  2224   if (SuperwordUseVSX) {
  2225     assert(MaxVectorSize == 16, "");
  2225     assert(MaxVectorSize == 16, "");
  2226     return 16;
  2226     return 16;
  2227   } else {
  2227   } else {
  2228     assert(MaxVectorSize == 8, "");
  2228     assert(MaxVectorSize == 8, "");
  2229     return 8;
  2229     return 8;
  2230   }
  2230   }
  2231 }
  2231 }
  2232 
  2232 
  2233 // Vector ideal reg.
  2233 // Vector ideal reg.
  2234 const uint Matcher::vector_ideal_reg(int size) {
  2234 const uint Matcher::vector_ideal_reg(int size) {
  2235   if (VM_Version::has_vsx()) {
  2235   if (SuperwordUseVSX) {
  2236     assert(MaxVectorSize == 16 && size == 16, "");
  2236     assert(MaxVectorSize == 16 && size == 16, "");
  2237     return Op_VecX;
  2237     return Op_VecX;
  2238   } else {
  2238   } else {
  2239     assert(MaxVectorSize == 8 && size == 8, "");
  2239     assert(MaxVectorSize == 8 && size == 8, "");
  2240     return Op_RegL;
  2240     return Op_RegL;
  2256   return max_vector_size(bt); // Same as max.
  2256   return max_vector_size(bt); // Same as max.
  2257 }
  2257 }
  2258 
  2258 
  2259 // PPC doesn't support misaligned vectors store/load.
  2259 // PPC doesn't support misaligned vectors store/load.
  2260 const bool Matcher::misaligned_vectors_ok() {
  2260 const bool Matcher::misaligned_vectors_ok() {
  2261   if (VM_Version::has_vsx())
  2261   return !AlignVector; // can be changed by flag
  2262     return !AlignVector; // can be changed by flag
       
  2263   else
       
  2264     return false;
       
  2265 }
  2262 }
  2266 
  2263 
  2267 // PPC AES support not yet implemented
  2264 // PPC AES support not yet implemented
  2268 const bool Matcher::pass_original_key_for_aes() {
  2265 const bool Matcher::pass_original_key_for_aes() {
  2269   return false;
  2266   return false;