--- a/hotspot/src/cpu/x86/vm/globalDefinitions_x86.hpp Mon Oct 13 22:11:39 2014 +0200
+++ b/hotspot/src/cpu/x86/vm/globalDefinitions_x86.hpp Tue Oct 14 10:32:12 2014 -0700
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -35,4 +35,27 @@
#define SUPPORTS_NATIVE_CX8
+// The expected size in bytes of a cache line, used to pad data structures.
+#if defined(TIERED)
+ #ifdef _LP64
+ // tiered, 64-bit, large machine
+ #define DEFAULT_CACHE_LINE_SIZE 128
+ #else
+ // tiered, 32-bit, medium machine
+ #define DEFAULT_CACHE_LINE_SIZE 64
+ #endif
+#elif defined(COMPILER1)
+ // pure C1, 32-bit, small machine
+ // i486 was the last Intel chip with 16-byte cache line size
+ #define DEFAULT_CACHE_LINE_SIZE 32
+#elif defined(COMPILER2) || defined(SHARK)
+ #ifdef _LP64
+ // pure C2, 64-bit, large machine
+ #define DEFAULT_CACHE_LINE_SIZE 128
+ #else
+ // pure C2, 32-bit, medium machine
+ #define DEFAULT_CACHE_LINE_SIZE 64
+ #endif
+#endif
+
#endif // CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP