src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64Assembler.java
equal
deleted
inserted
replaced
206 private static final int VEX_SIMD_F3 = 0x2; |
206 private static final int VEX_SIMD_F3 = 0x2; |
207 private static final int VEX_SIMD_F2 = 0x3; |
207 private static final int VEX_SIMD_F2 = 0x3; |
208 } |
208 } |
209 |
209 |
210 private static class VexOpcode { |
210 private static class VexOpcode { |
211 private static final int VEX_OPCODE_NONE = 0x0; |
|
212 private static final int VEX_OPCODE_0F = 0x1; |
211 private static final int VEX_OPCODE_0F = 0x1; |
213 private static final int VEX_OPCODE_0F_38 = 0x2; |
212 private static final int VEX_OPCODE_0F_38 = 0x2; |
214 private static final int VEX_OPCODE_0F_3A = 0x3; |
213 private static final int VEX_OPCODE_0F_3A = 0x3; |
215 } |
214 } |
216 |
215 |
859 case 0x5F: |
858 case 0x5F: |
860 isSimd = true; |
859 isSimd = true; |
861 break; |
860 break; |
862 } |
861 } |
863 |
862 |
|
863 int opc = 0; |
|
864 if (isSimd) { |
|
865 switch (prefix2) { |
|
866 case P_0F: |
|
867 opc = VexOpcode.VEX_OPCODE_0F; |
|
868 break; |
|
869 case P_0F38: |
|
870 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
871 break; |
|
872 case P_0F3A: |
|
873 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
874 break; |
|
875 default: |
|
876 isSimd = false; |
|
877 break; |
|
878 } |
|
879 } |
|
880 |
864 if (isSimd) { |
881 if (isSimd) { |
865 int pre; |
882 int pre; |
866 int opc; |
|
867 boolean rexVexW = (size == QWORD) ? true : false; |
883 boolean rexVexW = (size == QWORD) ? true : false; |
868 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
884 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
869 int curPrefix = size.sizePrefix | prefix1; |
885 int curPrefix = size.sizePrefix | prefix1; |
870 switch (curPrefix) { |
886 switch (curPrefix) { |
871 case 0x66: |
887 case 0x66: |
877 case 0xF3: |
893 case 0xF3: |
878 pre = VexSimdPrefix.VEX_SIMD_F3; |
894 pre = VexSimdPrefix.VEX_SIMD_F3; |
879 break; |
895 break; |
880 default: |
896 default: |
881 pre = VexSimdPrefix.VEX_SIMD_NONE; |
897 pre = VexSimdPrefix.VEX_SIMD_NONE; |
882 break; |
|
883 } |
|
884 switch (prefix2) { |
|
885 case P_0F: |
|
886 opc = VexOpcode.VEX_OPCODE_0F; |
|
887 break; |
|
888 case P_0F38: |
|
889 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
890 break; |
|
891 case P_0F3A: |
|
892 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
893 break; |
|
894 default: |
|
895 opc = VexOpcode.VEX_OPCODE_NONE; |
|
896 break; |
898 break; |
897 } |
899 } |
898 int encode; |
900 int encode; |
899 if (noNds) { |
901 if (noNds) { |
900 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes); |
902 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes); |
936 case 0x5F: |
938 case 0x5F: |
937 isSimd = true; |
939 isSimd = true; |
938 break; |
940 break; |
939 } |
941 } |
940 |
942 |
|
943 int opc = 0; |
|
944 if (isSimd) { |
|
945 switch (prefix2) { |
|
946 case P_0F: |
|
947 opc = VexOpcode.VEX_OPCODE_0F; |
|
948 break; |
|
949 case P_0F38: |
|
950 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
951 break; |
|
952 case P_0F3A: |
|
953 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
954 break; |
|
955 default: |
|
956 isSimd = false; |
|
957 break; |
|
958 } |
|
959 } |
|
960 |
941 if (isSimd) { |
961 if (isSimd) { |
942 int pre; |
962 int pre; |
943 int opc; |
|
944 boolean rexVexW = (size == QWORD) ? true : false; |
963 boolean rexVexW = (size == QWORD) ? true : false; |
945 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
964 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
946 int curPrefix = size.sizePrefix | prefix1; |
965 int curPrefix = size.sizePrefix | prefix1; |
947 switch (curPrefix) { |
966 switch (curPrefix) { |
948 case 0x66: |
967 case 0x66: |
954 case 0xF3: |
973 case 0xF3: |
955 pre = VexSimdPrefix.VEX_SIMD_F3; |
974 pre = VexSimdPrefix.VEX_SIMD_F3; |
956 break; |
975 break; |
957 default: |
976 default: |
958 pre = VexSimdPrefix.VEX_SIMD_NONE; |
977 pre = VexSimdPrefix.VEX_SIMD_NONE; |
959 break; |
|
960 } |
|
961 switch (prefix2) { |
|
962 case P_0F: |
|
963 opc = VexOpcode.VEX_OPCODE_0F; |
|
964 break; |
|
965 case P_0F38: |
|
966 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
967 break; |
|
968 case P_0F3A: |
|
969 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
970 break; |
|
971 default: |
|
972 opc = VexOpcode.VEX_OPCODE_NONE; |
|
973 break; |
978 break; |
974 } |
979 } |
975 if (noNds) { |
980 if (noNds) { |
976 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes); |
981 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes); |
977 } else { |
982 } else { |
1053 break; |
1058 break; |
1054 case P_0F3A: |
1059 case P_0F3A: |
1055 opc = VexOpcode.VEX_OPCODE_0F_3A; |
1060 opc = VexOpcode.VEX_OPCODE_0F_3A; |
1056 break; |
1061 break; |
1057 default: |
1062 default: |
1058 opc = VexOpcode.VEX_OPCODE_NONE; |
1063 throw GraalError.shouldNotReachHere("invalid VEX instruction prefix"); |
1059 break; |
|
1060 } |
1064 } |
1061 int encode; |
1065 int encode; |
1062 encode = asm.simdPrefixAndEncode(dst, nds, src, pre, opc, attributes); |
1066 encode = asm.simdPrefixAndEncode(dst, nds, src, pre, opc, attributes); |
1063 asm.emitByte(op); |
1067 asm.emitByte(op); |
1064 asm.emitByte(0xC0 | encode); |
1068 asm.emitByte(0xC0 | encode); |
1094 break; |
1098 break; |
1095 case P_0F3A: |
1099 case P_0F3A: |
1096 opc = VexOpcode.VEX_OPCODE_0F_3A; |
1100 opc = VexOpcode.VEX_OPCODE_0F_3A; |
1097 break; |
1101 break; |
1098 default: |
1102 default: |
1099 opc = VexOpcode.VEX_OPCODE_NONE; |
1103 throw GraalError.shouldNotReachHere("invalid VEX instruction prefix"); |
1100 break; |
|
1101 } |
1104 } |
1102 asm.simdPrefix(dst, nds, src, pre, opc, attributes); |
1105 asm.simdPrefix(dst, nds, src, pre, opc, attributes); |
1103 asm.emitByte(op); |
1106 asm.emitByte(op); |
1104 asm.emitOperandHelper(dst, src, 0); |
1107 asm.emitOperandHelper(dst, src, 0); |
1105 } |
1108 } |
1161 case 0x11: |
1164 case 0x11: |
1162 isSimd = true; |
1165 isSimd = true; |
1163 break; |
1166 break; |
1164 } |
1167 } |
1165 |
1168 |
|
1169 int opc = 0; |
|
1170 if (isSimd) { |
|
1171 switch (prefix2) { |
|
1172 case P_0F: |
|
1173 opc = VexOpcode.VEX_OPCODE_0F; |
|
1174 break; |
|
1175 case P_0F38: |
|
1176 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1177 break; |
|
1178 case P_0F3A: |
|
1179 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1180 break; |
|
1181 default: |
|
1182 isSimd = false; |
|
1183 break; |
|
1184 } |
|
1185 } |
|
1186 |
1166 if (isSimd) { |
1187 if (isSimd) { |
1167 int pre; |
1188 int pre; |
1168 int opc; |
|
1169 boolean rexVexW = (size == QWORD) ? true : false; |
1189 boolean rexVexW = (size == QWORD) ? true : false; |
1170 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1190 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1171 int curPrefix = size.sizePrefix | prefix1; |
1191 int curPrefix = size.sizePrefix | prefix1; |
1172 switch (curPrefix) { |
1192 switch (curPrefix) { |
1173 case 0x66: |
1193 case 0x66: |
1179 case 0xF3: |
1199 case 0xF3: |
1180 pre = VexSimdPrefix.VEX_SIMD_F3; |
1200 pre = VexSimdPrefix.VEX_SIMD_F3; |
1181 break; |
1201 break; |
1182 default: |
1202 default: |
1183 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1203 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1184 break; |
|
1185 } |
|
1186 switch (prefix2) { |
|
1187 case P_0F: |
|
1188 opc = VexOpcode.VEX_OPCODE_0F; |
|
1189 break; |
|
1190 case P_0F38: |
|
1191 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1192 break; |
|
1193 case P_0F3A: |
|
1194 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1195 break; |
|
1196 default: |
|
1197 opc = VexOpcode.VEX_OPCODE_NONE; |
|
1198 break; |
1204 break; |
1199 } |
1205 } |
1200 int encode; |
1206 int encode; |
1201 if (noNds) { |
1207 if (noNds) { |
1202 encode = asm.simdPrefixAndEncode(src, Register.None, dst, pre, opc, attributes); |
1208 encode = asm.simdPrefixAndEncode(src, Register.None, dst, pre, opc, attributes); |
1220 case 0x11: |
1226 case 0x11: |
1221 isSimd = true; |
1227 isSimd = true; |
1222 break; |
1228 break; |
1223 } |
1229 } |
1224 |
1230 |
|
1231 int opc = 0; |
|
1232 if (isSimd) { |
|
1233 switch (prefix2) { |
|
1234 case P_0F: |
|
1235 opc = VexOpcode.VEX_OPCODE_0F; |
|
1236 break; |
|
1237 case P_0F38: |
|
1238 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1239 break; |
|
1240 case P_0F3A: |
|
1241 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1242 break; |
|
1243 default: |
|
1244 isSimd = false; |
|
1245 break; |
|
1246 } |
|
1247 } |
|
1248 |
1225 if (isSimd) { |
1249 if (isSimd) { |
1226 int pre; |
1250 int pre; |
1227 int opc; |
|
1228 boolean rexVexW = (size == QWORD) ? true : false; |
1251 boolean rexVexW = (size == QWORD) ? true : false; |
1229 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1252 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1230 int curPrefix = size.sizePrefix | prefix1; |
1253 int curPrefix = size.sizePrefix | prefix1; |
1231 switch (curPrefix) { |
1254 switch (curPrefix) { |
1232 case 0x66: |
1255 case 0x66: |
1238 case 0xF3: |
1261 case 0xF3: |
1239 pre = VexSimdPrefix.VEX_SIMD_F3; |
1262 pre = VexSimdPrefix.VEX_SIMD_F3; |
1240 break; |
1263 break; |
1241 default: |
1264 default: |
1242 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1265 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1243 break; |
|
1244 } |
|
1245 switch (prefix2) { |
|
1246 case P_0F: |
|
1247 opc = VexOpcode.VEX_OPCODE_0F; |
|
1248 break; |
|
1249 case P_0F38: |
|
1250 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1251 break; |
|
1252 case P_0F3A: |
|
1253 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1254 break; |
|
1255 default: |
|
1256 opc = VexOpcode.VEX_OPCODE_NONE; |
|
1257 break; |
1266 break; |
1258 } |
1267 } |
1259 asm.simdPrefix(src, Register.None, dst, pre, opc, attributes); |
1268 asm.simdPrefix(src, Register.None, dst, pre, opc, attributes); |
1260 asm.emitByte(op); |
1269 asm.emitByte(op); |
1261 asm.emitOperandHelper(src, dst, 0); |
1270 asm.emitOperandHelper(src, dst, 0); |
1388 isSimd = true; |
1397 isSimd = true; |
1389 noNds = true; |
1398 noNds = true; |
1390 break; |
1399 break; |
1391 } |
1400 } |
1392 |
1401 |
|
1402 int opc = 0; |
|
1403 if (isSimd) { |
|
1404 switch (prefix2) { |
|
1405 case P_0F: |
|
1406 opc = VexOpcode.VEX_OPCODE_0F; |
|
1407 break; |
|
1408 case P_0F38: |
|
1409 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1410 break; |
|
1411 case P_0F3A: |
|
1412 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1413 break; |
|
1414 default: |
|
1415 isSimd = false; |
|
1416 break; |
|
1417 } |
|
1418 } |
|
1419 |
1393 if (isSimd) { |
1420 if (isSimd) { |
1394 int pre; |
1421 int pre; |
1395 int opc; |
|
1396 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1422 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1397 int curPrefix = size.sizePrefix | prefix1; |
1423 int curPrefix = size.sizePrefix | prefix1; |
1398 switch (curPrefix) { |
1424 switch (curPrefix) { |
1399 case 0x66: |
1425 case 0x66: |
1400 pre = VexSimdPrefix.VEX_SIMD_66; |
1426 pre = VexSimdPrefix.VEX_SIMD_66; |
1405 case 0xF3: |
1431 case 0xF3: |
1406 pre = VexSimdPrefix.VEX_SIMD_F3; |
1432 pre = VexSimdPrefix.VEX_SIMD_F3; |
1407 break; |
1433 break; |
1408 default: |
1434 default: |
1409 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1435 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1410 break; |
|
1411 } |
|
1412 switch (prefix2) { |
|
1413 case P_0F: |
|
1414 opc = VexOpcode.VEX_OPCODE_0F; |
|
1415 break; |
|
1416 case P_0F38: |
|
1417 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1418 break; |
|
1419 case P_0F3A: |
|
1420 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1421 break; |
|
1422 default: |
|
1423 opc = VexOpcode.VEX_OPCODE_NONE; |
|
1424 break; |
1436 break; |
1425 } |
1437 } |
1426 int encode; |
1438 int encode; |
1427 if (noNds) { |
1439 if (noNds) { |
1428 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes); |
1440 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes); |
1451 isSimd = true; |
1463 isSimd = true; |
1452 noNds = true; |
1464 noNds = true; |
1453 break; |
1465 break; |
1454 } |
1466 } |
1455 |
1467 |
|
1468 int opc = 0; |
|
1469 if (isSimd) { |
|
1470 switch (prefix2) { |
|
1471 case P_0F: |
|
1472 opc = VexOpcode.VEX_OPCODE_0F; |
|
1473 break; |
|
1474 case P_0F38: |
|
1475 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1476 break; |
|
1477 case P_0F3A: |
|
1478 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1479 break; |
|
1480 default: |
|
1481 isSimd = false; |
|
1482 break; |
|
1483 } |
|
1484 } |
|
1485 |
1456 if (isSimd) { |
1486 if (isSimd) { |
1457 int pre; |
1487 int pre; |
1458 int opc; |
|
1459 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1488 AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target); |
1460 int curPrefix = size.sizePrefix | prefix1; |
1489 int curPrefix = size.sizePrefix | prefix1; |
1461 switch (curPrefix) { |
1490 switch (curPrefix) { |
1462 case 0x66: |
1491 case 0x66: |
1463 pre = VexSimdPrefix.VEX_SIMD_66; |
1492 pre = VexSimdPrefix.VEX_SIMD_66; |
1470 break; |
1499 break; |
1471 default: |
1500 default: |
1472 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1501 pre = VexSimdPrefix.VEX_SIMD_NONE; |
1473 break; |
1502 break; |
1474 } |
1503 } |
1475 switch (prefix2) { |
|
1476 case P_0F: |
|
1477 opc = VexOpcode.VEX_OPCODE_0F; |
|
1478 break; |
|
1479 case P_0F38: |
|
1480 opc = VexOpcode.VEX_OPCODE_0F_38; |
|
1481 break; |
|
1482 case P_0F3A: |
|
1483 opc = VexOpcode.VEX_OPCODE_0F_3A; |
|
1484 break; |
|
1485 default: |
|
1486 opc = VexOpcode.VEX_OPCODE_NONE; |
|
1487 break; |
|
1488 } |
|
1489 |
|
1490 if (noNds) { |
1504 if (noNds) { |
1491 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes); |
1505 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes); |
1492 } else { |
1506 } else { |
1493 asm.simdPrefix(dst, dst, src, pre, opc, attributes); |
1507 asm.simdPrefix(dst, dst, src, pre, opc, attributes); |
1494 } |
1508 } |