--- a/hotspot/src/cpu/sparc/vm/sparc.ad	Fri Mar 25 18:19:22 2011 -0400
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad	Fri Mar 25 09:35:39 2011 +0100
@@ -1843,6 +1843,10 @@
 // registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = false;
 
+// Do we need to mask the count passed to shift instructions or does
+// the cpu only look at the lower 5/6 bits anyway?
+const bool Matcher::need_masked_shift_count = false;
+
 bool Matcher::narrow_oop_use_complex_address() {
   NOT_LP64(ShouldNotCallThis());
   assert(UseCompressedOops, "only for compressed oops code");