22 */ |
22 */ |
23 |
23 |
24 |
24 |
25 package org.graalvm.compiler.lir.amd64.vector; |
25 package org.graalvm.compiler.lir.amd64.vector; |
26 |
26 |
27 import jdk.vm.ci.meta.AllocatableValue; |
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28 import org.graalvm.compiler.asm.amd64.AMD64Address; |
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29 import org.graalvm.compiler.asm.amd64.AMD64VectorAssembler; |
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30 import org.graalvm.compiler.asm.amd64.AVXKind; |
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31 import org.graalvm.compiler.lir.LIRFrameState; |
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32 import org.graalvm.compiler.lir.LIRInstructionClass; |
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33 import org.graalvm.compiler.lir.Opcode; |
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34 import org.graalvm.compiler.lir.amd64.AMD64AddressValue; |
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35 import org.graalvm.compiler.lir.asm.CompilationResultBuilder; |
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36 |
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37 import static jdk.vm.ci.code.ValueUtil.asRegister; |
27 import static jdk.vm.ci.code.ValueUtil.asRegister; |
38 import static jdk.vm.ci.code.ValueUtil.isRegister; |
28 import static jdk.vm.ci.code.ValueUtil.isRegister; |
39 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE; |
29 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE; |
40 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; |
30 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; |
41 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK; |
31 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK; |
42 |
32 |
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33 import org.graalvm.compiler.asm.amd64.AMD64Address; |
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34 import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRRIOp; |
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35 import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp; |
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36 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler; |
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37 import org.graalvm.compiler.asm.amd64.AVXKind; |
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38 import org.graalvm.compiler.lir.LIRFrameState; |
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39 import org.graalvm.compiler.lir.LIRInstructionClass; |
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40 import org.graalvm.compiler.lir.Opcode; |
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41 import org.graalvm.compiler.lir.amd64.AMD64AddressValue; |
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42 import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction; |
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43 import org.graalvm.compiler.lir.asm.CompilationResultBuilder; |
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44 |
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45 import jdk.vm.ci.meta.AllocatableValue; |
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46 |
43 public class AMD64VectorBinary { |
47 public class AMD64VectorBinary { |
44 |
48 |
45 public static final class AVXBinaryOp extends AMD64VectorLIRInstruction { |
49 public static final class AVXBinaryOp extends AMD64LIRInstruction { |
46 public static final LIRInstructionClass<AVXBinaryOp> TYPE = LIRInstructionClass.create(AVXBinaryOp.class); |
50 public static final LIRInstructionClass<AVXBinaryOp> TYPE = LIRInstructionClass.create(AVXBinaryOp.class); |
47 |
51 |
48 @Opcode private final AMD64VectorAssembler.VexRVMOp opcode; |
52 @Opcode private final VexRVMOp opcode; |
49 private final AVXKind.AVXSize size; |
53 private final AVXKind.AVXSize size; |
50 |
54 |
51 @Def({REG}) protected AllocatableValue result; |
55 @Def({REG}) protected AllocatableValue result; |
52 @Use({REG}) protected AllocatableValue x; |
56 @Use({REG}) protected AllocatableValue x; |
53 @Use({REG, STACK}) protected AllocatableValue y; |
57 @Use({REG, STACK}) protected AllocatableValue y; |
54 |
58 |
55 public AVXBinaryOp(AMD64VectorAssembler.VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) { |
59 public AVXBinaryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) { |
56 super(TYPE); |
60 super(TYPE); |
57 this.opcode = opcode; |
61 this.opcode = opcode; |
58 this.size = size; |
62 this.size = size; |
59 this.result = result; |
63 this.result = result; |
60 this.x = x; |
64 this.x = x; |
61 this.y = y; |
65 this.y = y; |
62 } |
66 } |
63 |
67 |
64 @Override |
68 @Override |
65 public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) { |
69 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { |
66 if (isRegister(y)) { |
70 if (isRegister(y)) { |
67 opcode.emit(vasm, size, asRegister(result), asRegister(x), asRegister(y)); |
71 opcode.emit(masm, size, asRegister(result), asRegister(x), asRegister(y)); |
68 } else { |
72 } else { |
69 opcode.emit(vasm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y)); |
73 opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y)); |
70 } |
74 } |
71 } |
75 } |
72 } |
76 } |
73 |
77 |
74 public static final class AVXBinaryConstOp extends AMD64VectorLIRInstruction { |
78 public static final class AVXBinaryConstOp extends AMD64LIRInstruction { |
75 |
79 |
76 public static final LIRInstructionClass<AVXBinaryConstOp> TYPE = LIRInstructionClass.create(AVXBinaryConstOp.class); |
80 public static final LIRInstructionClass<AVXBinaryConstOp> TYPE = LIRInstructionClass.create(AVXBinaryConstOp.class); |
77 |
81 |
78 @Opcode private final AMD64VectorAssembler.VexRRIOp opcode; |
82 @Opcode private final VexRRIOp opcode; |
79 private final AVXKind.AVXSize size; |
83 private final AVXKind.AVXSize size; |
80 |
84 |
81 @Def({REG}) protected AllocatableValue result; |
85 @Def({REG}) protected AllocatableValue result; |
82 @Use({REG}) protected AllocatableValue x; |
86 @Use({REG}) protected AllocatableValue x; |
83 protected int y; |
87 protected int y; |
84 |
88 |
85 public AVXBinaryConstOp(AMD64VectorAssembler.VexRRIOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, int y) { |
89 public AVXBinaryConstOp(VexRRIOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, int y) { |
86 super(TYPE); |
90 super(TYPE); |
87 assert (y & 0xFF) == y; |
91 assert (y & 0xFF) == y; |
88 this.opcode = opcode; |
92 this.opcode = opcode; |
89 this.size = size; |
93 this.size = size; |
90 this.result = result; |
94 this.result = result; |
91 this.x = x; |
95 this.x = x; |
92 this.y = y; |
96 this.y = y; |
93 } |
97 } |
94 |
98 |
95 @Override |
99 @Override |
96 public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) { |
100 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { |
97 opcode.emit(vasm, size, asRegister(result), asRegister(x), y); |
101 opcode.emit(masm, size, asRegister(result), asRegister(x), y); |
98 } |
102 } |
99 } |
103 } |
100 |
104 |
101 public static final class AVXBinaryMemoryOp extends AMD64VectorLIRInstruction { |
105 public static final class AVXBinaryMemoryOp extends AMD64LIRInstruction { |
102 public static final LIRInstructionClass<AVXBinaryMemoryOp> TYPE = LIRInstructionClass.create(AVXBinaryMemoryOp.class); |
106 public static final LIRInstructionClass<AVXBinaryMemoryOp> TYPE = LIRInstructionClass.create(AVXBinaryMemoryOp.class); |
103 |
107 |
104 @Opcode private final AMD64VectorAssembler.VexRVMOp opcode; |
108 @Opcode private final VexRVMOp opcode; |
105 private final AVXKind.AVXSize size; |
109 private final AVXKind.AVXSize size; |
106 |
110 |
107 @Def({REG}) protected AllocatableValue result; |
111 @Def({REG}) protected AllocatableValue result; |
108 @Use({REG}) protected AllocatableValue x; |
112 @Use({REG}) protected AllocatableValue x; |
109 @Use({COMPOSITE}) protected AMD64AddressValue y; |
113 @Use({COMPOSITE}) protected AMD64AddressValue y; |
110 @State protected LIRFrameState state; |
114 @State protected LIRFrameState state; |
111 |
115 |
112 public AVXBinaryMemoryOp(AMD64VectorAssembler.VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) { |
116 public AVXBinaryMemoryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) { |
113 super(TYPE); |
117 super(TYPE); |
114 this.opcode = opcode; |
118 this.opcode = opcode; |
115 this.size = size; |
119 this.size = size; |
116 this.result = result; |
120 this.result = result; |
117 this.x = x; |
121 this.x = x; |
118 this.y = y; |
122 this.y = y; |
119 this.state = state; |
123 this.state = state; |
120 } |
124 } |
121 |
125 |
122 @Override |
126 @Override |
123 public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) { |
127 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { |
124 if (state != null) { |
128 if (state != null) { |
125 crb.recordImplicitException(vasm.position(), state); |
129 crb.recordImplicitException(masm.position(), state); |
126 } |
130 } |
127 opcode.emit(vasm, size, asRegister(result), asRegister(x), y.toAddress()); |
131 opcode.emit(masm, size, asRegister(result), asRegister(x), y.toAddress()); |
128 } |
132 } |
129 } |
133 } |
130 } |
134 } |