1540 |
1540 |
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1542 return EBP_REG_mask(); |
1542 return EBP_REG_mask(); |
1543 } |
1543 } |
1544 |
1544 |
1545 const RegMask Matcher::mathExactI_result_proj_mask() { |
|
1546 return EAX_REG_mask(); |
|
1547 } |
|
1548 |
|
1549 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
1550 ShouldNotReachHere(); |
|
1551 return RegMask(); |
|
1552 } |
|
1553 |
|
1554 const RegMask Matcher::mathExactI_flags_proj_mask() { |
|
1555 return INT_FLAGS_mask(); |
|
1556 } |
|
1557 |
|
1558 // Returns true if the high 32 bits of the value is known to be zero. |
1545 // Returns true if the high 32 bits of the value is known to be zero. |
1559 bool is_operand_hi32_zero(Node* n) { |
1546 bool is_operand_hi32_zero(Node* n) { |
1560 int opc = n->Opcode(); |
1547 int opc = n->Opcode(); |
1561 if (opc == Op_AndL) { |
1548 if (opc == Op_AndL) { |
1562 Node* o2 = n->in(2); |
1549 Node* o2 = n->in(2); |
7007 %} |
6994 %} |
7008 |
6995 |
7009 //----------Arithmetic Instructions-------------------------------------------- |
6996 //----------Arithmetic Instructions-------------------------------------------- |
7010 //----------Addition Instructions---------------------------------------------- |
6997 //----------Addition Instructions---------------------------------------------- |
7011 |
6998 |
7012 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
|
7013 %{ |
|
7014 match(AddExactI dst src); |
|
7015 effect(DEF cr); |
|
7016 |
|
7017 format %{ "ADD $dst, $src\t# addExact int" %} |
|
7018 ins_encode %{ |
|
7019 __ addl($dst$$Register, $src$$Register); |
|
7020 %} |
|
7021 ins_pipe(ialu_reg_reg); |
|
7022 %} |
|
7023 |
|
7024 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) |
|
7025 %{ |
|
7026 match(AddExactI dst src); |
|
7027 effect(DEF cr); |
|
7028 |
|
7029 format %{ "ADD $dst, $src\t# addExact int" %} |
|
7030 ins_encode %{ |
|
7031 __ addl($dst$$Register, $src$$constant); |
|
7032 %} |
|
7033 ins_pipe(ialu_reg_reg); |
|
7034 %} |
|
7035 |
|
7036 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
7037 %{ |
|
7038 match(AddExactI dst (LoadI src)); |
|
7039 effect(DEF cr); |
|
7040 |
|
7041 ins_cost(125); |
|
7042 format %{ "ADD $dst,$src\t# addExact int" %} |
|
7043 ins_encode %{ |
|
7044 __ addl($dst$$Register, $src$$Address); |
|
7045 %} |
|
7046 ins_pipe( ialu_reg_mem ); |
|
7047 %} |
|
7048 |
|
7049 |
|
7050 // Integer Addition Instructions |
6999 // Integer Addition Instructions |
7051 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7000 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7052 match(Set dst (AddI dst src)); |
7001 match(Set dst (AddI dst src)); |
7053 effect(KILL cr); |
7002 effect(KILL cr); |
7054 |
7003 |
7354 ins_pipe( pipe_cmpxchg ); |
7303 ins_pipe( pipe_cmpxchg ); |
7355 %} |
7304 %} |
7356 |
7305 |
7357 //----------Subtraction Instructions------------------------------------------- |
7306 //----------Subtraction Instructions------------------------------------------- |
7358 |
7307 |
7359 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
|
7360 %{ |
|
7361 match(SubExactI dst src); |
|
7362 effect(DEF cr); |
|
7363 |
|
7364 format %{ "SUB $dst, $src\t# subExact int" %} |
|
7365 ins_encode %{ |
|
7366 __ subl($dst$$Register, $src$$Register); |
|
7367 %} |
|
7368 ins_pipe(ialu_reg_reg); |
|
7369 %} |
|
7370 |
|
7371 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr) |
|
7372 %{ |
|
7373 match(SubExactI dst src); |
|
7374 effect(DEF cr); |
|
7375 |
|
7376 format %{ "SUB $dst, $src\t# subExact int" %} |
|
7377 ins_encode %{ |
|
7378 __ subl($dst$$Register, $src$$constant); |
|
7379 %} |
|
7380 ins_pipe(ialu_reg_reg); |
|
7381 %} |
|
7382 |
|
7383 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
7384 %{ |
|
7385 match(SubExactI dst (LoadI src)); |
|
7386 effect(DEF cr); |
|
7387 |
|
7388 ins_cost(125); |
|
7389 format %{ "SUB $dst,$src\t# subExact int" %} |
|
7390 ins_encode %{ |
|
7391 __ subl($dst$$Register, $src$$Address); |
|
7392 %} |
|
7393 ins_pipe( ialu_reg_mem ); |
|
7394 %} |
|
7395 |
|
7396 // Integer Subtraction Instructions |
7308 // Integer Subtraction Instructions |
7397 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7309 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
7398 match(Set dst (SubI dst src)); |
7310 match(Set dst (SubI dst src)); |
7399 effect(KILL cr); |
7311 effect(KILL cr); |
7400 |
7312 |
7457 size(2); |
7369 size(2); |
7458 format %{ "NEG $dst" %} |
7370 format %{ "NEG $dst" %} |
7459 opcode(0xF7,0x03); // Opcode F7 /3 |
7371 opcode(0xF7,0x03); // Opcode F7 /3 |
7460 ins_encode( OpcP, RegOpc( dst ) ); |
7372 ins_encode( OpcP, RegOpc( dst ) ); |
7461 ins_pipe( ialu_reg ); |
7373 ins_pipe( ialu_reg ); |
7462 %} |
|
7463 |
|
7464 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{ |
|
7465 match(NegExactI dst); |
|
7466 effect(DEF cr); |
|
7467 |
|
7468 format %{ "NEG $dst\t# negExact int"%} |
|
7469 ins_encode %{ |
|
7470 __ negl($dst$$Register); |
|
7471 %} |
|
7472 ins_pipe(ialu_reg); |
|
7473 %} |
7374 %} |
7474 |
7375 |
7475 //----------Multiplication/Division Instructions------------------------------- |
7376 //----------Multiplication/Division Instructions------------------------------- |
7476 // Integer Multiplication Instructions |
7377 // Integer Multiplication Instructions |
7477 // Multiply Register |
7378 // Multiply Register |
7680 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" |
7581 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" |
7681 "ADD EDX,$tmp" %} |
7582 "ADD EDX,$tmp" %} |
7682 ins_encode( long_multiply_con( dst, src, tmp ) ); |
7583 ins_encode( long_multiply_con( dst, src, tmp ) ); |
7683 ins_pipe( pipe_slow ); |
7584 ins_pipe( pipe_slow ); |
7684 %} |
7585 %} |
7685 |
|
7686 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr) |
|
7687 %{ |
|
7688 match(MulExactI dst src); |
|
7689 effect(DEF cr); |
|
7690 |
|
7691 ins_cost(300); |
|
7692 format %{ "IMUL $dst, $src\t# mulExact int" %} |
|
7693 ins_encode %{ |
|
7694 __ imull($dst$$Register, $src$$Register); |
|
7695 %} |
|
7696 ins_pipe(ialu_reg_reg_alu0); |
|
7697 %} |
|
7698 |
|
7699 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr) |
|
7700 %{ |
|
7701 match(MulExactI src imm); |
|
7702 effect(DEF cr); |
|
7703 |
|
7704 ins_cost(300); |
|
7705 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %} |
|
7706 ins_encode %{ |
|
7707 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
7708 %} |
|
7709 ins_pipe(ialu_reg_reg_alu0); |
|
7710 %} |
|
7711 |
|
7712 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr) |
|
7713 %{ |
|
7714 match(MulExactI dst (LoadI src)); |
|
7715 effect(DEF cr); |
|
7716 |
|
7717 ins_cost(350); |
|
7718 format %{ "IMUL $dst, $src\t# mulExact int" %} |
|
7719 ins_encode %{ |
|
7720 __ imull($dst$$Register, $src$$Address); |
|
7721 %} |
|
7722 ins_pipe(ialu_reg_mem_alu0); |
|
7723 %} |
|
7724 |
|
7725 |
7586 |
7726 // Integer DIV with Register |
7587 // Integer DIV with Register |
7727 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ |
7588 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ |
7728 match(Set rax (DivI rax div)); |
7589 match(Set rax (DivI rax div)); |
7729 effect(KILL rdx, KILL cr); |
7590 effect(KILL rdx, KILL cr); |
8586 |
8447 |
8587 /* If I enable this, I encourage spilling in the inner loop of compress. |
8448 /* If I enable this, I encourage spilling in the inner loop of compress. |
8588 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
8449 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
8589 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
8450 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
8590 */ |
8451 */ |
|
8452 //----------Overflow Math Instructions----------------------------------------- |
|
8453 |
|
8454 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
8455 %{ |
|
8456 match(Set cr (OverflowAddI op1 op2)); |
|
8457 effect(DEF cr, USE_KILL op1, USE op2); |
|
8458 |
|
8459 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
8460 |
|
8461 ins_encode %{ |
|
8462 __ addl($op1$$Register, $op2$$Register); |
|
8463 %} |
|
8464 ins_pipe(ialu_reg_reg); |
|
8465 %} |
|
8466 |
|
8467 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
|
8468 %{ |
|
8469 match(Set cr (OverflowAddI op1 op2)); |
|
8470 effect(DEF cr, USE_KILL op1, USE op2); |
|
8471 |
|
8472 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
8473 |
|
8474 ins_encode %{ |
|
8475 __ addl($op1$$Register, $op2$$constant); |
|
8476 %} |
|
8477 ins_pipe(ialu_reg_reg); |
|
8478 %} |
|
8479 |
|
8480 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
|
8481 %{ |
|
8482 match(Set cr (OverflowSubI op1 op2)); |
|
8483 |
|
8484 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
8485 ins_encode %{ |
|
8486 __ cmpl($op1$$Register, $op2$$Register); |
|
8487 %} |
|
8488 ins_pipe(ialu_reg_reg); |
|
8489 %} |
|
8490 |
|
8491 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
|
8492 %{ |
|
8493 match(Set cr (OverflowSubI op1 op2)); |
|
8494 |
|
8495 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
8496 ins_encode %{ |
|
8497 __ cmpl($op1$$Register, $op2$$constant); |
|
8498 %} |
|
8499 ins_pipe(ialu_reg_reg); |
|
8500 %} |
|
8501 |
|
8502 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
|
8503 %{ |
|
8504 match(Set cr (OverflowSubI zero op2)); |
|
8505 effect(DEF cr, USE_KILL op2); |
|
8506 |
|
8507 format %{ "NEG $op2\t# overflow check int" %} |
|
8508 ins_encode %{ |
|
8509 __ negl($op2$$Register); |
|
8510 %} |
|
8511 ins_pipe(ialu_reg_reg); |
|
8512 %} |
|
8513 |
|
8514 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
8515 %{ |
|
8516 match(Set cr (OverflowMulI op1 op2)); |
|
8517 effect(DEF cr, USE_KILL op1, USE op2); |
|
8518 |
|
8519 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
|
8520 ins_encode %{ |
|
8521 __ imull($op1$$Register, $op2$$Register); |
|
8522 %} |
|
8523 ins_pipe(ialu_reg_reg_alu0); |
|
8524 %} |
|
8525 |
|
8526 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
8527 %{ |
|
8528 match(Set cr (OverflowMulI op1 op2)); |
|
8529 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
8530 |
|
8531 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
|
8532 ins_encode %{ |
|
8533 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
8534 %} |
|
8535 ins_pipe(ialu_reg_reg_alu0); |
|
8536 %} |
8591 |
8537 |
8592 //----------Long Instructions------------------------------------------------ |
8538 //----------Long Instructions------------------------------------------------ |
8593 // Add Long Register with Register |
8539 // Add Long Register with Register |
8594 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ |
8540 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ |
8595 match(Set dst (AddL dst src)); |
8541 match(Set dst (AddL dst src)); |