5166   predicate(UseCountTrailingZerosInstruction);

  5167   match(Set dst (CountTrailingZerosI src));

  5168   effect(KILL cr);

  5169 

  5170   format %{ "TZCNT    $dst, $src\t# count trailing zeros (int)" %}

  5171   ins_encode %{

  5172     __ tzcntl($dst$$Register, $src$$Register);

  5173   %}

  5174   ins_pipe(ialu_reg);

  5175 %}

  5176 

  5177 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{

  5178   predicate(!UseCountTrailingZerosInstruction);

  5198   predicate(UseCountTrailingZerosInstruction);

  5199   match(Set dst (CountTrailingZerosL src));

  5200   effect(TEMP dst, KILL cr);

  5201 

  5202   format %{ "TZCNT  $dst, $src.lo\t# count trailing zeros (long) \n\t"

  5203             "JNC    done\n\t"

  5204             "TZCNT  $dst, $src.hi\n\t"

  5205             "ADD    $dst, 32\n"

  5206             "done:" %}

  5207   ins_encode %{

  5208     Register Rdst = $dst$$Register;

  5209     Register Rsrc = $src$$Register;

  5210     Label done;

  5211     __ tzcntl(Rdst, Rsrc);

  5212     __ jccb(Assembler::carryClear, done);

  5213     __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));

  5214     __ addl(Rdst, BitsPerInt);

  5215     __ bind(done);

  5216   %}

  5217   ins_pipe(ialu_reg);

  5218 %}

  5219 

  5220 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{

  5221   predicate(!UseCountTrailingZerosInstruction);

  8067 // BMI1 instructions

  8068 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{

  8069   match(Set dst (AndI (XorI src1 minus_1) src2));

  8070   predicate(UseBMI1Instructions);

  8071   effect(KILL cr);

  8072 

  8073   format %{ "ANDNL  $dst, $src1, $src2" %}

  8074 

  8075   ins_encode %{

  8076     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);

  8077   %}

  8078   ins_pipe(ialu_reg);

  8079 %}

  8080 

  8081 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{

  8082   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));

  8083   predicate(UseBMI1Instructions);

  8084   effect(KILL cr);

  8085 

  8086   ins_cost(125);

  8087   format %{ "ANDNL  $dst, $src1, $src2" %}

  8088 

  8089   ins_encode %{

  8090     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);

  8091   %}

  8092   ins_pipe(ialu_reg_mem);

  8093 %}

  8094 

  8095 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{

  8096   match(Set dst (AndI (SubI imm_zero src) src));

  8097   predicate(UseBMI1Instructions);

  8098   effect(KILL cr);

  8099 

  8100   format %{ "BLSIL  $dst, $src" %}

  8101 

  8102   ins_encode %{

  8103     __ blsil($dst$$Register, $src$$Register);

  8104   %}

  8105   ins_pipe(ialu_reg);

  8106 %}

  8107 

  8108 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{

  8109   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));

  8110   predicate(UseBMI1Instructions);

  8111   effect(KILL cr);

  8112 

  8113   ins_cost(125);

  8114   format %{ "BLSIL  $dst, $src" %}

  8115 

  8116   ins_encode %{

  8117     __ blsil($dst$$Register, $src$$Address);

  8118   %}

  8119   ins_pipe(ialu_reg_mem);

  8120 %}

  8121 

  8122 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)

  8123 %{

  8124   match(Set dst (XorI (AddI src minus_1) src));

  8125   predicate(UseBMI1Instructions);

  8126   effect(KILL cr);

  8127 

  8128   format %{ "BLSMSKL $dst, $src" %}

  8129 

  8130   ins_encode %{

  8131     __ blsmskl($dst$$Register, $src$$Register);

  8132   %}

  8133 

  8134   ins_pipe(ialu_reg);

  8135 %}

  8136 

  8137 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)

  8138 %{

  8139   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));

  8140   predicate(UseBMI1Instructions);

  8141   effect(KILL cr);

  8142 

  8143   ins_cost(125);

  8144   format %{ "BLSMSKL $dst, $src" %}

  8145 

  8146   ins_encode %{

  8147     __ blsmskl($dst$$Register, $src$$Address);

  8148   %}

  8149 

  8150   ins_pipe(ialu_reg_mem);

  8151 %}

  8152 

  8153 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)

  8154 %{

  8155   match(Set dst (AndI (AddI src minus_1) src) );

  8156   predicate(UseBMI1Instructions);

  8157   effect(KILL cr);

  8158 

  8159   format %{ "BLSRL  $dst, $src" %}

  8160 

  8161   ins_encode %{

  8162     __ blsrl($dst$$Register, $src$$Register);

  8163   %}

  8164 

  8165   ins_pipe(ialu_reg);

  8166 %}

  8167 

  8168 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)

  8169 %{

  8170   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));

  8171   predicate(UseBMI1Instructions);

  8172   effect(KILL cr);

  8173 

  8174   ins_cost(125);

  8175   format %{ "BLSRL  $dst, $src" %}

  8176 

  8177   ins_encode %{

  8178     __ blsrl($dst$$Register, $src$$Address);

  8179   %}

  8180 

  8181   ins_pipe(ialu_reg_mem);

  8182 %}

  8183 

  8804 %}

  8805 

  8806 // BMI1 instructions

  8807 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{

  8808   match(Set dst (AndL (XorL src1 minus_1) src2));

  8809   predicate(UseBMI1Instructions);

  8810   effect(KILL cr, TEMP dst);

  8811 

  8812   format %{ "ANDNL  $dst.lo, $src1.lo, $src2.lo\n\t"

  8813             "ANDNL  $dst.hi, $src1.hi, $src2.hi"

  8814          %}

  8815 

  8816   ins_encode %{

  8817     Register Rdst = $dst$$Register;

  8818     Register Rsrc1 = $src1$$Register;

  8819     Register Rsrc2 = $src2$$Register;

  8820     __ andnl(Rdst, Rsrc1, Rsrc2);

  8821     __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));

  8822   %}

  8823   ins_pipe(ialu_reg_reg_long);

  8824 %}

  8825 

  8826 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{

  8827   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));

  8828   predicate(UseBMI1Instructions);

  8829   effect(KILL cr, TEMP dst);

  8830 

  8831   ins_cost(125);

  8832   format %{ "ANDNL  $dst.lo, $src1.lo, $src2\n\t"

  8833             "ANDNL  $dst.hi, $src1.hi, $src2+4"

  8834          %}

  8835 

  8836   ins_encode %{

  8837     Register Rdst = $dst$$Register;

  8838     Register Rsrc1 = $src1$$Register;

  8839     Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);

  8840 

  8841     __ andnl(Rdst, Rsrc1, $src2$$Address);

  8842     __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);

  8843   %}

  8844   ins_pipe(ialu_reg_mem);

  8845 %}

  8846 

  8847 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{

  8848   match(Set dst (AndL (SubL imm_zero src) src));

  8849   predicate(UseBMI1Instructions);

  8850   effect(KILL cr, TEMP dst);

  8851 

  8852   format %{ "MOVL   $dst.hi, 0\n\t"

  8853             "BLSIL  $dst.lo, $src.lo\n\t"

  8854             "JNZ    done\n\t"

  8855             "BLSIL  $dst.hi, $src.hi\n"

  8856             "done:"

  8857          %}

  8858 

  8859   ins_encode %{

  8860     Label done;

  8861     Register Rdst = $dst$$Register;

  8862     Register Rsrc = $src$$Register;

  8863     __ movl(HIGH_FROM_LOW(Rdst), 0);

  8864     __ blsil(Rdst, Rsrc);

  8865     __ jccb(Assembler::notZero, done);

  8866     __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));

  8867     __ bind(done);

  8868   %}

  8869   ins_pipe(ialu_reg);

  8870 %}

  8871 

  8872 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{

  8873   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));

  8874   predicate(UseBMI1Instructions);

  8875   effect(KILL cr, TEMP dst);

  8876 

  8877   ins_cost(125);

  8878   format %{ "MOVL   $dst.hi, 0\n\t"

  8879             "BLSIL  $dst.lo, $src\n\t"

  8880             "JNZ    done\n\t"

  8881             "BLSIL  $dst.hi, $src+4\n"

  8882             "done:"

  8883          %}

  8884 

  8885   ins_encode %{

  8886     Label done;

  8887     Register Rdst = $dst$$Register;

  8888     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);

  8889 

  8890     __ movl(HIGH_FROM_LOW(Rdst), 0);

  8891     __ blsil(Rdst, $src$$Address);

  8892     __ jccb(Assembler::notZero, done);

  8893     __ blsil(HIGH_FROM_LOW(Rdst), src_hi);

  8894     __ bind(done);

  8895   %}

  8896   ins_pipe(ialu_reg_mem);

  8897 %}

  8898 

  8899 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)

  8900 %{

  8901   match(Set dst (XorL (AddL src minus_1) src));

  8902   predicate(UseBMI1Instructions);

  8903   effect(KILL cr, TEMP dst);

  8904 

  8905   format %{ "MOVL    $dst.hi, 0\n\t"

  8906             "BLSMSKL $dst.lo, $src.lo\n\t"

  8907             "JNC     done\n\t"

  8908             "BLSMSKL $dst.hi, $src.hi\n"

  8909             "done:"

  8910          %}

  8911 

  8912   ins_encode %{

  8913     Label done;

  8914     Register Rdst = $dst$$Register;

  8915     Register Rsrc = $src$$Register;

  8916     __ movl(HIGH_FROM_LOW(Rdst), 0);

  8917     __ blsmskl(Rdst, Rsrc);

  8918     __ jccb(Assembler::carryClear, done);

  8919     __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));

  8920     __ bind(done);

  8921   %}

  8922 

  8923   ins_pipe(ialu_reg);

  8924 %}

  8925 

  8926 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)

  8927 %{

  8928   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));

  8929   predicate(UseBMI1Instructions);

  8930   effect(KILL cr, TEMP dst);

  8931 

  8932   ins_cost(125);

  8933   format %{ "MOVL    $dst.hi, 0\n\t"

  8934             "BLSMSKL $dst.lo, $src\n\t"

  8935             "JNC     done\n\t"

  8936             "BLSMSKL $dst.hi, $src+4\n"

  8937             "done:"

  8938          %}

  8939 

  8940   ins_encode %{

  8941     Label done;

  8942     Register Rdst = $dst$$Register;

  8943     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);

  8944 

  8945     __ movl(HIGH_FROM_LOW(Rdst), 0);

  8946     __ blsmskl(Rdst, $src$$Address);

  8947     __ jccb(Assembler::carryClear, done);

  8948     __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);

  8949     __ bind(done);

  8950   %}

  8951 

  8952   ins_pipe(ialu_reg_mem);

  8953 %}

  8954 

  8955 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)

  8956 %{

  8957   match(Set dst (AndL (AddL src minus_1) src) );

  8958   predicate(UseBMI1Instructions);

  8959   effect(KILL cr, TEMP dst);

  8960 

  8961   format %{ "MOVL   $dst.hi, $src.hi\n\t"

  8962             "BLSRL  $dst.lo, $src.lo\n\t"

  8963             "JNC    done\n\t"

  8964             "BLSRL  $dst.hi, $src.hi\n"

  8965             "done:"

  8966   %}

  8967 

  8968   ins_encode %{

  8969     Label done;

  8970     Register Rdst = $dst$$Register;

  8971     Register Rsrc = $src$$Register;

  8972     __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));

  8973     __ blsrl(Rdst, Rsrc);

  8974     __ jccb(Assembler::carryClear, done);

  8975     __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));

  8976     __ bind(done);

  8977   %}

  8978 

  8979   ins_pipe(ialu_reg);

  8980 %}

  8981 

  8982 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)

  8983 %{

  8984   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));

  8985   predicate(UseBMI1Instructions);

  8986   effect(KILL cr, TEMP dst);

  8987 

  8988   ins_cost(125);

  8989   format %{ "MOVL   $dst.hi, $src+4\n\t"

  8990             "BLSRL  $dst.lo, $src\n\t"

  8991             "JNC    done\n\t"

  8992             "BLSRL  $dst.hi, $src+4\n"

  8993             "done:"

  8994   %}

  8995 

  8996   ins_encode %{

  8997     Label done;

  8998     Register Rdst = $dst$$Register;

  8999     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);

  9000     __ movl(HIGH_FROM_LOW(Rdst), src_hi);

  9001     __ blsrl(Rdst, $src$$Address);

  9002     __ jccb(Assembler::carryClear, done);

  9003     __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);

  9004     __ bind(done);

  9005   %}

  9006 

  9007   ins_pipe(ialu_reg_mem);