3114 op_cost(15); |
3114 op_cost(15); |
3115 format %{ %} |
3115 format %{ %} |
3116 interface(CONST_INTER); |
3116 interface(CONST_INTER); |
3117 %} |
3117 %} |
3118 |
3118 |
|
3119 operand immL_Pow2() |
|
3120 %{ |
|
3121 predicate(is_power_of_2_long(n->get_long())); |
|
3122 match(ConL); |
|
3123 |
|
3124 op_cost(15); |
|
3125 format %{ %} |
|
3126 interface(CONST_INTER); |
|
3127 %} |
|
3128 |
|
3129 operand immL_NotPow2() |
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3130 %{ |
|
3131 predicate(is_power_of_2_long(~n->get_long())); |
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3132 match(ConL); |
|
3133 |
|
3134 op_cost(15); |
|
3135 format %{ %} |
|
3136 interface(CONST_INTER); |
|
3137 %} |
|
3138 |
3119 // Long Immediate zero |
3139 // Long Immediate zero |
3120 operand immL0() |
3140 operand immL0() |
3121 %{ |
3141 %{ |
3122 predicate(n->get_long() == 0L); |
3142 predicate(n->get_long() == 0L); |
3123 match(ConL); |
3143 match(ConL); |
9839 ins_encode(REX_mem_wide(dst), OpcSE(src), |
9859 ins_encode(REX_mem_wide(dst), OpcSE(src), |
9840 RM_opc_mem(secondary, dst), Con8or32(src)); |
9860 RM_opc_mem(secondary, dst), Con8or32(src)); |
9841 ins_pipe(ialu_mem_imm); |
9861 ins_pipe(ialu_mem_imm); |
9842 %} |
9862 %} |
9843 |
9863 |
|
9864 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr) |
|
9865 %{ |
|
9866 // con should be a pure 64-bit immediate given that not(con) is a power of 2 |
|
9867 // because AND/OR works well enough for 8/32-bit values. |
|
9868 predicate(log2_long(~n->in(3)->in(2)->get_long()) > 30); |
|
9869 |
|
9870 match(Set dst (StoreL dst (AndL (LoadL dst) con))); |
|
9871 effect(KILL cr); |
|
9872 |
|
9873 ins_cost(125); |
|
9874 format %{ "btrq $dst, log2(not($con))\t# long" %} |
|
9875 ins_encode %{ |
|
9876 __ btrq($dst$$Address, log2_long(~$con$$constant)); |
|
9877 %} |
|
9878 ins_pipe(ialu_mem_imm); |
|
9879 %} |
|
9880 |
9844 // BMI1 instructions |
9881 // BMI1 instructions |
9845 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ |
9882 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ |
9846 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); |
9883 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); |
9847 predicate(UseBMI1Instructions); |
9884 predicate(UseBMI1Instructions); |
9848 effect(KILL cr); |
9885 effect(KILL cr); |
10029 ins_cost(125); |
10066 ins_cost(125); |
10030 format %{ "orq $dst, $src\t# long" %} |
10067 format %{ "orq $dst, $src\t# long" %} |
10031 opcode(0x81, 0x1); /* Opcode 81 /1 id */ |
10068 opcode(0x81, 0x1); /* Opcode 81 /1 id */ |
10032 ins_encode(REX_mem_wide(dst), OpcSE(src), |
10069 ins_encode(REX_mem_wide(dst), OpcSE(src), |
10033 RM_opc_mem(secondary, dst), Con8or32(src)); |
10070 RM_opc_mem(secondary, dst), Con8or32(src)); |
|
10071 ins_pipe(ialu_mem_imm); |
|
10072 %} |
|
10073 |
|
10074 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr) |
|
10075 %{ |
|
10076 // con should be a pure 64-bit power of 2 immediate |
|
10077 // because AND/OR works well enough for 8/32-bit values. |
|
10078 predicate(log2_long(n->in(3)->in(2)->get_long()) > 31); |
|
10079 |
|
10080 match(Set dst (StoreL dst (OrL (LoadL dst) con))); |
|
10081 effect(KILL cr); |
|
10082 |
|
10083 ins_cost(125); |
|
10084 format %{ "btsq $dst, log2($con)\t# long" %} |
|
10085 ins_encode %{ |
|
10086 __ btsq($dst$$Address, log2_long($con$$constant)); |
|
10087 %} |
10034 ins_pipe(ialu_mem_imm); |
10088 ins_pipe(ialu_mem_imm); |
10035 %} |
10089 %} |
10036 |
10090 |
10037 // Xor Instructions |
10091 // Xor Instructions |
10038 // Xor Register with Register |
10092 // Xor Register with Register |