1056 |
1056 |
1057 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
1057 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
1058 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
1058 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
1059 int src_hi, int dst_hi, uint ireg, outputStream* st); |
1059 int src_hi, int dst_hi, uint ireg, outputStream* st); |
1060 |
1060 |
1061 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
1061 int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
1062 int stack_offset, int reg, uint ireg, outputStream* st); |
1062 int stack_offset, int reg, uint ireg, outputStream* st); |
1063 |
1063 |
1064 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
1064 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
1065 int dst_offset, uint ireg, outputStream* st) { |
1065 int dst_offset, uint ireg, outputStream* st) { |
1066 if (cbuf) { |
1066 if (cbuf) { |
1067 MacroAssembler _masm(cbuf); |
1067 MacroAssembler _masm(cbuf); |
4258 overflow(0x0, "o"); |
4258 overflow(0x0, "o"); |
4259 no_overflow(0x1, "no"); |
4259 no_overflow(0x1, "no"); |
4260 %} |
4260 %} |
4261 %} |
4261 %} |
4262 |
4262 |
4263 // Operands for bound floating pointer register arguments |
|
4264 operand rxmm0() %{ |
|
4265 constraint(ALLOC_IN_RC(xmm0_reg)); |
|
4266 match(VecX); |
|
4267 format%{%} |
|
4268 interface(REG_INTER); |
|
4269 %} |
|
4270 operand rxmm1() %{ |
|
4271 constraint(ALLOC_IN_RC(xmm1_reg)); |
|
4272 match(VecX); |
|
4273 format%{%} |
|
4274 interface(REG_INTER); |
|
4275 %} |
|
4276 operand rxmm2() %{ |
|
4277 constraint(ALLOC_IN_RC(xmm2_reg)); |
|
4278 match(VecX); |
|
4279 format%{%} |
|
4280 interface(REG_INTER); |
|
4281 %} |
|
4282 operand rxmm3() %{ |
|
4283 constraint(ALLOC_IN_RC(xmm3_reg)); |
|
4284 match(VecX); |
|
4285 format%{%} |
|
4286 interface(REG_INTER); |
|
4287 %} |
|
4288 operand rxmm4() %{ |
|
4289 constraint(ALLOC_IN_RC(xmm4_reg)); |
|
4290 match(VecX); |
|
4291 format%{%} |
|
4292 interface(REG_INTER); |
|
4293 %} |
|
4294 operand rxmm5() %{ |
|
4295 constraint(ALLOC_IN_RC(xmm5_reg)); |
|
4296 match(VecX); |
|
4297 format%{%} |
|
4298 interface(REG_INTER); |
|
4299 %} |
|
4300 operand rxmm6() %{ |
|
4301 constraint(ALLOC_IN_RC(xmm6_reg)); |
|
4302 match(VecX); |
|
4303 format%{%} |
|
4304 interface(REG_INTER); |
|
4305 %} |
|
4306 operand rxmm7() %{ |
|
4307 constraint(ALLOC_IN_RC(xmm7_reg)); |
|
4308 match(VecX); |
|
4309 format%{%} |
|
4310 interface(REG_INTER); |
|
4311 %} |
|
4312 operand rxmm8() %{ |
|
4313 constraint(ALLOC_IN_RC(xmm8_reg)); |
|
4314 match(VecX); |
|
4315 format%{%} |
|
4316 interface(REG_INTER); |
|
4317 %} |
|
4318 operand rxmm9() %{ |
|
4319 constraint(ALLOC_IN_RC(xmm9_reg)); |
|
4320 match(VecX); |
|
4321 format%{%} |
|
4322 interface(REG_INTER); |
|
4323 %} |
|
4324 operand rxmm10() %{ |
|
4325 constraint(ALLOC_IN_RC(xmm10_reg)); |
|
4326 match(VecX); |
|
4327 format%{%} |
|
4328 interface(REG_INTER); |
|
4329 %} |
|
4330 operand rxmm11() %{ |
|
4331 constraint(ALLOC_IN_RC(xmm11_reg)); |
|
4332 match(VecX); |
|
4333 format%{%} |
|
4334 interface(REG_INTER); |
|
4335 %} |
|
4336 operand rxmm12() %{ |
|
4337 constraint(ALLOC_IN_RC(xmm12_reg)); |
|
4338 match(VecX); |
|
4339 format%{%} |
|
4340 interface(REG_INTER); |
|
4341 %} |
|
4342 operand rxmm13() %{ |
|
4343 constraint(ALLOC_IN_RC(xmm13_reg)); |
|
4344 match(VecX); |
|
4345 format%{%} |
|
4346 interface(REG_INTER); |
|
4347 %} |
|
4348 operand rxmm14() %{ |
|
4349 constraint(ALLOC_IN_RC(xmm14_reg)); |
|
4350 match(VecX); |
|
4351 format%{%} |
|
4352 interface(REG_INTER); |
|
4353 %} |
|
4354 operand rxmm15() %{ |
|
4355 constraint(ALLOC_IN_RC(xmm15_reg)); |
|
4356 match(VecX); |
|
4357 format%{%} |
|
4358 interface(REG_INTER); |
|
4359 %} |
|
4360 operand rxmm16() %{ |
|
4361 constraint(ALLOC_IN_RC(xmm16_reg)); |
|
4362 match(VecX); |
|
4363 format%{%} |
|
4364 interface(REG_INTER); |
|
4365 %} |
|
4366 operand rxmm17() %{ |
|
4367 constraint(ALLOC_IN_RC(xmm17_reg)); |
|
4368 match(VecX); |
|
4369 format%{%} |
|
4370 interface(REG_INTER); |
|
4371 %} |
|
4372 operand rxmm18() %{ |
|
4373 constraint(ALLOC_IN_RC(xmm18_reg)); |
|
4374 match(VecX); |
|
4375 format%{%} |
|
4376 interface(REG_INTER); |
|
4377 %} |
|
4378 operand rxmm19() %{ |
|
4379 constraint(ALLOC_IN_RC(xmm19_reg)); |
|
4380 match(VecX); |
|
4381 format%{%} |
|
4382 interface(REG_INTER); |
|
4383 %} |
|
4384 operand rxmm20() %{ |
|
4385 constraint(ALLOC_IN_RC(xmm20_reg)); |
|
4386 match(VecX); |
|
4387 format%{%} |
|
4388 interface(REG_INTER); |
|
4389 %} |
|
4390 operand rxmm21() %{ |
|
4391 constraint(ALLOC_IN_RC(xmm21_reg)); |
|
4392 match(VecX); |
|
4393 format%{%} |
|
4394 interface(REG_INTER); |
|
4395 %} |
|
4396 operand rxmm22() %{ |
|
4397 constraint(ALLOC_IN_RC(xmm22_reg)); |
|
4398 match(VecX); |
|
4399 format%{%} |
|
4400 interface(REG_INTER); |
|
4401 %} |
|
4402 operand rxmm23() %{ |
|
4403 constraint(ALLOC_IN_RC(xmm23_reg)); |
|
4404 match(VecX); |
|
4405 format%{%} |
|
4406 interface(REG_INTER); |
|
4407 %} |
|
4408 operand rxmm24() %{ |
|
4409 constraint(ALLOC_IN_RC(xmm24_reg)); |
|
4410 match(VecX); |
|
4411 format%{%} |
|
4412 interface(REG_INTER); |
|
4413 %} |
|
4414 operand rxmm25() %{ |
|
4415 constraint(ALLOC_IN_RC(xmm25_reg)); |
|
4416 match(VecX); |
|
4417 format%{%} |
|
4418 interface(REG_INTER); |
|
4419 %} |
|
4420 operand rxmm26() %{ |
|
4421 constraint(ALLOC_IN_RC(xmm26_reg)); |
|
4422 match(VecX); |
|
4423 format%{%} |
|
4424 interface(REG_INTER); |
|
4425 %} |
|
4426 operand rxmm27() %{ |
|
4427 constraint(ALLOC_IN_RC(xmm27_reg)); |
|
4428 match(VecX); |
|
4429 format%{%} |
|
4430 interface(REG_INTER); |
|
4431 %} |
|
4432 operand rxmm28() %{ |
|
4433 constraint(ALLOC_IN_RC(xmm28_reg)); |
|
4434 match(VecX); |
|
4435 format%{%} |
|
4436 interface(REG_INTER); |
|
4437 %} |
|
4438 operand rxmm29() %{ |
|
4439 constraint(ALLOC_IN_RC(xmm29_reg)); |
|
4440 match(VecX); |
|
4441 format%{%} |
|
4442 interface(REG_INTER); |
|
4443 %} |
|
4444 operand rxmm30() %{ |
|
4445 constraint(ALLOC_IN_RC(xmm30_reg)); |
|
4446 match(VecX); |
|
4447 format%{%} |
|
4448 interface(REG_INTER); |
|
4449 %} |
|
4450 operand rxmm31() %{ |
|
4451 constraint(ALLOC_IN_RC(xmm31_reg)); |
|
4452 match(VecX); |
|
4453 format%{%} |
|
4454 interface(REG_INTER); |
|
4455 %} |
|
4456 |
|
4457 //----------OPERAND CLASSES---------------------------------------------------- |
4263 //----------OPERAND CLASSES---------------------------------------------------- |
4458 // Operand Classes are groups of operands that are used as to simplify |
4264 // Operand Classes are groups of operands that are used as to simplify |
4459 // instruction definitions by not requiring the AD writer to specify separate |
4265 // instruction definitions by not requiring the AD writer to specify separate |
4460 // instructions for every form of operand when the instruction accepts |
4266 // instructions for every form of operand when the instruction accepts |
4461 // multiple operand types with the same basic encoding and format. The classic |
4267 // multiple operand types with the same basic encoding and format. The classic |
5344 |
5150 |
5345 // Load Pointer |
5151 // Load Pointer |
5346 instruct loadP(rRegP dst, memory mem) |
5152 instruct loadP(rRegP dst, memory mem) |
5347 %{ |
5153 %{ |
5348 match(Set dst (LoadP mem)); |
5154 match(Set dst (LoadP mem)); |
|
5155 predicate(n->as_Load()->barrier_data() == 0); |
5349 |
5156 |
5350 ins_cost(125); // XXX |
5157 ins_cost(125); // XXX |
5351 format %{ "movq $dst, $mem\t# ptr" %} |
5158 format %{ "movq $dst, $mem\t# ptr" %} |
5352 opcode(0x8B); |
5159 opcode(0x8B); |
5353 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5160 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
7792 |
7599 |
7793 instruct storePConditional(memory heap_top_ptr, |
7600 instruct storePConditional(memory heap_top_ptr, |
7794 rax_RegP oldval, rRegP newval, |
7601 rax_RegP oldval, rRegP newval, |
7795 rFlagsReg cr) |
7602 rFlagsReg cr) |
7796 %{ |
7603 %{ |
|
7604 predicate(n->as_LoadStore()->barrier_data() == 0); |
7797 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); |
7605 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); |
7798 |
7606 |
7799 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
7607 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
7800 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} |
7608 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} |
7801 opcode(0x0F, 0xB1); |
7609 opcode(0x0F, 0xB1); |
7843 instruct compareAndSwapP(rRegI res, |
7651 instruct compareAndSwapP(rRegI res, |
7844 memory mem_ptr, |
7652 memory mem_ptr, |
7845 rax_RegP oldval, rRegP newval, |
7653 rax_RegP oldval, rRegP newval, |
7846 rFlagsReg cr) |
7654 rFlagsReg cr) |
7847 %{ |
7655 %{ |
7848 predicate(VM_Version::supports_cx8()); |
7656 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); |
7849 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7657 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7850 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); |
7658 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); |
7851 effect(KILL cr, KILL oldval); |
7659 effect(KILL cr, KILL oldval); |
7852 |
7660 |
7853 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
7661 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
8085 instruct compareAndExchangeP( |
7893 instruct compareAndExchangeP( |
8086 memory mem_ptr, |
7894 memory mem_ptr, |
8087 rax_RegP oldval, rRegP newval, |
7895 rax_RegP oldval, rRegP newval, |
8088 rFlagsReg cr) |
7896 rFlagsReg cr) |
8089 %{ |
7897 %{ |
8090 predicate(VM_Version::supports_cx8()); |
7898 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); |
8091 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); |
7899 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); |
8092 effect(KILL cr); |
7900 effect(KILL cr); |
8093 |
7901 |
8094 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
7902 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
8095 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} |
7903 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} |
8230 ins_pipe( pipe_cmpxchg ); |
8038 ins_pipe( pipe_cmpxchg ); |
8231 %} |
8039 %} |
8232 |
8040 |
8233 instruct xchgP( memory mem, rRegP newval) %{ |
8041 instruct xchgP( memory mem, rRegP newval) %{ |
8234 match(Set newval (GetAndSetP mem newval)); |
8042 match(Set newval (GetAndSetP mem newval)); |
|
8043 predicate(n->as_LoadStore()->barrier_data() == 0); |
8235 format %{ "XCHGQ $newval,[$mem]" %} |
8044 format %{ "XCHGQ $newval,[$mem]" %} |
8236 ins_encode %{ |
8045 ins_encode %{ |
8237 __ xchgq($newval$$Register, $mem$$Address); |
8046 __ xchgq($newval$$Register, $mem$$Address); |
8238 %} |
8047 %} |
8239 ins_pipe( pipe_cmpxchg ); |
8048 ins_pipe( pipe_cmpxchg ); |
11972 %} |
11781 %} |
11973 |
11782 |
11974 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) |
11783 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) |
11975 %{ |
11784 %{ |
11976 match(Set cr (CmpP op1 (LoadP op2))); |
11785 match(Set cr (CmpP op1 (LoadP op2))); |
|
11786 predicate(n->in(2)->as_Load()->barrier_data() == 0); |
11977 |
11787 |
11978 ins_cost(500); // XXX |
11788 ins_cost(500); // XXX |
11979 format %{ "cmpq $op1, $op2\t# ptr" %} |
11789 format %{ "cmpq $op1, $op2\t# ptr" %} |
11980 opcode(0x3B); /* Opcode 3B /r */ |
11790 opcode(0x3B); /* Opcode 3B /r */ |
11981 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11791 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11997 // Compare raw pointer (used in out-of-heap check). |
11807 // Compare raw pointer (used in out-of-heap check). |
11998 // Only works because non-oop pointers must be raw pointers |
11808 // Only works because non-oop pointers must be raw pointers |
11999 // and raw pointers have no anti-dependencies. |
11809 // and raw pointers have no anti-dependencies. |
12000 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) |
11810 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) |
12001 %{ |
11811 %{ |
12002 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
11812 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none && |
|
11813 n->in(2)->as_Load()->barrier_data() == 0); |
12003 match(Set cr (CmpP op1 (LoadP op2))); |
11814 match(Set cr (CmpP op1 (LoadP op2))); |
12004 |
11815 |
12005 format %{ "cmpq $op1, $op2\t# raw ptr" %} |
11816 format %{ "cmpq $op1, $op2\t# raw ptr" %} |
12006 opcode(0x3B); /* Opcode 3B /r */ |
11817 opcode(0x3B); /* Opcode 3B /r */ |
12007 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11818 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
12022 |
11833 |
12023 // This will generate a signed flags result. This should be OK since |
11834 // This will generate a signed flags result. This should be OK since |
12024 // any compare to a zero should be eq/neq. |
11835 // any compare to a zero should be eq/neq. |
12025 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
11836 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
12026 %{ |
11837 %{ |
12027 predicate(!UseCompressedOops || (CompressedOops::base() != NULL)); |
11838 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) && |
|
11839 n->in(1)->as_Load()->barrier_data() == 0); |
12028 match(Set cr (CmpP (LoadP op) zero)); |
11840 match(Set cr (CmpP (LoadP op) zero)); |
12029 |
11841 |
12030 ins_cost(500); // XXX |
11842 ins_cost(500); // XXX |
12031 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
11843 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
12032 opcode(0xF7); /* Opcode F7 /0 */ |
11844 opcode(0xF7); /* Opcode F7 /0 */ |
12035 ins_pipe(ialu_cr_reg_imm); |
11847 ins_pipe(ialu_cr_reg_imm); |
12036 %} |
11848 %} |
12037 |
11849 |
12038 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
11850 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
12039 %{ |
11851 %{ |
12040 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); |
11852 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && |
|
11853 (CompressedKlassPointers::base() == NULL) && |
|
11854 n->in(1)->as_Load()->barrier_data() == 0); |
12041 match(Set cr (CmpP (LoadP mem) zero)); |
11855 match(Set cr (CmpP (LoadP mem) zero)); |
12042 |
11856 |
12043 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
11857 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
12044 ins_encode %{ |
11858 ins_encode %{ |
12045 __ cmpq(r12, $mem$$Address); |
11859 __ cmpq(r12, $mem$$Address); |