equal
deleted
inserted
replaced
403 } |
403 } |
404 inline void umull(Register Rd, Register Rn, Register Rm) { |
404 inline void umull(Register Rd, Register Rn, Register Rm) { |
405 umaddl(Rd, Rn, Rm, zr); |
405 umaddl(Rd, Rn, Rm, zr); |
406 } |
406 } |
407 |
407 |
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408 #define WRAP(INSN) \ |
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409 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ |
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410 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \ |
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411 nop(); \ |
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412 Assembler::INSN(Rd, Rn, Rm, Ra); \ |
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413 } |
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414 |
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415 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) |
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416 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) |
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417 #undef WRAP |
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418 |
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419 |
408 // macro assembly operations needed for aarch64 |
420 // macro assembly operations needed for aarch64 |
409 |
421 |
410 // first two private routines for loading 32 bit or 64 bit constants |
422 // first two private routines for loading 32 bit or 64 bit constants |
411 private: |
423 private: |
412 |
424 |
1091 } |
1103 } |
1092 } |
1104 } |
1093 |
1105 |
1094 address read_polling_page(Register r, address page, relocInfo::relocType rtype); |
1106 address read_polling_page(Register r, address page, relocInfo::relocType rtype); |
1095 address read_polling_page(Register r, relocInfo::relocType rtype); |
1107 address read_polling_page(Register r, relocInfo::relocType rtype); |
1096 |
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1097 // Used by aarch64.ad to control code generation |
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1098 static bool use_acq_rel_for_volatile_fields(); |
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1099 |
1108 |
1100 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. |
1109 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. |
1101 void update_byte_crc32(Register crc, Register val, Register table); |
1110 void update_byte_crc32(Register crc, Register val, Register table); |
1102 void update_word_crc32(Register crc, Register v, Register tmp, |
1111 void update_word_crc32(Register crc, Register v, Register tmp, |
1103 Register table0, Register table1, Register table2, Register table3, |
1112 Register table0, Register table1, Register table2, Register table3, |
1148 // Uses rscratch2. |
1157 // Uses rscratch2. |
1149 Address offsetted_address(Register r, Register r1, Address::extend ext, |
1158 Address offsetted_address(Register r, Register r1, Address::extend ext, |
1150 int offset, int size); |
1159 int offset, int size); |
1151 }; |
1160 }; |
1152 |
1161 |
1153 // Used by aarch64.ad to control code generation |
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1154 #define treat_as_volatile(MEM_NODE) \ |
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1155 (MacroAssembler::use_acq_rel_for_volatile_fields() ? (MEM_NODE)->is_volatile() : false) |
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1156 |
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1157 #ifdef ASSERT |
1162 #ifdef ASSERT |
1158 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } |
1163 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } |
1159 #endif |
1164 #endif |
1160 |
1165 |
1161 /** |
1166 /** |