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hotspot/src/cpu/x86/vm/assembler_x86.cpp
changeset 35154 a9b3c1984a01
parent 35146 9ebfec283f56
child 35540 e001ad24dcdb
equal deleted inserted replaced
35153:0341260cd1f2 35154:a9b3c1984a01 
  3347 }
 
  3347 }
 
  3348 
  3348 
  3349 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
 
  3349 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
 
  3350   assert(VM_Version::supports_sse4_1(), "");
 
  3350   assert(VM_Version::supports_sse4_1(), "");
 
  3351   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3351   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3352   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3352   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3353   emit_int8(0x16);
 
  3353   emit_int8(0x16);
 
  3354   emit_int8((unsigned char)(0xC0 | encode));
 
  3354   emit_int8((unsigned char)(0xC0 | encode));
 
       
  3355   emit_int8(imm8);
 
       
  3356 }
 
       
  3357 
       
  3358 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
 
       
  3359   assert(VM_Version::supports_sse4_1(), "");
 
       
  3360   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3361   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 
       
  3362   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3363   emit_int8(0x16);
 
       
  3364   emit_operand(src, dst);
 
  3355   emit_int8(imm8);
 
  3365   emit_int8(imm8);
 
  3356 }
 
  3366 }
 
  3357 
  3367 
  3358 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
 
  3368 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
 
  3359   assert(VM_Version::supports_sse4_1(), "");
 
  3369   assert(VM_Version::supports_sse4_1(), "");
 
  3360   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3370   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3361   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3371   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3362   emit_int8(0x16);
 
  3372   emit_int8(0x16);
 
  3363   emit_int8((unsigned char)(0xC0 | encode));
 
  3373   emit_int8((unsigned char)(0xC0 | encode));
 
  3364   emit_int8(imm8);
 
  3374   emit_int8(imm8);
 
  3365 }
 
  3375 }
 
  3366 
  3376 
  3367 // The encoding for pextrw is SSE2 to support the LIBM implementation.
 
  3377 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
 
       
  3378   assert(VM_Version::supports_sse4_1(), "");
 
       
  3379   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3380   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 
       
  3381   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3382   emit_int8(0x16);
 
       
  3383   emit_operand(src, dst);
 
       
  3384   emit_int8(imm8);
 
       
  3385 }
 
       
  3386 
  3368 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
 
  3387 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
 
  3369   assert(VM_Version::supports_sse2(), "");
 
  3388   assert(VM_Version::supports_sse2(), "");
 
  3370   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3389   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3371   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  3390   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  3372   emit_int8((unsigned char)0xC5);
 
  3391   emit_int8((unsigned char)0xC5);
 
  3373   emit_int8((unsigned char)(0xC0 | encode));
 
  3392   emit_int8((unsigned char)(0xC0 | encode));
 
  3374   emit_int8(imm8);
 
  3393   emit_int8(imm8);
 
  3375 }
 
  3394 }
 
  3376 
  3395 
       
  3396 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
 
       
  3397   assert(VM_Version::supports_sse4_1(), "");
 
       
  3398   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3399   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 
       
  3400   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3401   emit_int8((unsigned char)0x15);
 
       
  3402   emit_operand(src, dst);
 
       
  3403   emit_int8(imm8);
 
       
  3404 }
 
       
  3405 
       
  3406 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
 
       
  3407   assert(VM_Version::supports_sse4_1(), "");
 
       
  3408   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3409   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
 
       
  3410   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3411   emit_int8(0x14);
 
       
  3412   emit_operand(src, dst);
 
       
  3413   emit_int8(imm8);
 
       
  3414 }
 
       
  3415 
  3377 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
 
  3416 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
 
  3378   assert(VM_Version::supports_sse4_1(), "");
 
  3417   assert(VM_Version::supports_sse4_1(), "");
 
  3379   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3418   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3380   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3419   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3381   emit_int8(0x22);
 
  3420   emit_int8(0x22);
 
  3382   emit_int8((unsigned char)(0xC0 | encode));
 
  3421   emit_int8((unsigned char)(0xC0 | encode));
 
  3383   emit_int8(imm8);
 
  3422   emit_int8(imm8);
 
  3384 }
 
  3423 }
 
  3385 
  3424 
       
  3425 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
 
       
  3426   assert(VM_Version::supports_sse4_1(), "");
 
       
  3427   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3428   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 
       
  3429   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3430   emit_int8(0x22);
 
       
  3431   emit_operand(dst,src);
 
       
  3432   emit_int8(imm8);
 
       
  3433 }
 
       
  3434 
  3386 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
 
  3435 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
 
  3387   assert(VM_Version::supports_sse4_1(), "");
 
  3436   assert(VM_Version::supports_sse4_1(), "");
 
  3388   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3437   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3389   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3438   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  3390   emit_int8(0x22);
 
  3439   emit_int8(0x22);
 
  3391   emit_int8((unsigned char)(0xC0 | encode));
 
  3440   emit_int8((unsigned char)(0xC0 | encode));
 
  3392   emit_int8(imm8);
 
  3441   emit_int8(imm8);
 
  3393 }
 
  3442 }
 
  3394 
  3443 
       
  3444 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
 
       
  3445   assert(VM_Version::supports_sse4_1(), "");
 
       
  3446   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3447   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 
       
  3448   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3449   emit_int8(0x22);
 
       
  3450   emit_operand(dst, src);
 
       
  3451   emit_int8(imm8);
 
       
  3452 }
 
       
  3453 
  3395 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
 
  3454 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
 
  3396   assert(VM_Version::supports_sse2(), "");
 
  3455   assert(VM_Version::supports_sse2(), "");
 
  3397   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3456   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
  3398   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  3457   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  3399   emit_int8((unsigned char)0xC4);
 
  3458   emit_int8((unsigned char)0xC4);
 
  3400   emit_int8((unsigned char)(0xC0 | encode));
 
  3459   emit_int8((unsigned char)(0xC0 | encode));
 
       
  3460   emit_int8(imm8);
 
       
  3461 }
 
       
  3462 
       
  3463 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
 
       
  3464   assert(VM_Version::supports_sse2(), "");
 
       
  3465   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3466   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 
       
  3467   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
       
  3468   emit_int8((unsigned char)0xC4);
 
       
  3469   emit_operand(dst, src);
 
       
  3470   emit_int8(imm8);
 
       
  3471 }
 
       
  3472 
       
  3473 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
 
       
  3474   assert(VM_Version::supports_sse4_1(), "");
 
       
  3475   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  3476   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
 
       
  3477   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
       
  3478   emit_int8(0x20);
 
       
  3479   emit_operand(dst, src);
 
  3401   emit_int8(imm8);
 
  3480   emit_int8(imm8);
 
  3402 }
 
  3481 }
 
  3403 
  3482 
  3404 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
 
  3483 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
 
  3405   assert(VM_Version::supports_sse4_1(), "");
 
  3484   assert(VM_Version::supports_sse4_1(), "");
 
  4186 void Assembler::xorl(Register dst, Register src) {
 
  4265 void Assembler::xorl(Register dst, Register src) {
 
  4187   (void) prefix_and_encode(dst->encoding(), src->encoding());
 
  4266   (void) prefix_and_encode(dst->encoding(), src->encoding());
 
  4188   emit_arith(0x33, 0xC0, dst, src);
 
  4267   emit_arith(0x33, 0xC0, dst, src);
 
  4189 }
 
  4268 }
 
  4190 
  4269 
       
  4270 void Assembler::xorb(Register dst, Address src) {
 
       
  4271   InstructionMark im(this);
 
       
  4272   prefix(src, dst);
 
       
  4273   emit_int8(0x32);
 
       
  4274   emit_operand(dst, src);
 
       
  4275 }
 
  4191 
  4276 
  4192 // AVX 3-operands scalar float-point arithmetic instructions
 
  4277 // AVX 3-operands scalar float-point arithmetic instructions
 
  4193 
  4278 
  4194 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
 
  4279 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
 
  4195   assert(VM_Version::supports_avx(), "");
 
  4280   assert(VM_Version::supports_avx(), "");
jdk-sandbox