3361 emit_int8(0x16); |
3362 emit_int8(0x16); |
3362 emit_int8((unsigned char)(0xC0 | encode)); |
3363 emit_int8((unsigned char)(0xC0 | encode)); |
3363 emit_int8(imm8); |
3364 emit_int8(imm8); |
3364 } |
3365 } |
3365 |
3366 |
|
3367 // The encoding for pextrw is SSE2 to support the LIBM implementation. |
3366 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { |
3368 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { |
3367 assert(VM_Version::supports_sse2(), ""); |
3369 assert(VM_Version::supports_sse2(), ""); |
3368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); |
3370 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); |
3369 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); |
3371 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); |
3370 emit_int8((unsigned char)0xC5); |
3372 emit_int8((unsigned char)0xC5); |
4358 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); |
4360 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); |
4359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); |
4361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); |
4360 emit_int8(0x58); |
4362 emit_int8(0x58); |
4361 emit_int8((unsigned char)(0xC0 | encode)); |
4363 emit_int8((unsigned char)(0xC0 | encode)); |
4362 } |
4364 } |
|
4365 |
|
4366 void Assembler::addpd(XMMRegister dst, Address src) { |
|
4367 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
4368 InstructionMark im(this); |
|
4369 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); |
|
4370 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); |
|
4371 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); |
|
4372 emit_int8(0x58); |
|
4373 emit_operand(dst, src); |
|
4374 } |
|
4375 |
4363 |
4376 |
4364 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
4377 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
4365 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4378 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4366 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); |
4379 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); |
4367 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); |
4380 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); |