2272 emit_int8(0x0F); |
2272 emit_int8(0x0F); |
2273 emit_int8((unsigned char)0xAE); |
2273 emit_int8((unsigned char)0xAE); |
2274 emit_int8((unsigned char)0xF0); |
2274 emit_int8((unsigned char)0xF0); |
2275 } |
2275 } |
2276 |
2276 |
|
2277 // Emit sfence instruction |
|
2278 void Assembler::sfence() { |
|
2279 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
|
2280 emit_int8(0x0F); |
|
2281 emit_int8((unsigned char)0xAE); |
|
2282 emit_int8((unsigned char)0xF8); |
|
2283 } |
|
2284 |
2277 void Assembler::mov(Register dst, Register src) { |
2285 void Assembler::mov(Register dst, Register src) { |
2278 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
2286 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
2279 } |
2287 } |
2280 |
2288 |
2281 void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
2289 void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
8615 prefix(REX_W); |
8623 prefix(REX_W); |
8616 emit_int8((unsigned char)0x99); |
8624 emit_int8((unsigned char)0x99); |
8617 } |
8625 } |
8618 |
8626 |
8619 void Assembler::clflush(Address adr) { |
8627 void Assembler::clflush(Address adr) { |
|
8628 assert(VM_Version::supports_clflush(), "should do"); |
8620 prefix(adr); |
8629 prefix(adr); |
8621 emit_int8(0x0F); |
8630 emit_int8(0x0F); |
8622 emit_int8((unsigned char)0xAE); |
8631 emit_int8((unsigned char)0xAE); |
8623 emit_operand(rdi, adr); |
8632 emit_operand(rdi, adr); |
|
8633 } |
|
8634 |
|
8635 void Assembler::clflushopt(Address adr) { |
|
8636 assert(VM_Version::supports_clflushopt(), "should do!"); |
|
8637 // adr should be base reg only with no index or offset |
|
8638 assert(adr.index() == noreg, "index should be noreg"); |
|
8639 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); |
|
8640 assert(adr.disp() == 0, "displacement should be 0"); |
|
8641 // instruction prefix is 0x66 |
|
8642 emit_int8(0x66); |
|
8643 prefix(adr); |
|
8644 // opcode family is 0x0f 0xAE |
|
8645 emit_int8(0x0F); |
|
8646 emit_int8((unsigned char)0xAE); |
|
8647 // extended opcode byte is 7 == rdi |
|
8648 emit_operand(rdi, adr); |
|
8649 } |
|
8650 |
|
8651 void Assembler::clwb(Address adr) { |
|
8652 assert(VM_Version::supports_clwb(), "should do!"); |
|
8653 // adr should be base reg only with no index or offset |
|
8654 assert(adr.index() == noreg, "index should be noreg"); |
|
8655 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); |
|
8656 assert(adr.disp() == 0, "displacement should be 0"); |
|
8657 // instruction prefix is 0x66 |
|
8658 emit_int8(0x66); |
|
8659 prefix(adr); |
|
8660 // opcode family is 0x0f 0xAE |
|
8661 emit_int8(0x0F); |
|
8662 emit_int8((unsigned char)0xAE); |
|
8663 // extended opcode byte is 6 == rsi |
|
8664 emit_operand(rsi, adr); |
8624 } |
8665 } |
8625 |
8666 |
8626 void Assembler::cmovq(Condition cc, Register dst, Register src) { |
8667 void Assembler::cmovq(Condition cc, Register dst, Register src) { |
8627 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
8668 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
8628 emit_int8(0x0F); |
8669 emit_int8(0x0F); |