1378 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1378 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1379 emit_int8((unsigned char)0xDC); |
1379 emit_int8((unsigned char)0xDC); |
1380 emit_int8(0xC0 | encode); |
1380 emit_int8(0xC0 | encode); |
1381 } |
1381 } |
1382 |
1382 |
|
1383 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { |
|
1384 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); |
|
1385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
1386 attributes.set_is_evex_instruction(); |
|
1387 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
|
1388 emit_int8((unsigned char)0xDC); |
|
1389 emit_int8((unsigned char)(0xC0 | encode)); |
|
1390 } |
|
1391 |
1383 void Assembler::aesenclast(XMMRegister dst, Address src) { |
1392 void Assembler::aesenclast(XMMRegister dst, Address src) { |
1384 assert(VM_Version::supports_aes(), ""); |
1393 assert(VM_Version::supports_aes(), ""); |
1385 InstructionMark im(this); |
1394 InstructionMark im(this); |
1386 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1387 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1396 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1391 |
1400 |
1392 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { |
1401 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { |
1393 assert(VM_Version::supports_aes(), ""); |
1402 assert(VM_Version::supports_aes(), ""); |
1394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1395 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1404 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
|
1405 emit_int8((unsigned char)0xDD); |
|
1406 emit_int8((unsigned char)(0xC0 | encode)); |
|
1407 } |
|
1408 |
|
1409 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { |
|
1410 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); |
|
1411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
1412 attributes.set_is_evex_instruction(); |
|
1413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1396 emit_int8((unsigned char)0xDD); |
1414 emit_int8((unsigned char)0xDD); |
1397 emit_int8((unsigned char)(0xC0 | encode)); |
1415 emit_int8((unsigned char)(0xC0 | encode)); |
1398 } |
1416 } |
1399 |
1417 |
1400 void Assembler::andl(Address dst, int32_t imm32) { |
1418 void Assembler::andl(Address dst, int32_t imm32) { |