equal
deleted
inserted
replaced
40 ins_encode %{ |
40 ins_encode %{ |
41 __ $3(as_Register($dst$$reg), |
41 __ $3(as_Register($dst$$reg), |
42 as_Register($src1$$reg), |
42 as_Register($src1$$reg), |
43 as_Register($src2$$reg), |
43 as_Register($src2$$reg), |
44 Assembler::$5, |
44 Assembler::$5, |
45 $src3$$constant & 0x3f); |
45 $src3$$constant & ifelse($1,I,0x1f,0x3f)); |
46 %} |
46 %} |
47 |
47 |
48 ins_pipe(ialu_reg_reg_shift); |
48 ins_pipe(ialu_reg_reg_shift); |
49 %}')dnl |
49 %}')dnl |
50 define(`BASE_INVERTED_INSN', |
50 define(`BASE_INVERTED_INSN', |
85 ins_encode %{ |
85 ins_encode %{ |
86 __ $3(as_Register($dst$$reg), |
86 __ $3(as_Register($dst$$reg), |
87 as_Register($src1$$reg), |
87 as_Register($src1$$reg), |
88 as_Register($src2$$reg), |
88 as_Register($src2$$reg), |
89 Assembler::$5, |
89 Assembler::$5, |
90 $src3$$constant & 0x3f); |
90 $src3$$constant & ifelse($1,I,0x1f,0x3f)); |
91 %} |
91 %} |
92 |
92 |
93 ins_pipe(ialu_reg_reg_shift); |
93 ins_pipe(ialu_reg_reg_shift); |
94 %}')dnl |
94 %}')dnl |
95 define(`NOT_INSN', |
95 define(`NOT_INSN', |