266 as_Register($shift$$reg)); |
266 as_Register($shift$$reg)); |
267 %} |
267 %} |
268 ins_pipe(ialu_reg_reg_vshift); |
268 ins_pipe(ialu_reg_reg_vshift); |
269 %}')dnl |
269 %}')dnl |
270 define(ROL_INSN, ` |
270 define(ROL_INSN, ` |
271 instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr) |
271 instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr) |
272 %{ |
272 %{ |
273 match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift)))); |
273 match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift)))); |
274 |
274 |
275 expand %{ |
275 expand %{ |
276 $3L_rReg(dst, src, shift, cr); |
276 $3$1_rReg(dst, src, shift, cr); |
277 %} |
277 %} |
278 %}')dnl |
278 %}')dnl |
279 define(ROR_INSN, ` |
279 define(ROR_INSN, ` |
280 instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr) |
280 instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr) |
281 %{ |
281 %{ |
282 match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift)))); |
282 match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift)))); |
283 |
283 |
284 expand %{ |
284 expand %{ |
285 $3L_rReg(dst, src, shift, cr); |
285 $3$1_rReg(dst, src, shift, cr); |
286 %} |
286 %} |
287 %}')dnl |
287 %}')dnl |
288 ROL_EXPAND(L, rol, rorv) |
288 ROL_EXPAND(L, rol, rorv) |
289 ROL_EXPAND(I, rol, rorvw) |
289 ROL_EXPAND(I, rol, rorvw) |
290 ROL_INSN(L, _64, rol) |
290 ROL_INSN(L, _64, rol) |
361 ADD_SUB_ZERO_EXTEND(I,255,Sub,subw,uxtb) |
361 ADD_SUB_ZERO_EXTEND(I,255,Sub,subw,uxtb) |
362 ADD_SUB_ZERO_EXTEND(I,65535,Sub,subw,uxth) |
362 ADD_SUB_ZERO_EXTEND(I,65535,Sub,subw,uxth) |
363 ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb) |
363 ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb) |
364 ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth) |
364 ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth) |
365 ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw) |
365 ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw) |
366 |
366 dnl |
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367 dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type) |
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368 define(`ADD_SUB_EXTENDED_SHIFT', ` |
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369 instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr) |
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370 %{ |
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371 match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2))); |
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372 ins_cost(1.9 * INSN_COST); |
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373 format %{ "$5 $dst, $src1, $src2, $6 #lshift2" %} |
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374 |
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375 ins_encode %{ |
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376 __ $5(as_Register($dst$$reg), as_Register($src1$$reg), |
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377 as_Register($src2$$reg), ext::$6, ($lshift2$$constant)); |
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378 %} |
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379 ins_pipe(ialu_reg_reg_shift); |
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380 %}') |
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381 dnl $1 $2 $3 $4 $5 $6 $7 |
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382 ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64) |
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383 ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64) |
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384 ADD_SUB_EXTENDED_SHIFT(L,32,Add,RShift,add,sxtw,64) |
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385 dnl |
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386 ADD_SUB_EXTENDED_SHIFT(L,8,Sub,RShift,sub,sxtb,64) |
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387 ADD_SUB_EXTENDED_SHIFT(L,16,Sub,RShift,sub,sxth,64) |
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388 ADD_SUB_EXTENDED_SHIFT(L,32,Sub,RShift,sub,sxtw,64) |
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389 dnl |
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390 ADD_SUB_EXTENDED_SHIFT(I,8,Add,RShift,addw,sxtb,32) |
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391 ADD_SUB_EXTENDED_SHIFT(I,16,Add,RShift,addw,sxth,32) |
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392 dnl |
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393 ADD_SUB_EXTENDED_SHIFT(I,8,Sub,RShift,subw,sxtb,32) |
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394 ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32) |
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395 dnl |
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396 dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type) |
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397 define(`ADD_SUB_CONV_SHIFT', ` |
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398 instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr) |
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399 %{ |
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400 match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift))); |
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401 ins_cost(1.9 * INSN_COST); |
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402 format %{ "$3 $dst, $src1, $src2, $4 #lshift" %} |
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403 |
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404 ins_encode %{ |
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405 __ $3(as_Register($dst$$reg), as_Register($src1$$reg), |
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406 as_Register($src2$$reg), ext::$4, ($lshift$$constant)); |
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407 %} |
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408 ins_pipe(ialu_reg_reg_shift); |
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409 %}') |
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410 dnl |
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411 ADD_SUB_CONV_SHIFT(L,Add,add,sxtw); |
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412 ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw); |
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413 dnl |
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414 dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type) |
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415 define(`ADD_SUB_ZERO_EXTEND_SHIFT', ` |
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416 instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr) |
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417 %{ |
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418 match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift))); |
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419 ins_cost(1.9 * INSN_COST); |
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420 format %{ "$4 $dst, $src1, $src2, $5 #lshift" %} |
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421 |
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422 ins_encode %{ |
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423 __ $4(as_Register($dst$$reg), as_Register($src1$$reg), |
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424 as_Register($src2$$reg), ext::$5, ($lshift$$constant)); |
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425 %} |
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426 ins_pipe(ialu_reg_reg_shift); |
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427 %}') |
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428 dnl |
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429 dnl $1 $2 $3 $4 $5 |
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430 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb) |
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431 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth) |
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432 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Add,add,uxtw) |
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433 dnl |
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434 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Sub,sub,uxtb) |
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435 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Sub,sub,uxth) |
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436 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Sub,sub,uxtw) |
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437 dnl |
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438 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Add,addw,uxtb) |
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439 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Add,addw,uxth) |
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440 dnl |
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441 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb) |
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442 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth) |
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443 dnl |
367 // END This section of the file is automatically generated. Do not edit -------------- |
444 // END This section of the file is automatically generated. Do not edit -------------- |