26 #include "c1/c1_MacroAssembler.hpp" |
26 #include "c1/c1_MacroAssembler.hpp" |
27 #include "gc/shenandoah/shenandoahBarrierSet.hpp" |
27 #include "gc/shenandoah/shenandoahBarrierSet.hpp" |
28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" |
28 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" |
29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" |
29 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp" |
30 |
30 |
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31 #define __ masm->masm()-> |
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32 |
31 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { |
33 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) { |
32 Register addr = _addr->as_register_lo(); |
34 Register addr = _addr->as_register_lo(); |
33 Register newval = _new_value->as_register(); |
35 Register newval = _new_value->as_register(); |
34 Register cmpval = _cmp_value->as_register(); |
36 Register cmpval = _cmp_value->as_register(); |
35 Register tmp1 = _tmp1->as_register(); |
37 Register tmp1 = _tmp1->as_register(); |
36 Register tmp2 = _tmp2->as_register(); |
38 Register tmp2 = _tmp2->as_register(); |
37 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, true, tmp1, tmp2); |
39 Register result = result_opr()->as_register(); |
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40 |
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41 ShenandoahBarrierSet::assembler()->storeval_barrier(masm->masm(), newval, rscratch2); |
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42 |
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43 if (UseCompressedOops) { |
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44 __ encode_heap_oop(tmp1, cmpval); |
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45 cmpval = tmp1; |
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46 __ encode_heap_oop(tmp2, newval); |
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47 newval = tmp2; |
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48 } |
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49 |
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50 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, result); |
38 } |
51 } |
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52 |
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53 #undef __ |
39 |
54 |
40 #ifdef ASSERT |
55 #ifdef ASSERT |
41 #define __ gen->lir(__FILE__, __LINE__)-> |
56 #define __ gen->lir(__FILE__, __LINE__)-> |
42 #else |
57 #else |
43 #define __ gen->lir()-> |
58 #define __ gen->lir()-> |
56 new_value.load_item(); |
71 new_value.load_item(); |
57 |
72 |
58 LIR_Opr t1 = gen->new_register(T_OBJECT); |
73 LIR_Opr t1 = gen->new_register(T_OBJECT); |
59 LIR_Opr t2 = gen->new_register(T_OBJECT); |
74 LIR_Opr t2 = gen->new_register(T_OBJECT); |
60 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); |
75 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base(); |
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76 LIR_Opr result = gen->new_register(T_INT); |
61 |
77 |
62 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, |
78 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result)); |
63 LIR_OprFact::illegalOpr)); |
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64 |
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65 LIR_Opr result = gen->new_register(T_INT); |
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66 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), |
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67 result, T_INT); |
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68 return result; |
79 return result; |
69 } |
80 } |
70 } |
81 } |
71 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); |
82 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value); |
72 } |
83 } |