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1 /* |
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2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef SHARE_VM_RUNTIME_ORDERACCESS_HPP |
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26 #define SHARE_VM_RUNTIME_ORDERACCESS_HPP |
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27 |
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28 #include "memory/allocation.hpp" |
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29 |
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30 // Memory Access Ordering Model |
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31 // |
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32 // This interface is based on the JSR-133 Cookbook for Compiler Writers. |
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33 // |
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34 // In the following, the terms 'previous', 'subsequent', 'before', |
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35 // 'after', 'preceding' and 'succeeding' refer to program order. The |
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36 // terms 'down' and 'below' refer to forward load or store motion |
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37 // relative to program order, while 'up' and 'above' refer to backward |
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38 // motion. |
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39 // |
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40 // We define four primitive memory barrier operations. |
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41 // |
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42 // LoadLoad: Load1(s); LoadLoad; Load2 |
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43 // |
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44 // Ensures that Load1 completes (obtains the value it loads from memory) |
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45 // before Load2 and any subsequent load operations. Loads before Load1 |
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46 // may *not* float below Load2 and any subsequent load operations. |
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47 // |
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48 // StoreStore: Store1(s); StoreStore; Store2 |
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49 // |
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50 // Ensures that Store1 completes (the effect on memory of Store1 is made |
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51 // visible to other processors) before Store2 and any subsequent store |
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52 // operations. Stores before Store1 may *not* float below Store2 and any |
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53 // subsequent store operations. |
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54 // |
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55 // LoadStore: Load1(s); LoadStore; Store2 |
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56 // |
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57 // Ensures that Load1 completes before Store2 and any subsequent store |
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58 // operations. Loads before Load1 may *not* float below Store2 and any |
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59 // subsequent store operations. |
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60 // |
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61 // StoreLoad: Store1(s); StoreLoad; Load2 |
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62 // |
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63 // Ensures that Store1 completes before Load2 and any subsequent load |
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64 // operations. Stores before Store1 may *not* float below Load2 and any |
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65 // subsequent load operations. |
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66 // |
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67 // We define two further barriers: acquire and release. |
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68 // |
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69 // Conceptually, acquire/release semantics form unidirectional and |
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70 // asynchronous barriers w.r.t. a synchronizing load(X) and store(X) pair. |
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71 // They should always be used in pairs to publish (release store) and |
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72 // access (load acquire) some implicitly understood shared data between |
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73 // threads in a relatively cheap fashion not requiring storeload. If not |
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74 // used in such a pair, it is advised to use a membar instead: |
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75 // acquire/release only make sense as pairs. |
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76 // |
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77 // T1: access_shared_data |
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78 // T1: ]release |
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79 // T1: (...) |
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80 // T1: store(X) |
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81 // |
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82 // T2: load(X) |
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83 // T2: (...) |
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84 // T2: acquire[ |
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85 // T2: access_shared_data |
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86 // |
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87 // It is guaranteed that if T2: load(X) synchronizes with (observes the |
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88 // value written by) T1: store(X), then the memory accesses before the T1: |
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89 // ]release happen before the memory accesses after the T2: acquire[. |
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90 // |
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91 // Total Store Order (TSO) machines can be seen as machines issuing a |
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92 // release store for each store and a load acquire for each load. Therefore |
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93 // there is an inherent resemblence between TSO and acquire/release |
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94 // semantics. TSO can be seen as an abstract machine where loads are |
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95 // executed immediately when encountered (hence loadload reordering not |
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96 // happening) but enqueues stores in a FIFO queue |
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97 // for asynchronous serialization (neither storestore or loadstore |
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98 // reordering happening). The only reordering happening is storeload due to |
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99 // the queue asynchronously serializing stores (yet in order). |
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100 // |
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101 // Acquire/release semantics essentially exploits this asynchronicity: when |
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102 // the load(X) acquire[ observes the store of ]release store(X), the |
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103 // accesses before the release must have happened before the accesses after |
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104 // acquire. |
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105 // |
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106 // The API offers both stand-alone acquire() and release() as well as bound |
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107 // load_acquire() and release_store(). It is guaranteed that these are |
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108 // semantically equivalent w.r.t. the defined model. However, since |
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109 // stand-alone acquire()/release() does not know which previous |
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110 // load/subsequent store is considered the synchronizing load/store, they |
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111 // may be more conservative in implementations. We advise using the bound |
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112 // variants whenever possible. |
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113 // |
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114 // Finally, we define a "fence" operation, as a bidirectional barrier. |
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115 // It guarantees that any memory access preceding the fence is not |
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116 // reordered w.r.t. any memory accesses subsequent to the fence in program |
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117 // order. This may be used to prevent sequences of loads from floating up |
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118 // above sequences of stores. |
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119 // |
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120 // The following table shows the implementations on some architectures: |
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121 // |
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122 // Constraint x86 sparc TSO ppc |
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123 // --------------------------------------------------------------------------- |
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124 // fence LoadStore | lock membar #StoreLoad sync |
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125 // StoreStore | addl 0,(sp) |
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126 // LoadLoad | |
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127 // StoreLoad |
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128 // |
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129 // release LoadStore | lwsync |
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130 // StoreStore |
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131 // |
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132 // acquire LoadLoad | lwsync |
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133 // LoadStore |
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134 // |
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135 // release_store <store> <store> lwsync |
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136 // <store> |
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137 // |
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138 // release_store_fence xchg <store> lwsync |
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139 // membar #StoreLoad <store> |
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140 // sync |
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141 // |
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142 // |
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143 // load_acquire <load> <load> <load> |
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144 // lwsync |
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145 // |
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146 // Ordering a load relative to preceding stores requires a StoreLoad, |
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147 // which implies a membar #StoreLoad between the store and load under |
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148 // sparc-TSO. On x86, we use explicitly locked add. |
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149 // |
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150 // Conventional usage is to issue a load_acquire for ordered loads. Use |
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151 // release_store for ordered stores when you care only that prior stores |
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152 // are visible before the release_store, but don't care exactly when the |
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153 // store associated with the release_store becomes visible. Use |
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154 // release_store_fence to update values like the thread state, where we |
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155 // don't want the current thread to continue until all our prior memory |
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156 // accesses (including the new thread state) are visible to other threads. |
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157 // This is equivalent to the volatile semantics of the Java Memory Model. |
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158 // |
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159 // C++ Volatile Semantics |
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160 // |
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161 // C++ volatile semantics prevent compiler re-ordering between |
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162 // volatile memory accesses. However, reordering between non-volatile |
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163 // and volatile memory accesses is in general undefined. For compiler |
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164 // reordering constraints taking non-volatile memory accesses into |
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165 // consideration, a compiler barrier has to be used instead. Some |
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166 // compiler implementations may choose to enforce additional |
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167 // constraints beyond those required by the language. Note also that |
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168 // both volatile semantics and compiler barrier do not prevent |
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169 // hardware reordering. |
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170 // |
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171 // os::is_MP Considered Redundant |
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172 // |
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173 // Callers of this interface do not need to test os::is_MP() before |
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174 // issuing an operation. The test is taken care of by the implementation |
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175 // of the interface (depending on the vm version and platform, the test |
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176 // may or may not be actually done by the implementation). |
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177 // |
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178 // |
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179 // A Note on Memory Ordering and Cache Coherency |
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180 // |
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181 // Cache coherency and memory ordering are orthogonal concepts, though they |
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182 // interact. E.g., all existing itanium machines are cache-coherent, but |
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183 // the hardware can freely reorder loads wrt other loads unless it sees a |
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184 // load-acquire instruction. All existing sparc machines are cache-coherent |
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185 // and, unlike itanium, TSO guarantees that the hardware orders loads wrt |
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186 // loads and stores, and stores wrt to each other. |
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187 // |
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188 // Consider the implementation of loadload. *If* your platform *isn't* |
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189 // cache-coherent, then loadload must not only prevent hardware load |
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190 // instruction reordering, but it must *also* ensure that subsequent |
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191 // loads from addresses that could be written by other processors (i.e., |
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192 // that are broadcast by other processors) go all the way to the first |
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193 // level of memory shared by those processors and the one issuing |
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194 // the loadload. |
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195 // |
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196 // So if we have a MP that has, say, a per-processor D$ that doesn't see |
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197 // writes by other processors, and has a shared E$ that does, the loadload |
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198 // barrier would have to make sure that either |
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199 // |
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200 // 1. cache lines in the issuing processor's D$ that contained data from |
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201 // addresses that could be written by other processors are invalidated, so |
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202 // subsequent loads from those addresses go to the E$, (it could do this |
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203 // by tagging such cache lines as 'shared', though how to tell the hardware |
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204 // to do the tagging is an interesting problem), or |
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205 // |
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206 // 2. there never are such cache lines in the issuing processor's D$, which |
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207 // means all references to shared data (however identified: see above) |
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208 // bypass the D$ (i.e., are satisfied from the E$). |
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209 // |
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210 // If your machine doesn't have an E$, substitute 'main memory' for 'E$'. |
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211 // |
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212 // Either of these alternatives is a pain, so no current machine we know of |
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213 // has incoherent caches. |
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214 // |
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215 // If loadload didn't have these properties, the store-release sequence for |
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216 // publishing a shared data structure wouldn't work, because a processor |
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217 // trying to read data newly published by another processor might go to |
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218 // its own incoherent caches to satisfy the read instead of to the newly |
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219 // written shared memory. |
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220 // |
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221 // |
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222 // NOTE WELL!! |
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223 // |
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224 // A Note on MutexLocker and Friends |
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225 // |
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226 // See mutexLocker.hpp. We assume throughout the VM that MutexLocker's |
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227 // and friends' constructors do a fence, a lock and an acquire *in that |
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228 // order*. And that their destructors do a release and unlock, in *that* |
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229 // order. If their implementations change such that these assumptions |
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230 // are violated, a whole lot of code will break. |
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231 |
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232 enum ScopedFenceType { |
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233 X_ACQUIRE |
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234 , RELEASE_X |
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235 , RELEASE_X_FENCE |
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236 }; |
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237 |
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238 template <ScopedFenceType T> |
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239 class ScopedFenceGeneral: public StackObj { |
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240 public: |
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241 void prefix() {} |
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242 void postfix() {} |
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243 }; |
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244 |
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245 template <ScopedFenceType T> |
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246 class ScopedFence : public ScopedFenceGeneral<T> { |
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247 void *const _field; |
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248 public: |
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249 ScopedFence(void *const field) : _field(field) { prefix(); } |
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250 ~ScopedFence() { postfix(); } |
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251 void prefix() { ScopedFenceGeneral<T>::prefix(); } |
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252 void postfix() { ScopedFenceGeneral<T>::postfix(); } |
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253 }; |
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254 |
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255 class OrderAccess : AllStatic { |
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256 public: |
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257 // barriers |
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258 static void loadload(); |
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259 static void storestore(); |
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260 static void loadstore(); |
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261 static void storeload(); |
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262 |
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263 static void acquire(); |
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264 static void release(); |
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265 static void fence(); |
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266 |
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267 static jbyte load_acquire(const volatile jbyte* p); |
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268 static jshort load_acquire(const volatile jshort* p); |
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269 static jint load_acquire(const volatile jint* p); |
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270 static jlong load_acquire(const volatile jlong* p); |
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271 static jubyte load_acquire(const volatile jubyte* p); |
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272 static jushort load_acquire(const volatile jushort* p); |
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273 static juint load_acquire(const volatile juint* p); |
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274 static julong load_acquire(const volatile julong* p); |
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275 static jfloat load_acquire(const volatile jfloat* p); |
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276 static jdouble load_acquire(const volatile jdouble* p); |
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277 |
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278 static intptr_t load_ptr_acquire(const volatile intptr_t* p); |
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279 static void* load_ptr_acquire(const volatile void* p); |
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280 |
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281 static void release_store(volatile jbyte* p, jbyte v); |
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282 static void release_store(volatile jshort* p, jshort v); |
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283 static void release_store(volatile jint* p, jint v); |
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284 static void release_store(volatile jlong* p, jlong v); |
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285 static void release_store(volatile jubyte* p, jubyte v); |
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286 static void release_store(volatile jushort* p, jushort v); |
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287 static void release_store(volatile juint* p, juint v); |
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288 static void release_store(volatile julong* p, julong v); |
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289 static void release_store(volatile jfloat* p, jfloat v); |
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290 static void release_store(volatile jdouble* p, jdouble v); |
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291 |
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292 static void release_store_ptr(volatile intptr_t* p, intptr_t v); |
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293 static void release_store_ptr(volatile void* p, void* v); |
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294 |
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295 static void release_store_fence(volatile jbyte* p, jbyte v); |
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296 static void release_store_fence(volatile jshort* p, jshort v); |
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297 static void release_store_fence(volatile jint* p, jint v); |
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298 static void release_store_fence(volatile jlong* p, jlong v); |
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299 static void release_store_fence(volatile jubyte* p, jubyte v); |
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300 static void release_store_fence(volatile jushort* p, jushort v); |
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301 static void release_store_fence(volatile juint* p, juint v); |
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302 static void release_store_fence(volatile julong* p, julong v); |
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303 static void release_store_fence(volatile jfloat* p, jfloat v); |
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304 static void release_store_fence(volatile jdouble* p, jdouble v); |
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305 |
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306 static void release_store_ptr_fence(volatile intptr_t* p, intptr_t v); |
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307 static void release_store_ptr_fence(volatile void* p, void* v); |
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308 |
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309 private: |
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310 // This is a helper that invokes the StubRoutines::fence_entry() |
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311 // routine if it exists, It should only be used by platforms that |
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312 // don't have another way to do the inline assembly. |
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313 static void StubRoutines_fence(); |
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314 |
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315 // Give platforms a variation point to specialize. |
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316 template<typename T> static T specialized_load_acquire (const volatile T* p); |
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317 template<typename T> static void specialized_release_store (volatile T* p, T v); |
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318 template<typename T> static void specialized_release_store_fence(volatile T* p, T v); |
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319 |
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320 template<typename FieldType, ScopedFenceType FenceType> |
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321 static void ordered_store(volatile FieldType* p, FieldType v); |
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322 |
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323 template<typename FieldType, ScopedFenceType FenceType> |
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324 static FieldType ordered_load(const volatile FieldType* p); |
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325 |
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326 static void store(volatile jbyte* p, jbyte v); |
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327 static void store(volatile jshort* p, jshort v); |
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328 static void store(volatile jint* p, jint v); |
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329 static void store(volatile jlong* p, jlong v); |
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330 static void store(volatile jdouble* p, jdouble v); |
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331 static void store(volatile jfloat* p, jfloat v); |
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332 |
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333 static jbyte load(const volatile jbyte* p); |
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334 static jshort load(const volatile jshort* p); |
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335 static jint load(const volatile jint* p); |
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336 static jlong load(const volatile jlong* p); |
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337 static jdouble load(const volatile jdouble* p); |
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338 static jfloat load(const volatile jfloat* p); |
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339 |
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340 // The following store_fence methods are deprecated and will be removed |
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341 // when all repos conform to the new generalized OrderAccess. |
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342 static void store_fence(jbyte* p, jbyte v); |
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343 static void store_fence(jshort* p, jshort v); |
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344 static void store_fence(jint* p, jint v); |
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345 static void store_fence(jlong* p, jlong v); |
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346 static void store_fence(jubyte* p, jubyte v); |
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347 static void store_fence(jushort* p, jushort v); |
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348 static void store_fence(juint* p, juint v); |
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349 static void store_fence(julong* p, julong v); |
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350 static void store_fence(jfloat* p, jfloat v); |
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351 static void store_fence(jdouble* p, jdouble v); |
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352 |
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353 static void store_ptr_fence(intptr_t* p, intptr_t v); |
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354 static void store_ptr_fence(void** p, void* v); |
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355 }; |
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356 |
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357 #endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP |