jdk-sandbox: comparison hotspot/src/share/vm/c1/c1

equal deleted inserted replaced

-:dbeb68f8a0ee
+:717c3345024f
 , _has_info(0)
 , _has_call(0)
 , _scope_value_cache(0) // initialized later with correct length
 , _interval_in_loop(0, 0) // initialized later with correct length
 , _cached_blocks(*ir->linear_scan_order())
-#ifdef IA32
+#ifdef X86
 , _fpu_stack_allocator(NULL)
 #endif
 {
 // note: to use more than on instance of LinearScan at a time this function call has to
 //       be moved somewhere outside of this constructor:
 return opr->vreg_number();
 } else if (opr->is_single_cpu()) {
 return opr->cpu_regnr();
 } else if (opr->is_double_cpu()) {
 return opr->cpu_regnrLo();
-#ifdef IA32
+#ifdef X86
 } else if (opr->is_single_xmm()) {
 return opr->fpu_regnr() + pd_first_xmm_reg;
 } else if (opr->is_double_xmm()) {
 return opr->fpu_regnrLo() + pd_first_xmm_reg;
 #endif
 return opr->fpu_regnr() + pd_first_fpu_reg;
 } else if (opr->is_double_fpu()) {
 return opr->fpu_regnrLo() + pd_first_fpu_reg;
 } else {
 ShouldNotReachHere();
+return -1;
 }
 }
 int LinearScan::reg_numHi(LIR_Opr opr) {
 assert(opr->is_register(), "should not call this otherwise");
 return -1;
 } else if (opr->is_single_cpu()) {
 return -1;
 } else if (opr->is_double_cpu()) {
 return opr->cpu_regnrHi();
-#ifdef IA32
+#ifdef X86
 } else if (opr->is_single_xmm()) {
 return -1;
 } else if (opr->is_double_xmm()) {
 return -1;
 #endif
 return -1;
 } else if (opr->is_double_fpu()) {
 return opr->fpu_regnrHi() + pd_first_fpu_reg;
 } else {
 ShouldNotReachHere();
+return -1;
 }
 }
 // ********** functions for classification of intervals
 return shouldHaveRegister;
 }
 }
-#ifdef IA32
+#ifdef X86
 if (op->code() == lir_cmove) {
 // conditional moves can handle stack operands
 assert(op->result_opr()->is_register(), "result must always be in a register");
 return shouldHaveRegister;
 }
 return shouldHaveRegister;
 }
 }
 }
 }
-#endif // IA32
+#endif // X86
 // all other operands require a register
 return mustHaveRegister;
 }
 // temp ranges for fpu registers are only created when the method has
 // virtual fpu operands. Otherwise no allocation for fpu registers is
 // perfomed and so the temp ranges would be useless
 if (has_fpu_registers()) {
-#ifdef IA32
+#ifdef X86
 if (UseSSE < 2) {
 #endif
 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
 }
-#ifdef IA32
+#ifdef X86
 }
 if (UseSSE > 0) {
 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
 assert(block_from == instructions->at(0)->id(), "must be");
 assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
 // Update intervals for registers live at the end of this block;
 BitMap live = block->live_out();
-int size = live.size();
+int size = (int)live.size();
-for (int number = live.get_next_one_offset(0, size); number < size; number = live.get_next_one_offset(number + 1, size)) {
+for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
 assert(live.at(number), "should not stop here otherwise");
 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
 const int num_regs = num_virtual_regs();
 const int size = live_set_size();
 const BitMap live_at_edge = to_block->live_in();
 // visit all registers where the live_at_edge bit is set
-for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
+for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
 assert(r < num_regs, "live information set for not exisiting interval");
 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
 Interval* from_interval = interval_at_block_end(from_block, r);
 Interval* to_interval = interval_at_block_begin(to_block, r);
 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
 DEBUG_ONLY(move_resolver.check_empty());
 // visit all registers where the live_in bit is set
 int size = live_set_size();
-for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
+for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
 resolve_exception_entry(block, r, move_resolver);
 }
 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
 for_each_phi_fun(block, phi,
 assert(handler->entry_code() == NULL, "code already present");
 // visit all registers where the live_in bit is set
 BlockBegin* block = handler->entry_block();
 int size = live_set_size();
-for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
+for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
 }
 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
 for_each_phi_fun(block, phi,
 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
 if (requires_adjacent_regs(T_LONG)) {
 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
 }
-#ifdef SPARC
 #ifdef _LP64
 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
 #else
+#ifdef SPARC
 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
-#endif
 #else
 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
-#endif
+#endif // SPARC
+#endif // LP64
 }
 case T_FLOAT: {
-#ifdef IA32
+#ifdef X86
 if (UseSSE >= 1) {
 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
 }
 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
 }
 case T_DOUBLE: {
-#ifdef IA32
+#ifdef X86
 if (UseSSE >= 2) {
 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
 }
 interval = split_child_at_op_id(interval, op_id, mode);
 }
 LIR_Opr res = operand_for_interval(interval);
-#ifdef IA32
+#ifdef X86
 // new semantic for is_last_use: not only set on definite end of interval,
 // but also before hole
 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
 // last use information is completely correct
 // information is only needed for fpu stack allocation
 return 2;
 }
 default:
 ShouldNotReachHere();
+return -1;
 }
 }
 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
 if (opr->is_single_stack()) {
 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : Location::normal, frame_map()->regname(opr)))));
 scope_values->append(sv);
 return 1;
-#ifdef IA32
+#ifdef X86
 } else if (opr->is_single_xmm()) {
 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
 scope_values->append(sv);
 return 1;
 #endif
 } else if (opr->is_single_fpu()) {
-#ifdef IA32
+#ifdef X86
 // the exact location of fpu stack values is only known
 // during fpu stack allocation, so the stack allocator object
 // must be present
 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
 assert(_fpu_stack_allocator != NULL, "must be present");
 ScopeValue* first;
 ScopeValue* second;
 if (opr->is_double_stack()) {
+#ifdef _LP64
+Location loc1;
+Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
+if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
+bailout("too large frame");
+}
+// Does this reverse on x86 vs. sparc?
+first =  new LocationValue(loc1);
+second = &_int_0_scope_value;
+#else
 Location loc1, loc2;
 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
 bailout("too large frame");
 }
 first =  new LocationValue(loc1);
 second = new LocationValue(loc2);
+#endif // _LP64
 } else if (opr->is_double_cpu()) {
 #ifdef _LP64
 VMReg rname_first = opr->as_register_lo()->as_VMReg();
 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
 rname_second = tmp;
 }
 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
-#endif
+#endif //_LP64
-#ifdef IA32
+#ifdef X86
 } else if (opr->is_double_xmm()) {
 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
 VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
 // %%% This is probably a waste but we'll keep things as they were for now
 }
 #endif
 } else if (opr->is_double_fpu()) {
 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
-// the double as float registers in the native ordering. On IA32,
+// the double as float registers in the native ordering. On X86,
 // fpu_regnrLo is a FPU stack slot whose VMReg represents
 // the low-order word of the double and fpu_regnrLo + 1 is the
 // name for the other half.  *first and *second must represent the
 // least and most significant words, respectively.
-#ifdef IA32
+#ifdef X86
 // the exact location of fpu stack values is only known
 // during fpu stack allocation, so the stack allocator object
 // must be present
 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
 assert(_fpu_stack_allocator != NULL, "must be present");
 #ifdef ASSERT
 // make sure we haven't made the op invalid.
 op->verify();
 #endif
-#ifndef _LP64
 // remove useless moves
 if (op->code() == lir_move) {
 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 LIR_Op1* move = (LIR_Op1*)op;
 LIR_Opr src = move->in_opr();
 src->is_same_register(dst)) {
 instructions->at_put(j, NULL);
 has_dead = true;
 }
 }
-#endif
 }
 if (has_dead) {
 // iterate all instructions of the block and remove all null-values.
 int insert_point = 0;
 for (int i = 0; i < num_blocks; i++) {
 BlockBegin* block = block_at(i);
 BitMap live_at_edge = block->live_in();
 // visit all registers where the live_at_edge bit is set
-for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
+for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
 Value value = gen()->instruction_for_vreg(r);
 assert(value != NULL, "all intervals live across block boundaries must have Value");
 }
 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
 }
-#ifdef IA32
+#ifdef X86
 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
 }
 #endif
 }
 // need a temporary operand for fixed intervals because type() cannot be called
 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
 opr = LIR_OprFact::single_cpu(assigned_reg());
 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
-#ifdef IA32
+#ifdef X86
 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
 #endif
 } else {
 ShouldNotReachHere();
 split_and_spill_intersecting_intervals(reg, regHi);
 }
 }
 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
-#ifdef IA32
+#ifdef X86
 // fast calculation of intervals that can never get a register because the
 // the next instruction is a call that blocks all registers
 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
 // check if this interval is the result of a split operation

changeset 1066	717c3345024f
parent 1	489c9b5090e2
child 1217	5eb97f366a6a