3991 input_size_in_bits = EVEX_32bit; |
3991 input_size_in_bits = EVEX_32bit; |
3992 } |
3992 } |
3993 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len); |
3993 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len); |
3994 } |
3994 } |
3995 |
3995 |
|
3996 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { |
|
3997 assert(VM_Version::supports_avx(), ""); |
|
3998 if (VM_Version::supports_evex()) { |
|
3999 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len); |
|
4000 } else { |
|
4001 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len); |
|
4002 } |
|
4003 } |
|
4004 |
|
4005 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { |
|
4006 assert(VM_Version::supports_avx(), ""); |
|
4007 if (VM_Version::supports_evex()) { |
|
4008 tuple_type = EVEX_FV; |
|
4009 input_size_in_bits = EVEX_64bit; |
|
4010 emit_vex_arith_q(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len); |
|
4011 } else { |
|
4012 emit_vex_arith(0x51, dst, xnoreg, src, VEX_SIMD_66, vector_len); |
|
4013 } |
|
4014 } |
|
4015 |
3996 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
4016 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
3997 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4017 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3998 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { |
4018 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) { |
3999 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66); |
4019 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66); |
4000 } else { |
4020 } else { |