1 /*

     2  * Copyright 1997-2007 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 class BiasedLockingCounters;

    26 

    27 // <sys/trap.h> promises that the system will not use traps 16-31

    28 #define ST_RESERVED_FOR_USER_0 0x10

    29 

    30 /* Written: David Ungar 4/19/97 */

    31 

    32 // Contains all the definitions needed for sparc assembly code generation.

    33 

    34 // Register aliases for parts of the system:

    35 

    36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe

    37 // across context switches in V8+ ABI.  Of course, there are no 64 bit regs

    38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.

    39 

    40 // g2-g4 are scratch registers called "application globals".  Their

    41 // meaning is reserved to the "compilation system"--which means us!

    42 // They are are not supposed to be touched by ordinary C code, although

    43 // highly-optimized C code might steal them for temps.  They are safe

    44 // across thread switches, and the ABI requires that they be safe

    45 // across function calls.

    46 //

    47 // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered

    48 // across func calls, and V8+ also allows g5 to be clobbered across

    49 // func calls.  Also, g1 and g5 can get touched while doing shared

    50 // library loading.

    51 //

    52 // We must not touch g7 (it is the thread-self register) and g6 is

    53 // reserved for certain tools.  g0, of course, is always zero.

    54 //

    55 // (Sources:  SunSoft Compilers Group, thread library engineers.)

    56 

    57 // %%%% The interpreter should be revisited to reduce global scratch regs.

    58 

    59 // This global always holds the current JavaThread pointer:

    60 

    61 REGISTER_DECLARATION(Register, G2_thread , G2);

    62 

    63 // The following globals are part of the Java calling convention:

    64 

    65 REGISTER_DECLARATION(Register, G5_method             , G5);

    66 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);

    67 REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);

    68 

    69 // The following globals are used for the new C1 & interpreter calling convention:

    70 REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument

    71 

    72 // This local is used to preserve G2_thread in the interpreter and in stubs:

    73 REGISTER_DECLARATION(Register, L7_thread_cache , L7);

    74 

    75 // These globals are used as scratch registers in the interpreter:

    76 

    77 REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch

    78 REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME

    79 REGISTER_DECLARATION(Register, G3_scratch    , G3);

    80 REGISTER_DECLARATION(Register, G4_scratch    , G4);

    81 

    82 // These globals are used as short-lived scratch registers in the compiler:

    83 

    84 REGISTER_DECLARATION(Register, Gtemp  , G5);

    85 

    86 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,

    87 // because a single patchable "set" instruction (NativeMovConstReg,

    88 // or NativeMovConstPatching for compiler1) instruction

    89 // serves to set up either quantity, depending on whether the compiled

    90 // call site is an inline cache or is megamorphic.  See the function

    91 // CompiledIC::set_to_megamorphic.

    92 //

    93 // On the other hand, G5_inline_cache_klass must differ from G5_method,

    94 // because both registers are needed for an inline cache that calls

    95 // an interpreted method.

    96 //

    97 // Note that G5_method is only the method-self for the interpreter,

    98 // and is logically unrelated to G5_megamorphic_method.

    99 //

   100 // Invariants on G2_thread (the JavaThread pointer):

   101 //  - it should not be used for any other purpose anywhere

   102 //  - it must be re-initialized by StubRoutines::call_stub()

   103 //  - it must be preserved around every use of call_VM

   104 

   105 // We can consider using g2/g3/g4 to cache more values than the

   106 // JavaThread, such as the card-marking base or perhaps pointers into

   107 // Eden.  It's something of a waste to use them as scratch temporaries,

   108 // since they are not supposed to be volatile.  (Of course, if we find

   109 // that Java doesn't benefit from application globals, then we can just

   110 // use them as ordinary temporaries.)

   111 //

   112 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,

   113 // it makes sense to use them routinely for procedure linkage,

   114 // whenever the On registers are not applicable.  Examples:  G5_method,

   115 // G5_inline_cache_klass, and a double handful of miscellaneous compiler

   116 // stubs.  This means that compiler stubs, etc., should be kept to a

   117 // maximum of two or three G-register arguments.

   118 

   119 

   120 // stub frames

   121 

   122 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself

   123 

   124 // Interpreter frames

   125 

   126 #ifdef CC_INTERP

   127 REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer

   128 REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch

   129 REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)

   130 REGISTER_DECLARATION(Register, L2_scratch       , L2);

   131 REGISTER_DECLARATION(Register, L3_scratch       , L3);

   132 REGISTER_DECLARATION(Register, L4_scratch       , L4);

   133 REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses

   134 REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses

   135 REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache

   136 REGISTER_DECLARATION(Register, O5_savedSP       , O5);

   137 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply

   138                                                        // a copy SP, so in 64-bit it's a biased value.  The bias

   139                                                        // is added and removed as needed in the frame code.

   140 // Interface to signature handler

   141 REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler

   142 REGISTER_DECLARATION(Register, Lmethod          , L6); // methodOop when calling signature handler

   143 

   144 #else

   145 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer

   146 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode

   147 REGISTER_DECLARATION(Register, Lmethod          , L2);

   148 REGISTER_DECLARATION(Register, Llocals          , L3);

   149 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler

   150                                                        // must match Llocals in asm interpreter

   151 REGISTER_DECLARATION(Register, Lmonitors        , L4);

   152 REGISTER_DECLARATION(Register, Lbyte_code       , L5);

   153 // When calling out from the interpreter we record SP so that we can remove any extra stack

   154 // space allocated during adapter transitions. This register is only live from the point

   155 // of the call until we return.

   156 REGISTER_DECLARATION(Register, Llast_SP         , L5);

   157 REGISTER_DECLARATION(Register, Lscratch         , L5);

   158 REGISTER_DECLARATION(Register, Lscratch2        , L6);

   159 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache

   160 

   161 REGISTER_DECLARATION(Register, O5_savedSP       , O5);

   162 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply

   163                                                        // a copy SP, so in 64-bit it's a biased value.  The bias

   164                                                        // is added and removed as needed in the frame code.

   165 REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables

   166 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode

   167 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data

   168 #endif /* CC_INTERP */

   169 

   170 // NOTE: Lscratch2 and LcpoolCache point to the same registers in

   171 //       the interpreter code. If Lscratch2 needs to be used for some

   172 //       purpose than LcpoolCache should be restore after that for

   173 //       the interpreter to work right

   174 // (These assignments must be compatible with L7_thread_cache; see above.)

   175 

   176 // Since Lbcp points into the middle of the method object,

   177 // it is temporarily converted into a "bcx" during GC.

   178 

   179 // Exception processing

   180 // These registers are passed into exception handlers.

   181 // All exception handlers require the exception object being thrown.

   182 // In addition, an nmethod's exception handler must be passed

   183 // the address of the call site within the nmethod, to allow

   184 // proper selection of the applicable catch block.

   185 // (Interpreter frames use their own bcp() for this purpose.)

   186 //

   187 // The Oissuing_pc value is not always needed.  When jumping to a

   188 // handler that is known to be interpreted, the Oissuing_pc value can be

   189 // omitted.  An actual catch block in compiled code receives (from its

   190 // nmethod's exception handler) the thrown exception in the Oexception,

   191 // but it doesn't need the Oissuing_pc.

   192 //

   193 // If an exception handler (either interpreted or compiled)

   194 // discovers there is no applicable catch block, it updates

   195 // the Oissuing_pc to the continuation PC of its own caller,

   196 // pops back to that caller's stack frame, and executes that

   197 // caller's exception handler.  Obviously, this process will

   198 // iterate until the control stack is popped back to a method

   199 // containing an applicable catch block.  A key invariant is

   200 // that the Oissuing_pc value is always a value local to

   201 // the method whose exception handler is currently executing.

   202 //

   203 // Note:  The issuing PC value is __not__ a raw return address (I7 value).

   204 // It is a "return pc", the address __following__ the call.

   205 // Raw return addresses are converted to issuing PCs by frame::pc(),

   206 // or by stubs.  Issuing PCs can be used directly with PC range tables.

   207 //

   208 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown

   209 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from

   210 

   211 

   212 // These must occur after the declarations above

   213 #ifndef DONT_USE_REGISTER_DEFINES

   214 

   215 #define Gthread             AS_REGISTER(Register, Gthread)

   216 #define Gmethod             AS_REGISTER(Register, Gmethod)

   217 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)

   218 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)

   219 #define Gargs               AS_REGISTER(Register, Gargs)

   220 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)

   221 #define Gframe_size         AS_REGISTER(Register, Gframe_size)

   222 #define Gtemp               AS_REGISTER(Register, Gtemp)

   223 

   224 #ifdef CC_INTERP

   225 #define Lstate              AS_REGISTER(Register, Lstate)

   226 #define Lesp                AS_REGISTER(Register, Lesp)

   227 #define L1_scratch          AS_REGISTER(Register, L1_scratch)

   228 #define Lmirror             AS_REGISTER(Register, Lmirror)

   229 #define L2_scratch          AS_REGISTER(Register, L2_scratch)

   230 #define L3_scratch          AS_REGISTER(Register, L3_scratch)

   231 #define L4_scratch          AS_REGISTER(Register, L4_scratch)

   232 #define Lscratch            AS_REGISTER(Register, Lscratch)

   233 #define Lscratch2           AS_REGISTER(Register, Lscratch2)

   234 #define L7_scratch          AS_REGISTER(Register, L7_scratch)

   235 #define Ostate              AS_REGISTER(Register, Ostate)

   236 #else

   237 #define Lesp                AS_REGISTER(Register, Lesp)

   238 #define Lbcp                AS_REGISTER(Register, Lbcp)

   239 #define Lmethod             AS_REGISTER(Register, Lmethod)

   240 #define Llocals             AS_REGISTER(Register, Llocals)

   241 #define Lmonitors           AS_REGISTER(Register, Lmonitors)

   242 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)

   243 #define Lscratch            AS_REGISTER(Register, Lscratch)

   244 #define Lscratch2           AS_REGISTER(Register, Lscratch2)

   245 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)

   246 #endif /* ! CC_INTERP */

   247 

   248 #define Lentry_args         AS_REGISTER(Register, Lentry_args)

   249 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)

   250 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)

   251 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)

   252 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)

   253 #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)

   254 

   255 #define Oexception          AS_REGISTER(Register, Oexception)

   256 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)

   257 

   258 

   259 #endif

   260 

   261 // Address is an abstraction used to represent a memory location.

   262 //

   263 // Note: A register location is represented via a Register, not

   264 //       via an address for efficiency & simplicity reasons.

   265 

   266 class Address VALUE_OBJ_CLASS_SPEC {

   267  private:

   268   Register              _base;

   269 #ifdef _LP64

   270   int                   _hi32;          // bits 63::32

   271   int                   _low32;         // bits 31::0

   272 #endif

   273   int                   _hi;

   274   int                   _disp;

   275   RelocationHolder      _rspec;

   276 

   277   RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {

   278     switch (rt) {

   279     case relocInfo::external_word_type:

   280       return external_word_Relocation::spec(a);

   281     case relocInfo::internal_word_type:

   282       return internal_word_Relocation::spec(a);

   283 #ifdef _LP64

   284     case relocInfo::opt_virtual_call_type:

   285       return opt_virtual_call_Relocation::spec();

   286     case relocInfo::static_call_type:

   287       return static_call_Relocation::spec();

   288     case relocInfo::runtime_call_type:

   289       return runtime_call_Relocation::spec();

   290 #endif

   291     case relocInfo::none:

   292       return RelocationHolder();

   293     default:

   294       ShouldNotReachHere();

   295       return RelocationHolder();

   296     }

   297   }

   298 

   299  public:

   300   Address(Register b, address a, relocInfo::relocType rt = relocInfo::none)

   301     : _rspec(rspec_from_rtype(rt, a))

   302   {

   303     _base  = b;

   304 #ifdef _LP64

   305     _hi32  = (intptr_t)a >> 32;    // top 32 bits in 64 bit word

   306     _low32 = (intptr_t)a & ~0;     // low 32 bits in 64 bit word

   307 #endif

   308     _hi    = (intptr_t)a & ~0x3ff; // top    22 bits in low word

   309     _disp  = (intptr_t)a &  0x3ff; // bottom 10 bits

   310   }

   311 

   312   Address(Register b, address a, RelocationHolder const& rspec)

   313     : _rspec(rspec)

   314   {

   315     _base  = b;

   316 #ifdef _LP64

   317     _hi32  = (intptr_t)a >> 32;    // top 32 bits in 64 bit word

   318     _low32 = (intptr_t)a & ~0;     // low 32 bits in 64 bit word

   319 #endif

   320     _hi    = (intptr_t)a & ~0x3ff; // top    22 bits

   321     _disp  = (intptr_t)a &  0x3ff; // bottom 10 bits

   322   }

   323 

   324   Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder())

   325     : _rspec(rspec)

   326   {

   327     _base  = b;

   328 #ifdef _LP64

   329 // [RGV] Put in Assert to force me to check usage of this constructor

   330      assert( h == 0, "Check usage of this constructor" );

   331     _hi32  = h;

   332     _low32 = d;

   333     _hi    = h;

   334     _disp  = d;

   335 #else

   336     _hi    = h;

   337     _disp  = d;

   338 #endif

   339   }

   340 

   341   Address()

   342     : _rspec(RelocationHolder())

   343   {

   344     _base  = G0;

   345 #ifdef _LP64

   346     _hi32  = 0;

   347     _low32 = 0;

   348 #endif

   349     _hi    = 0;

   350     _disp  = 0;

   351   }

   352 

   353   // fancier constructors

   354 

   355   enum addr_type {

   356     extra_in_argument,  // in the In registers

   357     extra_out_argument  // in the Outs

   358   };

   359 

   360   Address( addr_type, int );

   361 

   362   // accessors

   363 

   364   Register               base() const { return _base; }

   365 #ifdef _LP64

   366   int                   hi32()  const { return _hi32; }

   367   int                   low32() const { return _low32; }

   368 #endif

   369   int                      hi() const { return _hi;  }

   370   int                    disp() const { return _disp; }

   371 #ifdef _LP64

   372   intptr_t              value() const { return ((intptr_t)_hi32 << 32) |

   373                                                 (intptr_t)(uint32_t)_low32; }

   374 #else

   375   int                   value() const { return _hi | _disp; }

   376 #endif

   377   const relocInfo::relocType  rtype() { return _rspec.type(); }

   378   const RelocationHolder&     rspec() { return _rspec; }

   379 

   380   RelocationHolder      rspec(int offset) const {

   381     return offset == 0 ? _rspec : _rspec.plus(offset);

   382   }

   383 

   384   inline bool is_simm13(int offset = 0);  // check disp+offset for overflow

   385 

   386   Address split_disp() const {            // deal with disp overflow

   387     Address a = (*this);

   388     int hi_disp = _disp & ~0x3ff;

   389     if (hi_disp != 0) {

   390       a._disp -= hi_disp;

   391       a._hi   += hi_disp;

   392     }

   393     return a;

   394   }

   395 

   396   Address after_save() const {

   397     Address a = (*this);

   398     a._base = a._base->after_save();

   399     return a;

   400   }

   401 

   402   Address after_restore() const {

   403     Address a = (*this);

   404     a._base = a._base->after_restore();

   405     return a;

   406   }

   407 

   408   friend class Assembler;

   409 };

   410 

   411 

   412 inline Address RegisterImpl::address_in_saved_window() const {

   413    return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));

   414 }

   415 

   416 

   417 

   418 // Argument is an abstraction used to represent an outgoing

   419 // actual argument or an incoming formal parameter, whether

   420 // it resides in memory or in a register, in a manner consistent

   421 // with the SPARC Application Binary Interface, or ABI.  This is

   422 // often referred to as the native or C calling convention.

   423 

   424 class Argument VALUE_OBJ_CLASS_SPEC {

   425  private:

   426   int _number;

   427   bool _is_in;

   428 

   429  public:

   430 #ifdef _LP64

   431   enum {

   432     n_register_parameters = 6,          // only 6 registers may contain integer parameters

   433     n_float_register_parameters = 16    // Can have up to 16 floating registers

   434   };

   435 #else

   436   enum {

   437     n_register_parameters = 6           // only 6 registers may contain integer parameters

   438   };

   439 #endif

   440 

   441   // creation

   442   Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}

   443 

   444   int  number() const  { return _number;  }

   445   bool is_in()  const  { return _is_in;   }

   446   bool is_out() const  { return !is_in(); }

   447 

   448   Argument successor() const  { return Argument(number() + 1, is_in()); }

   449   Argument as_in()     const  { return Argument(number(), true ); }

   450   Argument as_out()    const  { return Argument(number(), false); }

   451 

   452   // locating register-based arguments:

   453   bool is_register() const { return _number < n_register_parameters; }

   454 

   455 #ifdef _LP64

   456   // locating Floating Point register-based arguments:

   457   bool is_float_register() const { return _number < n_float_register_parameters; }

   458 

   459   FloatRegister as_float_register() const {

   460     assert(is_float_register(), "must be a register argument");

   461     return as_FloatRegister(( number() *2 ) + 1);

   462   }

   463   FloatRegister as_double_register() const {

   464     assert(is_float_register(), "must be a register argument");

   465     return as_FloatRegister(( number() *2 ));

   466   }

   467 #endif

   468 

   469   Register as_register() const {

   470     assert(is_register(), "must be a register argument");

   471     return is_in() ? as_iRegister(number()) : as_oRegister(number());

   472   }

   473 

   474   // locating memory-based arguments

   475   Address as_address() const {

   476     assert(!is_register(), "must be a memory argument");

   477     return address_in_frame();

   478   }

   479 

   480   // When applied to a register-based argument, give the corresponding address

   481   // into the 6-word area "into which callee may store register arguments"

   482   // (This is a different place than the corresponding register-save area location.)

   483   Address address_in_frame() const {

   484     return Address( is_in()   ? Address::extra_in_argument

   485                               : Address::extra_out_argument,

   486                     _number );

   487   }

   488 

   489   // debugging

   490   const char* name() const;

   491 

   492   friend class Assembler;

   493 };

   494 

   495 

   496 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction

   497 // level; i.e., what you write

   498 // is what you get. The Assembler is generating code into a CodeBuffer.

   499 

   500 class Assembler : public AbstractAssembler  {

   501  protected:

   502 

   503   static void print_instruction(int inst);

   504   static int  patched_branch(int dest_pos, int inst, int inst_pos);

   505   static int  branch_destination(int inst, int pos);

   506 

   507 

   508   friend class AbstractAssembler;

   509 

   510   // code patchers need various routines like inv_wdisp()

   511   friend class NativeInstruction;

   512   friend class NativeGeneralJump;

   513   friend class Relocation;

   514   friend class Label;

   515 

   516  public:

   517   // op carries format info; see page 62 & 267

   518 

   519   enum ops {

   520     call_op   = 1, // fmt 1

   521     branch_op = 0, // also sethi (fmt2)

   522     arith_op  = 2, // fmt 3, arith & misc

   523     ldst_op   = 3  // fmt 3, load/store

   524   };

   525 

   526   enum op2s {

   527     bpr_op2   = 3,

   528     fb_op2    = 6,

   529     fbp_op2   = 5,

   530     br_op2    = 2,

   531     bp_op2    = 1,

   532     cb_op2    = 7, // V8

   533     sethi_op2 = 4

   534   };

   535 

   536   enum op3s {

   537     // selected op3s

   538     add_op3      = 0x00,

   539     and_op3      = 0x01,

   540     or_op3       = 0x02,

   541     xor_op3      = 0x03,

   542     sub_op3      = 0x04,

   543     andn_op3     = 0x05,

   544     orn_op3      = 0x06,

   545     xnor_op3     = 0x07,

   546     addc_op3     = 0x08,

   547     mulx_op3     = 0x09,

   548     umul_op3     = 0x0a,

   549     smul_op3     = 0x0b,

   550     subc_op3     = 0x0c,

   551     udivx_op3    = 0x0d,

   552     udiv_op3     = 0x0e,

   553     sdiv_op3     = 0x0f,

   554 

   555     addcc_op3    = 0x10,

   556     andcc_op3    = 0x11,

   557     orcc_op3     = 0x12,

   558     xorcc_op3    = 0x13,

   559     subcc_op3    = 0x14,

   560     andncc_op3   = 0x15,

   561     orncc_op3    = 0x16,

   562     xnorcc_op3   = 0x17,

   563     addccc_op3   = 0x18,

   564     umulcc_op3   = 0x1a,

   565     smulcc_op3   = 0x1b,

   566     subccc_op3   = 0x1c,

   567     udivcc_op3   = 0x1e,

   568     sdivcc_op3   = 0x1f,

   569 

   570     taddcc_op3   = 0x20,

   571     tsubcc_op3   = 0x21,

   572     taddcctv_op3 = 0x22,

   573     tsubcctv_op3 = 0x23,

   574     mulscc_op3   = 0x24,

   575     sll_op3      = 0x25,

   576     sllx_op3     = 0x25,

   577     srl_op3      = 0x26,

   578     srlx_op3     = 0x26,

   579     sra_op3      = 0x27,

   580     srax_op3     = 0x27,

   581     rdreg_op3    = 0x28,

   582     membar_op3   = 0x28,

   583 

   584     flushw_op3   = 0x2b,

   585     movcc_op3    = 0x2c,

   586     sdivx_op3    = 0x2d,

   587     popc_op3     = 0x2e,

   588     movr_op3     = 0x2f,

   589 

   590     sir_op3      = 0x30,

   591     wrreg_op3    = 0x30,

   592     saved_op3    = 0x31,

   593 

   594     fpop1_op3    = 0x34,

   595     fpop2_op3    = 0x35,

   596     impdep1_op3  = 0x36,

   597     impdep2_op3  = 0x37,

   598     jmpl_op3     = 0x38,

   599     rett_op3     = 0x39,

   600     trap_op3     = 0x3a,

   601     flush_op3    = 0x3b,

   602     save_op3     = 0x3c,

   603     restore_op3  = 0x3d,

   604     done_op3     = 0x3e,

   605     retry_op3    = 0x3e,

   606 

   607     lduw_op3     = 0x00,

   608     ldub_op3     = 0x01,

   609     lduh_op3     = 0x02,

   610     ldd_op3      = 0x03,

   611     stw_op3      = 0x04,

   612     stb_op3      = 0x05,

   613     sth_op3      = 0x06,

   614     std_op3      = 0x07,

   615     ldsw_op3     = 0x08,

   616     ldsb_op3     = 0x09,

   617     ldsh_op3     = 0x0a,

   618     ldx_op3      = 0x0b,

   619 

   620     ldstub_op3   = 0x0d,

   621     stx_op3      = 0x0e,

   622     swap_op3     = 0x0f,

   623 

   624     lduwa_op3    = 0x10,

   625     ldxa_op3     = 0x1b,

   626 

   627     stwa_op3     = 0x14,

   628     stxa_op3     = 0x1e,

   629 

   630     ldf_op3      = 0x20,

   631     ldfsr_op3    = 0x21,

   632     ldqf_op3     = 0x22,

   633     lddf_op3     = 0x23,

   634     stf_op3      = 0x24,

   635     stfsr_op3    = 0x25,

   636     stqf_op3     = 0x26,

   637     stdf_op3     = 0x27,

   638 

   639     prefetch_op3 = 0x2d,

   640 

   641 

   642     ldc_op3      = 0x30,

   643     ldcsr_op3    = 0x31,

   644     lddc_op3     = 0x33,

   645     stc_op3      = 0x34,

   646     stcsr_op3    = 0x35,

   647     stdcq_op3    = 0x36,

   648     stdc_op3     = 0x37,

   649 

   650     casa_op3     = 0x3c,

   651     casxa_op3    = 0x3e,

   652 

   653     alt_bit_op3  = 0x10,

   654      cc_bit_op3  = 0x10

   655   };

   656 

   657   enum opfs {

   658     // selected opfs

   659     fmovs_opf   = 0x01,

   660     fmovd_opf   = 0x02,

   661 

   662     fnegs_opf   = 0x05,

   663     fnegd_opf   = 0x06,

   664 

   665     fadds_opf   = 0x41,

   666     faddd_opf   = 0x42,

   667     fsubs_opf   = 0x45,

   668     fsubd_opf   = 0x46,

   669 

   670     fmuls_opf   = 0x49,

   671     fmuld_opf   = 0x4a,

   672     fdivs_opf   = 0x4d,

   673     fdivd_opf   = 0x4e,

   674 

   675     fcmps_opf   = 0x51,

   676     fcmpd_opf   = 0x52,

   677 

   678     fstox_opf   = 0x81,

   679     fdtox_opf   = 0x82,

   680     fxtos_opf   = 0x84,

   681     fxtod_opf   = 0x88,

   682     fitos_opf   = 0xc4,

   683     fdtos_opf   = 0xc6,

   684     fitod_opf   = 0xc8,

   685     fstod_opf   = 0xc9,

   686     fstoi_opf   = 0xd1,

   687     fdtoi_opf   = 0xd2

   688   };

   689 

   690   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };

   691 

   692   enum Condition {

   693      // for FBfcc & FBPfcc instruction

   694     f_never                     = 0,

   695     f_notEqual                  = 1,

   696     f_notZero                   = 1,

   697     f_lessOrGreater             = 2,

   698     f_unorderedOrLess           = 3,

   699     f_less                      = 4,

   700     f_unorderedOrGreater        = 5,

   701     f_greater                   = 6,

   702     f_unordered                 = 7,

   703     f_always                    = 8,

   704     f_equal                     = 9,

   705     f_zero                      = 9,

   706     f_unorderedOrEqual          = 10,

   707     f_greaterOrEqual            = 11,

   708     f_unorderedOrGreaterOrEqual = 12,

   709     f_lessOrEqual               = 13,

   710     f_unorderedOrLessOrEqual    = 14,

   711     f_ordered                   = 15,

   712 

   713     // V8 coproc, pp 123 v8 manual

   714 

   715     cp_always  = 8,

   716     cp_never   = 0,

   717     cp_3       = 7,

   718     cp_2       = 6,

   719     cp_2or3    = 5,

   720     cp_1       = 4,

   721     cp_1or3    = 3,

   722     cp_1or2    = 2,

   723     cp_1or2or3 = 1,

   724     cp_0       = 9,

   725     cp_0or3    = 10,

   726     cp_0or2    = 11,

   727     cp_0or2or3 = 12,

   728     cp_0or1    = 13,

   729     cp_0or1or3 = 14,

   730     cp_0or1or2 = 15,

   731 

   732 

   733     // for integers

   734 

   735     never                 =  0,

   736     equal                 =  1,

   737     zero                  =  1,

   738     lessEqual             =  2,

   739     less                  =  3,

   740     lessEqualUnsigned     =  4,

   741     lessUnsigned          =  5,

   742     carrySet              =  5,

   743     negative              =  6,

   744     overflowSet           =  7,

   745     always                =  8,

   746     notEqual              =  9,

   747     notZero               =  9,

   748     greater               =  10,

   749     greaterEqual          =  11,

   750     greaterUnsigned       =  12,

   751     greaterEqualUnsigned  =  13,

   752     carryClear            =  13,

   753     positive              =  14,

   754     overflowClear         =  15

   755   };

   756 

   757   enum CC {

   758     icc  = 0,  xcc  = 2,

   759     // ptr_cc is the correct condition code for a pointer or intptr_t:

   760     ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),

   761     fcc0 = 0,  fcc1 = 1, fcc2 = 2, fcc3 = 3

   762   };

   763 

   764   enum PrefetchFcn {

   765     severalReads = 0,  oneRead = 1,  severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4

   766   };

   767 

   768  public:

   769   // Helper functions for groups of instructions

   770 

   771   enum Predict { pt = 1, pn = 0 }; // pt = predict taken

   772 

   773   enum Membar_mask_bits { // page 184, v9

   774     StoreStore = 1 << 3,

   775     LoadStore  = 1 << 2,

   776     StoreLoad  = 1 << 1,

   777     LoadLoad   = 1 << 0,

   778 

   779     Sync       = 1 << 6,

   780     MemIssue   = 1 << 5,

   781     Lookaside  = 1 << 4

   782   };

   783 

   784   // test if x is within signed immediate range for nbits

   785   static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 )  <= x   &&   x  <  ( 1 << nbits-1 ); }

   786 

   787   // test if -4096 <= x <= 4095

   788   static bool is_simm13(int x) { return is_simm(x, 13); }

   789 

   790   enum ASIs { // page 72, v9

   791     ASI_PRIMARY        = 0x80,

   792     ASI_PRIMARY_LITTLE = 0x88

   793     // add more from book as needed

   794   };

   795 

   796  protected:

   797   // helpers

   798 

   799   // x is supposed to fit in a field "nbits" wide

   800   // and be sign-extended. Check the range.

   801 

   802   static void assert_signed_range(intptr_t x, int nbits) {

   803     assert( nbits == 32

   804         ||  -(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1),

   805       "value out of range");

   806   }

   807 

   808   static void assert_signed_word_disp_range(intptr_t x, int nbits) {

   809     assert( (x & 3) == 0, "not word aligned");

   810     assert_signed_range(x, nbits + 2);

   811   }

   812 

   813   static void assert_unsigned_const(int x, int nbits) {

   814     assert( juint(x)  <  juint(1 << nbits), "unsigned constant out of range");

   815   }

   816 

   817   // fields: note bits numbered from LSB = 0,

   818   //  fields known by inclusive bit range

   819 

   820   static int fmask(juint hi_bit, juint lo_bit) {

   821     assert( hi_bit >= lo_bit  &&  0 <= lo_bit  &&  hi_bit < 32, "bad bits");

   822     return (1 << ( hi_bit-lo_bit + 1 )) - 1;

   823   }

   824 

   825   // inverse of u_field

   826 

   827   static int inv_u_field(int x, int hi_bit, int lo_bit) {

   828     juint r = juint(x) >> lo_bit;

   829     r &= fmask( hi_bit, lo_bit);

   830     return int(r);

   831   }

   832 

   833 

   834   // signed version: extract from field and sign-extend

   835 

   836   static int inv_s_field(int x, int hi_bit, int lo_bit) {

   837     int sign_shift = 31 - hi_bit;

   838     return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);

   839   }

   840 

   841   // given a field that ranges from hi_bit to lo_bit (inclusive,

   842   // LSB = 0), and an unsigned value for the field,

   843   // shift it into the field

   844 

   845 #ifdef ASSERT

   846   static int u_field(int x, int hi_bit, int lo_bit) {

   847     assert( ( x & ~fmask(hi_bit, lo_bit))  == 0,

   848             "value out of range");

   849     int r = x << lo_bit;

   850     assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");

   851     return r;

   852   }

   853 #else

   854   // make sure this is inlined as it will reduce code size significantly

   855   #define u_field(x, hi_bit, lo_bit)   ((x) << (lo_bit))

   856 #endif

   857 

   858   static int inv_op(  int x ) { return inv_u_field(x, 31, 30); }

   859   static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }

   860   static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }

   861   static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }

   862 

   863   static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }

   864 

   865   static Register inv_rd(  int x ) { return as_Register(inv_u_field(x, 29, 25)); }

   866   static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }

   867   static Register inv_rs2( int x ) { return as_Register(inv_u_field(x,  4,  0)); }

   868 

   869   static int op(       int         x)  { return  u_field(x,             31, 30); }

   870   static int rd(       Register    r)  { return  u_field(r->encoding(), 29, 25); }

   871   static int fcn(      int         x)  { return  u_field(x,             29, 25); }

   872   static int op3(      int         x)  { return  u_field(x,             24, 19); }

   873   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }

   874   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }

   875   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }

   876   static int cond(     int         x)  { return  u_field(x,             28, 25); }

   877   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }

   878   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }

   879   static int op2(      int         x)  { return  u_field(x,             24, 22); }

   880   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }

   881   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }

   882   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }

   883   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }

   884   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }

   885   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }

   886   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }

   887   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }

   888   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit

   889   static int opf(      int         x)  { return  u_field(x,             13,  5); }

   890 

   891   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }

   892   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }

   893 

   894   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };

   895   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };

   896   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };

   897 

   898   // some float instructions use this encoding on the op3 field

   899   static int alt_op3(int op, FloatRegisterImpl::Width w) {

   900     int r;

   901     switch(w) {

   902      case FloatRegisterImpl::S: r = op + 0;  break;

   903      case FloatRegisterImpl::D: r = op + 3;  break;

   904      case FloatRegisterImpl::Q: r = op + 2;  break;

   905      default: ShouldNotReachHere(); break;

   906     }

   907     return op3(r);

   908   }

   909 

   910 

   911   // compute inverse of simm

   912   static int inv_simm(int x, int nbits) {

   913     return (int)(x << (32 - nbits)) >> (32 - nbits);

   914   }

   915 

   916   static int inv_simm13( int x ) { return inv_simm(x, 13); }

   917 

   918   // signed immediate, in low bits, nbits long

   919   static int simm(int x, int nbits) {

   920     assert_signed_range(x, nbits);

   921     return x  &  (( 1 << nbits ) - 1);

   922   }

   923 

   924   // compute inverse of wdisp16

   925   static intptr_t inv_wdisp16(int x, intptr_t pos) {

   926     int lo = x & (( 1 << 14 ) - 1);

   927     int hi = (x >> 20) & 3;

   928     if (hi >= 2) hi |= ~1;

   929     return (((hi << 14) | lo) << 2) + pos;

   930   }

   931 

   932   // word offset, 14 bits at LSend, 2 bits at B21, B20

   933   static int wdisp16(intptr_t x, intptr_t off) {

   934     intptr_t xx = x - off;

   935     assert_signed_word_disp_range(xx, 16);

   936     int r =  (xx >> 2) & ((1 << 14) - 1)

   937            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );

   938     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");

   939     return r;

   940   }

   941 

   942 

   943   // word displacement in low-order nbits bits

   944 

   945   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {

   946     int pre_sign_extend = x & (( 1 << nbits ) - 1);

   947     int r =  pre_sign_extend >= ( 1 << (nbits-1) )

   948        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)

   949        :   pre_sign_extend;

   950     return (r << 2) + pos;

   951   }

   952 

   953   static int wdisp( intptr_t x, intptr_t off, int nbits ) {

   954     intptr_t xx = x - off;

   955     assert_signed_word_disp_range(xx, nbits);

   956     int r =  (xx >> 2) & (( 1 << nbits ) - 1);

   957     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");

   958     return r;

   959   }

   960 

   961 

   962   // Extract the top 32 bits in a 64 bit word

   963   static int32_t hi32( int64_t x ) {

   964     int32_t r = int32_t( (uint64_t)x >> 32 );

   965     return r;

   966   }

   967 

   968   // given a sethi instruction, extract the constant, left-justified

   969   static int inv_hi22( int x ) {

   970     return x << 10;

   971   }

   972 

   973   // create an imm22 field, given a 32-bit left-justified constant

   974   static int hi22( int x ) {

   975     int r = int( juint(x) >> 10 );

   976     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");

   977     return r;

   978   }

   979 

   980   // create a low10 __value__ (not a field) for a given a 32-bit constant

   981   static int low10( int x ) {

   982     return x & ((1 << 10) - 1);

   983   }

   984 

   985   // instruction only in v9

   986   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }

   987 

   988   // instruction only in v8

   989   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }

   990 

   991   // instruction deprecated in v9

   992   static void v9_dep()  { } // do nothing for now

   993 

   994   // some float instructions only exist for single prec. on v8

   995   static void v8_s_only(FloatRegisterImpl::Width w)  { if (w != FloatRegisterImpl::S)  v9_only(); }

   996 

   997   // v8 has no CC field

   998   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }

   999 

  1000  protected:

  1001   // Simple delay-slot scheme:

  1002   // In order to check the programmer, the assembler keeps track of deley slots.

  1003   // It forbids CTIs in delay slots (conservative, but should be OK).

  1004   // Also, when putting an instruction into a delay slot, you must say

  1005   // asm->delayed()->add(...), in order to check that you don't omit

  1006   // delay-slot instructions.

  1007   // To implement this, we use a simple FSA

  1008 

  1009 #ifdef ASSERT

  1010   #define CHECK_DELAY

  1011 #endif

  1012 #ifdef CHECK_DELAY

  1013   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;

  1014 #endif

  1015 

  1016  public:

  1017   // Tells assembler next instruction must NOT be in delay slot.

  1018   // Use at start of multinstruction macros.

  1019   void assert_not_delayed() {

  1020     // This is a separate overloading to avoid creation of string constants

  1021     // in non-asserted code--with some compilers this pollutes the object code.

  1022 #ifdef CHECK_DELAY

  1023     assert_not_delayed("next instruction should not be a delay slot");

  1024 #endif

  1025   }

  1026   void assert_not_delayed(const char* msg) {

  1027 #ifdef CHECK_DELAY

  1028     assert_msg ( delay_state == no_delay, msg);

  1029 #endif

  1030   }

  1031 

  1032  protected:

  1033   // Delay slot helpers

  1034   // cti is called when emitting control-transfer instruction,

  1035   // BEFORE doing the emitting.

  1036   // Only effective when assertion-checking is enabled.

  1037   void cti() {

  1038 #ifdef CHECK_DELAY

  1039     assert_not_delayed("cti should not be in delay slot");

  1040 #endif

  1041   }

  1042 

  1043   // called when emitting cti with a delay slot, AFTER emitting

  1044   void has_delay_slot() {

  1045 #ifdef CHECK_DELAY

  1046     assert_not_delayed("just checking");

  1047     delay_state = at_delay_slot;

  1048 #endif

  1049   }

  1050 

  1051 public:

  1052   // Tells assembler you know that next instruction is delayed

  1053   Assembler* delayed() {

  1054 #ifdef CHECK_DELAY

  1055     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");

  1056     delay_state = filling_delay_slot;

  1057 #endif

  1058     return this;

  1059   }

  1060 

  1061   void flush() {

  1062 #ifdef CHECK_DELAY

  1063     assert ( delay_state == no_delay, "ending code with a delay slot");

  1064 #endif

  1065     AbstractAssembler::flush();

  1066   }

  1067 

  1068   inline void emit_long(int);  // shadows AbstractAssembler::emit_long

  1069   inline void emit_data(int x) { emit_long(x); }

  1070   inline void emit_data(int, RelocationHolder const&);

  1071   inline void emit_data(int, relocInfo::relocType rtype);

  1072   // helper for above fcns

  1073   inline void check_delay();

  1074 

  1075 

  1076  public:

  1077   // instructions, refer to page numbers in the SPARC Architecture Manual, V9

  1078 

  1079   // pp 135 (addc was addx in v8)

  1080 

  1081   inline void add(    Register s1, Register s2, Register d );

  1082   inline void add(    Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);

  1083   inline void add(    Register s1, int simm13a, Register d, RelocationHolder const& rspec);

  1084   inline void add(    const Address&  a,              Register d, int offset = 0);

  1085 

  1086   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }

  1087   void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }

  1088   void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }

  1089   void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }

  1090   void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }

  1091   void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }

  1092 

  1093   // pp 136

  1094 

  1095   inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );

  1096   inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);

  1097 

  1098  protected: // use MacroAssembler::br instead

  1099 

  1100   // pp 138

  1101 

  1102   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );

  1103   inline void fb( Condition c, bool a, Label& L );

  1104 

  1105   // pp 141

  1106 

  1107   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );

  1108   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );

  1109 

  1110  public:

  1111 

  1112   // pp 144

  1113 

  1114   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );

  1115   inline void br( Condition c, bool a, Label& L );

  1116 

  1117   // pp 146

  1118 

  1119   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );

  1120   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );

  1121 

  1122   // pp 121 (V8)

  1123 

  1124   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );

  1125   inline void cb( Condition c, bool a, Label& L );

  1126 

  1127   // pp 149

  1128 

  1129   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );

  1130   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );

  1131 

  1132   // pp 150

  1133 

  1134   // These instructions compare the contents of s2 with the contents of

  1135   // memory at address in s1. If the values are equal, the contents of memory