16522 %} |
16527 %} |
16523 ins_pipe(vlogical128); |
16528 ins_pipe(vlogical128); |
16524 %} |
16529 %} |
16525 |
16530 |
16526 // ------------------------------ Shift --------------------------------------- |
16531 // ------------------------------ Shift --------------------------------------- |
16527 |
16532 instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{ |
16528 instruct vshiftcntL(vecX dst, iRegIorL2I cnt) %{ |
16533 predicate(n->as_Vector()->length_in_bytes() == 8); |
16529 match(Set dst (LShiftCntV cnt)); |
16534 match(Set dst (LShiftCntV cnt)); |
16530 format %{ "dup $dst, $cnt\t# shift count (vecX)" %} |
16535 match(Set dst (RShiftCntV cnt)); |
|
16536 format %{ "dup $dst, $cnt\t# shift count vector (8B)" %} |
|
16537 ins_encode %{ |
|
16538 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg)); |
|
16539 %} |
|
16540 ins_pipe(vdup_reg_reg64); |
|
16541 %} |
|
16542 |
|
16543 instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{ |
|
16544 predicate(n->as_Vector()->length_in_bytes() == 16); |
|
16545 match(Set dst (LShiftCntV cnt)); |
|
16546 match(Set dst (RShiftCntV cnt)); |
|
16547 format %{ "dup $dst, $cnt\t# shift count vector (16B)" %} |
16531 ins_encode %{ |
16548 ins_encode %{ |
16532 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
16549 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
16533 %} |
16550 %} |
16534 ins_pipe(vdup_reg_reg128); |
16551 ins_pipe(vdup_reg_reg128); |
16535 %} |
16552 %} |
16536 |
16553 |
16537 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount |
16554 instruct vsll8B(vecD dst, vecD src, vecD shift) %{ |
16538 instruct vshiftcntR(vecX dst, iRegIorL2I cnt) %{ |
|
16539 match(Set dst (RShiftCntV cnt)); |
|
16540 format %{ "dup $dst, $cnt\t# shift count (vecX)\n\tneg $dst, $dst\t T16B" %} |
|
16541 ins_encode %{ |
|
16542 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
|
16543 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg)); |
|
16544 %} |
|
16545 ins_pipe(vdup_reg_reg128); |
|
16546 %} |
|
16547 |
|
16548 instruct vsll8B(vecD dst, vecD src, vecX shift) %{ |
|
16549 predicate(n->as_Vector()->length() == 4 || |
16555 predicate(n->as_Vector()->length() == 4 || |
16550 n->as_Vector()->length() == 8); |
16556 n->as_Vector()->length() == 8); |
16551 match(Set dst (LShiftVB src shift)); |
16557 match(Set dst (LShiftVB src shift)); |
16552 match(Set dst (RShiftVB src shift)); |
|
16553 ins_cost(INSN_COST); |
16558 ins_cost(INSN_COST); |
16554 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %} |
16559 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %} |
16555 ins_encode %{ |
16560 ins_encode %{ |
16556 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
16561 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
16557 as_FloatRegister($src$$reg), |
16562 as_FloatRegister($src$$reg), |
16561 %} |
16566 %} |
16562 |
16567 |
16563 instruct vsll16B(vecX dst, vecX src, vecX shift) %{ |
16568 instruct vsll16B(vecX dst, vecX src, vecX shift) %{ |
16564 predicate(n->as_Vector()->length() == 16); |
16569 predicate(n->as_Vector()->length() == 16); |
16565 match(Set dst (LShiftVB src shift)); |
16570 match(Set dst (LShiftVB src shift)); |
16566 match(Set dst (RShiftVB src shift)); |
|
16567 ins_cost(INSN_COST); |
16571 ins_cost(INSN_COST); |
16568 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %} |
16572 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %} |
16569 ins_encode %{ |
16573 ins_encode %{ |
16570 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
16574 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
16571 as_FloatRegister($src$$reg), |
16575 as_FloatRegister($src$$reg), |
16572 as_FloatRegister($shift$$reg)); |
16576 as_FloatRegister($shift$$reg)); |
16573 %} |
16577 %} |
16574 ins_pipe(vshift128); |
16578 ins_pipe(vshift128); |
16575 %} |
16579 %} |
16576 |
16580 |
16577 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{ |
16581 // Right shifts with vector shift count on aarch64 SIMD are implemented |
|
16582 // as left shift by negative shift count. |
|
16583 // There are two cases for vector shift count. |
|
16584 // |
|
16585 // Case 1: The vector shift count is from replication. |
|
16586 // | | |
|
16587 // LoadVector RShiftCntV |
|
16588 // | / |
|
16589 // RShiftVI |
|
16590 // Note: In inner loop, multiple neg instructions are used, which can be |
|
16591 // moved to outer loop and merge into one neg instruction. |
|
16592 // |
|
16593 // Case 2: The vector shift count is from loading. |
|
16594 // This case isn't supported by middle-end now. But it's supported by |
|
16595 // panama/vectorIntrinsics(JEP 338: Vector API). |
|
16596 // | | |
|
16597 // LoadVector LoadVector |
|
16598 // | / |
|
16599 // RShiftVI |
|
16600 // |
|
16601 |
|
16602 instruct vsra8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
16603 predicate(n->as_Vector()->length() == 4 || |
|
16604 n->as_Vector()->length() == 8); |
|
16605 match(Set dst (RShiftVB src shift)); |
|
16606 ins_cost(INSN_COST); |
|
16607 effect(TEMP tmp); |
|
16608 format %{ "negr $tmp,$shift\t" |
|
16609 "sshl $dst,$src,$tmp\t# vector (8B)" %} |
|
16610 ins_encode %{ |
|
16611 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16612 as_FloatRegister($shift$$reg)); |
|
16613 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
|
16614 as_FloatRegister($src$$reg), |
|
16615 as_FloatRegister($tmp$$reg)); |
|
16616 %} |
|
16617 ins_pipe(vshift64); |
|
16618 %} |
|
16619 |
|
16620 instruct vsra16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
16621 predicate(n->as_Vector()->length() == 16); |
|
16622 match(Set dst (RShiftVB src shift)); |
|
16623 ins_cost(INSN_COST); |
|
16624 effect(TEMP tmp); |
|
16625 format %{ "negr $tmp,$shift\t" |
|
16626 "sshl $dst,$src,$tmp\t# vector (16B)" %} |
|
16627 ins_encode %{ |
|
16628 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16629 as_FloatRegister($shift$$reg)); |
|
16630 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
|
16631 as_FloatRegister($src$$reg), |
|
16632 as_FloatRegister($tmp$$reg)); |
|
16633 %} |
|
16634 ins_pipe(vshift128); |
|
16635 %} |
|
16636 |
|
16637 instruct vsrl8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16578 predicate(n->as_Vector()->length() == 4 || |
16638 predicate(n->as_Vector()->length() == 4 || |
16579 n->as_Vector()->length() == 8); |
16639 n->as_Vector()->length() == 8); |
16580 match(Set dst (URShiftVB src shift)); |
16640 match(Set dst (URShiftVB src shift)); |
16581 ins_cost(INSN_COST); |
16641 ins_cost(INSN_COST); |
16582 format %{ "ushl $dst,$src,$shift\t# vector (8B)" %} |
16642 effect(TEMP tmp); |
16583 ins_encode %{ |
16643 format %{ "negr $tmp,$shift\t" |
|
16644 "ushl $dst,$src,$tmp\t# vector (8B)" %} |
|
16645 ins_encode %{ |
|
16646 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16647 as_FloatRegister($shift$$reg)); |
16584 __ ushl(as_FloatRegister($dst$$reg), __ T8B, |
16648 __ ushl(as_FloatRegister($dst$$reg), __ T8B, |
16585 as_FloatRegister($src$$reg), |
16649 as_FloatRegister($src$$reg), |
16586 as_FloatRegister($shift$$reg)); |
16650 as_FloatRegister($tmp$$reg)); |
16587 %} |
16651 %} |
16588 ins_pipe(vshift64); |
16652 ins_pipe(vshift64); |
16589 %} |
16653 %} |
16590 |
16654 |
16591 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{ |
16655 instruct vsrl16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16592 predicate(n->as_Vector()->length() == 16); |
16656 predicate(n->as_Vector()->length() == 16); |
16593 match(Set dst (URShiftVB src shift)); |
16657 match(Set dst (URShiftVB src shift)); |
16594 ins_cost(INSN_COST); |
16658 ins_cost(INSN_COST); |
16595 format %{ "ushl $dst,$src,$shift\t# vector (16B)" %} |
16659 effect(TEMP tmp); |
16596 ins_encode %{ |
16660 format %{ "negr $tmp,$shift\t" |
|
16661 "ushl $dst,$src,$tmp\t# vector (16B)" %} |
|
16662 ins_encode %{ |
|
16663 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16664 as_FloatRegister($shift$$reg)); |
16597 __ ushl(as_FloatRegister($dst$$reg), __ T16B, |
16665 __ ushl(as_FloatRegister($dst$$reg), __ T16B, |
16598 as_FloatRegister($src$$reg), |
16666 as_FloatRegister($src$$reg), |
16599 as_FloatRegister($shift$$reg)); |
16667 as_FloatRegister($tmp$$reg)); |
16600 %} |
16668 %} |
16601 ins_pipe(vshift128); |
16669 ins_pipe(vshift128); |
16602 %} |
16670 %} |
16603 |
16671 |
16604 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{ |
16672 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{ |
16724 %} |
16791 %} |
16725 |
16792 |
16726 instruct vsll8S(vecX dst, vecX src, vecX shift) %{ |
16793 instruct vsll8S(vecX dst, vecX src, vecX shift) %{ |
16727 predicate(n->as_Vector()->length() == 8); |
16794 predicate(n->as_Vector()->length() == 8); |
16728 match(Set dst (LShiftVS src shift)); |
16795 match(Set dst (LShiftVS src shift)); |
16729 match(Set dst (RShiftVS src shift)); |
|
16730 ins_cost(INSN_COST); |
16796 ins_cost(INSN_COST); |
16731 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %} |
16797 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %} |
16732 ins_encode %{ |
16798 ins_encode %{ |
16733 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
16799 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
16734 as_FloatRegister($src$$reg), |
16800 as_FloatRegister($src$$reg), |
16735 as_FloatRegister($shift$$reg)); |
16801 as_FloatRegister($shift$$reg)); |
16736 %} |
16802 %} |
16737 ins_pipe(vshift128); |
16803 ins_pipe(vshift128); |
16738 %} |
16804 %} |
16739 |
16805 |
16740 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{ |
16806 instruct vsra4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
16807 predicate(n->as_Vector()->length() == 2 || |
|
16808 n->as_Vector()->length() == 4); |
|
16809 match(Set dst (RShiftVS src shift)); |
|
16810 ins_cost(INSN_COST); |
|
16811 effect(TEMP tmp); |
|
16812 format %{ "negr $tmp,$shift\t" |
|
16813 "sshl $dst,$src,$tmp\t# vector (4H)" %} |
|
16814 ins_encode %{ |
|
16815 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16816 as_FloatRegister($shift$$reg)); |
|
16817 __ sshl(as_FloatRegister($dst$$reg), __ T4H, |
|
16818 as_FloatRegister($src$$reg), |
|
16819 as_FloatRegister($tmp$$reg)); |
|
16820 %} |
|
16821 ins_pipe(vshift64); |
|
16822 %} |
|
16823 |
|
16824 instruct vsra8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
16825 predicate(n->as_Vector()->length() == 8); |
|
16826 match(Set dst (RShiftVS src shift)); |
|
16827 ins_cost(INSN_COST); |
|
16828 effect(TEMP tmp); |
|
16829 format %{ "negr $tmp,$shift\t" |
|
16830 "sshl $dst,$src,$tmp\t# vector (8H)" %} |
|
16831 ins_encode %{ |
|
16832 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16833 as_FloatRegister($shift$$reg)); |
|
16834 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
|
16835 as_FloatRegister($src$$reg), |
|
16836 as_FloatRegister($tmp$$reg)); |
|
16837 %} |
|
16838 ins_pipe(vshift128); |
|
16839 %} |
|
16840 |
|
16841 instruct vsrl4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16741 predicate(n->as_Vector()->length() == 2 || |
16842 predicate(n->as_Vector()->length() == 2 || |
16742 n->as_Vector()->length() == 4); |
16843 n->as_Vector()->length() == 4); |
16743 match(Set dst (URShiftVS src shift)); |
16844 match(Set dst (URShiftVS src shift)); |
16744 ins_cost(INSN_COST); |
16845 ins_cost(INSN_COST); |
16745 format %{ "ushl $dst,$src,$shift\t# vector (4H)" %} |
16846 effect(TEMP tmp); |
16746 ins_encode %{ |
16847 format %{ "negr $tmp,$shift\t" |
|
16848 "ushl $dst,$src,$tmp\t# vector (4H)" %} |
|
16849 ins_encode %{ |
|
16850 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16851 as_FloatRegister($shift$$reg)); |
16747 __ ushl(as_FloatRegister($dst$$reg), __ T4H, |
16852 __ ushl(as_FloatRegister($dst$$reg), __ T4H, |
16748 as_FloatRegister($src$$reg), |
16853 as_FloatRegister($src$$reg), |
16749 as_FloatRegister($shift$$reg)); |
16854 as_FloatRegister($tmp$$reg)); |
16750 %} |
16855 %} |
16751 ins_pipe(vshift64); |
16856 ins_pipe(vshift64); |
16752 %} |
16857 %} |
16753 |
16858 |
16754 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{ |
16859 instruct vsrl8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16755 predicate(n->as_Vector()->length() == 8); |
16860 predicate(n->as_Vector()->length() == 8); |
16756 match(Set dst (URShiftVS src shift)); |
16861 match(Set dst (URShiftVS src shift)); |
16757 ins_cost(INSN_COST); |
16862 ins_cost(INSN_COST); |
16758 format %{ "ushl $dst,$src,$shift\t# vector (8H)" %} |
16863 effect(TEMP tmp); |
16759 ins_encode %{ |
16864 format %{ "negr $tmp,$shift\t" |
|
16865 "ushl $dst,$src,$tmp\t# vector (8H)" %} |
|
16866 ins_encode %{ |
|
16867 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16868 as_FloatRegister($shift$$reg)); |
16760 __ ushl(as_FloatRegister($dst$$reg), __ T8H, |
16869 __ ushl(as_FloatRegister($dst$$reg), __ T8H, |
16761 as_FloatRegister($src$$reg), |
16870 as_FloatRegister($src$$reg), |
16762 as_FloatRegister($shift$$reg)); |
16871 as_FloatRegister($tmp$$reg)); |
16763 %} |
16872 %} |
16764 ins_pipe(vshift128); |
16873 ins_pipe(vshift128); |
16765 %} |
16874 %} |
16766 |
16875 |
16767 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{ |
16876 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{ |
16886 %} |
16994 %} |
16887 |
16995 |
16888 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
16996 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
16889 predicate(n->as_Vector()->length() == 4); |
16997 predicate(n->as_Vector()->length() == 4); |
16890 match(Set dst (LShiftVI src shift)); |
16998 match(Set dst (LShiftVI src shift)); |
16891 match(Set dst (RShiftVI src shift)); |
|
16892 ins_cost(INSN_COST); |
16999 ins_cost(INSN_COST); |
16893 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %} |
17000 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %} |
16894 ins_encode %{ |
17001 ins_encode %{ |
16895 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
17002 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
16896 as_FloatRegister($src$$reg), |
17003 as_FloatRegister($src$$reg), |
16897 as_FloatRegister($shift$$reg)); |
17004 as_FloatRegister($shift$$reg)); |
16898 %} |
17005 %} |
16899 ins_pipe(vshift128); |
17006 ins_pipe(vshift128); |
16900 %} |
17007 %} |
16901 |
17008 |
16902 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{ |
17009 instruct vsra2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
17010 predicate(n->as_Vector()->length() == 2); |
|
17011 match(Set dst (RShiftVI src shift)); |
|
17012 ins_cost(INSN_COST); |
|
17013 effect(TEMP tmp); |
|
17014 format %{ "negr $tmp,$shift\t" |
|
17015 "sshl $dst,$src,$tmp\t# vector (2S)" %} |
|
17016 ins_encode %{ |
|
17017 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
17018 as_FloatRegister($shift$$reg)); |
|
17019 __ sshl(as_FloatRegister($dst$$reg), __ T2S, |
|
17020 as_FloatRegister($src$$reg), |
|
17021 as_FloatRegister($tmp$$reg)); |
|
17022 %} |
|
17023 ins_pipe(vshift64); |
|
17024 %} |
|
17025 |
|
17026 instruct vsra4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
17027 predicate(n->as_Vector()->length() == 4); |
|
17028 match(Set dst (RShiftVI src shift)); |
|
17029 ins_cost(INSN_COST); |
|
17030 effect(TEMP tmp); |
|
17031 format %{ "negr $tmp,$shift\t" |
|
17032 "sshl $dst,$src,$tmp\t# vector (4S)" %} |
|
17033 ins_encode %{ |
|
17034 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17035 as_FloatRegister($shift$$reg)); |
|
17036 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
|
17037 as_FloatRegister($src$$reg), |
|
17038 as_FloatRegister($tmp$$reg)); |
|
17039 %} |
|
17040 ins_pipe(vshift128); |
|
17041 %} |
|
17042 |
|
17043 instruct vsrl2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16903 predicate(n->as_Vector()->length() == 2); |
17044 predicate(n->as_Vector()->length() == 2); |
16904 match(Set dst (URShiftVI src shift)); |
17045 match(Set dst (URShiftVI src shift)); |
16905 ins_cost(INSN_COST); |
17046 ins_cost(INSN_COST); |
16906 format %{ "ushl $dst,$src,$shift\t# vector (2S)" %} |
17047 effect(TEMP tmp); |
16907 ins_encode %{ |
17048 format %{ "negr $tmp,$shift\t" |
|
17049 "ushl $dst,$src,$tmp\t# vector (2S)" %} |
|
17050 ins_encode %{ |
|
17051 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
17052 as_FloatRegister($shift$$reg)); |
16908 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
17053 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
16909 as_FloatRegister($src$$reg), |
17054 as_FloatRegister($src$$reg), |
16910 as_FloatRegister($shift$$reg)); |
17055 as_FloatRegister($tmp$$reg)); |
16911 %} |
17056 %} |
16912 ins_pipe(vshift64); |
17057 ins_pipe(vshift64); |
16913 %} |
17058 %} |
16914 |
17059 |
16915 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{ |
17060 instruct vsrl4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16916 predicate(n->as_Vector()->length() == 4); |
17061 predicate(n->as_Vector()->length() == 4); |
16917 match(Set dst (URShiftVI src shift)); |
17062 match(Set dst (URShiftVI src shift)); |
16918 ins_cost(INSN_COST); |
17063 ins_cost(INSN_COST); |
16919 format %{ "ushl $dst,$src,$shift\t# vector (4S)" %} |
17064 effect(TEMP tmp); |
16920 ins_encode %{ |
17065 format %{ "negr $tmp,$shift\t" |
|
17066 "ushl $dst,$src,$tmp\t# vector (4S)" %} |
|
17067 ins_encode %{ |
|
17068 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17069 as_FloatRegister($shift$$reg)); |
16921 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
17070 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
16922 as_FloatRegister($src$$reg), |
17071 as_FloatRegister($src$$reg), |
16923 as_FloatRegister($shift$$reg)); |
17072 as_FloatRegister($tmp$$reg)); |
16924 %} |
17073 %} |
16925 ins_pipe(vshift128); |
17074 ins_pipe(vshift128); |
16926 %} |
17075 %} |
16927 |
17076 |
16928 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
17077 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
17004 %} |
17153 %} |
17005 |
17154 |
17006 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
17155 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
17007 predicate(n->as_Vector()->length() == 2); |
17156 predicate(n->as_Vector()->length() == 2); |
17008 match(Set dst (LShiftVL src shift)); |
17157 match(Set dst (LShiftVL src shift)); |
17009 match(Set dst (RShiftVL src shift)); |
|
17010 ins_cost(INSN_COST); |
17158 ins_cost(INSN_COST); |
17011 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %} |
17159 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %} |
17012 ins_encode %{ |
17160 ins_encode %{ |
17013 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
17161 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
17014 as_FloatRegister($src$$reg), |
17162 as_FloatRegister($src$$reg), |
17015 as_FloatRegister($shift$$reg)); |
17163 as_FloatRegister($shift$$reg)); |
17016 %} |
17164 %} |
17017 ins_pipe(vshift128); |
17165 ins_pipe(vshift128); |
17018 %} |
17166 %} |
17019 |
17167 |
17020 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{ |
17168 instruct vsra2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
17169 predicate(n->as_Vector()->length() == 2); |
|
17170 match(Set dst (RShiftVL src shift)); |
|
17171 ins_cost(INSN_COST); |
|
17172 effect(TEMP tmp); |
|
17173 format %{ "negr $tmp,$shift\t" |
|
17174 "sshl $dst,$src,$tmp\t# vector (2D)" %} |
|
17175 ins_encode %{ |
|
17176 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17177 as_FloatRegister($shift$$reg)); |
|
17178 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
|
17179 as_FloatRegister($src$$reg), |
|
17180 as_FloatRegister($tmp$$reg)); |
|
17181 %} |
|
17182 ins_pipe(vshift128); |
|
17183 %} |
|
17184 |
|
17185 instruct vsrl2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
17021 predicate(n->as_Vector()->length() == 2); |
17186 predicate(n->as_Vector()->length() == 2); |
17022 match(Set dst (URShiftVL src shift)); |
17187 match(Set dst (URShiftVL src shift)); |
17023 ins_cost(INSN_COST); |
17188 ins_cost(INSN_COST); |
17024 format %{ "ushl $dst,$src,$shift\t# vector (2D)" %} |
17189 effect(TEMP tmp); |
17025 ins_encode %{ |
17190 format %{ "negr $tmp,$shift\t" |
|
17191 "ushl $dst,$src,$tmp\t# vector (2D)" %} |
|
17192 ins_encode %{ |
|
17193 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17194 as_FloatRegister($shift$$reg)); |
17026 __ ushl(as_FloatRegister($dst$$reg), __ T2D, |
17195 __ ushl(as_FloatRegister($dst$$reg), __ T2D, |
17027 as_FloatRegister($src$$reg), |
17196 as_FloatRegister($src$$reg), |
17028 as_FloatRegister($shift$$reg)); |
17197 as_FloatRegister($tmp$$reg)); |
17029 %} |
17198 %} |
17030 ins_pipe(vshift128); |
17199 ins_pipe(vshift128); |
17031 %} |
17200 %} |
17032 |
17201 |
17033 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{ |
17202 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{ |