16579 %} |
16584 %} |
16580 ins_pipe(vlogical128); |
16585 ins_pipe(vlogical128); |
16581 %} |
16586 %} |
16582 |
16587 |
16583 // ------------------------------ Shift --------------------------------------- |
16588 // ------------------------------ Shift --------------------------------------- |
16584 |
16589 instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{ |
16585 instruct vshiftcntL(vecX dst, iRegIorL2I cnt) %{ |
16590 predicate(n->as_Vector()->length_in_bytes() == 8); |
16586 match(Set dst (LShiftCntV cnt)); |
16591 match(Set dst (LShiftCntV cnt)); |
16587 format %{ "dup $dst, $cnt\t# shift count (vecX)" %} |
16592 match(Set dst (RShiftCntV cnt)); |
|
16593 format %{ "dup $dst, $cnt\t# shift count vector (8B)" %} |
|
16594 ins_encode %{ |
|
16595 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg)); |
|
16596 %} |
|
16597 ins_pipe(vdup_reg_reg64); |
|
16598 %} |
|
16599 |
|
16600 instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{ |
|
16601 predicate(n->as_Vector()->length_in_bytes() == 16); |
|
16602 match(Set dst (LShiftCntV cnt)); |
|
16603 match(Set dst (RShiftCntV cnt)); |
|
16604 format %{ "dup $dst, $cnt\t# shift count vector (16B)" %} |
16588 ins_encode %{ |
16605 ins_encode %{ |
16589 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
16606 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
16590 %} |
16607 %} |
16591 ins_pipe(vdup_reg_reg128); |
16608 ins_pipe(vdup_reg_reg128); |
16592 %} |
16609 %} |
16593 |
16610 |
16594 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount |
16611 instruct vsll8B(vecD dst, vecD src, vecD shift) %{ |
16595 instruct vshiftcntR(vecX dst, iRegIorL2I cnt) %{ |
|
16596 match(Set dst (RShiftCntV cnt)); |
|
16597 format %{ "dup $dst, $cnt\t# shift count (vecX)\n\tneg $dst, $dst\t T16B" %} |
|
16598 ins_encode %{ |
|
16599 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg)); |
|
16600 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg)); |
|
16601 %} |
|
16602 ins_pipe(vdup_reg_reg128); |
|
16603 %} |
|
16604 |
|
16605 instruct vsll8B(vecD dst, vecD src, vecX shift) %{ |
|
16606 predicate(n->as_Vector()->length() == 4 || |
16612 predicate(n->as_Vector()->length() == 4 || |
16607 n->as_Vector()->length() == 8); |
16613 n->as_Vector()->length() == 8); |
16608 match(Set dst (LShiftVB src shift)); |
16614 match(Set dst (LShiftVB src shift)); |
16609 match(Set dst (RShiftVB src shift)); |
|
16610 ins_cost(INSN_COST); |
16615 ins_cost(INSN_COST); |
16611 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %} |
16616 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %} |
16612 ins_encode %{ |
16617 ins_encode %{ |
16613 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
16618 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
16614 as_FloatRegister($src$$reg), |
16619 as_FloatRegister($src$$reg), |
16618 %} |
16623 %} |
16619 |
16624 |
16620 instruct vsll16B(vecX dst, vecX src, vecX shift) %{ |
16625 instruct vsll16B(vecX dst, vecX src, vecX shift) %{ |
16621 predicate(n->as_Vector()->length() == 16); |
16626 predicate(n->as_Vector()->length() == 16); |
16622 match(Set dst (LShiftVB src shift)); |
16627 match(Set dst (LShiftVB src shift)); |
16623 match(Set dst (RShiftVB src shift)); |
|
16624 ins_cost(INSN_COST); |
16628 ins_cost(INSN_COST); |
16625 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %} |
16629 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %} |
16626 ins_encode %{ |
16630 ins_encode %{ |
16627 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
16631 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
16628 as_FloatRegister($src$$reg), |
16632 as_FloatRegister($src$$reg), |
16629 as_FloatRegister($shift$$reg)); |
16633 as_FloatRegister($shift$$reg)); |
16630 %} |
16634 %} |
16631 ins_pipe(vshift128); |
16635 ins_pipe(vshift128); |
16632 %} |
16636 %} |
16633 |
16637 |
16634 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{ |
16638 // Right shifts with vector shift count on aarch64 SIMD are implemented |
|
16639 // as left shift by negative shift count. |
|
16640 // There are two cases for vector shift count. |
|
16641 // |
|
16642 // Case 1: The vector shift count is from replication. |
|
16643 // | | |
|
16644 // LoadVector RShiftCntV |
|
16645 // | / |
|
16646 // RShiftVI |
|
16647 // Note: In inner loop, multiple neg instructions are used, which can be |
|
16648 // moved to outer loop and merge into one neg instruction. |
|
16649 // |
|
16650 // Case 2: The vector shift count is from loading. |
|
16651 // This case isn't supported by middle-end now. But it's supported by |
|
16652 // panama/vectorIntrinsics(JEP 338: Vector API). |
|
16653 // | | |
|
16654 // LoadVector LoadVector |
|
16655 // | / |
|
16656 // RShiftVI |
|
16657 // |
|
16658 |
|
16659 instruct vsra8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
16660 predicate(n->as_Vector()->length() == 4 || |
|
16661 n->as_Vector()->length() == 8); |
|
16662 match(Set dst (RShiftVB src shift)); |
|
16663 ins_cost(INSN_COST); |
|
16664 effect(TEMP tmp); |
|
16665 format %{ "negr $tmp,$shift\t" |
|
16666 "sshl $dst,$src,$tmp\t# vector (8B)" %} |
|
16667 ins_encode %{ |
|
16668 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16669 as_FloatRegister($shift$$reg)); |
|
16670 __ sshl(as_FloatRegister($dst$$reg), __ T8B, |
|
16671 as_FloatRegister($src$$reg), |
|
16672 as_FloatRegister($tmp$$reg)); |
|
16673 %} |
|
16674 ins_pipe(vshift64); |
|
16675 %} |
|
16676 |
|
16677 instruct vsra16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
16678 predicate(n->as_Vector()->length() == 16); |
|
16679 match(Set dst (RShiftVB src shift)); |
|
16680 ins_cost(INSN_COST); |
|
16681 effect(TEMP tmp); |
|
16682 format %{ "negr $tmp,$shift\t" |
|
16683 "sshl $dst,$src,$tmp\t# vector (16B)" %} |
|
16684 ins_encode %{ |
|
16685 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16686 as_FloatRegister($shift$$reg)); |
|
16687 __ sshl(as_FloatRegister($dst$$reg), __ T16B, |
|
16688 as_FloatRegister($src$$reg), |
|
16689 as_FloatRegister($tmp$$reg)); |
|
16690 %} |
|
16691 ins_pipe(vshift128); |
|
16692 %} |
|
16693 |
|
16694 instruct vsrl8B(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16635 predicate(n->as_Vector()->length() == 4 || |
16695 predicate(n->as_Vector()->length() == 4 || |
16636 n->as_Vector()->length() == 8); |
16696 n->as_Vector()->length() == 8); |
16637 match(Set dst (URShiftVB src shift)); |
16697 match(Set dst (URShiftVB src shift)); |
16638 ins_cost(INSN_COST); |
16698 ins_cost(INSN_COST); |
16639 format %{ "ushl $dst,$src,$shift\t# vector (8B)" %} |
16699 effect(TEMP tmp); |
16640 ins_encode %{ |
16700 format %{ "negr $tmp,$shift\t" |
|
16701 "ushl $dst,$src,$tmp\t# vector (8B)" %} |
|
16702 ins_encode %{ |
|
16703 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16704 as_FloatRegister($shift$$reg)); |
16641 __ ushl(as_FloatRegister($dst$$reg), __ T8B, |
16705 __ ushl(as_FloatRegister($dst$$reg), __ T8B, |
16642 as_FloatRegister($src$$reg), |
16706 as_FloatRegister($src$$reg), |
16643 as_FloatRegister($shift$$reg)); |
16707 as_FloatRegister($tmp$$reg)); |
16644 %} |
16708 %} |
16645 ins_pipe(vshift64); |
16709 ins_pipe(vshift64); |
16646 %} |
16710 %} |
16647 |
16711 |
16648 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{ |
16712 instruct vsrl16B(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16649 predicate(n->as_Vector()->length() == 16); |
16713 predicate(n->as_Vector()->length() == 16); |
16650 match(Set dst (URShiftVB src shift)); |
16714 match(Set dst (URShiftVB src shift)); |
16651 ins_cost(INSN_COST); |
16715 ins_cost(INSN_COST); |
16652 format %{ "ushl $dst,$src,$shift\t# vector (16B)" %} |
16716 effect(TEMP tmp); |
16653 ins_encode %{ |
16717 format %{ "negr $tmp,$shift\t" |
|
16718 "ushl $dst,$src,$tmp\t# vector (16B)" %} |
|
16719 ins_encode %{ |
|
16720 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16721 as_FloatRegister($shift$$reg)); |
16654 __ ushl(as_FloatRegister($dst$$reg), __ T16B, |
16722 __ ushl(as_FloatRegister($dst$$reg), __ T16B, |
16655 as_FloatRegister($src$$reg), |
16723 as_FloatRegister($src$$reg), |
16656 as_FloatRegister($shift$$reg)); |
16724 as_FloatRegister($tmp$$reg)); |
16657 %} |
16725 %} |
16658 ins_pipe(vshift128); |
16726 ins_pipe(vshift128); |
16659 %} |
16727 %} |
16660 |
16728 |
16661 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{ |
16729 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{ |
16781 %} |
16848 %} |
16782 |
16849 |
16783 instruct vsll8S(vecX dst, vecX src, vecX shift) %{ |
16850 instruct vsll8S(vecX dst, vecX src, vecX shift) %{ |
16784 predicate(n->as_Vector()->length() == 8); |
16851 predicate(n->as_Vector()->length() == 8); |
16785 match(Set dst (LShiftVS src shift)); |
16852 match(Set dst (LShiftVS src shift)); |
16786 match(Set dst (RShiftVS src shift)); |
|
16787 ins_cost(INSN_COST); |
16853 ins_cost(INSN_COST); |
16788 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %} |
16854 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %} |
16789 ins_encode %{ |
16855 ins_encode %{ |
16790 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
16856 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
16791 as_FloatRegister($src$$reg), |
16857 as_FloatRegister($src$$reg), |
16792 as_FloatRegister($shift$$reg)); |
16858 as_FloatRegister($shift$$reg)); |
16793 %} |
16859 %} |
16794 ins_pipe(vshift128); |
16860 ins_pipe(vshift128); |
16795 %} |
16861 %} |
16796 |
16862 |
16797 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{ |
16863 instruct vsra4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
16864 predicate(n->as_Vector()->length() == 2 || |
|
16865 n->as_Vector()->length() == 4); |
|
16866 match(Set dst (RShiftVS src shift)); |
|
16867 ins_cost(INSN_COST); |
|
16868 effect(TEMP tmp); |
|
16869 format %{ "negr $tmp,$shift\t" |
|
16870 "sshl $dst,$src,$tmp\t# vector (4H)" %} |
|
16871 ins_encode %{ |
|
16872 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16873 as_FloatRegister($shift$$reg)); |
|
16874 __ sshl(as_FloatRegister($dst$$reg), __ T4H, |
|
16875 as_FloatRegister($src$$reg), |
|
16876 as_FloatRegister($tmp$$reg)); |
|
16877 %} |
|
16878 ins_pipe(vshift64); |
|
16879 %} |
|
16880 |
|
16881 instruct vsra8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
16882 predicate(n->as_Vector()->length() == 8); |
|
16883 match(Set dst (RShiftVS src shift)); |
|
16884 ins_cost(INSN_COST); |
|
16885 effect(TEMP tmp); |
|
16886 format %{ "negr $tmp,$shift\t" |
|
16887 "sshl $dst,$src,$tmp\t# vector (8H)" %} |
|
16888 ins_encode %{ |
|
16889 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16890 as_FloatRegister($shift$$reg)); |
|
16891 __ sshl(as_FloatRegister($dst$$reg), __ T8H, |
|
16892 as_FloatRegister($src$$reg), |
|
16893 as_FloatRegister($tmp$$reg)); |
|
16894 %} |
|
16895 ins_pipe(vshift128); |
|
16896 %} |
|
16897 |
|
16898 instruct vsrl4S(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16798 predicate(n->as_Vector()->length() == 2 || |
16899 predicate(n->as_Vector()->length() == 2 || |
16799 n->as_Vector()->length() == 4); |
16900 n->as_Vector()->length() == 4); |
16800 match(Set dst (URShiftVS src shift)); |
16901 match(Set dst (URShiftVS src shift)); |
16801 ins_cost(INSN_COST); |
16902 ins_cost(INSN_COST); |
16802 format %{ "ushl $dst,$src,$shift\t# vector (4H)" %} |
16903 effect(TEMP tmp); |
16803 ins_encode %{ |
16904 format %{ "negr $tmp,$shift\t" |
|
16905 "ushl $dst,$src,$tmp\t# vector (4H)" %} |
|
16906 ins_encode %{ |
|
16907 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
16908 as_FloatRegister($shift$$reg)); |
16804 __ ushl(as_FloatRegister($dst$$reg), __ T4H, |
16909 __ ushl(as_FloatRegister($dst$$reg), __ T4H, |
16805 as_FloatRegister($src$$reg), |
16910 as_FloatRegister($src$$reg), |
16806 as_FloatRegister($shift$$reg)); |
16911 as_FloatRegister($tmp$$reg)); |
16807 %} |
16912 %} |
16808 ins_pipe(vshift64); |
16913 ins_pipe(vshift64); |
16809 %} |
16914 %} |
16810 |
16915 |
16811 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{ |
16916 instruct vsrl8S(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16812 predicate(n->as_Vector()->length() == 8); |
16917 predicate(n->as_Vector()->length() == 8); |
16813 match(Set dst (URShiftVS src shift)); |
16918 match(Set dst (URShiftVS src shift)); |
16814 ins_cost(INSN_COST); |
16919 ins_cost(INSN_COST); |
16815 format %{ "ushl $dst,$src,$shift\t# vector (8H)" %} |
16920 effect(TEMP tmp); |
16816 ins_encode %{ |
16921 format %{ "negr $tmp,$shift\t" |
|
16922 "ushl $dst,$src,$tmp\t# vector (8H)" %} |
|
16923 ins_encode %{ |
|
16924 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
16925 as_FloatRegister($shift$$reg)); |
16817 __ ushl(as_FloatRegister($dst$$reg), __ T8H, |
16926 __ ushl(as_FloatRegister($dst$$reg), __ T8H, |
16818 as_FloatRegister($src$$reg), |
16927 as_FloatRegister($src$$reg), |
16819 as_FloatRegister($shift$$reg)); |
16928 as_FloatRegister($tmp$$reg)); |
16820 %} |
16929 %} |
16821 ins_pipe(vshift128); |
16930 ins_pipe(vshift128); |
16822 %} |
16931 %} |
16823 |
16932 |
16824 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{ |
16933 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{ |
16943 %} |
17051 %} |
16944 |
17052 |
16945 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
17053 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
16946 predicate(n->as_Vector()->length() == 4); |
17054 predicate(n->as_Vector()->length() == 4); |
16947 match(Set dst (LShiftVI src shift)); |
17055 match(Set dst (LShiftVI src shift)); |
16948 match(Set dst (RShiftVI src shift)); |
|
16949 ins_cost(INSN_COST); |
17056 ins_cost(INSN_COST); |
16950 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %} |
17057 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %} |
16951 ins_encode %{ |
17058 ins_encode %{ |
16952 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
17059 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
16953 as_FloatRegister($src$$reg), |
17060 as_FloatRegister($src$$reg), |
16954 as_FloatRegister($shift$$reg)); |
17061 as_FloatRegister($shift$$reg)); |
16955 %} |
17062 %} |
16956 ins_pipe(vshift128); |
17063 ins_pipe(vshift128); |
16957 %} |
17064 %} |
16958 |
17065 |
16959 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{ |
17066 instruct vsra2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
|
17067 predicate(n->as_Vector()->length() == 2); |
|
17068 match(Set dst (RShiftVI src shift)); |
|
17069 ins_cost(INSN_COST); |
|
17070 effect(TEMP tmp); |
|
17071 format %{ "negr $tmp,$shift\t" |
|
17072 "sshl $dst,$src,$tmp\t# vector (2S)" %} |
|
17073 ins_encode %{ |
|
17074 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
17075 as_FloatRegister($shift$$reg)); |
|
17076 __ sshl(as_FloatRegister($dst$$reg), __ T2S, |
|
17077 as_FloatRegister($src$$reg), |
|
17078 as_FloatRegister($tmp$$reg)); |
|
17079 %} |
|
17080 ins_pipe(vshift64); |
|
17081 %} |
|
17082 |
|
17083 instruct vsra4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
17084 predicate(n->as_Vector()->length() == 4); |
|
17085 match(Set dst (RShiftVI src shift)); |
|
17086 ins_cost(INSN_COST); |
|
17087 effect(TEMP tmp); |
|
17088 format %{ "negr $tmp,$shift\t" |
|
17089 "sshl $dst,$src,$tmp\t# vector (4S)" %} |
|
17090 ins_encode %{ |
|
17091 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17092 as_FloatRegister($shift$$reg)); |
|
17093 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
|
17094 as_FloatRegister($src$$reg), |
|
17095 as_FloatRegister($tmp$$reg)); |
|
17096 %} |
|
17097 ins_pipe(vshift128); |
|
17098 %} |
|
17099 |
|
17100 instruct vsrl2I(vecD dst, vecD src, vecD shift, vecD tmp) %{ |
16960 predicate(n->as_Vector()->length() == 2); |
17101 predicate(n->as_Vector()->length() == 2); |
16961 match(Set dst (URShiftVI src shift)); |
17102 match(Set dst (URShiftVI src shift)); |
16962 ins_cost(INSN_COST); |
17103 ins_cost(INSN_COST); |
16963 format %{ "ushl $dst,$src,$shift\t# vector (2S)" %} |
17104 effect(TEMP tmp); |
16964 ins_encode %{ |
17105 format %{ "negr $tmp,$shift\t" |
|
17106 "ushl $dst,$src,$tmp\t# vector (2S)" %} |
|
17107 ins_encode %{ |
|
17108 __ negr(as_FloatRegister($tmp$$reg), __ T8B, |
|
17109 as_FloatRegister($shift$$reg)); |
16965 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
17110 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
16966 as_FloatRegister($src$$reg), |
17111 as_FloatRegister($src$$reg), |
16967 as_FloatRegister($shift$$reg)); |
17112 as_FloatRegister($tmp$$reg)); |
16968 %} |
17113 %} |
16969 ins_pipe(vshift64); |
17114 ins_pipe(vshift64); |
16970 %} |
17115 %} |
16971 |
17116 |
16972 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{ |
17117 instruct vsrl4I(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
16973 predicate(n->as_Vector()->length() == 4); |
17118 predicate(n->as_Vector()->length() == 4); |
16974 match(Set dst (URShiftVI src shift)); |
17119 match(Set dst (URShiftVI src shift)); |
16975 ins_cost(INSN_COST); |
17120 ins_cost(INSN_COST); |
16976 format %{ "ushl $dst,$src,$shift\t# vector (4S)" %} |
17121 effect(TEMP tmp); |
16977 ins_encode %{ |
17122 format %{ "negr $tmp,$shift\t" |
|
17123 "ushl $dst,$src,$tmp\t# vector (4S)" %} |
|
17124 ins_encode %{ |
|
17125 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17126 as_FloatRegister($shift$$reg)); |
16978 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
17127 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
16979 as_FloatRegister($src$$reg), |
17128 as_FloatRegister($src$$reg), |
16980 as_FloatRegister($shift$$reg)); |
17129 as_FloatRegister($tmp$$reg)); |
16981 %} |
17130 %} |
16982 ins_pipe(vshift128); |
17131 ins_pipe(vshift128); |
16983 %} |
17132 %} |
16984 |
17133 |
16985 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
17134 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
17061 %} |
17210 %} |
17062 |
17211 |
17063 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
17212 instruct vsll2L(vecX dst, vecX src, vecX shift) %{ |
17064 predicate(n->as_Vector()->length() == 2); |
17213 predicate(n->as_Vector()->length() == 2); |
17065 match(Set dst (LShiftVL src shift)); |
17214 match(Set dst (LShiftVL src shift)); |
17066 match(Set dst (RShiftVL src shift)); |
|
17067 ins_cost(INSN_COST); |
17215 ins_cost(INSN_COST); |
17068 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %} |
17216 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %} |
17069 ins_encode %{ |
17217 ins_encode %{ |
17070 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
17218 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
17071 as_FloatRegister($src$$reg), |
17219 as_FloatRegister($src$$reg), |
17072 as_FloatRegister($shift$$reg)); |
17220 as_FloatRegister($shift$$reg)); |
17073 %} |
17221 %} |
17074 ins_pipe(vshift128); |
17222 ins_pipe(vshift128); |
17075 %} |
17223 %} |
17076 |
17224 |
17077 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{ |
17225 instruct vsra2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
|
17226 predicate(n->as_Vector()->length() == 2); |
|
17227 match(Set dst (RShiftVL src shift)); |
|
17228 ins_cost(INSN_COST); |
|
17229 effect(TEMP tmp); |
|
17230 format %{ "negr $tmp,$shift\t" |
|
17231 "sshl $dst,$src,$tmp\t# vector (2D)" %} |
|
17232 ins_encode %{ |
|
17233 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17234 as_FloatRegister($shift$$reg)); |
|
17235 __ sshl(as_FloatRegister($dst$$reg), __ T2D, |
|
17236 as_FloatRegister($src$$reg), |
|
17237 as_FloatRegister($tmp$$reg)); |
|
17238 %} |
|
17239 ins_pipe(vshift128); |
|
17240 %} |
|
17241 |
|
17242 instruct vsrl2L(vecX dst, vecX src, vecX shift, vecX tmp) %{ |
17078 predicate(n->as_Vector()->length() == 2); |
17243 predicate(n->as_Vector()->length() == 2); |
17079 match(Set dst (URShiftVL src shift)); |
17244 match(Set dst (URShiftVL src shift)); |
17080 ins_cost(INSN_COST); |
17245 ins_cost(INSN_COST); |
17081 format %{ "ushl $dst,$src,$shift\t# vector (2D)" %} |
17246 effect(TEMP tmp); |
17082 ins_encode %{ |
17247 format %{ "negr $tmp,$shift\t" |
|
17248 "ushl $dst,$src,$tmp\t# vector (2D)" %} |
|
17249 ins_encode %{ |
|
17250 __ negr(as_FloatRegister($tmp$$reg), __ T16B, |
|
17251 as_FloatRegister($shift$$reg)); |
17083 __ ushl(as_FloatRegister($dst$$reg), __ T2D, |
17252 __ ushl(as_FloatRegister($dst$$reg), __ T2D, |
17084 as_FloatRegister($src$$reg), |
17253 as_FloatRegister($src$$reg), |
17085 as_FloatRegister($shift$$reg)); |
17254 as_FloatRegister($tmp$$reg)); |
17086 %} |
17255 %} |
17087 ins_pipe(vshift128); |
17256 ins_pipe(vshift128); |
17088 %} |
17257 %} |
17089 |
17258 |
17090 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{ |
17259 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{ |