author | mbaesken |
Thu, 26 Sep 2019 14:04:25 +0200 | |
changeset 58356 | feff88c68082 |
parent 47216 | 71c04702a3d5 |
permissions | -rw-r--r-- |
42065 | 1 |
/* |
58356
feff88c68082
8231448: s390 and ppc - replace JVM type comparisons to T_OBJECT and T_ARRAY with call to is_reference_type
mbaesken
parents:
47216
diff
changeset
|
2 |
* Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. |
feff88c68082
8231448: s390 and ppc - replace JVM type comparisons to T_OBJECT and T_ARRAY with call to is_reference_type
mbaesken
parents:
47216
diff
changeset
|
3 |
* Copyright (c) 2016, 2019, SAP SE. All rights reserved. |
42065 | 4 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
5 |
* |
|
6 |
* This code is free software; you can redistribute it and/or modify it |
|
7 |
* under the terms of the GNU General Public License version 2 only, as |
|
8 |
* published by the Free Software Foundation. |
|
9 |
* |
|
10 |
* This code is distributed in the hope that it will be useful, but WITHOUT |
|
11 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
12 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
13 |
* version 2 for more details (a copy is included in the LICENSE file that |
|
14 |
* accompanied this code). |
|
15 |
* |
|
16 |
* You should have received a copy of the GNU General Public License version |
|
17 |
* 2 along with this work; if not, write to the Free Software Foundation, |
|
18 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
19 |
* |
|
20 |
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
21 |
* or visit www.oracle.com if you need additional information or have any |
|
22 |
* questions. |
|
23 |
* |
|
24 |
*/ |
|
25 |
||
26 |
#include "precompiled.hpp" |
|
27 |
#include "c1/c1_FrameMap.hpp" |
|
28 |
#include "c1/c1_LIR.hpp" |
|
29 |
#include "runtime/sharedRuntime.hpp" |
|
30 |
#include "vmreg_s390.inline.hpp" |
|
31 |
||
32 |
||
33 |
const int FrameMap::pd_c_runtime_reserved_arg_size = 7; |
|
34 |
||
35 |
LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { |
|
36 |
LIR_Opr opr = LIR_OprFact::illegalOpr; |
|
37 |
VMReg r_1 = reg->first(); |
|
38 |
VMReg r_2 = reg->second(); |
|
39 |
if (r_1->is_stack()) { |
|
40 |
// Convert stack slot to an SP offset. |
|
41 |
// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value |
|
42 |
// so we must add it in here. |
|
43 |
int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; |
|
44 |
opr = LIR_OprFact::address(new LIR_Address(Z_SP_opr, st_off, type)); |
|
45 |
} else if (r_1->is_Register()) { |
|
46 |
Register reg = r_1->as_Register(); |
|
47 |
if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
|
48 |
opr = as_long_opr(reg); |
|
58356
feff88c68082
8231448: s390 and ppc - replace JVM type comparisons to T_OBJECT and T_ARRAY with call to is_reference_type
mbaesken
parents:
47216
diff
changeset
|
49 |
} else if (is_reference_type(type)) { |
42065 | 50 |
opr = as_oop_opr(reg); |
51 |
} else if (type == T_METADATA) { |
|
52 |
opr = as_metadata_opr(reg); |
|
53 |
} else { |
|
54 |
opr = as_opr(reg); |
|
55 |
} |
|
56 |
} else if (r_1->is_FloatRegister()) { |
|
57 |
assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); |
|
58 |
FloatRegister f = r_1->as_FloatRegister(); |
|
59 |
if (type == T_FLOAT) { |
|
60 |
opr = as_float_opr(f); |
|
61 |
} else { |
|
62 |
opr = as_double_opr(f); |
|
63 |
} |
|
64 |
} else { |
|
65 |
ShouldNotReachHere(); |
|
66 |
} |
|
67 |
return opr; |
|
68 |
} |
|
69 |
||
70 |
// FrameMap |
|
71 |
//-------------------------------------------------------- |
|
72 |
||
73 |
FloatRegister FrameMap::_fpu_rnr2reg [FrameMap::nof_fpu_regs]; // mapping c1 regnr. -> FloatRegister |
|
74 |
int FrameMap::_fpu_reg2rnr [FrameMap::nof_fpu_regs]; // mapping assembler encoding -> c1 regnr. |
|
75 |
||
76 |
// Some useful constant RInfo's: |
|
77 |
LIR_Opr FrameMap::Z_R0_opr; |
|
78 |
LIR_Opr FrameMap::Z_R1_opr; |
|
79 |
LIR_Opr FrameMap::Z_R2_opr; |
|
80 |
LIR_Opr FrameMap::Z_R3_opr; |
|
81 |
LIR_Opr FrameMap::Z_R4_opr; |
|
82 |
LIR_Opr FrameMap::Z_R5_opr; |
|
83 |
LIR_Opr FrameMap::Z_R6_opr; |
|
84 |
LIR_Opr FrameMap::Z_R7_opr; |
|
85 |
LIR_Opr FrameMap::Z_R8_opr; |
|
86 |
LIR_Opr FrameMap::Z_R9_opr; |
|
87 |
LIR_Opr FrameMap::Z_R10_opr; |
|
88 |
LIR_Opr FrameMap::Z_R11_opr; |
|
89 |
LIR_Opr FrameMap::Z_R12_opr; |
|
90 |
LIR_Opr FrameMap::Z_R13_opr; |
|
91 |
LIR_Opr FrameMap::Z_R14_opr; |
|
92 |
LIR_Opr FrameMap::Z_R15_opr; |
|
93 |
||
94 |
LIR_Opr FrameMap::Z_R0_oop_opr; |
|
95 |
LIR_Opr FrameMap::Z_R1_oop_opr; |
|
96 |
LIR_Opr FrameMap::Z_R2_oop_opr; |
|
97 |
LIR_Opr FrameMap::Z_R3_oop_opr; |
|
98 |
LIR_Opr FrameMap::Z_R4_oop_opr; |
|
99 |
LIR_Opr FrameMap::Z_R5_oop_opr; |
|
100 |
LIR_Opr FrameMap::Z_R6_oop_opr; |
|
101 |
LIR_Opr FrameMap::Z_R7_oop_opr; |
|
102 |
LIR_Opr FrameMap::Z_R8_oop_opr; |
|
103 |
LIR_Opr FrameMap::Z_R9_oop_opr; |
|
104 |
LIR_Opr FrameMap::Z_R10_oop_opr; |
|
105 |
LIR_Opr FrameMap::Z_R11_oop_opr; |
|
106 |
LIR_Opr FrameMap::Z_R12_oop_opr; |
|
107 |
LIR_Opr FrameMap::Z_R13_oop_opr; |
|
108 |
LIR_Opr FrameMap::Z_R14_oop_opr; |
|
109 |
LIR_Opr FrameMap::Z_R15_oop_opr; |
|
110 |
||
111 |
LIR_Opr FrameMap::Z_R0_metadata_opr; |
|
112 |
LIR_Opr FrameMap::Z_R1_metadata_opr; |
|
113 |
LIR_Opr FrameMap::Z_R2_metadata_opr; |
|
114 |
LIR_Opr FrameMap::Z_R3_metadata_opr; |
|
115 |
LIR_Opr FrameMap::Z_R4_metadata_opr; |
|
116 |
LIR_Opr FrameMap::Z_R5_metadata_opr; |
|
117 |
LIR_Opr FrameMap::Z_R6_metadata_opr; |
|
118 |
LIR_Opr FrameMap::Z_R7_metadata_opr; |
|
119 |
LIR_Opr FrameMap::Z_R8_metadata_opr; |
|
120 |
LIR_Opr FrameMap::Z_R9_metadata_opr; |
|
121 |
LIR_Opr FrameMap::Z_R10_metadata_opr; |
|
122 |
LIR_Opr FrameMap::Z_R11_metadata_opr; |
|
123 |
LIR_Opr FrameMap::Z_R12_metadata_opr; |
|
124 |
LIR_Opr FrameMap::Z_R13_metadata_opr; |
|
125 |
LIR_Opr FrameMap::Z_R14_metadata_opr; |
|
126 |
LIR_Opr FrameMap::Z_R15_metadata_opr; |
|
127 |
||
128 |
LIR_Opr FrameMap::Z_SP_opr; |
|
129 |
LIR_Opr FrameMap::Z_FP_opr; |
|
130 |
||
131 |
LIR_Opr FrameMap::Z_R2_long_opr; |
|
132 |
LIR_Opr FrameMap::Z_R10_long_opr; |
|
133 |
LIR_Opr FrameMap::Z_R11_long_opr; |
|
134 |
||
135 |
LIR_Opr FrameMap::Z_F0_opr; |
|
136 |
LIR_Opr FrameMap::Z_F0_double_opr; |
|
137 |
||
138 |
||
139 |
LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
|
140 |
LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; |
|
141 |
||
142 |
||
143 |
// c1 rnr -> FloatRegister |
|
144 |
FloatRegister FrameMap::nr2floatreg (int rnr) { |
|
145 |
assert(_init_done, "tables not initialized"); |
|
146 |
debug_only(fpu_range_check(rnr);) |
|
147 |
return _fpu_rnr2reg[rnr]; |
|
148 |
} |
|
149 |
||
150 |
void FrameMap::map_float_register(int rnr, FloatRegister reg) { |
|
151 |
debug_only(fpu_range_check(rnr);) |
|
152 |
debug_only(fpu_range_check(reg->encoding());) |
|
153 |
_fpu_rnr2reg[rnr] = reg; // mapping c1 regnr. -> FloatRegister |
|
154 |
_fpu_reg2rnr[reg->encoding()] = rnr; // mapping assembler encoding -> c1 regnr. |
|
155 |
} |
|
156 |
||
157 |
void FrameMap::initialize() { |
|
158 |
assert(!_init_done, "once"); |
|
159 |
||
160 |
DEBUG_ONLY(int allocated = 0;) |
|
161 |
DEBUG_ONLY(int unallocated = 0;) |
|
162 |
||
163 |
// Register usage: |
|
164 |
// Z_thread (Z_R8) |
|
165 |
// Z_fp (Z_R9) |
|
166 |
// Z_SP (Z_R15) |
|
167 |
DEBUG_ONLY(allocated++); map_register(0, Z_R2); |
|
168 |
DEBUG_ONLY(allocated++); map_register(1, Z_R3); |
|
169 |
DEBUG_ONLY(allocated++); map_register(2, Z_R4); |
|
170 |
DEBUG_ONLY(allocated++); map_register(3, Z_R5); |
|
171 |
DEBUG_ONLY(allocated++); map_register(4, Z_R6); |
|
172 |
DEBUG_ONLY(allocated++); map_register(5, Z_R7); |
|
173 |
DEBUG_ONLY(allocated++); map_register(6, Z_R10); |
|
174 |
DEBUG_ONLY(allocated++); map_register(7, Z_R11); |
|
175 |
DEBUG_ONLY(allocated++); map_register(8, Z_R12); |
|
176 |
DEBUG_ONLY(allocated++); map_register(9, Z_R13); // <- last register visible in RegAlloc |
|
177 |
DEBUG_ONLY(unallocated++); map_register(11, Z_R0); // Z_R0_scratch |
|
178 |
DEBUG_ONLY(unallocated++); map_register(12, Z_R1); // Z_R1_scratch |
|
179 |
DEBUG_ONLY(unallocated++); map_register(10, Z_R14); // return pc; TODO: Try to let c1/c2 allocate R14. |
|
180 |
||
181 |
// The following registers are usually unavailable. |
|
182 |
DEBUG_ONLY(unallocated++); map_register(13, Z_R8); |
|
183 |
DEBUG_ONLY(unallocated++); map_register(14, Z_R9); |
|
184 |
DEBUG_ONLY(unallocated++); map_register(15, Z_R15); |
|
185 |
assert(allocated-1 == pd_last_cpu_reg, "wrong number/mapping of allocated CPU registers"); |
|
186 |
assert(unallocated == pd_nof_cpu_regs_unallocated, "wrong number of unallocated CPU registers"); |
|
187 |
assert(nof_cpu_regs == allocated+unallocated, "wrong number of CPU registers"); |
|
188 |
||
189 |
int j = 0; |
|
190 |
for (int i = 0; i < nof_fpu_regs; i++) { |
|
191 |
if (as_FloatRegister(i) == Z_fscratch_1) continue; // unallocated |
|
192 |
map_float_register(j++, as_FloatRegister(i)); |
|
193 |
} |
|
194 |
assert(j == nof_fpu_regs-1, "missed one fpu reg?"); |
|
195 |
map_float_register(j++, Z_fscratch_1); |
|
196 |
||
197 |
_init_done = true; |
|
198 |
||
199 |
Z_R0_opr = as_opr(Z_R0); |
|
200 |
Z_R1_opr = as_opr(Z_R1); |
|
201 |
Z_R2_opr = as_opr(Z_R2); |
|
202 |
Z_R3_opr = as_opr(Z_R3); |
|
203 |
Z_R4_opr = as_opr(Z_R4); |
|
204 |
Z_R5_opr = as_opr(Z_R5); |
|
205 |
Z_R6_opr = as_opr(Z_R6); |
|
206 |
Z_R7_opr = as_opr(Z_R7); |
|
207 |
Z_R8_opr = as_opr(Z_R8); |
|
208 |
Z_R9_opr = as_opr(Z_R9); |
|
209 |
Z_R10_opr = as_opr(Z_R10); |
|
210 |
Z_R11_opr = as_opr(Z_R11); |
|
211 |
Z_R12_opr = as_opr(Z_R12); |
|
212 |
Z_R13_opr = as_opr(Z_R13); |
|
213 |
Z_R14_opr = as_opr(Z_R14); |
|
214 |
Z_R15_opr = as_opr(Z_R15); |
|
215 |
||
216 |
Z_R0_oop_opr = as_oop_opr(Z_R0); |
|
217 |
Z_R1_oop_opr = as_oop_opr(Z_R1); |
|
218 |
Z_R2_oop_opr = as_oop_opr(Z_R2); |
|
219 |
Z_R3_oop_opr = as_oop_opr(Z_R3); |
|
220 |
Z_R4_oop_opr = as_oop_opr(Z_R4); |
|
221 |
Z_R5_oop_opr = as_oop_opr(Z_R5); |
|
222 |
Z_R6_oop_opr = as_oop_opr(Z_R6); |
|
223 |
Z_R7_oop_opr = as_oop_opr(Z_R7); |
|
224 |
Z_R8_oop_opr = as_oop_opr(Z_R8); |
|
225 |
Z_R9_oop_opr = as_oop_opr(Z_R9); |
|
226 |
Z_R10_oop_opr = as_oop_opr(Z_R10); |
|
227 |
Z_R11_oop_opr = as_oop_opr(Z_R11); |
|
228 |
Z_R12_oop_opr = as_oop_opr(Z_R12); |
|
229 |
Z_R13_oop_opr = as_oop_opr(Z_R13); |
|
230 |
Z_R14_oop_opr = as_oop_opr(Z_R14); |
|
231 |
Z_R15_oop_opr = as_oop_opr(Z_R15); |
|
232 |
||
233 |
Z_R0_metadata_opr = as_metadata_opr(Z_R0); |
|
234 |
Z_R1_metadata_opr = as_metadata_opr(Z_R1); |
|
235 |
Z_R2_metadata_opr = as_metadata_opr(Z_R2); |
|
236 |
Z_R3_metadata_opr = as_metadata_opr(Z_R3); |
|
237 |
Z_R4_metadata_opr = as_metadata_opr(Z_R4); |
|
238 |
Z_R5_metadata_opr = as_metadata_opr(Z_R5); |
|
239 |
Z_R6_metadata_opr = as_metadata_opr(Z_R6); |
|
240 |
Z_R7_metadata_opr = as_metadata_opr(Z_R7); |
|
241 |
Z_R8_metadata_opr = as_metadata_opr(Z_R8); |
|
242 |
Z_R9_metadata_opr = as_metadata_opr(Z_R9); |
|
243 |
Z_R10_metadata_opr = as_metadata_opr(Z_R10); |
|
244 |
Z_R11_metadata_opr = as_metadata_opr(Z_R11); |
|
245 |
Z_R12_metadata_opr = as_metadata_opr(Z_R12); |
|
246 |
Z_R13_metadata_opr = as_metadata_opr(Z_R13); |
|
247 |
Z_R14_metadata_opr = as_metadata_opr(Z_R14); |
|
248 |
Z_R15_metadata_opr = as_metadata_opr(Z_R15); |
|
249 |
||
250 |
// TODO: needed? Or can we make Z_R9 available for linear scan allocation. |
|
251 |
Z_FP_opr = as_pointer_opr(Z_fp); |
|
252 |
Z_SP_opr = as_pointer_opr(Z_SP); |
|
253 |
||
254 |
Z_R2_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R2), cpu_reg2rnr(Z_R2)); |
|
255 |
Z_R10_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R10), cpu_reg2rnr(Z_R10)); |
|
256 |
Z_R11_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R11), cpu_reg2rnr(Z_R11)); |
|
257 |
||
258 |
Z_F0_opr = as_float_opr(Z_F0); |
|
259 |
Z_F0_double_opr = as_double_opr(Z_F0); |
|
260 |
||
261 |
// All allocated cpu regs are caller saved. |
|
262 |
for (int c1rnr = 0; c1rnr < max_nof_caller_save_cpu_regs; c1rnr++) { |
|
263 |
_caller_save_cpu_regs[c1rnr] = as_opr(cpu_rnr2reg(c1rnr)); |
|
264 |
} |
|
265 |
||
266 |
// All allocated fpu regs are caller saved. |
|
267 |
for (int c1rnr = 0; c1rnr < nof_caller_save_fpu_regs; c1rnr++) { |
|
268 |
_caller_save_fpu_regs[c1rnr] = as_float_opr(nr2floatreg(c1rnr)); |
|
269 |
} |
|
270 |
} |
|
271 |
||
272 |
Address FrameMap::make_new_address(ByteSize sp_offset) const { |
|
273 |
return Address(Z_SP, sp_offset); |
|
274 |
} |
|
275 |
||
276 |
VMReg FrameMap::fpu_regname (int n) { |
|
277 |
return nr2floatreg(n)->as_VMReg(); |
|
278 |
} |
|
279 |
||
280 |
LIR_Opr FrameMap::stack_pointer() { |
|
281 |
return Z_SP_opr; |
|
282 |
} |
|
283 |
||
284 |
// JSR 292 |
|
285 |
// On ZARCH_64, there is no need to save the SP, because neither |
|
286 |
// method handle intrinsics nor compiled lambda forms modify it. |
|
287 |
LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { |
|
288 |
return LIR_OprFact::illegalOpr; |
|
289 |
} |
|
290 |
||
291 |
bool FrameMap::validate_frame() { |
|
292 |
return true; |
|
293 |
} |