/*

 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.

 * Copyright 2012, 2015 SAP AG. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "compiler/disassembler.hpp"

#include "gc/shared/cardTableModRefBS.hpp"

#include "gc/shared/collectedHeap.inline.hpp"

#include "interpreter/interpreter.hpp"

#include "memory/resourceArea.hpp"

#include "prims/methodHandles.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/icache.hpp"

#include "runtime/interfaceSupport.hpp"

#include "runtime/objectMonitor.hpp"

#include "runtime/os.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "utilities/macros.hpp"

#if INCLUDE_ALL_GCS

#include "gc/g1/g1CollectedHeap.inline.hpp"

#include "gc/g1/g1SATBCardTableModRefBS.hpp"

#include "gc/g1/heapRegion.hpp"

#endif // INCLUDE_ALL_GCS

#ifdef PRODUCT

#define BLOCK_COMMENT(str) // nothing

#else

#define BLOCK_COMMENT(str) block_comment(str)

#endif

#ifdef ASSERT

// On RISC, there's no benefit to verifying instruction boundaries.

bool AbstractAssembler::pd_check_instruction_mark() { return false; }

#endif

void MacroAssembler::ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop) {

  assert(Assembler::is_simm(si31, 31) && si31 >= 0, "si31 out of range");

  if (Assembler::is_simm(si31, 16)) {

    ld(d, si31, a);

    if (emit_filler_nop) nop();

  } else {

    const int hi = MacroAssembler::largeoffset_si16_si16_hi(si31);

    const int lo = MacroAssembler::largeoffset_si16_si16_lo(si31);

    addis(d, a, hi);

    ld(d, lo, d);

  }

}

void MacroAssembler::ld_largeoffset(Register d, int si31, Register a, int emit_filler_nop) {

  assert_different_registers(d, a);

  ld_largeoffset_unchecked(d, si31, a, emit_filler_nop);

}

void MacroAssembler::load_sized_value(Register dst, RegisterOrConstant offs, Register base,

                                      size_t size_in_bytes, bool is_signed) {

  switch (size_in_bytes) {

  case  8:              ld(dst, offs, base);                         break;

  case  4:  is_signed ? lwa(dst, offs, base) : lwz(dst, offs, base); break;

  case  2:  is_signed ? lha(dst, offs, base) : lhz(dst, offs, base); break;

  case  1:  lbz(dst, offs, base); if (is_signed) extsb(dst, dst);    break; // lba doesn't exist :(

  default:  ShouldNotReachHere();

  }

}

void MacroAssembler::store_sized_value(Register dst, RegisterOrConstant offs, Register base,

                                       size_t size_in_bytes) {

  switch (size_in_bytes) {

  case  8:  std(dst, offs, base); break;

  case  4:  stw(dst, offs, base); break;

  case  2:  sth(dst, offs, base); break;

  case  1:  stb(dst, offs, base); break;

  default:  ShouldNotReachHere();

  }

}

void MacroAssembler::align(int modulus, int max, int rem) {

  int padding = (rem + modulus - (offset() % modulus)) % modulus;

  if (padding > max) return;

  for (int c = (padding >> 2); c > 0; --c) { nop(); }

}

// Issue instructions that calculate given TOC from global TOC.

void MacroAssembler::calculate_address_from_global_toc(Register dst, address addr, bool hi16, bool lo16,

                                                       bool add_relocation, bool emit_dummy_addr) {

  int offset = -1;

  if (emit_dummy_addr) {

    offset = -128; // dummy address

  } else if (addr != (address)(intptr_t)-1) {

    offset = MacroAssembler::offset_to_global_toc(addr);

  }

  if (hi16) {

    addis(dst, R29, MacroAssembler::largeoffset_si16_si16_hi(offset));

  }

  if (lo16) {

    if (add_relocation) {

      // Relocate at the addi to avoid confusion with a load from the method's TOC.

      relocate(internal_word_Relocation::spec(addr));

    }

    addi(dst, dst, MacroAssembler::largeoffset_si16_si16_lo(offset));

  }

}

int MacroAssembler::patch_calculate_address_from_global_toc_at(address a, address bound, address addr) {

  const int offset = MacroAssembler::offset_to_global_toc(addr);

  const address inst2_addr = a;

  const int inst2 = *(int *)inst2_addr;

  // The relocation points to the second instruction, the addi,

  // and the addi reads and writes the same register dst.

  const int dst = inv_rt_field(inst2);

  assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");

  // Now, find the preceding addis which writes to dst.

  int inst1 = 0;

  address inst1_addr = inst2_addr - BytesPerInstWord;

  while (inst1_addr >= bound) {

    inst1 = *(int *) inst1_addr;

    if (is_addis(inst1) && inv_rt_field(inst1) == dst) {

      // Stop, found the addis which writes dst.

      break;

    }

    inst1_addr -= BytesPerInstWord;

  }

  assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");

  set_imm((int *)inst1_addr, MacroAssembler::largeoffset_si16_si16_hi(offset));

  set_imm((int *)inst2_addr, MacroAssembler::largeoffset_si16_si16_lo(offset));

  return (int)((intptr_t)addr - (intptr_t)inst1_addr);

}

address MacroAssembler::get_address_of_calculate_address_from_global_toc_at(address a, address bound) {

  const address inst2_addr = a;

  const int inst2 = *(int *)inst2_addr;

  // The relocation points to the second instruction, the addi,

  // and the addi reads and writes the same register dst.

  const int dst = inv_rt_field(inst2);

  assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");

  // Now, find the preceding addis which writes to dst.

  int inst1 = 0;

  address inst1_addr = inst2_addr - BytesPerInstWord;

  while (inst1_addr >= bound) {

    inst1 = *(int *) inst1_addr;

    if (is_addis(inst1) && inv_rt_field(inst1) == dst) {

      // stop, found the addis which writes dst

      break;

    }

    inst1_addr -= BytesPerInstWord;

  }

  assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");

  int offset = (get_imm(inst1_addr, 0) << 16) + get_imm(inst2_addr, 0);

  // -1 is a special case

  if (offset == -1) {

    return (address)(intptr_t)-1;

  } else {

    return global_toc() + offset;

  }

}

#ifdef _LP64

// Patch compressed oops or klass constants.

// Assembler sequence is

// 1) compressed oops:

//    lis  rx = const.hi

//    ori rx = rx | const.lo

// 2) compressed klass:

//    lis  rx = const.hi

//    clrldi rx = rx & 0xFFFFffff // clearMS32b, optional

//    ori rx = rx | const.lo

// Clrldi will be passed by.

int MacroAssembler::patch_set_narrow_oop(address a, address bound, narrowOop data) {

  assert(UseCompressedOops, "Should only patch compressed oops");

  const address inst2_addr = a;

  const int inst2 = *(int *)inst2_addr;

  // The relocation points to the second instruction, the ori,

  // and the ori reads and writes the same register dst.

  const int dst = inv_rta_field(inst2);

  assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");

  // Now, find the preceding addis which writes to dst.

  int inst1 = 0;

  address inst1_addr = inst2_addr - BytesPerInstWord;

  bool inst1_found = false;

  while (inst1_addr >= bound) {

    inst1 = *(int *)inst1_addr;

    if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break; }

    inst1_addr -= BytesPerInstWord;

  }

  assert(inst1_found, "inst is not lis");

  int xc = (data >> 16) & 0xffff;

  int xd = (data >>  0) & 0xffff;

  set_imm((int *)inst1_addr, (short)(xc)); // see enc_load_con_narrow_hi/_lo

  set_imm((int *)inst2_addr,        (xd)); // unsigned int

  return (int)((intptr_t)inst2_addr - (intptr_t)inst1_addr);

}

// Get compressed oop or klass constant.

narrowOop MacroAssembler::get_narrow_oop(address a, address bound) {

  assert(UseCompressedOops, "Should only patch compressed oops");

  const address inst2_addr = a;

  const int inst2 = *(int *)inst2_addr;

  // The relocation points to the second instruction, the ori,

  // and the ori reads and writes the same register dst.

  const int dst = inv_rta_field(inst2);

  assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");

  // Now, find the preceding lis which writes to dst.

  int inst1 = 0;

  address inst1_addr = inst2_addr - BytesPerInstWord;

  bool inst1_found = false;

  while (inst1_addr >= bound) {

    inst1 = *(int *) inst1_addr;

    if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break;}

    inst1_addr -= BytesPerInstWord;

  }

  assert(inst1_found, "inst is not lis");

  uint xl = ((unsigned int) (get_imm(inst2_addr, 0) & 0xffff));

  uint xh = (((get_imm(inst1_addr, 0)) & 0xffff) << 16);

  return (int) (xl | xh);

}

#endif // _LP64

void MacroAssembler::load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc) {

  int toc_offset = 0;

  // Use RelocationHolder::none for the constant pool entry, otherwise

  // we will end up with a failing NativeCall::verify(x) where x is

  // the address of the constant pool entry.

  // FIXME: We should insert relocation information for oops at the constant

  // pool entries instead of inserting it at the loads; patching of a constant

  // pool entry should be less expensive.

  address oop_address = address_constant((address)a.value(), RelocationHolder::none);

  // Relocate at the pc of the load.

  relocate(a.rspec());

  toc_offset = (int)(oop_address - code()->consts()->start());

  ld_largeoffset_unchecked(dst, toc_offset, toc, true);

}

bool MacroAssembler::is_load_const_from_method_toc_at(address a) {

  const address inst1_addr = a;

  const int inst1 = *(int *)inst1_addr;

   // The relocation points to the ld or the addis.

   return (is_ld(inst1)) ||

          (is_addis(inst1) && inv_ra_field(inst1) != 0);

}

int MacroAssembler::get_offset_of_load_const_from_method_toc_at(address a) {

  assert(is_load_const_from_method_toc_at(a), "must be load_const_from_method_toc");

  const address inst1_addr = a;

  const int inst1 = *(int *)inst1_addr;

  if (is_ld(inst1)) {

    return inv_d1_field(inst1);

  } else if (is_addis(inst1)) {

    const int dst = inv_rt_field(inst1);

    // Now, find the succeeding ld which reads and writes to dst.

    address inst2_addr = inst1_addr + BytesPerInstWord;

    int inst2 = 0;

    while (true) {

      inst2 = *(int *) inst2_addr;

      if (is_ld(inst2) && inv_ra_field(inst2) == dst && inv_rt_field(inst2) == dst) {

        // Stop, found the ld which reads and writes dst.

        break;

      }

      inst2_addr += BytesPerInstWord;

    }

    return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);

  }

  ShouldNotReachHere();

  return 0;

}

// Get the constant from a `load_const' sequence.

long MacroAssembler::get_const(address a) {

  assert(is_load_const_at(a), "not a load of a constant");

  const int *p = (const int*) a;

  unsigned long x = (((unsigned long) (get_imm(a,0) & 0xffff)) << 48);

  if (is_ori(*(p+1))) {

    x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 32);

    x |= (((unsigned long) (get_imm(a,3) & 0xffff)) << 16);

    x |= (((unsigned long) (get_imm(a,4) & 0xffff)));

  } else if (is_lis(*(p+1))) {

    x |= (((unsigned long) (get_imm(a,2) & 0xffff)) << 32);

    x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 16);

    x |= (((unsigned long) (get_imm(a,3) & 0xffff)));

  } else {

    ShouldNotReachHere();

    return (long) 0;

  }

  return (long) x;

}

// Patch the 64 bit constant of a `load_const' sequence. This is a low

// level procedure. It neither flushes the instruction cache nor is it

// mt safe.

void MacroAssembler::patch_const(address a, long x) {

  assert(is_load_const_at(a), "not a load of a constant");

  int *p = (int*) a;

  if (is_ori(*(p+1))) {

    set_imm(0 + p, (x >> 48) & 0xffff);

    set_imm(1 + p, (x >> 32) & 0xffff);

    set_imm(3 + p, (x >> 16) & 0xffff);

    set_imm(4 + p, x & 0xffff);

  } else if (is_lis(*(p+1))) {

    set_imm(0 + p, (x >> 48) & 0xffff);

    set_imm(2 + p, (x >> 32) & 0xffff);

    set_imm(1 + p, (x >> 16) & 0xffff);

    set_imm(3 + p, x & 0xffff);

  } else {

    ShouldNotReachHere();

  }

}

AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {

  assert(oop_recorder() != NULL, "this assembler needs a Recorder");

  int index = oop_recorder()->allocate_metadata_index(obj);

  RelocationHolder rspec = metadata_Relocation::spec(index);

  return AddressLiteral((address)obj, rspec);

}

AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {

  assert(oop_recorder() != NULL, "this assembler needs a Recorder");

  int index = oop_recorder()->find_index(obj);

  RelocationHolder rspec = metadata_Relocation::spec(index);

  return AddressLiteral((address)obj, rspec);

}

AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {

  assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");

  int oop_index = oop_recorder()->allocate_oop_index(obj);

  return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));

}

AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {

  assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");

  int oop_index = oop_recorder()->find_index(obj);

  return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));

}

RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,

                                                      Register tmp, int offset) {

  intptr_t value = *delayed_value_addr;

  if (value != 0) {

    return RegisterOrConstant(value + offset);

  }

  // Load indirectly to solve generation ordering problem.

  // static address, no relocation

  int simm16_offset = load_const_optimized(tmp, delayed_value_addr, noreg, true);

  ld(tmp, simm16_offset, tmp); // must be aligned ((xa & 3) == 0)

  if (offset != 0) {

    addi(tmp, tmp, offset);

  }

  return RegisterOrConstant(tmp);

}

#ifndef PRODUCT

void MacroAssembler::pd_print_patched_instruction(address branch) {

  Unimplemented(); // TODO: PPC port

}

#endif // ndef PRODUCT

// Conditional far branch for destinations encodable in 24+2 bits.

void MacroAssembler::bc_far(int boint, int biint, Label& dest, int optimize) {

  // If requested by flag optimize, relocate the bc_far as a

  // runtime_call and prepare for optimizing it when the code gets

  // relocated.

  if (optimize == bc_far_optimize_on_relocate) {

    relocate(relocInfo::runtime_call_type);

  }

  // variant 2:

  //

  //    b!cxx SKIP

  //    bxx   DEST

  //  SKIP:

  //

  const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),

                                                opposite_bcond(inv_boint_bcond(boint)));

  // We emit two branches.

  // First, a conditional branch which jumps around the far branch.

  const address not_taken_pc = pc() + 2 * BytesPerInstWord;

  const address bc_pc        = pc();

  bc(opposite_boint, biint, not_taken_pc);

  const int bc_instr = *(int*)bc_pc;

  assert(not_taken_pc == (address)inv_bd_field(bc_instr, (intptr_t)bc_pc), "postcondition");

  assert(opposite_boint == inv_bo_field(bc_instr), "postcondition");

  assert(boint == add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(bc_instr))),

                                     opposite_bcond(inv_boint_bcond(inv_bo_field(bc_instr)))),

         "postcondition");

  assert(biint == inv_bi_field(bc_instr), "postcondition");

  // Second, an unconditional far branch which jumps to dest.

  // Note: target(dest) remembers the current pc (see CodeSection::target)

  //       and returns the current pc if the label is not bound yet; when

  //       the label gets bound, the unconditional far branch will be patched.

  const address target_pc = target(dest);

  const address b_pc  = pc();

  b(target_pc);

  assert(not_taken_pc == pc(),                     "postcondition");

  assert(dest.is_bound() || target_pc == b_pc, "postcondition");

}

bool MacroAssembler::is_bc_far_at(address instruction_addr) {

  return is_bc_far_variant1_at(instruction_addr) ||

         is_bc_far_variant2_at(instruction_addr) ||

         is_bc_far_variant3_at(instruction_addr);

}

address MacroAssembler::get_dest_of_bc_far_at(address instruction_addr) {

  if (is_bc_far_variant1_at(instruction_addr)) {

    const address instruction_1_addr = instruction_addr;

    const int instruction_1 = *(int*)instruction_1_addr;

    return (address)inv_bd_field(instruction_1, (intptr_t)instruction_1_addr);

  } else if (is_bc_far_variant2_at(instruction_addr)) {

    const address instruction_2_addr = instruction_addr + 4;

    return bxx_destination(instruction_2_addr);

  } else if (is_bc_far_variant3_at(instruction_addr)) {

    return instruction_addr + 8;

  }

  // variant 4 ???

  ShouldNotReachHere();

  return NULL;

}

void MacroAssembler::set_dest_of_bc_far_at(address instruction_addr, address dest) {

  if (is_bc_far_variant3_at(instruction_addr)) {

    // variant 3, far cond branch to the next instruction, already patched to nops:

    //

    //    nop

    //    endgroup

    //  SKIP/DEST:

    //

    return;

  }

  // first, extract boint and biint from the current branch

  int boint = 0;

  int biint = 0;

  ResourceMark rm;

  const int code_size = 2 * BytesPerInstWord;

  CodeBuffer buf(instruction_addr, code_size);

  MacroAssembler masm(&buf);

  if (is_bc_far_variant2_at(instruction_addr) && dest == instruction_addr + 8) {

    // Far branch to next instruction: Optimize it by patching nops (produce variant 3).

    masm.nop();

    masm.endgroup();

  } else {

    if (is_bc_far_variant1_at(instruction_addr)) {

      // variant 1, the 1st instruction contains the destination address:

      //

      //    bcxx  DEST

      //    endgroup

      //

      const int instruction_1 = *(int*)(instruction_addr);

      boint = inv_bo_field(instruction_1);

      biint = inv_bi_field(instruction_1);

    } else if (is_bc_far_variant2_at(instruction_addr)) {

      // variant 2, the 2nd instruction contains the destination address:

      //

      //    b!cxx SKIP

      //    bxx   DEST

      //  SKIP:

      //

      const int instruction_1 = *(int*)(instruction_addr);

      boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(instruction_1))),

          opposite_bcond(inv_boint_bcond(inv_bo_field(instruction_1))));

      biint = inv_bi_field(instruction_1);

    } else {

      // variant 4???

      ShouldNotReachHere();

    }

    // second, set the new branch destination and optimize the code

    if (dest != instruction_addr + 4 && // the bc_far is still unbound!

        masm.is_within_range_of_bcxx(dest, instruction_addr)) {

      // variant 1:

      //

      //    bcxx  DEST