hotspot/src/cpu/x86/vm/vm_version_x86.cpp
author kvn
Mon, 11 Apr 2011 15:30:31 -0700
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child 9325 2b95b2b2b60f
permissions -rw-r--r--
7035713: 3DNow Prefetch Instruction Support Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set. Reviewed-by: kvn Contributed-by: tom.deneau@amd.com
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/*
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 * Copyright (c) 1997, 2011, Oracle and/or its affiliates.  All Rights Reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "assembler_x86.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_x86.hpp"
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#ifdef TARGET_OS_FAMILY_linux
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# include "os_linux.inline.hpp"
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#endif
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#ifdef TARGET_OS_FAMILY_solaris
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# include "os_solaris.inline.hpp"
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#endif
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#ifdef TARGET_OS_FAMILY_windows
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# include "os_windows.inline.hpp"
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#endif
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_stepping;
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int VM_Version::_cpuFeatures;
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const char*           VM_Version::_features_str = "";
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VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
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static BufferBlob* stub_blob;
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static const int stub_size = 400;
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extern "C" {
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  typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_getPsrInfo() {
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    // Flags to test CPU type.
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    const uint32_t EFL_AC           = 0x40000;
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    const uint32_t EFL_ID           = 0x200000;
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    // Values for when we don't have a CPUID instruction.
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    const int      CPU_FAMILY_SHIFT = 8;
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    const uint32_t CPU_FAMILY_386   = (3 << CPU_FAMILY_SHIFT);
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    const uint32_t CPU_FAMILY_486   = (4 << CPU_FAMILY_SHIFT);
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    Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
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    Label ext_cpuid1, ext_cpuid5, done;
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    StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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#   define __ _masm->
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    address start = __ pc();
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    //
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    // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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    //
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    // LP64: rcx and rdx are first and second argument registers on windows
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    __ push(rbp);
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#ifdef _LP64
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    __ mov(rbp, c_rarg0); // cpuid_info address
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#else
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    __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
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#endif
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    __ push(rbx);
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    __ push(rsi);
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    __ pushf();          // preserve rbx, and flags
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    __ pop(rax);
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    __ push(rax);
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    __ mov(rcx, rax);
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    //
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    // if we are unable to change the AC flag, we have a 386
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    //
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    __ xorl(rax, EFL_AC);
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    __ push(rax);
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    __ popf();
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    __ pushf();
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    __ pop(rax);
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    __ cmpptr(rax, rcx);
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    __ jccb(Assembler::notEqual, detect_486);
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    __ movl(rax, CPU_FAMILY_386);
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    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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    __ jmp(done);
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    //
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    // If we are unable to change the ID flag, we have a 486 which does
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    // not support the "cpuid" instruction.
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    //
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    __ bind(detect_486);
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    __ mov(rax, rcx);
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    __ xorl(rax, EFL_ID);
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    __ push(rax);
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    __ popf();
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    __ pushf();
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    __ pop(rax);
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    __ cmpptr(rcx, rax);
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    __ jccb(Assembler::notEqual, detect_586);
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    __ bind(cpu486);
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    __ movl(rax, CPU_FAMILY_486);
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    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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    __ jmp(done);
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    //
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    // At this point, we have a chip which supports the "cpuid" instruction
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    //
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    __ bind(detect_586);
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    __ xorl(rax, rax);
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    __ cpuid();
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    __ orl(rax, rax);
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    __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
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                                        // value of at least 1, we give up and
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                                        // assume a 486
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
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    __ jccb(Assembler::belowEqual, std_cpuid4);
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    //
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    // cpuid(0xB) Processor Topology
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    //
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    __ movl(rax, 0xb);
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    __ xorl(rcx, rcx);   // Threads level
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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   162
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    __ movl(rax, 0xb);
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    __ movl(rcx, 1);     // Cores level
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    __ cpuid();
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    __ push(rax);
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   167
    __ andl(rax, 0x1f);  // Determine if valid topology level
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    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
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    __ andl(rax, 0xffff);
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid4);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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   176
    __ movl(Address(rsi, 8), rcx);
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   177
    __ movl(Address(rsi,12), rdx);
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   178
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    __ movl(rax, 0xb);
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    __ movl(rcx, 2);     // Packages level
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    __ cpuid();
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    __ push(rax);
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   183
    __ andl(rax, 0x1f);  // Determine if valid topology level
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    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
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    __ andl(rax, 0xffff);
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid4);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
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    __ movl(Address(rsi, 0), rax);
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   191
    __ movl(Address(rsi, 4), rbx);
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   192
    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // cpuid(0x4) Deterministic cache params
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    //
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    __ bind(std_cpuid4);
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    __ movl(rax, 4);
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    __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
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    __ jccb(Assembler::greater, std_cpuid1);
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    __ xorl(rcx, rcx);   // L1 cache
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    __ cpuid();
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    __ push(rax);
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    __ andl(rax, 0x1f);  // Determine if valid cache parameters used
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    __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid1);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Standard cpuid(0x1)
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    //
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    __ bind(std_cpuid1);
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    __ movl(rax, 1);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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   228
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    __ movl(rax, 0x80000000);
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   230
    __ cpuid();
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    __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
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    __ jcc(Assembler::belowEqual, done);
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    __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid1);
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   235
    __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid5);
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    //
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    // Extended cpuid(0x80000008)
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    //
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    __ movl(rax, 0x80000008);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Extended cpuid(0x80000005)
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    //
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    __ bind(ext_cpuid5);
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    __ movl(rax, 0x80000005);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Extended cpuid(0x80000001)
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    //
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    __ bind(ext_cpuid1);
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    __ movl(rax, 0x80000001);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // return
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    //
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    __ bind(done);
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    __ popf();
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    __ pop(rsi);
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    __ pop(rbx);
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    __ pop(rbp);
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    __ ret(0);
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#   undef __
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    return start;
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  };
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};
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void VM_Version::get_processor_features() {
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  _cpu = 4; // 486 by default
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  _model = 0;
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  _stepping = 0;
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  _cpuFeatures = 0;
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  _logical_processors_per_package = 1;
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  if (!Use486InstrsOnly) {
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    // Get raw processor info
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    getPsrInfo_stub(&_cpuid_info);
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    assert_is_initialized();
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    _cpu = extended_cpu_family();
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    _model = extended_cpu_model();
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    _stepping = cpu_stepping();
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    if (cpu_family() > 4) { // it supports CPUID
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      _cpuFeatures = feature_flags();
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      // Logical processors are only available on P4s and above,
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      // and only if hyperthreading is available.
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      _logical_processors_per_package = logical_processor_count();
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    }
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  }
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  _supports_cx8 = supports_cmpxchg8();
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#ifdef _LP64
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  // OS should support SSE for x64 and hardware should support at least SSE2.
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  if (!VM_Version::supports_sse2()) {
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    vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
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  }
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  // in 64 bit the use of SSE2 is the minimum
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  if (UseSSE < 2) UseSSE = 2;
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#endif
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  // If the OS doesn't support SSE, we can't use this feature even if the HW does
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  if (!os::supports_sse())
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    _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
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  if (UseSSE < 4) {
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    _cpuFeatures &= ~CPU_SSE4_1;
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    _cpuFeatures &= ~CPU_SSE4_2;
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  }
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  if (UseSSE < 3) {
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    _cpuFeatures &= ~CPU_SSE3;
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    _cpuFeatures &= ~CPU_SSSE3;
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    _cpuFeatures &= ~CPU_SSE4A;
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  }
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  if (UseSSE < 2)
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    _cpuFeatures &= ~CPU_SSE2;
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  if (UseSSE < 1)
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    _cpuFeatures &= ~CPU_SSE;
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  if (logical_processors_per_package() == 1) {
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    // HT processor could be installed on a system which doesn't support HT.
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    _cpuFeatures &= ~CPU_HT;
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  }
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  char buf[256];
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  jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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               cores_per_cpu(), threads_per_core(),
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               cpu_family(), _model, _stepping,
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               (supports_cmov() ? ", cmov" : ""),
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               (supports_cmpxchg8() ? ", cx8" : ""),
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               (supports_fxsr() ? ", fxsr" : ""),
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               (supports_mmx()  ? ", mmx"  : ""),
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               (supports_sse()  ? ", sse"  : ""),
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               (supports_sse2() ? ", sse2" : ""),
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               (supports_sse3() ? ", sse3" : ""),
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               (supports_ssse3()? ", ssse3": ""),
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               (supports_sse4_1() ? ", sse4.1" : ""),
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               (supports_sse4_2() ? ", sse4.2" : ""),
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               (supports_popcnt() ? ", popcnt" : ""),
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               (supports_mmx_ext() ? ", mmxext" : ""),
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               (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
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               (supports_lzcnt()   ? ", lzcnt": ""),
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               (supports_sse4a()   ? ", sse4a": ""),
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               (supports_ht() ? ", ht": ""));
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  _features_str = strdup(buf);
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  // UseSSE is set to the smaller of what hardware supports and what
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  // the command line requires.  I.e., you cannot set UseSSE to 2 on
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  // older Pentiums which do not support it.
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  if( UseSSE > 4 ) UseSSE=4;
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  if( UseSSE < 0 ) UseSSE=0;
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  if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
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    UseSSE = MIN2((intx)3,UseSSE);
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  if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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    UseSSE = MIN2((intx)2,UseSSE);
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  if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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    UseSSE = MIN2((intx)1,UseSSE);
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  if( !supports_sse () ) // Drop to 0 if no SSE  support
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    UseSSE = 0;
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  // On new cpus instructions which update whole XMM register should be used
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  // to prevent partial register stall due to dependencies on high half.
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  //
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  // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
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  // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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  // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
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  // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
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  if( is_amd() ) { // AMD cpus specific settings
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    if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
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      // Use it on new AMD cpus starting from Opteron.
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      UseAddressNop = true;
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    }
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    if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
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      // Use it on new AMD cpus starting from Opteron.
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      UseNewLongLShift = true;
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    }
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    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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      if( supports_sse4a() ) {
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   405
        UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   406
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   407
        UseXmmLoadAndClearUpper = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   408
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   409
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   410
    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   411
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   412
        UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   413
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   414
        UseXmmRegToRegMoveAll = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   415
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   416
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   417
    if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   418
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   419
        UseXmmI2F = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   420
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   421
        UseXmmI2F = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   422
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   423
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   424
    if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   425
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   426
        UseXmmI2D = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   427
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   428
        UseXmmI2D = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   429
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   430
    }
8873
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   431
    if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   432
      if( supports_sse4_2() && UseSSE >= 4 ) {
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   433
        UseSSE42Intrinsics = true;
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   434
      }
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   435
    }
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   436
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   437
    // Use count leading zeros count instruction if available.
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   438
    if (supports_lzcnt()) {
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   439
      if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   440
        UseCountLeadingZerosInstruction = true;
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   441
      }
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   442
    }
8677
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   443
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   444
    // On family 21 processors default is no sw prefetch
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   445
    if ( cpu_family() == 21 ) {
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   446
      if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   447
        AllocatePrefetchStyle = 0;
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   448
      }
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   449
    }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   450
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   451
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   452
  if( is_intel() ) { // Intel cpus specific settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   453
    if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   454
      UseStoreImmI16 = false; // don't use it on Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   455
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   456
    if( cpu_family() == 6 || cpu_family() == 15 ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   457
      if( FLAG_IS_DEFAULT(UseAddressNop) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   458
        // Use it on all Intel cpus starting from PentiumPro
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   459
        UseAddressNop = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   460
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   461
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   462
    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   463
      UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   464
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   465
    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   466
      if( supports_sse3() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   467
        UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   468
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   469
        UseXmmRegToRegMoveAll = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   470
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   471
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   472
    if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   473
#ifdef COMPILER2
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   474
      if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   475
        // For new Intel cpus do the next optimization:
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   476
        // don't align the beginning of a loop if there are enough instructions
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   477
        // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   478
        // in current fetch line (OptoLoopAlignment) or the padding
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   479
        // is big (> MaxLoopPad).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   480
        // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   481
        // generated NOP instructions. 11 is the largest size of one
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   482
        // address NOP instruction '0F 1F' (see Assembler::nop(i)).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   483
        MaxLoopPad = 11;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   484
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   485
#endif // COMPILER2
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   486
      if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   487
        UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   488
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   489
      if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   490
        if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   491
          UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   492
        }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   493
      }
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   494
      if( supports_sse4_2() && UseSSE >= 4 ) {
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   495
        if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   496
          UseSSE42Intrinsics = true;
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   497
        }
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   498
      }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   499
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   500
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   501
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   502
  // Use population count instruction if available.
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   503
  if (supports_popcnt()) {
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   504
    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   505
      UsePopCountInstruction = true;
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   506
    }
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   507
  }
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   508
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   509
#ifdef COMPILER2
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   510
  if (UseFPUForSpilling) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   511
    if (UseSSE < 2) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   512
      // Only supported with SSE2+
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   513
      FLAG_SET_DEFAULT(UseFPUForSpilling, false);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   514
    }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   515
  }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   516
#endif
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   517
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   518
  assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   519
  assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   520
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   521
  // set valid Prefetch instruction
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   522
  if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   523
  if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   524
  if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   525
  if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   526
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   527
  if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   528
  if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   529
  if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   530
  if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   531
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   532
  // Allocation prefetch settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   533
  intx cache_line_size = L1_data_cache_line_size();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   534
  if( cache_line_size > AllocatePrefetchStepSize )
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   535
    AllocatePrefetchStepSize = cache_line_size;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   536
  if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   537
    AllocatePrefetchLines = 3; // Optimistic value
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   538
  assert(AllocatePrefetchLines > 0, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   539
  if( AllocatePrefetchLines < 1 ) // set valid value in product VM
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   540
    AllocatePrefetchLines = 1; // Conservative value
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   541
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   542
  AllocatePrefetchDistance = allocate_prefetch_distance();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   543
  AllocatePrefetchStyle    = allocate_prefetch_style();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   544
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   545
  if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   546
    if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   547
#ifdef _LP64
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   548
      AllocatePrefetchDistance = 384;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   549
#else
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   550
      AllocatePrefetchDistance = 320;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   551
#endif
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   552
    }
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   553
    if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   554
      AllocatePrefetchDistance = 192;
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   555
      AllocatePrefetchLines = 4;
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   556
#ifdef COMPILER2
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   557
      if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   558
        FLAG_SET_DEFAULT(UseFPUForSpilling, true);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   559
      }
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
   560
#endif
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
   561
    }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   562
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   563
  assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   564
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   565
#ifdef _LP64
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   566
  // Prefetch settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   567
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   568
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   569
  PrefetchFieldsAhead         = prefetch_fields_ahead();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   570
#endif
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   571
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   572
#ifndef PRODUCT
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   573
  if (PrintMiscellaneous && Verbose) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   574
    tty->print_cr("Logical CPUs per core: %u",
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   575
                  logical_processors_per_package());
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   576
    tty->print_cr("UseSSE=%d",UseSSE);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   577
    tty->print("Allocation: ");
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   578
    if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   579
      tty->print_cr("no prefetching");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   580
    } else {
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   581
      if (UseSSE == 0 && supports_3dnow_prefetch()) {
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   582
        tty->print("PREFETCHW");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   583
      } else if (UseSSE >= 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   584
        if (AllocatePrefetchInstr == 0) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   585
          tty->print("PREFETCHNTA");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   586
        } else if (AllocatePrefetchInstr == 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   587
          tty->print("PREFETCHT0");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   588
        } else if (AllocatePrefetchInstr == 2) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   589
          tty->print("PREFETCHT2");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   590
        } else if (AllocatePrefetchInstr == 3) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   591
          tty->print("PREFETCHW");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   592
        }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   593
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   594
      if (AllocatePrefetchLines > 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   595
        tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   596
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   597
        tty->print_cr(" %d, one line", AllocatePrefetchDistance);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   598
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   599
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   600
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   601
    if (PrefetchCopyIntervalInBytes > 0) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   602
      tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   603
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   604
    if (PrefetchScanIntervalInBytes > 0) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   605
      tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   606
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   607
    if (PrefetchFieldsAhead > 0) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   608
      tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   609
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   610
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   611
#endif // !PRODUCT
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   612
}
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   613
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   614
void VM_Version::initialize() {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   615
  ResourceMark rm;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   616
  // Making this stub must be FIRST use of assembler
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   617
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   618
  stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   619
  if (stub_blob == NULL) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   620
    vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   621
  }
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 6272
diff changeset
   622
  CodeBuffer c(stub_blob);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   623
  VM_Version_StubGenerator g(&c);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   624
  getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   625
                                   g.generate_getPsrInfo());
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   626
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   627
  get_processor_features();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   628
}