hotspot/src/cpu/x86/vm/nativeInst_x86.hpp
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Thu, 27 May 2010 19:08:38 -0700
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6941466: Oracle rebranding changes for Hotspot repositories Summary: Change all the Sun copyrights to Oracle copyright Reviewed-by: ohair
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/*
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 * Copyright (c) 1997, 2008, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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// We have interfaces for the following instructions:
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// - NativeInstruction
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// - - NativeCall
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// - - NativeMovConstReg
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// - - NativeMovConstRegPatching
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// - - NativeMovRegMem
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// - - NativeMovRegMemPatching
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// - - NativeJump
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// - - NativeIllegalOpCode
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// - - NativeGeneralJump
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// - - NativeReturn
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// - - NativeReturnX (return with argument)
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// - - NativePushConst
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// - - NativeTstRegMem
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// The base class for different kinds of native instruction abstractions.
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// Provides the primitive operations to manipulate code relative to this.
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class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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  friend class Relocation;
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 public:
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  enum Intel_specific_constants {
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    nop_instruction_code        = 0x90,
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    nop_instruction_size        =    1
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  };
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  bool is_nop()                        { return ubyte_at(0) == nop_instruction_code; }
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  bool is_dtrace_trap();
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  inline bool is_call();
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  inline bool is_illegal();
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  inline bool is_return();
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  inline bool is_jump();
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  inline bool is_cond_jump();
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  inline bool is_safepoint_poll();
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  inline bool is_mov_literal64();
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 protected:
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  address addr_at(int offset) const    { return address(this) + offset; }
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  s_char sbyte_at(int offset) const    { return *(s_char*) addr_at(offset); }
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  u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
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  jint int_at(int offset) const         { return *(jint*) addr_at(offset); }
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  intptr_t ptr_at(int offset) const    { return *(intptr_t*) addr_at(offset); }
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  oop  oop_at (int offset) const       { return *(oop*) addr_at(offset); }
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  void set_char_at(int offset, char c)        { *addr_at(offset) = (u_char)c; wrote(offset); }
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  void set_int_at(int offset, jint  i)        { *(jint*)addr_at(offset) = i;  wrote(offset); }
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  void set_ptr_at (int offset, intptr_t  ptr) { *(intptr_t*) addr_at(offset) = ptr;  wrote(offset); }
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  void set_oop_at (int offset, oop  o)        { *(oop*) addr_at(offset) = o;  wrote(offset); }
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  // This doesn't really do anything on Intel, but it is the place where
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  // cache invalidation belongs, generically:
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  void wrote(int offset);
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  // unit test stuff
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  static void test() {}                 // override for testing
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  inline friend NativeInstruction* nativeInstruction_at(address address);
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};
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inline NativeInstruction* nativeInstruction_at(address address) {
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  NativeInstruction* inst = (NativeInstruction*)address;
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#ifdef ASSERT
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  //inst->verify();
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#endif
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  return inst;
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}
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inline NativeCall* nativeCall_at(address address);
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// The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
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// instructions (used to manipulate inline caches, primitive & dll calls, etc.).
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class NativeCall: public NativeInstruction {
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 public:
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  enum Intel_specific_constants {
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    instruction_code            = 0xE8,
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    instruction_size            =    5,
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    instruction_offset          =    0,
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    displacement_offset         =    1,
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    return_address_offset       =    5
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  };
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  enum { cache_line_size = BytesPerWord };  // conservative estimate!
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  address instruction_address() const       { return addr_at(instruction_offset); }
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  address next_instruction_address() const  { return addr_at(return_address_offset); }
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  int   displacement() const                { return (jint) int_at(displacement_offset); }
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  address displacement_address() const      { return addr_at(displacement_offset); }
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  address return_address() const            { return addr_at(return_address_offset); }
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  address destination() const;
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  void  set_destination(address dest)       {
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#ifdef AMD64
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    assert((labs((intptr_t) dest - (intptr_t) return_address())  &
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            0xFFFFFFFF00000000) == 0,
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           "must be 32bit offset");
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#endif // AMD64
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    set_int_at(displacement_offset, dest - return_address());
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  }
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  void  set_destination_mt_safe(address dest);
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  void  verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
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  void  verify();
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  void  print();
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  // Creation
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  inline friend NativeCall* nativeCall_at(address address);
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  inline friend NativeCall* nativeCall_before(address return_address);
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  static bool is_call_at(address instr) {
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    return ((*instr) & 0xFF) == NativeCall::instruction_code;
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  }
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  static bool is_call_before(address return_address) {
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    return is_call_at(return_address - NativeCall::return_address_offset);
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  }
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  static bool is_call_to(address instr, address target) {
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    return nativeInstruction_at(instr)->is_call() &&
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      nativeCall_at(instr)->destination() == target;
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  }
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  // MT-safe patching of a call instruction.
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  static void insert(address code_pos, address entry);
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  static void replace_mt_safe(address instr_addr, address code_buffer);
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};
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inline NativeCall* nativeCall_at(address address) {
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  NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
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#ifdef ASSERT
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  call->verify();
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#endif
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  return call;
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}
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inline NativeCall* nativeCall_before(address return_address) {
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  NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
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#ifdef ASSERT
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  call->verify();
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#endif
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  return call;
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}
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// An interface for accessing/manipulating native mov reg, imm32 instructions.
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// (used to manipulate inlined 32bit data dll calls, etc.)
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class NativeMovConstReg: public NativeInstruction {
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#ifdef AMD64
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  static const bool has_rex = true;
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  static const int rex_size = 1;
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#else
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  static const bool has_rex = false;
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  static const int rex_size = 0;
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#endif // AMD64
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 public:
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  enum Intel_specific_constants {
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    instruction_code            = 0xB8,
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    instruction_size            =    1 + rex_size + wordSize,
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    instruction_offset          =    0,
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    data_offset                 =    1 + rex_size,
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    next_instruction_offset     =    instruction_size,
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    register_mask               = 0x07
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  };
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  address instruction_address() const       { return addr_at(instruction_offset); }
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  address next_instruction_address() const  { return addr_at(next_instruction_offset); }
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  intptr_t data() const                     { return ptr_at(data_offset); }
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  void  set_data(intptr_t x)                { set_ptr_at(data_offset, x); }
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  void  verify();
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  void  print();
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  // unit test stuff
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  static void test() {}
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  // Creation
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  inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
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  inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
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};
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inline NativeMovConstReg* nativeMovConstReg_at(address address) {
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  NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
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#ifdef ASSERT
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  test->verify();
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#endif
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  return test;
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}
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inline NativeMovConstReg* nativeMovConstReg_before(address address) {
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  NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
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#ifdef ASSERT
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  test->verify();
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#endif
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  return test;
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}
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class NativeMovConstRegPatching: public NativeMovConstReg {
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 private:
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    friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
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    NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
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    #ifdef ASSERT
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      test->verify();
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    #endif
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    return test;
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  }
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};
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// An interface for accessing/manipulating native moves of the form:
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//      mov[b/w/l/q] [reg + offset], reg   (instruction_code_reg2mem)
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//      mov[b/w/l/q] reg, [reg+offset]     (instruction_code_mem2reg
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//      mov[s/z]x[w/b/q] [reg + offset], reg
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//      fld_s  [reg+offset]
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//      fld_d  [reg+offset]
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//      fstp_s [reg + offset]
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//      fstp_d [reg + offset]
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//      mov_literal64  scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
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//
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// Warning: These routines must be able to handle any instruction sequences
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// that are generated as a result of the load/store byte,word,long
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// macros.  For example: The load_unsigned_byte instruction generates
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// an xor reg,reg inst prior to generating the movb instruction.  This
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// class must skip the xor instruction.
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class NativeMovRegMem: public NativeInstruction {
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 public:
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  enum Intel_specific_constants {
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    instruction_prefix_wide_lo          = Assembler::REX,
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    instruction_prefix_wide_hi          = Assembler::REX_WRXB,
1
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    instruction_code_xor                = 0x33,
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    instruction_extended_prefix         = 0x0F,
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    instruction_code_mem2reg_movslq     = 0x63,
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    instruction_code_mem2reg_movzxb     = 0xB6,
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    instruction_code_mem2reg_movsxb     = 0xBE,
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    instruction_code_mem2reg_movzxw     = 0xB7,
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    instruction_code_mem2reg_movsxw     = 0xBF,
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    instruction_operandsize_prefix      = 0x66,
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    instruction_code_reg2mem            = 0x89,
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    instruction_code_mem2reg            = 0x8b,
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    instruction_code_reg2memb           = 0x88,
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    instruction_code_mem2regb           = 0x8a,
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    instruction_code_float_s            = 0xd9,
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    instruction_code_float_d            = 0xdd,
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    instruction_code_long_volatile      = 0xdf,
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    instruction_code_xmm_ss_prefix      = 0xf3,
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    instruction_code_xmm_sd_prefix      = 0xf2,
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    instruction_code_xmm_code           = 0x0f,
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    instruction_code_xmm_load           = 0x10,
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    instruction_code_xmm_store          = 0x11,
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    instruction_code_xmm_lpd            = 0x12,
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    instruction_size                    = 4,
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    instruction_offset                  = 0,
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    data_offset                         = 2,
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    next_instruction_offset             = 4
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  };
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  // helper
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  int instruction_start() const;
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  address instruction_address() const;
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  address next_instruction_address() const;
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  int   offset() const;
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  void  set_offset(int x);
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  void  add_offset_in_bytes(int add_offset)     { set_offset ( ( offset() + add_offset ) ); }
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  void verify();
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  void print ();
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  // unit test stuff
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  static void test() {}
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 private:
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  inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
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};
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inline NativeMovRegMem* nativeMovRegMem_at (address address) {
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  NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
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#ifdef ASSERT
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  test->verify();
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#endif
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  return test;
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}
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class NativeMovRegMemPatching: public NativeMovRegMem {
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 private:
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  friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
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    NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
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    #ifdef ASSERT
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      test->verify();
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    #endif
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    return test;
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  }
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};
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// An interface for accessing/manipulating native leal instruction of form:
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//        leal reg, [reg + offset]
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class NativeLoadAddress: public NativeMovRegMem {
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#ifdef AMD64
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  static const bool has_rex = true;
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  static const int rex_size = 1;
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#else
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  static const bool has_rex = false;
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  static const int rex_size = 0;
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#endif // AMD64
1
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 public:
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  enum Intel_specific_constants {
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    instruction_prefix_wide             = Assembler::REX_W,
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    instruction_prefix_wide_extended    = Assembler::REX_WB,
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    lea_instruction_code                = 0x8D,
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    mov64_instruction_code              = 0xB8
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  };
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  void verify();
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  void print ();
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  // unit test stuff
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  static void test() {}
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 private:
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  friend NativeLoadAddress* nativeLoadAddress_at (address address) {
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    NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
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    #ifdef ASSERT
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      test->verify();
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    #endif
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    return test;
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  }
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};
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// jump rel32off
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class NativeJump: public NativeInstruction {
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 public:
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  enum Intel_specific_constants {
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    instruction_code            = 0xe9,
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    instruction_size            =    5,
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    instruction_offset          =    0,
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    data_offset                 =    1,
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    next_instruction_offset     =    5
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  };
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  address instruction_address() const       { return addr_at(instruction_offset); }
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  address next_instruction_address() const  { return addr_at(next_instruction_offset); }
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  address jump_destination() const          {
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     address dest = (int_at(data_offset)+next_instruction_address());
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     // 32bit used to encode unresolved jmp as jmp -1
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     // 64bit can't produce this so it used jump to self.
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     // Now 32bit and 64bit use jump to self as the unresolved address
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     // which the inline cache code (and relocs) know about
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1
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     // return -1 if jump to self
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    dest = (dest == (address) this) ? (address) -1 : dest;
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    return dest;
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  }
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  void  set_jump_destination(address dest)  {
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    intptr_t val = dest - next_instruction_address();
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a4f1c0615381 6744422: incorrect handling of -1 in set_jump_destination
never
parents: 1066
diff changeset
   394
    if (dest == (address) -1) {
a4f1c0615381 6744422: incorrect handling of -1 in set_jump_destination
never
parents: 1066
diff changeset
   395
      val = -5; // jump to self
a4f1c0615381 6744422: incorrect handling of -1 in set_jump_destination
never
parents: 1066
diff changeset
   396
    }
1
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   397
#ifdef AMD64
1066
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parents: 670
diff changeset
   398
    assert((labs(val)  & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
1
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parents:
diff changeset
   399
#endif // AMD64
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   400
    set_int_at(data_offset, (jint)val);
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parents:
diff changeset
   401
  }
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parents:
diff changeset
   402
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parents:
diff changeset
   403
  // Creation
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   404
  inline friend NativeJump* nativeJump_at(address address);
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parents:
diff changeset
   405
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parents:
diff changeset
   406
  void verify();
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parents:
diff changeset
   407
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parents:
diff changeset
   408
  // Unit testing stuff
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   409
  static void test() {}
489c9b5090e2 Initial load
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parents:
diff changeset
   410
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parents:
diff changeset
   411
  // Insertion of native jump instruction
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   412
  static void insert(address code_pos, address entry);
489c9b5090e2 Initial load
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parents:
diff changeset
   413
  // MT-safe insertion of native jump at verified method entry
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parents:
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   414
  static void check_verified_entry_alignment(address entry, address verified_entry);
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parents:
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   415
  static void patch_verified_entry(address entry, address verified_entry, address dest);
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   416
};
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parents:
diff changeset
   417
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parents:
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   418
inline NativeJump* nativeJump_at(address address) {
489c9b5090e2 Initial load
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   419
  NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
489c9b5090e2 Initial load
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parents:
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   420
#ifdef ASSERT
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parents:
diff changeset
   421
  jump->verify();
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parents:
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   422
#endif
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parents:
diff changeset
   423
  return jump;
489c9b5090e2 Initial load
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parents:
diff changeset
   424
}
489c9b5090e2 Initial load
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parents:
diff changeset
   425
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parents:
diff changeset
   426
// Handles all kinds of jump on Intel. Long/far, conditional/unconditional
489c9b5090e2 Initial load
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parents:
diff changeset
   427
class NativeGeneralJump: public NativeInstruction {
489c9b5090e2 Initial load
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parents:
diff changeset
   428
 public:
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parents:
diff changeset
   429
  enum Intel_specific_constants {
489c9b5090e2 Initial load
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   430
    // Constants does not apply, since the lengths and offsets depends on the actual jump
489c9b5090e2 Initial load
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   431
    // used
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parents:
diff changeset
   432
    // Instruction codes:
489c9b5090e2 Initial load
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parents:
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   433
    //   Unconditional jumps: 0xE9    (rel32off), 0xEB (rel8off)
489c9b5090e2 Initial load
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parents:
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   434
    //   Conditional jumps:   0x0F8x  (rel32off), 0x7x (rel8off)
489c9b5090e2 Initial load
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parents:
diff changeset
   435
    unconditional_long_jump  = 0xe9,
489c9b5090e2 Initial load
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parents:
diff changeset
   436
    unconditional_short_jump = 0xeb,
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parents:
diff changeset
   437
    instruction_size = 5
489c9b5090e2 Initial load
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parents:
diff changeset
   438
  };
489c9b5090e2 Initial load
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parents:
diff changeset
   439
489c9b5090e2 Initial load
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parents:
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   440
  address instruction_address() const       { return addr_at(0); }
489c9b5090e2 Initial load
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parents:
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   441
  address jump_destination()    const;
489c9b5090e2 Initial load
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parents:
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   442
489c9b5090e2 Initial load
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parents:
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   443
  // Creation
489c9b5090e2 Initial load
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parents:
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   444
  inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
489c9b5090e2 Initial load
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parents:
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   445
489c9b5090e2 Initial load
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parents:
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   446
  // Insertion of native general jump instruction
489c9b5090e2 Initial load
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parents:
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   447
  static void insert_unconditional(address code_pos, address entry);
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parents:
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   448
  static void replace_mt_safe(address instr_addr, address code_buffer);
489c9b5090e2 Initial load
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parents:
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   449
489c9b5090e2 Initial load
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parents:
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   450
  void verify();
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parents:
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   451
};
489c9b5090e2 Initial load
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parents:
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   452
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parents:
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   453
inline NativeGeneralJump* nativeGeneralJump_at(address address) {
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parents:
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   454
  NativeGeneralJump* jump = (NativeGeneralJump*)(address);
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   455
  debug_only(jump->verify();)
489c9b5090e2 Initial load
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parents:
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   456
  return jump;
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parents:
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   457
}
489c9b5090e2 Initial load
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   458
489c9b5090e2 Initial load
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parents:
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   459
class NativePopReg : public NativeInstruction {
489c9b5090e2 Initial load
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parents:
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   460
 public:
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parents:
diff changeset
   461
  enum Intel_specific_constants {
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parents:
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   462
    instruction_code            = 0x58,
489c9b5090e2 Initial load
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parents:
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   463
    instruction_size            =    1,
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parents:
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   464
    instruction_offset          =    0,
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parents:
diff changeset
   465
    data_offset                 =    1,
489c9b5090e2 Initial load
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parents:
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   466
    next_instruction_offset     =    1
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parents:
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   467
  };
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parents:
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   468
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parents:
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   469
  // Insert a pop instruction
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parents:
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   470
  static void insert(address code_pos, Register reg);
489c9b5090e2 Initial load
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   471
};
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parents:
diff changeset
   472
489c9b5090e2 Initial load
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parents:
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   473
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parents:
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   474
class NativeIllegalInstruction: public NativeInstruction {
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parents:
diff changeset
   475
 public:
489c9b5090e2 Initial load
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parents:
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   476
  enum Intel_specific_constants {
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parents:
diff changeset
   477
    instruction_code            = 0x0B0F,    // Real byte order is: 0x0F, 0x0B
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parents:
diff changeset
   478
    instruction_size            =    2,
489c9b5090e2 Initial load
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parents:
diff changeset
   479
    instruction_offset          =    0,
489c9b5090e2 Initial load
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parents:
diff changeset
   480
    next_instruction_offset     =    2
489c9b5090e2 Initial load
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parents:
diff changeset
   481
  };
489c9b5090e2 Initial load
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parents:
diff changeset
   482
489c9b5090e2 Initial load
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parents:
diff changeset
   483
  // Insert illegal opcode as specific address
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parents:
diff changeset
   484
  static void insert(address code_pos);
489c9b5090e2 Initial load
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parents:
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   485
};
489c9b5090e2 Initial load
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parents:
diff changeset
   486
489c9b5090e2 Initial load
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parents:
diff changeset
   487
// return instruction that does not pop values of the stack
489c9b5090e2 Initial load
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parents:
diff changeset
   488
class NativeReturn: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
 public:
489c9b5090e2 Initial load
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parents:
diff changeset
   490
  enum Intel_specific_constants {
489c9b5090e2 Initial load
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parents:
diff changeset
   491
    instruction_code            = 0xC3,
489c9b5090e2 Initial load
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parents:
diff changeset
   492
    instruction_size            =    1,
489c9b5090e2 Initial load
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parents:
diff changeset
   493
    instruction_offset          =    0,
489c9b5090e2 Initial load
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parents:
diff changeset
   494
    next_instruction_offset     =    1
489c9b5090e2 Initial load
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parents:
diff changeset
   495
  };
489c9b5090e2 Initial load
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parents:
diff changeset
   496
};
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parents:
diff changeset
   497
489c9b5090e2 Initial load
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parents:
diff changeset
   498
// return instruction that does pop values of the stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
class NativeReturnX: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
  enum Intel_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
    instruction_code            = 0xC2,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
    instruction_size            =    2,
489c9b5090e2 Initial load
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parents:
diff changeset
   504
    instruction_offset          =    0,
489c9b5090e2 Initial load
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parents:
diff changeset
   505
    next_instruction_offset     =    2
489c9b5090e2 Initial load
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parents:
diff changeset
   506
  };
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
// Simple test vs memory
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
class NativeTstRegMem: public NativeInstruction {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   512
  enum Intel_specific_constants {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
    instruction_code_memXregl   = 0x85
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
  };
489c9b5090e2 Initial load
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parents:
diff changeset
   515
};
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
inline bool NativeInstruction::is_illegal()      { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
inline bool NativeInstruction::is_call()         { return ubyte_at(0) == NativeCall::instruction_code; }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
inline bool NativeInstruction::is_return()       { return ubyte_at(0) == NativeReturn::instruction_code ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   520
                                                          ubyte_at(0) == NativeReturnX::instruction_code; }
489c9b5090e2 Initial load
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parents:
diff changeset
   521
inline bool NativeInstruction::is_jump()         { return ubyte_at(0) == NativeJump::instruction_code ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
                                                          ubyte_at(0) == 0xEB; /* short jump */ }
489c9b5090e2 Initial load
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parents:
diff changeset
   523
inline bool NativeInstruction::is_cond_jump()    { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
489c9b5090e2 Initial load
duke
parents:
diff changeset
   524
                                                          (ubyte_at(0) & 0xF0) == 0x70;  /* short jump */ }
489c9b5090e2 Initial load
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parents:
diff changeset
   525
inline bool NativeInstruction::is_safepoint_poll() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
#ifdef AMD64
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   527
  if ( ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   528
       ubyte_at(1) == 0x05 ) { // 00 rax 101
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   529
     address fault = addr_at(6) + int_at(2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   530
     return os::is_poll_address(fault);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   531
  } else {
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   532
    return false;
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   533
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
#else
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 670
diff changeset
   535
  return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   536
           ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
           (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
           (os::is_poll_address((address)int_at(2)));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
#endif // AMD64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
}
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
inline bool NativeInstruction::is_mov_literal64() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
#ifdef AMD64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
  return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
          (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
  return false;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
#endif // AMD64
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
}