//

// Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

//

// SPARC Architecture Description File

//----------REGISTER DEFINITION BLOCK------------------------------------------

// This information is used by the matcher and the register allocator to

// describe individual registers and classes of registers within the target

// archtecture.

register %{

//----------Architecture Description Register Definitions----------------------

// General Registers

// "reg_def"  name ( register save type, C convention save type,

//                   ideal register type, encoding, vm name );

// Register Save Types:

//

// NS  = No-Save:       The register allocator assumes that these registers

//                      can be used without saving upon entry to the method, &

//                      that they do not need to be saved at call sites.

//

// SOC = Save-On-Call:  The register allocator assumes that these registers

//                      can be used without saving upon entry to the method,

//                      but that they must be saved at call sites.

//

// SOE = Save-On-Entry: The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, but they do not need to be saved at call

//                      sites.

//

// AS  = Always-Save:   The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, & that they must be saved at call sites.

//

// Ideal Register Type is used to determine how to save & restore a

// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

//

// The encoding number is the actual bit-pattern placed into the opcodes.

// ----------------------------

// Integer/Long Registers

// ----------------------------

// Need to expose the hi/lo aspect of 64-bit registers

// This register set is used for both the 64-bit build and

// the 32-bit build with 1-register longs.

// Global Registers 0-7

reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());

reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());

reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());

reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());

reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());

reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());

reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());

reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());

reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());

reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());

reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());

reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());

reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());

reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());

reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());

reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());

// Output Registers 0-7

reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());

reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());

reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());

reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());

reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());

reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());

reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());

reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());

reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());

reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());

reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());

reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());

reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());

reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());

reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());

reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());

// Local Registers 0-7

reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());

reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());

reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());

reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());

reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());

reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());

reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());

reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());

reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());

reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());

reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());

reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());

reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());

reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());

reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());

reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());

// Input Registers 0-7

reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());

reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());

reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());

reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());

reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());

reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());

reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());

reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());

reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());

reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());

reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());

reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());

reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());

reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());

reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());

reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());

// ----------------------------

// Float/Double Registers

// ----------------------------

// Float Registers

reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());

reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());

reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());

reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());

reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());

reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());

reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());

reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());

reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());

reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());

reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());

reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());

reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());

reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());

reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());

reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());

reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());

reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());

reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());

reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());

reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());

reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());

reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());

reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());

reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());

reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());

reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());

reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());

reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());

reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());

reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());

reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());

// Double Registers

// The rules of ADL require that double registers be defined in pairs.

// Each pair must be two 32-bit values, but not necessarily a pair of

// single float registers.  In each pair, ADLC-assigned register numbers

// must be adjacent, with the lower number even.  Finally, when the

// CPU stores such a register pair to memory, the word associated with

// the lower ADLC-assigned number must be stored to the lower address.

// These definitions specify the actual bit encodings of the sparc

// double fp register numbers.  FloatRegisterImpl in register_sparc.hpp

// wants 0-63, so we have to convert every time we want to use fp regs

// with the macroassembler, using reg_to_DoubleFloatRegister_object().

// 255 is a flag meaning "don't go here".

// I believe we can't handle callee-save doubles D32 and up until

// the place in the sparc stack crawler that asserts on the 255 is

// fixed up.

reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());

reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());

reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());

reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());

reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());

reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());

reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());

reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());

reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());

reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());

reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());

reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());

reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());

reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());

reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());

reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());

reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());

reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());

reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());

reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());

reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());

reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());

reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());

reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());

reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());

reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());

reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());

reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());

reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());

reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());

reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());

reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());

// ----------------------------

// Special Registers

// Condition Codes Flag Registers

// I tried to break out ICC and XCC but it's not very pretty.

// Every Sparc instruction which defs/kills one also kills the other.

// Hence every compare instruction which defs one kind of flags ends

// up needing a kill of the other.

reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());

reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());

reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());

reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());

reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());

// ----------------------------

// Specify the enum values for the registers.  These enums are only used by the

// OptoReg "class". We can convert these enum values at will to VMReg when needed

// for visibility to the rest of the vm. The order of this enum influences the

// register allocator so having the freedom to set this order and not be stuck

// with the order that is natural for the rest of the vm is worth it.

alloc_class chunk0(

  R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,

  R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,

  R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,

  R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);

// Note that a register is not allocatable unless it is also mentioned

// in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.

alloc_class chunk1(

  // The first registers listed here are those most likely to be used

  // as temporaries.  We move F0..F7 away from the front of the list,

  // to reduce the likelihood of interferences with parameters and

  // return values.  Likewise, we avoid using F0/F1 for parameters,

  // since they are used for return values.

  // This FPU fine-tuning is worth about 1% on the SPEC geomean.

  R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

  R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,

  R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,

  R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values

  R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,

  R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,

  R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,

  R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);

alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);

//----------Architecture Description Register Classes--------------------------

// Several register classes are automatically defined based upon information in

// this architecture description.

// 1) reg_class inline_cache_reg           ( as defined in frame section )

// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )

// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

//

// G0 is not included in integer class since it has special meaning.

reg_class g0_reg(R_G0);

// ----------------------------

// Integer Register Classes

// ----------------------------

// Exclusions from i_reg:

// R_G0: hardwired zero

// R_G2: reserved by HotSpot to the TLS register (invariant within Java)

// R_G6: reserved by Solaris ABI to tools

// R_G7: reserved by Solaris ABI to libthread

// R_O7: Used as a temp in many encodings

reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

// Class for all integer registers, except the G registers.  This is used for

// encodings which use G registers as temps.  The regular inputs to such

// instructions use a "notemp_" prefix, as a hack to ensure that the allocator

// will not put an input into a temp register.

reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

reg_class g1_regI(R_G1);

reg_class g3_regI(R_G3);

reg_class g4_regI(R_G4);

reg_class o0_regI(R_O0);

reg_class o7_regI(R_O7);

// ----------------------------

// Pointer Register Classes

// ----------------------------

#ifdef _LP64

// 64-bit build means 64-bit pointers means hi/lo pairs

reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,

                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,

                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );

// Lock encodings use G3 and G4 internally

reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,

                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,

                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );

// Special class for storeP instructions, which can store SP or RPC to TLS.

// It is also used for memory addressing, allowing direct TLS addressing.

reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,

                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,

                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );

// R_L7 is the lowest-priority callee-save (i.e., NS) register

// We use it to save R_G2 across calls out of Java.

reg_class l7_regP(R_L7H,R_L7);

// Other special pointer regs

reg_class g1_regP(R_G1H,R_G1);

reg_class g2_regP(R_G2H,R_G2);

reg_class g3_regP(R_G3H,R_G3);

reg_class g4_regP(R_G4H,R_G4);

reg_class g5_regP(R_G5H,R_G5);

reg_class i0_regP(R_I0H,R_I0);

reg_class o0_regP(R_O0H,R_O0);

reg_class o1_regP(R_O1H,R_O1);

reg_class o2_regP(R_O2H,R_O2);

reg_class o7_regP(R_O7H,R_O7);

#else // _LP64

// 32-bit build means 32-bit pointers means 1 register.

reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,

                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,

                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

// Lock encodings use G3 and G4 internally

reg_class lock_ptr_reg(R_G1,               R_G5,

                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,

                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

// Special class for storeP instructions, which can store SP or RPC to TLS.

// It is also used for memory addressing, allowing direct TLS addressing.

reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,

                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,

                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);

// R_L7 is the lowest-priority callee-save (i.e., NS) register

// We use it to save R_G2 across calls out of Java.

reg_class l7_regP(R_L7);

// Other special pointer regs

reg_class g1_regP(R_G1);

reg_class g2_regP(R_G2);

reg_class g3_regP(R_G3);

reg_class g4_regP(R_G4);

reg_class g5_regP(R_G5);

reg_class i0_regP(R_I0);

reg_class o0_regP(R_O0);

reg_class o1_regP(R_O1);

reg_class o2_regP(R_O2);

reg_class o7_regP(R_O7);

#endif // _LP64

// ----------------------------

// Long Register Classes

// ----------------------------

// Longs in 1 register.  Aligned adjacent hi/lo pairs.

// Note:  O7 is never in this class; it is sometimes used as an encoding temp.

reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5

                   ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5

#ifdef _LP64

// 64-bit, longs in 1 register: use all 64-bit integer registers

// 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.

                   ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7

                   ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5

#endif // _LP64

                  );

reg_class g1_regL(R_G1H,R_G1);

reg_class g3_regL(R_G3H,R_G3);

reg_class o2_regL(R_O2H,R_O2);

reg_class o7_regL(R_O7H,R_O7);

// ----------------------------

// Special Class for Condition Code Flags Register

reg_class int_flags(CCR);

reg_class float_flags(FCC0,FCC1,FCC2,FCC3);

reg_class float_flag0(FCC0);

// ----------------------------

// Float Point Register Classes

// ----------------------------

// Skip F30/F31, they are reserved for mem-mem copies

reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);

// Paired floating point registers--they show up in the same order as the floats,

// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.

reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,

                   /* Use extra V9 double registers; this AD file does not support V8 */

                   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,

                   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x

                   );

// Paired floating point registers--they show up in the same order as the floats,

// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.

// This class is usable for mis-aligned loads as happen in I2C adapters.

reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);

%}

//----------DEFINITION BLOCK---------------------------------------------------

// Define name --> value mappings to inform the ADLC of an integer valued name

// Current support includes integer values in the range [0, 0x7FFFFFFF]

// Format:

//        int_def  <name>         ( <int_value>, <expression>);

// Generated Code in ad_<arch>.hpp

//        #define  <name>   (<expression>)

//        // value == <int_value>

// Generated code in ad_<arch>.cpp adlc_verification()

//        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");

//

definitions %{

// The default cost (of an ALU instruction).

  int_def DEFAULT_COST      (    100,     100);

  int_def HUGE_COST         (1000000, 1000000);

// Memory refs are twice as expensive as run-of-the-mill.

  int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);

// Branches are even more expensive.

  int_def BRANCH_COST       (    300, DEFAULT_COST * 3);

  int_def CALL_COST         (    300, DEFAULT_COST * 3);

%}

//----------SOURCE BLOCK-------------------------------------------------------

// This is a block of C++ code which provides values, functions, and

// definitions necessary in the rest of the architecture description

source_hpp %{

// Must be visible to the DFA in dfa_sparc.cpp

extern bool can_branch_register( Node *bol, Node *cmp );

extern bool use_block_zeroing(Node* count);

// Macros to extract hi & lo halves from a long pair.

// G0 is not part of any long pair, so assert on that.

// Prevents accidentally using G1 instead of G0.

#define LONG_HI_REG(x) (x)

#define LONG_LO_REG(x) (x)

%}

source %{

#define __ _masm.

// tertiary op of a LoadP or StoreP encoding

#define REGP_OP true

static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);

static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);

static Register reg_to_register_object(int register_encoding);

// Used by the DFA in dfa_sparc.cpp.

// Check for being able to use a V9 branch-on-register.  Requires a

// compare-vs-zero, equal/not-equal, of a value which was zero- or sign-

// extended.  Doesn't work following an integer ADD, for example, because of

// overflow (-1 incremented yields 0 plus a carry in the high-order word).  On

// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and

// replace them with zero, which could become sign-extension in a different OS

// release.  There's no obvious reason why an interrupt will ever fill these

// bits with non-zero junk (the registers are reloaded with standard LD

// instructions which either zero-fill or sign-fill).

bool can_branch_register( Node *bol, Node *cmp ) {

  if( !BranchOnRegister ) return false;

#ifdef _LP64

  if( cmp->Opcode() == Op_CmpP )

    return true;  // No problems with pointer compares

#endif

  if( cmp->Opcode() == Op_CmpL )

    return true;  // No problems with long compares

  if( !SparcV9RegsHiBitsZero ) return false;

  if( bol->as_Bool()->_test._test != BoolTest::ne &&

      bol->as_Bool()->_test._test != BoolTest::eq )

     return false;

  // Check for comparing against a 'safe' value.  Any operation which

  // clears out the high word is safe.  Thus, loads and certain shifts

  // are safe, as are non-negative constants.  Any operation which

  // preserves zero bits in the high word is safe as long as each of its

  // inputs are safe.  Thus, phis and bitwise booleans are safe if their

  // inputs are safe.  At present, the only important case to recognize

  // seems to be loads.  Constants should fold away, and shifts &

  // logicals can use the 'cc' forms.

  Node *x = cmp->in(1);

  if( x->is_Load() ) return true;

  if( x->is_Phi() ) {

    for( uint i = 1; i < x->req(); i++ )

      if( !x->in(i)->is_Load() )

        return false;

    return true;

  }

  return false;

}