/*

 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/assembler.hpp"

#include "asm/assembler.inline.hpp"

#include "asm/macroAssembler.hpp"

#include "ci/ciEnv.hpp"

#include "code/nativeInst.hpp"

#include "compiler/disassembler.hpp"

#include "gc/shared/cardTable.hpp"

#include "gc/shared/cardTableModRefBS.hpp"

#include "gc/shared/collectedHeap.inline.hpp"

#include "interpreter/interpreter.hpp"

#include "memory/resourceArea.hpp"

#include "oops/klass.inline.hpp"

#include "prims/methodHandles.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/objectMonitor.hpp"

#include "runtime/os.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/stubRoutines.hpp"

#include "utilities/macros.hpp"

#if INCLUDE_ALL_GCS

#include "gc/g1/g1BarrierSet.hpp"

#include "gc/g1/g1CardTable.hpp"

#include "gc/g1/g1CollectedHeap.inline.hpp"

#include "gc/g1/heapRegion.hpp"

#endif

// Implementation of AddressLiteral

void AddressLiteral::set_rspec(relocInfo::relocType rtype) {

  switch (rtype) {

  case relocInfo::oop_type:

    // Oops are a special case. Normally they would be their own section

    // but in cases like icBuffer they are literals in the code stream that

    // we don't have a section for. We use none so that we get a literal address

    // which is always patchable.

    break;

  case relocInfo::external_word_type:

    _rspec = external_word_Relocation::spec(_target);

    break;

  case relocInfo::internal_word_type:

    _rspec = internal_word_Relocation::spec(_target);

    break;

  case relocInfo::opt_virtual_call_type:

    _rspec = opt_virtual_call_Relocation::spec();

    break;

  case relocInfo::static_call_type:

    _rspec = static_call_Relocation::spec();

    break;

  case relocInfo::runtime_call_type:

    _rspec = runtime_call_Relocation::spec();

    break;

  case relocInfo::poll_type:

  case relocInfo::poll_return_type:

    _rspec = Relocation::spec_simple(rtype);

    break;

  case relocInfo::none:

    break;

  default:

    ShouldNotReachHere();

    break;

  }

}

// Initially added to the Assembler interface as a pure virtual:

//   RegisterConstant delayed_value(..)

// for:

//   6812678 macro assembler needs delayed binding of a few constants (for 6655638)

// this was subsequently modified to its present name and return type

RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,

                                                      Register tmp,

                                                      int offset) {

  ShouldNotReachHere();

  return RegisterOrConstant(-1);

}

#ifdef AARCH64

// Note: ARM32 version is OS dependent

void MacroAssembler::breakpoint(AsmCondition cond) {

  if (cond == al) {

    brk();

  } else {

    Label L;

    b(L, inverse(cond));

    brk();

    bind(L);

  }

}

#endif // AARCH64

// virtual method calling

void MacroAssembler::lookup_virtual_method(Register recv_klass,

                                           Register vtable_index,

                                           Register method_result) {

  const int base_offset = in_bytes(Klass::vtable_start_offset()) + vtableEntry::method_offset_in_bytes();

  assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");

  add(recv_klass, recv_klass, AsmOperand(vtable_index, lsl, LogBytesPerWord));

  ldr(method_result, Address(recv_klass, base_offset));

}

// Simplified, combined version, good for typical uses.

// Falls through on failure.

void MacroAssembler::check_klass_subtype(Register sub_klass,

                                         Register super_klass,

                                         Register temp_reg,

                                         Register temp_reg2,

                                         Register temp_reg3,

                                         Label& L_success) {

  Label L_failure;

  check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, temp_reg2, &L_success, &L_failure, NULL);

  check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, temp_reg2, temp_reg3, &L_success, NULL);

  bind(L_failure);

};

void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,

                                                   Register super_klass,

                                                   Register temp_reg,

                                                   Register temp_reg2,

                                                   Label* L_success,

                                                   Label* L_failure,

                                                   Label* L_slow_path) {

  assert_different_registers(sub_klass, super_klass, temp_reg, temp_reg2, noreg);

  const Register super_check_offset = temp_reg2;

  Label L_fallthrough;

  int label_nulls = 0;

  if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }

  if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }

  if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }

  assert(label_nulls <= 1, "at most one NULL in the batch");

  int sc_offset = in_bytes(Klass::secondary_super_cache_offset());

  int sco_offset = in_bytes(Klass::super_check_offset_offset());

  Address super_check_offset_addr(super_klass, sco_offset);

  // If the pointers are equal, we are done (e.g., String[] elements).

  // This self-check enables sharing of secondary supertype arrays among

  // non-primary types such as array-of-interface.  Otherwise, each such

  // type would need its own customized SSA.

  // We move this check to the front of the fast path because many

  // type checks are in fact trivially successful in this manner,

  // so we get a nicely predicted branch right at the start of the check.

  cmp(sub_klass, super_klass);

  b(*L_success, eq);

  // Check the supertype display:

  ldr_u32(super_check_offset, super_check_offset_addr);

  Address super_check_addr(sub_klass, super_check_offset);

  ldr(temp_reg, super_check_addr);

  cmp(super_klass, temp_reg); // load displayed supertype

  // This check has worked decisively for primary supers.

  // Secondary supers are sought in the super_cache ('super_cache_addr').

  // (Secondary supers are interfaces and very deeply nested subtypes.)

  // This works in the same check above because of a tricky aliasing

  // between the super_cache and the primary super display elements.

  // (The 'super_check_addr' can address either, as the case requires.)

  // Note that the cache is updated below if it does not help us find

  // what we need immediately.

  // So if it was a primary super, we can just fail immediately.

  // Otherwise, it's the slow path for us (no success at this point).

  b(*L_success, eq);

  cmp_32(super_check_offset, sc_offset);

  if (L_failure == &L_fallthrough) {

    b(*L_slow_path, eq);

  } else {

    b(*L_failure, ne);

    if (L_slow_path != &L_fallthrough) {

      b(*L_slow_path);

    }

  }

  bind(L_fallthrough);

}

void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,

                                                   Register super_klass,

                                                   Register temp_reg,

                                                   Register temp2_reg,

                                                   Register temp3_reg,

                                                   Label* L_success,

                                                   Label* L_failure,

                                                   bool set_cond_codes) {

#ifdef AARCH64

  NOT_IMPLEMENTED();

#else

  // Note: if used by code that expects a register to be 0 on success,

  // this register must be temp_reg and set_cond_codes must be true

  Register saved_reg = noreg;

  // get additional tmp registers

  if (temp3_reg == noreg) {

    saved_reg = temp3_reg = LR;

    push(saved_reg);

  }

  assert(temp2_reg != noreg, "need all the temporary registers");

  assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg);

  Register cmp_temp = temp_reg;

  Register scan_temp = temp3_reg;

  Register count_temp = temp2_reg;

  Label L_fallthrough;

  int label_nulls = 0;

  if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }

  if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }

  assert(label_nulls <= 1, "at most one NULL in the batch");

  // a couple of useful fields in sub_klass:

  int ss_offset = in_bytes(Klass::secondary_supers_offset());

  int sc_offset = in_bytes(Klass::secondary_super_cache_offset());

  Address secondary_supers_addr(sub_klass, ss_offset);

  Address super_cache_addr(     sub_klass, sc_offset);

#ifndef PRODUCT

  inc_counter((address)&SharedRuntime::_partial_subtype_ctr, scan_temp, count_temp);

#endif

  // We will consult the secondary-super array.

  ldr(scan_temp, Address(sub_klass, ss_offset));

  assert(! UseCompressedOops, "search_key must be the compressed super_klass");

  // else search_key is the

  Register search_key = super_klass;

  // Load the array length.

  ldr(count_temp, Address(scan_temp, Array<Klass*>::length_offset_in_bytes()));

  add(scan_temp, scan_temp, Array<Klass*>::base_offset_in_bytes());

  add(count_temp, count_temp, 1);

  Label L_loop, L_setnz_and_fail, L_fail;

  // Top of search loop

  bind(L_loop);

  // Notes:

  //  scan_temp starts at the array elements

  //  count_temp is 1+size

  subs(count_temp, count_temp, 1);

  if ((L_failure != &L_fallthrough) && (! set_cond_codes) && (saved_reg == noreg)) {

    // direct jump to L_failure if failed and no cleanup needed

    b(*L_failure, eq); // not found and

  } else {

    b(L_fail, eq); // not found in the array

  }

  // Load next super to check

  // In the array of super classes elements are pointer sized.

  int element_size = wordSize;

  ldr(cmp_temp, Address(scan_temp, element_size, post_indexed));

  // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list

  subs(cmp_temp, cmp_temp, search_key);

  // A miss means we are NOT a subtype and need to keep looping

  b(L_loop, ne);

  // Falling out the bottom means we found a hit; we ARE a subtype

  // Note: temp_reg/cmp_temp is already 0 and flag Z is set

  // Success.  Cache the super we found and proceed in triumph.

  str(super_klass, Address(sub_klass, sc_offset));

  if (saved_reg != noreg) {

    // Return success

    pop(saved_reg);

  }

  b(*L_success);

  bind(L_fail);

  // Note1: check "b(*L_failure, eq)" above if adding extra instructions here

  if (set_cond_codes) {

    movs(temp_reg, sub_klass); // clears Z and sets temp_reg to non-0 if needed

  }

  if (saved_reg != noreg) {

    pop(saved_reg);

  }

  if (L_failure != &L_fallthrough) {

    b(*L_failure);

  }

  bind(L_fallthrough);

#endif

}

// Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.

Address MacroAssembler::receiver_argument_address(Register params_base, Register params_count, Register tmp) {

  assert_different_registers(params_base, params_count);

  add(tmp, params_base, AsmOperand(params_count, lsl, Interpreter::logStackElementSize));

  return Address(tmp, -Interpreter::stackElementSize);

}

void MacroAssembler::align(int modulus) {

  while (offset() % modulus != 0) {

    nop();

  }

}

int MacroAssembler::set_last_Java_frame(Register last_java_sp,

                                        Register last_java_fp,

                                        bool save_last_java_pc,

                                        Register tmp) {

  int pc_offset;

  if (last_java_fp != noreg) {

    // optional

    str(last_java_fp, Address(Rthread, JavaThread::last_Java_fp_offset()));

    _fp_saved = true;

  } else {

    _fp_saved = false;

  }

  if (AARCH64_ONLY(true) NOT_AARCH64(save_last_java_pc)) { // optional on 32-bit ARM

#ifdef AARCH64

    pc_offset = mov_pc_to(tmp);

    str(tmp, Address(Rthread, JavaThread::last_Java_pc_offset()));

#else

    str(PC, Address(Rthread, JavaThread::last_Java_pc_offset()));

    pc_offset = offset() + VM_Version::stored_pc_adjustment();

#endif

    _pc_saved = true;

  } else {

    _pc_saved = false;

    pc_offset = -1;

  }

  // According to comment in javaFrameAnchorm SP must be saved last, so that other

  // entries are valid when SP is set.

  // However, this is probably not a strong constrainst since for instance PC is

  // sometimes read from the stack at SP... but is pushed later (by the call). Hence,

  // we now write the fields in the expected order but we have not added a StoreStore

  // barrier.

  // XXX: if the ordering is really important, PC should always be saved (without forgetting

  // to update oop_map offsets) and a StoreStore barrier might be needed.

  if (last_java_sp == noreg) {

    last_java_sp = SP; // always saved

  }

#ifdef AARCH64

  if (last_java_sp == SP) {

    mov(tmp, SP);

    str(tmp, Address(Rthread, JavaThread::last_Java_sp_offset()));

  } else {

    str(last_java_sp, Address(Rthread, JavaThread::last_Java_sp_offset()));

  }

#else

  str(last_java_sp, Address(Rthread, JavaThread::last_Java_sp_offset()));

#endif

  return pc_offset; // for oopmaps

}

void MacroAssembler::reset_last_Java_frame(Register tmp) {

  const Register Rzero = zero_register(tmp);

  str(Rzero, Address(Rthread, JavaThread::last_Java_sp_offset()));

  if (_fp_saved) {

    str(Rzero, Address(Rthread, JavaThread::last_Java_fp_offset()));

  }

  if (_pc_saved) {

    str(Rzero, Address(Rthread, JavaThread::last_Java_pc_offset()));

  }

}

// Implementation of call_VM versions

void MacroAssembler::call_VM_leaf_helper(address entry_point, int number_of_arguments) {

  assert(number_of_arguments >= 0, "cannot have negative number of arguments");

  assert(number_of_arguments <= 4, "cannot have more than 4 arguments");

#ifndef AARCH64

  // Safer to save R9 here since callers may have been written

  // assuming R9 survives. This is suboptimal but is not worth

  // optimizing for the few platforms where R9 is scratched.

  push(RegisterSet(R4) | R9ifScratched);

  mov(R4, SP);

  bic(SP, SP, StackAlignmentInBytes - 1);

#endif // AARCH64

  call(entry_point, relocInfo::runtime_call_type);

#ifndef AARCH64

  mov(SP, R4);

  pop(RegisterSet(R4) | R9ifScratched);

#endif // AARCH64

}

void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {

  assert(number_of_arguments >= 0, "cannot have negative number of arguments");

  assert(number_of_arguments <= 3, "cannot have more than 3 arguments");

  const Register tmp = Rtemp;

  assert_different_registers(oop_result, tmp);

  set_last_Java_frame(SP, FP, true, tmp);

#ifdef ASSERT

  AARCH64_ONLY(if (UseCompressedOops || UseCompressedClassPointers) { verify_heapbase("call_VM_helper: heap base corrupted?"); });

#endif // ASSERT

#ifndef AARCH64

#if R9_IS_SCRATCHED

  // Safer to save R9 here since callers may have been written

  // assuming R9 survives. This is suboptimal but is not worth

  // optimizing for the few platforms where R9 is scratched.

  // Note: cannot save R9 above the saved SP (some calls expect for

  // instance the Java stack top at the saved SP)

  // => once saved (with set_last_Java_frame), decrease SP before rounding to

  // ensure the slot at SP will be free for R9).

  sub(SP, SP, 4);

  bic(SP, SP, StackAlignmentInBytes - 1);

  str(R9, Address(SP, 0));

#else

  bic(SP, SP, StackAlignmentInBytes - 1);

#endif // R9_IS_SCRATCHED

#endif

  mov(R0, Rthread);

  call(entry_point, relocInfo::runtime_call_type);

#ifndef AARCH64

#if R9_IS_SCRATCHED

  ldr(R9, Address(SP, 0));

#endif

  ldr(SP, Address(Rthread, JavaThread::last_Java_sp_offset()));

#endif

  reset_last_Java_frame(tmp);

  // C++ interp handles this in the interpreter

  check_and_handle_popframe();

  check_and_handle_earlyret();

  if (check_exceptions) {

    // check for pending exceptions

    ldr(tmp, Address(Rthread, Thread::pending_exception_offset()));

#ifdef AARCH64

    Label L;

    cbz(tmp, L);

    mov_pc_to(Rexception_pc);

    b(StubRoutines::forward_exception_entry());

    bind(L);

#else

    cmp(tmp, 0);

    mov(Rexception_pc, PC, ne);

    b(StubRoutines::forward_exception_entry(), ne);

#endif // AARCH64

  }

  // get oop result if there is one and reset the value in the thread

  if (oop_result->is_valid()) {

    get_vm_result(oop_result, tmp);

  }

}

void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {

  call_VM_helper(oop_result, entry_point, 0, check_exceptions);

}

void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {

  assert (arg_1 == R1, "fixed register for arg_1");

  call_VM_helper(oop_result, entry_point, 1, check_exceptions);

}

void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {

  assert (arg_1 == R1, "fixed register for arg_1");

  assert (arg_2 == R2, "fixed register for arg_2");

  call_VM_helper(oop_result, entry_point, 2, check_exceptions);

}

void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {

  assert (arg_1 == R1, "fixed register for arg_1");

  assert (arg_2 == R2, "fixed register for arg_2");

  assert (arg_3 == R3, "fixed register for arg_3");

  call_VM_helper(oop_result, entry_point, 3, check_exceptions);

}

void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {

  // Not used on ARM

  Unimplemented();

}

void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {

  // Not used on ARM

  Unimplemented();

}