/*

 * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_S390_ASSEMBLER_S390_HPP

#define CPU_S390_ASSEMBLER_S390_HPP

#undef  LUCY_DBG

// Immediate is an abstraction to represent the various immediate

// operands which exist on z/Architecture. Neither this class nor

// instances hereof have an own state. It consists of methods only.

class Immediate {

 public:

    static bool is_simm(int64_t x, unsigned int nbits) {

      // nbits < 2   --> false

      // nbits >= 64 --> true

      assert(2 <= nbits && nbits < 64, "Don't call, use statically known result.");

      const int64_t min      = -(1L << (nbits-1));

      const int64_t maxplus1 =  (1L << (nbits-1));

      return min <= x && x < maxplus1;

    }

    static bool is_simm32(int64_t x) {

      return is_simm(x, 32);

    }

    static bool is_simm20(int64_t x) {

      return is_simm(x, 20);

    }

    static bool is_simm16(int64_t x) {

      return is_simm(x, 16);

    }

    static bool is_simm8(int64_t x) {

      return is_simm(x,  8);

    }

    // Test if x is within signed immediate range for nbits.

    static bool is_uimm(int64_t x, unsigned int nbits) {

      // nbits == 0  --> false

      // nbits >= 64 --> true

      assert(1 <= nbits && nbits < 64, "don't call, use statically known result");

      const uint64_t xu       = (unsigned long)x;

      const uint64_t maxplus1 = 1UL << nbits;

      return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large.

    }

    static bool is_uimm32(int64_t x) {

      return is_uimm(x, 32);

    }

    static bool is_uimm16(int64_t x) {

      return is_uimm(x, 16);

    }

    static bool is_uimm12(int64_t x) {

      return is_uimm(x, 12);

    }

    static bool is_uimm8(int64_t x) {

      return is_uimm(x,  8);

    }

};

// Displacement is an abstraction to represent the various

// displacements which exist with addresses on z/ArchiTecture.

// Neither this class nor instances hereof have an own state. It

// consists of methods only.

class Displacement {

 public: // These tests are used outside the (Macro)Assembler world, e.g. in ad-file.

  static bool is_longDisp(int64_t x) {  // Fits in a 20-bit displacement field.

    return Immediate::is_simm20(x);

  }

  static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field.

    return Immediate::is_uimm12(x);

  }

  static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints.

    return is_longDisp(x);

  }

};

// RelAddr is an abstraction to represent relative addresses in the

// form they are used on z/Architecture for instructions which access

// their operand with pc-relative addresses. Neither this class nor

// instances hereof have an own state. It consists of methods only.

class RelAddr {

 private: // No public use at all. Solely for (Macro)Assembler.

  static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) {

    // Guard against illegal branch targets, e.g. -1. Occurrences in

    // CompiledStaticCall and ad-file. Do not assert (it's a test

    // function!). Just return false in case of illegal operands.

    if ((((uint64_t)target) & 0x0001L) != 0) return false;

    if ((((uint64_t)pc)     & 0x0001L) != 0) return false;

    if (shortForm) {

      return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes.

    } else {

      return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes.

    }

  }

  static bool is_in_range_of_RelAddr16(address target, address pc) {

    return is_in_range_of_RelAddr(target, pc, true);

  }

  static bool is_in_range_of_RelAddr16(ptrdiff_t distance) {

    return is_in_range_of_RelAddr((address)distance, 0, true);

  }

  static bool is_in_range_of_RelAddr32(address target, address pc) {

    return is_in_range_of_RelAddr(target, pc, false);

  }

  static bool is_in_range_of_RelAddr32(ptrdiff_t distance) {

    return is_in_range_of_RelAddr((address)distance, 0, false);

  }

  static int pcrel_off(address target, address pc, bool shortForm) {

    assert(((uint64_t)target & 0x0001L) == 0, "target of a relative address must be aligned");

    assert(((uint64_t)pc     & 0x0001L) == 0, "origin of a relative address must be aligned");

    if ((target == NULL) || (target == pc)) {

      return 0;  // Yet unknown branch destination.

    } else {

      guarantee(is_in_range_of_RelAddr(target, pc, shortForm), "target not within reach");

      return (int)((target - pc)>>1);

    }

  }

  static int pcrel_off16(address target, address pc) {

    return pcrel_off(target, pc, true);

  }

  static int pcrel_off16(ptrdiff_t distance) {

    return pcrel_off((address)distance, 0, true);

  }

  static int pcrel_off32(address target, address pc) {

    return pcrel_off(target, pc, false);

  }

  static int pcrel_off32(ptrdiff_t distance) {

    return pcrel_off((address)distance, 0, false);

  }

  static ptrdiff_t inv_pcrel_off16(int offset) {

    return ((ptrdiff_t)offset)<<1;

  }

  static ptrdiff_t inv_pcrel_off32(int offset) {

    return ((ptrdiff_t)offset)<<1;

  }

  friend class Assembler;

  friend class MacroAssembler;

  friend class NativeGeneralJump;

};

// Address is an abstraction used to represent a memory location

// as passed to Z assembler instructions.

//

// Note: A register location is represented via a Register, not

// via an address for efficiency & simplicity reasons.

class Address {

 private:

  Register _base;    // Base register.

  Register _index;   // Index register

  intptr_t _disp;    // Constant displacement.

 public:

  Address() :

    _base(noreg),

    _index(noreg),

    _disp(0) {}

  Address(Register base, Register index, intptr_t disp = 0) :

    _base(base),

    _index(index),

    _disp(disp) {}

  Address(Register base, intptr_t disp = 0) :

    _base(base),

    _index(noreg),

    _disp(disp) {}

  Address(Register base, RegisterOrConstant roc, intptr_t disp = 0) :

    _base(base),

    _index(noreg),

    _disp(disp) {

    if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register();

  }

#ifdef ASSERT

  // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

  Address(Register base, ByteSize disp) :

    _base(base),

    _index(noreg),

    _disp(in_bytes(disp)) {}

  Address(Register base, Register index, ByteSize disp) :

    _base(base),

    _index(index),

    _disp(in_bytes(disp)) {}

#endif

  // Aborts if disp is a register and base and index are set already.

  Address plus_disp(RegisterOrConstant disp) const {

    Address a = (*this);

    a._disp += disp.constant_or_zero();

    if (disp.is_register()) {

      if (a._index == noreg) {

        a._index = disp.as_register();

      } else {

        guarantee(_base == noreg, "can not encode"); a._base = disp.as_register();

      }

    }

    return a;

  }

  // A call to this is generated by adlc for replacement variable $xxx$$Address.

  static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);

  bool is_same_address(Address a) const {

    return _base == a._base && _index == a._index && _disp == a._disp;

  }

  // testers

  bool has_base()  const { return _base  != noreg; }

  bool has_index() const { return _index != noreg; }

  bool has_disp()  const { return true; } // There is no "invalid" value.

  bool is_disp12() const { return Immediate::is_uimm12(disp()); }

  bool is_disp20() const { return Immediate::is_simm20(disp()); }

  bool is_RSform()  { return has_base() && !has_index() && is_disp12(); }

  bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }

  bool is_RXform()  { return has_base() &&  has_index() && is_disp12(); }

  bool is_RXYform() { return has_base() &&  has_index() && is_disp20(); }

  bool uses(Register r) { return _base == r || _index == r; };

  // accessors

  Register base()      const { return _base; }

  Register baseOrR0()  const { assert(_base  != Z_R0, ""); return _base  == noreg ? Z_R0 : _base; }

  Register index()     const { return _index; }

  Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; }

  intptr_t disp() const { return _disp; }

  // Specific version for short displacement instructions.

  int      disp12() const {

    assert(is_disp12(), "displacement out of range for uimm12");

    return _disp;

  }

  // Specific version for long displacement instructions.

  int      disp20() const {

    assert(is_disp20(), "displacement out of range for simm20");

    return _disp;

  }

  intptr_t value() const { return _disp; }

  friend class Assembler;

};

class AddressLiteral {

 private:

  address          _address;

  RelocationHolder _rspec;

  RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {

    switch (rtype) {

    case relocInfo::external_word_type:

      return external_word_Relocation::spec(addr);

    case relocInfo::internal_word_type:

      return internal_word_Relocation::spec(addr);

    case relocInfo::opt_virtual_call_type:

      return opt_virtual_call_Relocation::spec();

    case relocInfo::static_call_type:

      return static_call_Relocation::spec();

    case relocInfo::runtime_call_w_cp_type:

      return runtime_call_w_cp_Relocation::spec();

    case relocInfo::none:

      return RelocationHolder();

    default:

      ShouldNotReachHere();

      return RelocationHolder();

    }

  }

 protected:

  // creation

  AddressLiteral() : _address(NULL), _rspec(NULL) {}

 public:

  AddressLiteral(address addr, RelocationHolder const& rspec)

    : _address(addr),

      _rspec(rspec) {}

  // Some constructors to avoid casting at the call site.

  AddressLiteral(jobject obj, RelocationHolder const& rspec)

    : _address((address) obj),

      _rspec(rspec) {}

  AddressLiteral(intptr_t value, RelocationHolder const& rspec)

    : _address((address) value),

      _rspec(rspec) {}

  AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

    _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  // Some constructors to avoid casting at the call site.

  AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

    _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)

    : _address((address) addr),

      _rspec(rspec_from_rtype(rtype, (address) addr)) {}

  intptr_t value() const { return (intptr_t) _address; }

  const relocInfo::relocType rtype() const { return _rspec.type(); }

  const RelocationHolder&    rspec() const { return _rspec; }

  RelocationHolder rspec(int offset) const {

    return offset == 0 ? _rspec : _rspec.plus(offset);

  }

};

// Convenience classes

class ExternalAddress: public AddressLiteral {

 private:

  static relocInfo::relocType reloc_for_target(address target) {

    // Sometimes ExternalAddress is used for values which aren't

    // exactly addresses, like the card table base.

    // External_word_type can't be used for values in the first page

    // so just skip the reloc in that case.

    return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;

  }

 public:

  ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(          target)) {}

  ExternalAddress(oop*    target) : AddressLiteral(target, reloc_for_target((address) target)) {}

};

// Argument is an abstraction used to represent an outgoing actual

// argument or an incoming formal parameter, whether it resides in

// memory or in a register, in a manner consistent with the

// z/Architecture Application Binary Interface, or ABI. This is often

// referred to as the native or C calling convention.

class Argument {

 private:

  int _number;

  bool _is_in;

 public:

  enum {

    // Only 5 registers may contain integer parameters.

    n_register_parameters = 5,

    // Can have up to 4 floating registers.

    n_float_register_parameters = 4

  };

  // creation

  Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}

  Argument(int number) : _number(number) {}

  int number() const { return _number; }

  Argument successor() const { return Argument(number() + 1); }

  // Locating register-based arguments:

  bool is_register() const { return _number < n_register_parameters; }

  // Locating Floating Point register-based arguments:

  bool is_float_register() const { return _number < n_float_register_parameters; }

  FloatRegister as_float_register() const {

    assert(is_float_register(), "must be a register argument");

    return as_FloatRegister((number() *2) + 1);

  }

  FloatRegister as_double_register() const {

    assert(is_float_register(), "must be a register argument");

    return as_FloatRegister((number() *2));

  }

  Register as_register() const {

    assert(is_register(), "must be a register argument");

    return as_Register(number() + Z_ARG1->encoding());

  }

  // debugging

  const char* name() const;

  friend class Assembler;

};

// The z/Architecture Assembler: Pure assembler doing NO optimizations

// on the instruction level; i.e., what you write is what you get. The

// Assembler is generating code into a CodeBuffer.

class Assembler : public AbstractAssembler {

 protected:

  friend class AbstractAssembler;

  friend class AddressLiteral;

  // Code patchers need various routines like inv_wdisp().

  friend class NativeInstruction;

#ifndef COMPILER2

  friend class NativeGeneralJump;

#endif

  friend class Relocation;

 public:

// Addressing

// address calculation

#define LA_ZOPC     (unsigned  int)(0x41  << 24)

#define LAY_ZOPC    (unsigned long)(0xe3L << 40 | 0x71L)

#define LARL_ZOPC   (unsigned long)(0xc0L << 40 | 0x00L << 32)

// Data Transfer

// register to register transfer

#define LR_ZOPC     (unsigned  int)(24 << 8)

#define LBR_ZOPC    (unsigned  int)(0xb926 << 16)

#define LHR_ZOPC    (unsigned  int)(0xb927 << 16)

#define LGBR_ZOPC   (unsigned  int)(0xb906 << 16)

#define LGHR_ZOPC   (unsigned  int)(0xb907 << 16)

#define LGFR_ZOPC   (unsigned  int)(0xb914 << 16)

#define LGR_ZOPC    (unsigned  int)(0xb904 << 16)

#define LLHR_ZOPC   (unsigned  int)(0xb995 << 16)

#define LLGCR_ZOPC  (unsigned  int)(0xb984 << 16)

#define LLGHR_ZOPC  (unsigned  int)(0xb985 << 16)

#define LLGTR_ZOPC  (unsigned  int)(185 << 24 | 23 << 16)

#define LLGFR_ZOPC  (unsigned  int)(185 << 24 | 22 << 16)

#define LTR_ZOPC    (unsigned  int)(18 << 8)

#define LTGFR_ZOPC  (unsigned  int)(185 << 24 | 18 << 16)

#define LTGR_ZOPC   (unsigned  int)(185 << 24 | 2 << 16)

#define LER_ZOPC    (unsigned  int)(56 << 8)

#define LEDBR_ZOPC  (unsigned  int)(179 << 24 | 68 << 16)

#define LEXBR_ZOPC  (unsigned  int)(179 << 24 | 70 << 16)

#define LDEBR_ZOPC  (unsigned  int)(179 << 24 | 4 << 16)

#define LDR_ZOPC    (unsigned  int)(40 << 8)

#define LDXBR_ZOPC  (unsigned  int)(179 << 24 | 69 << 16)

#define LXEBR_ZOPC  (unsigned  int)(179 << 24 | 6 << 16)

#define LXDBR_ZOPC  (unsigned  int)(179 << 24 | 5 << 16)

#define LXR_ZOPC    (unsigned  int)(179 << 24 | 101 << 16)

#define LTEBR_ZOPC  (unsigned  int)(179 << 24 | 2 << 16)

#define LTDBR_ZOPC  (unsigned  int)(179 << 24 | 18 << 16)

#define LTXBR_ZOPC  (unsigned  int)(179 << 24 | 66 << 16)

#define LRVR_ZOPC   (unsigned  int)(0xb91f << 16)

#define LRVGR_ZOPC  (unsigned  int)(0xb90f << 16)

#define LDGR_ZOPC   (unsigned  int)(0xb3c1 << 16)                // z10

#define LGDR_ZOPC   (unsigned  int)(0xb3cd << 16)                // z10

#define LOCR_ZOPC   (unsigned  int)(0xb9f2 << 16)                // z196

#define LOCGR_ZOPC  (unsigned  int)(0xb9e2 << 16)                // z196

// immediate to register transfer

#define IIHH_ZOPC   (unsigned  int)(165 << 24)

#define IIHL_ZOPC   (unsigned  int)(165 << 24 | 1 << 16)

#define IILH_ZOPC   (unsigned  int)(165 << 24 | 2 << 16)

#define IILL_ZOPC   (unsigned  int)(165 << 24 | 3 << 16)

#define IIHF_ZOPC   (unsigned long)(0xc0L << 40 | 8L << 32)

#define IILF_ZOPC   (unsigned long)(0xc0L << 40 | 9L << 32)

#define LLIHH_ZOPC  (unsigned  int)(165 << 24 | 12 << 16)

#define LLIHL_ZOPC  (unsigned  int)(165 << 24 | 13 << 16)